1 /*
2  * Marvell EBU Armada SoCs thermal sensor driver
3  *
4  * Copyright (C) 2013 Marvell
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13  * GNU General Public License for more details.
14  *
15  */
16 #include <linux/device.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/kernel.h>
20 #include <linux/of.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/thermal.h>
26 #include <linux/iopoll.h>
27 
28 /* Thermal Manager Control and Status Register */
29 #define PMU_TDC0_SW_RST_MASK		(0x1 << 1)
30 #define PMU_TM_DISABLE_OFFS		0
31 #define PMU_TM_DISABLE_MASK		(0x1 << PMU_TM_DISABLE_OFFS)
32 #define PMU_TDC0_REF_CAL_CNT_OFFS	11
33 #define PMU_TDC0_REF_CAL_CNT_MASK	(0x1ff << PMU_TDC0_REF_CAL_CNT_OFFS)
34 #define PMU_TDC0_OTF_CAL_MASK		(0x1 << 30)
35 #define PMU_TDC0_START_CAL_MASK		(0x1 << 25)
36 
37 #define A375_UNIT_CONTROL_SHIFT		27
38 #define A375_UNIT_CONTROL_MASK		0x7
39 #define A375_READOUT_INVERT		BIT(15)
40 #define A375_HW_RESETn			BIT(8)
41 
42 /* Legacy bindings */
43 #define LEGACY_CONTROL_MEM_LEN		0x4
44 
45 /* Current bindings with the 2 control registers under the same memory area */
46 #define LEGACY_CONTROL1_OFFSET		0x0
47 #define CONTROL0_OFFSET			0x0
48 #define CONTROL1_OFFSET			0x4
49 
50 /* Errata fields */
51 #define CONTROL0_TSEN_TC_TRIM_MASK	0x7
52 #define CONTROL0_TSEN_TC_TRIM_VAL	0x3
53 
54 /* TSEN refers to the temperature sensors within the AP */
55 #define CONTROL0_TSEN_START		BIT(0)
56 #define CONTROL0_TSEN_RESET		BIT(1)
57 #define CONTROL0_TSEN_ENABLE		BIT(2)
58 
59 /* EXT_TSEN refers to the external temperature sensors, out of the AP */
60 #define CONTROL1_EXT_TSEN_SW_RESET	BIT(7)
61 #define CONTROL1_EXT_TSEN_HW_RESETn	BIT(8)
62 
63 #define STATUS_POLL_PERIOD_US		1000
64 #define STATUS_POLL_TIMEOUT_US		100000
65 
66 struct armada_thermal_data;
67 
68 /* Marvell EBU Thermal Sensor Dev Structure */
69 struct armada_thermal_priv {
70 	void __iomem *status;
71 	void __iomem *control0;
72 	void __iomem *control1;
73 	struct armada_thermal_data *data;
74 };
75 
76 struct armada_thermal_data {
77 	/* Initialize the sensor */
78 	void (*init_sensor)(struct platform_device *pdev,
79 			    struct armada_thermal_priv *);
80 
81 	/* Test for a valid sensor value (optional) */
82 	bool (*is_valid)(struct armada_thermal_priv *);
83 
84 	/* Formula coeficients: temp = (b - m * reg) / div */
85 	s64 coef_b;
86 	s64 coef_m;
87 	u32 coef_div;
88 	bool inverted;
89 	bool signed_sample;
90 
91 	/* Register shift and mask to access the sensor temperature */
92 	unsigned int temp_shift;
93 	unsigned int temp_mask;
94 	u32 is_valid_bit;
95 	bool needs_control0;
96 };
97 
98 static void armadaxp_init_sensor(struct platform_device *pdev,
99 				 struct armada_thermal_priv *priv)
100 {
101 	u32 reg;
102 
103 	reg = readl_relaxed(priv->control1);
104 	reg |= PMU_TDC0_OTF_CAL_MASK;
105 	writel(reg, priv->control1);
106 
107 	/* Reference calibration value */
108 	reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
109 	reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
110 	writel(reg, priv->control1);
111 
112 	/* Reset the sensor */
113 	reg = readl_relaxed(priv->control1);
114 	writel((reg | PMU_TDC0_SW_RST_MASK), priv->control1);
115 
116 	writel(reg, priv->control1);
117 
118 	/* Enable the sensor */
119 	reg = readl_relaxed(priv->status);
120 	reg &= ~PMU_TM_DISABLE_MASK;
121 	writel(reg, priv->status);
122 }
123 
124 static void armada370_init_sensor(struct platform_device *pdev,
125 				  struct armada_thermal_priv *priv)
126 {
127 	u32 reg;
128 
129 	reg = readl_relaxed(priv->control1);
130 	reg |= PMU_TDC0_OTF_CAL_MASK;
131 	writel(reg, priv->control1);
132 
133 	/* Reference calibration value */
134 	reg &= ~PMU_TDC0_REF_CAL_CNT_MASK;
135 	reg |= (0xf1 << PMU_TDC0_REF_CAL_CNT_OFFS);
136 	writel(reg, priv->control1);
137 
138 	reg &= ~PMU_TDC0_START_CAL_MASK;
139 	writel(reg, priv->control1);
140 
141 	msleep(10);
142 }
143 
144 static void armada375_init_sensor(struct platform_device *pdev,
145 				  struct armada_thermal_priv *priv)
146 {
147 	u32 reg;
148 
149 	reg = readl(priv->control1);
150 	reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
151 	reg &= ~A375_READOUT_INVERT;
152 	reg &= ~A375_HW_RESETn;
153 
154 	writel(reg, priv->control1);
155 	msleep(20);
156 
157 	reg |= A375_HW_RESETn;
158 	writel(reg, priv->control1);
159 	msleep(50);
160 }
161 
162 static void armada_wait_sensor_validity(struct armada_thermal_priv *priv)
163 {
164 	u32 reg;
165 
166 	readl_relaxed_poll_timeout(priv->status, reg,
167 				   reg & priv->data->is_valid_bit,
168 				   STATUS_POLL_PERIOD_US,
169 				   STATUS_POLL_TIMEOUT_US);
170 }
171 
172 static void armada380_init_sensor(struct platform_device *pdev,
173 				  struct armada_thermal_priv *priv)
174 {
175 	u32 reg = readl_relaxed(priv->control1);
176 
177 	/* Disable the HW/SW reset */
178 	reg |= CONTROL1_EXT_TSEN_HW_RESETn;
179 	reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
180 	writel(reg, priv->control1);
181 
182 	/* Set Tsen Tc Trim to correct default value (errata #132698) */
183 	if (priv->control0) {
184 		reg = readl_relaxed(priv->control0);
185 		reg &= ~CONTROL0_TSEN_TC_TRIM_MASK;
186 		reg |= CONTROL0_TSEN_TC_TRIM_VAL;
187 		writel(reg, priv->control0);
188 	}
189 
190 	/* Wait the sensors to be valid or the core will warn the user */
191 	armada_wait_sensor_validity(priv);
192 }
193 
194 static void armada_ap806_init_sensor(struct platform_device *pdev,
195 				     struct armada_thermal_priv *priv)
196 {
197 	u32 reg;
198 
199 	reg = readl_relaxed(priv->control0);
200 	reg &= ~CONTROL0_TSEN_RESET;
201 	reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
202 	writel(reg, priv->control0);
203 
204 	/* Wait the sensors to be valid or the core will warn the user */
205 	armada_wait_sensor_validity(priv);
206 }
207 
208 static bool armada_is_valid(struct armada_thermal_priv *priv)
209 {
210 	u32 reg = readl_relaxed(priv->status);
211 
212 	return reg & priv->data->is_valid_bit;
213 }
214 
215 static int armada_get_temp(struct thermal_zone_device *thermal,
216 			   int *temp)
217 {
218 	struct armada_thermal_priv *priv = thermal->devdata;
219 	u32 reg, div;
220 	s64 sample, b, m;
221 
222 	/* Valid check */
223 	if (priv->data->is_valid && !priv->data->is_valid(priv)) {
224 		dev_err(&thermal->device,
225 			"Temperature sensor reading not valid\n");
226 		return -EIO;
227 	}
228 
229 	reg = readl_relaxed(priv->status);
230 	reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
231 	if (priv->data->signed_sample)
232 		/* The most significant bit is the sign bit */
233 		sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
234 	else
235 		sample = reg;
236 
237 	/* Get formula coeficients */
238 	b = priv->data->coef_b;
239 	m = priv->data->coef_m;
240 	div = priv->data->coef_div;
241 
242 	if (priv->data->inverted)
243 		*temp = div_s64((m * sample) - b, div);
244 	else
245 		*temp = div_s64(b - (m * sample), div);
246 
247 	return 0;
248 }
249 
250 static struct thermal_zone_device_ops ops = {
251 	.get_temp = armada_get_temp,
252 };
253 
254 static const struct armada_thermal_data armadaxp_data = {
255 	.init_sensor = armadaxp_init_sensor,
256 	.temp_shift = 10,
257 	.temp_mask = 0x1ff,
258 	.coef_b = 3153000000ULL,
259 	.coef_m = 10000000ULL,
260 	.coef_div = 13825,
261 };
262 
263 static const struct armada_thermal_data armada370_data = {
264 	.is_valid = armada_is_valid,
265 	.init_sensor = armada370_init_sensor,
266 	.is_valid_bit = BIT(9),
267 	.temp_shift = 10,
268 	.temp_mask = 0x1ff,
269 	.coef_b = 3153000000ULL,
270 	.coef_m = 10000000ULL,
271 	.coef_div = 13825,
272 };
273 
274 static const struct armada_thermal_data armada375_data = {
275 	.is_valid = armada_is_valid,
276 	.init_sensor = armada375_init_sensor,
277 	.is_valid_bit = BIT(10),
278 	.temp_shift = 0,
279 	.temp_mask = 0x1ff,
280 	.coef_b = 3171900000ULL,
281 	.coef_m = 10000000ULL,
282 	.coef_div = 13616,
283 	.needs_control0 = true,
284 };
285 
286 static const struct armada_thermal_data armada380_data = {
287 	.is_valid = armada_is_valid,
288 	.init_sensor = armada380_init_sensor,
289 	.is_valid_bit = BIT(10),
290 	.temp_shift = 0,
291 	.temp_mask = 0x3ff,
292 	.coef_b = 1172499100ULL,
293 	.coef_m = 2000096ULL,
294 	.coef_div = 4201,
295 	.inverted = true,
296 };
297 
298 static const struct armada_thermal_data armada_ap806_data = {
299 	.is_valid = armada_is_valid,
300 	.init_sensor = armada_ap806_init_sensor,
301 	.is_valid_bit = BIT(16),
302 	.temp_shift = 0,
303 	.temp_mask = 0x3ff,
304 	.coef_b = -150000LL,
305 	.coef_m = 423ULL,
306 	.coef_div = 1,
307 	.inverted = true,
308 	.signed_sample = true,
309 	.needs_control0 = true,
310 };
311 
312 static const struct armada_thermal_data armada_cp110_data = {
313 	.is_valid = armada_is_valid,
314 	.init_sensor = armada380_init_sensor,
315 	.is_valid_bit = BIT(10),
316 	.temp_shift = 0,
317 	.temp_mask = 0x3ff,
318 	.coef_b = 1172499100ULL,
319 	.coef_m = 2000096ULL,
320 	.coef_div = 4201,
321 	.inverted = true,
322 	.needs_control0 = true,
323 };
324 
325 static const struct of_device_id armada_thermal_id_table[] = {
326 	{
327 		.compatible = "marvell,armadaxp-thermal",
328 		.data       = &armadaxp_data,
329 	},
330 	{
331 		.compatible = "marvell,armada370-thermal",
332 		.data       = &armada370_data,
333 	},
334 	{
335 		.compatible = "marvell,armada375-thermal",
336 		.data       = &armada375_data,
337 	},
338 	{
339 		.compatible = "marvell,armada380-thermal",
340 		.data       = &armada380_data,
341 	},
342 	{
343 		.compatible = "marvell,armada-ap806-thermal",
344 		.data       = &armada_ap806_data,
345 	},
346 	{
347 		.compatible = "marvell,armada-cp110-thermal",
348 		.data       = &armada_cp110_data,
349 	},
350 	{
351 		/* sentinel */
352 	},
353 };
354 MODULE_DEVICE_TABLE(of, armada_thermal_id_table);
355 
356 static int armada_thermal_probe(struct platform_device *pdev)
357 {
358 	void __iomem *control = NULL;
359 	struct thermal_zone_device *thermal;
360 	const struct of_device_id *match;
361 	struct armada_thermal_priv *priv;
362 	struct resource *res;
363 
364 	match = of_match_device(armada_thermal_id_table, &pdev->dev);
365 	if (!match)
366 		return -ENODEV;
367 
368 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
369 	if (!priv)
370 		return -ENOMEM;
371 
372 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
373 	priv->status = devm_ioremap_resource(&pdev->dev, res);
374 	if (IS_ERR(priv->status))
375 		return PTR_ERR(priv->status);
376 
377 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
378 	control = devm_ioremap_resource(&pdev->dev, res);
379 	if (IS_ERR(control))
380 		return PTR_ERR(control);
381 
382 	priv->data = (struct armada_thermal_data *)match->data;
383 
384 	/*
385 	 * Legacy DT bindings only described "control1" register (also referred
386 	 * as "control MSB" on old documentation). New bindings cover
387 	 * "control0/control LSB" and "control1/control MSB" registers within
388 	 * the same resource, which is then of size 8 instead of 4.
389 	 */
390 	if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
391 		/* ->control0 unavailable in this configuration */
392 		if (priv->data->needs_control0) {
393 			dev_err(&pdev->dev, "No access to control0 register\n");
394 			return -EINVAL;
395 		}
396 
397 		priv->control1 = control + LEGACY_CONTROL1_OFFSET;
398 	} else {
399 		priv->control0 = control + CONTROL0_OFFSET;
400 		priv->control1 = control + CONTROL1_OFFSET;
401 	}
402 
403 	priv->data->init_sensor(pdev, priv);
404 
405 	thermal = thermal_zone_device_register(dev_name(&pdev->dev), 0, 0, priv,
406 					       &ops, NULL, 0, 0);
407 	if (IS_ERR(thermal)) {
408 		dev_err(&pdev->dev,
409 			"Failed to register thermal zone device\n");
410 		return PTR_ERR(thermal);
411 	}
412 
413 	platform_set_drvdata(pdev, thermal);
414 
415 	return 0;
416 }
417 
418 static int armada_thermal_exit(struct platform_device *pdev)
419 {
420 	struct thermal_zone_device *armada_thermal =
421 		platform_get_drvdata(pdev);
422 
423 	thermal_zone_device_unregister(armada_thermal);
424 
425 	return 0;
426 }
427 
428 static struct platform_driver armada_thermal_driver = {
429 	.probe = armada_thermal_probe,
430 	.remove = armada_thermal_exit,
431 	.driver = {
432 		.name = "armada_thermal",
433 		.of_match_table = armada_thermal_id_table,
434 	},
435 };
436 
437 module_platform_driver(armada_thermal_driver);
438 
439 MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
440 MODULE_DESCRIPTION("Marvell EBU Armada SoCs thermal driver");
441 MODULE_LICENSE("GPL v2");
442