1 #ifndef TARGET_CORE_RD_H
2 #define TARGET_CORE_RD_H
3 
4 #define RD_HBA_VERSION		"v4.0"
5 #define RD_DR_VERSION		"4.0"
6 #define RD_MCP_VERSION		"4.0"
7 
8 /* Largest piece of memory kmalloc can allocate */
9 #define RD_MAX_ALLOCATION_SIZE	65536
10 /* Maximum queuedepth for the Ramdisk HBA */
11 #define RD_HBA_QUEUE_DEPTH	256
12 #define RD_DEVICE_QUEUE_DEPTH	32
13 #define RD_MAX_DEVICE_QUEUE_DEPTH 128
14 #define RD_BLOCKSIZE		512
15 #define RD_MAX_SECTORS		1024
16 
17 extern struct kmem_cache *se_mem_cache;
18 
19 /* Used in target_core_init_configfs() for virtual LUN 0 access */
20 int __init rd_module_init(void);
21 void rd_module_exit(void);
22 
23 #define RRF_EMULATE_CDB		0x01
24 #define RRF_GOT_LBA		0x02
25 
26 struct rd_request {
27 	struct se_task	rd_task;
28 
29 	/* SCSI CDB from iSCSI Command PDU */
30 	unsigned char	rd_scsi_cdb[TCM_MAX_COMMAND_SIZE];
31 	/* Offset from start of page */
32 	u32		rd_offset;
33 	/* Starting page in Ramdisk for request */
34 	u32		rd_page;
35 	/* Total number of pages needed for request */
36 	u32		rd_page_count;
37 	/* Scatterlist count */
38 	u32		rd_size;
39 	/* Ramdisk device */
40 	struct rd_dev	*rd_dev;
41 } ____cacheline_aligned;
42 
43 struct rd_dev_sg_table {
44 	u32		page_start_offset;
45 	u32		page_end_offset;
46 	u32		rd_sg_count;
47 	struct scatterlist *sg_table;
48 } ____cacheline_aligned;
49 
50 #define RDF_HAS_PAGE_COUNT	0x01
51 
52 struct rd_dev {
53 	int		rd_direct;
54 	u32		rd_flags;
55 	/* Unique Ramdisk Device ID in Ramdisk HBA */
56 	u32		rd_dev_id;
57 	/* Total page count for ramdisk device */
58 	u32		rd_page_count;
59 	/* Number of SG tables in sg_table_array */
60 	u32		sg_table_count;
61 	u32		rd_queue_depth;
62 	/* Array of rd_dev_sg_table_t containing scatterlists */
63 	struct rd_dev_sg_table *sg_table_array;
64 	/* Ramdisk HBA device is connected to */
65 	struct rd_host *rd_host;
66 } ____cacheline_aligned;
67 
68 struct rd_host {
69 	u32		rd_host_dev_id_count;
70 	u32		rd_host_id;		/* Unique Ramdisk Host ID */
71 } ____cacheline_aligned;
72 
73 #endif /* TARGET_CORE_RD_H */
74