1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * Purpose: rf function code 7 * 8 * Author: Jerry Chen 9 * 10 * Date: Feb. 19, 2004 11 * 12 * Functions: 13 * IFRFbWriteEmbedded - Embedded write RF register via MAC 14 * 15 * Revision History: 16 * RobertYu 2005 17 * chester 2008 18 * 19 */ 20 21 #include "mac.h" 22 #include "srom.h" 23 #include "rf.h" 24 #include "baseband.h" 25 26 #define BY_AL2230_REG_LEN 23 /* 24bit */ 27 #define CB_AL2230_INIT_SEQ 15 28 #define SWITCH_CHANNEL_DELAY_AL2230 200 /* us */ 29 #define AL2230_PWR_IDX_LEN 64 30 31 #define BY_AL7230_REG_LEN 23 /* 24bit */ 32 #define CB_AL7230_INIT_SEQ 16 33 #define SWITCH_CHANNEL_DELAY_AL7230 200 /* us */ 34 #define AL7230_PWR_IDX_LEN 64 35 36 static const unsigned long al2230_init_table[CB_AL2230_INIT_SEQ] = { 37 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 38 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 39 0x01A00200 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 40 0x00FFF300 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 41 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 42 0x0F4DC500 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 43 0x0805B600 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 44 0x0146C700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 45 0x00068800 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 46 0x0403B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 47 0x00DBBA00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 48 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 49 0x0BDFFC00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 50 0x00000D00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 51 0x00580F00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW 52 }; 53 54 static const unsigned long al2230_channel_table0[CB_MAX_CHANNEL] = { 55 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ 56 0x03F79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ 57 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ 58 0x03E79000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ 59 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ 60 0x03F7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ 61 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ 62 0x03E7A000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ 63 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ 64 0x03F7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ 65 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ 66 0x03E7B000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ 67 0x03F7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ 68 0x03E7C000 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */ 69 }; 70 71 static const unsigned long al2230_channel_table1[CB_MAX_CHANNEL] = { 72 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ 73 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ 74 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ 75 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ 76 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ 77 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ 78 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ 79 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ 80 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ 81 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ 82 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ 83 0x0B333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ 84 0x03333100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ 85 0x06666100 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 14, Tf = 2412M */ 86 }; 87 88 static unsigned long al2230_power_table[AL2230_PWR_IDX_LEN] = { 89 0x04040900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 90 0x04041900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 91 0x04042900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 92 0x04043900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 93 0x04044900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 94 0x04045900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 95 0x04046900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 96 0x04047900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 97 0x04048900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 98 0x04049900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 99 0x0404A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 100 0x0404B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 101 0x0404C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 102 0x0404D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 103 0x0404E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 104 0x0404F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 105 0x04050900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 106 0x04051900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 107 0x04052900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 108 0x04053900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 109 0x04054900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 110 0x04055900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 111 0x04056900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 112 0x04057900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 113 0x04058900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 114 0x04059900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 115 0x0405A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 116 0x0405B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 117 0x0405C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 118 0x0405D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 119 0x0405E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 120 0x0405F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 121 0x04060900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 122 0x04061900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 123 0x04062900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 124 0x04063900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 125 0x04064900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 126 0x04065900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 127 0x04066900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 128 0x04067900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 129 0x04068900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 130 0x04069900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 131 0x0406A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 132 0x0406B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 133 0x0406C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 134 0x0406D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 135 0x0406E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 136 0x0406F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 137 0x04070900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 138 0x04071900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 139 0x04072900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 140 0x04073900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 141 0x04074900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 142 0x04075900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 143 0x04076900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 144 0x04077900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 145 0x04078900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 146 0x04079900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 147 0x0407A900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 148 0x0407B900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 149 0x0407C900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 150 0x0407D900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 151 0x0407E900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW, 152 0x0407F900 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW 153 }; 154 155 /* 40MHz reference frequency 156 * Need to Pull PLLON(PE3) low when writing channel registers through 3-wire. 157 */ 158 static const unsigned long al7230_init_table[CB_AL7230_INIT_SEQ] = { 159 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ 160 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel1 // Need modify for 11a */ 161 0x841FF200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 451FE2 */ 162 0x3FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 5FDFA3 */ 163 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11b/g // Need modify for 11a */ 164 /* RoberYu:20050113, Rev0.47 Register Setting Guide */ 165 0x802B5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 8D1B55 */ 166 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 167 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 860207 */ 168 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 169 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 170 0xE0000A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: E0600A */ 171 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ 172 /* RoberYu:20050113, Rev0.47 Register Setting Guide */ 173 0x000A3C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11a: 00143C */ 174 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 175 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 176 0x1ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11a: 12BACF */ 177 }; 178 179 static const unsigned long al7230_init_table_a_mode[CB_AL7230_INIT_SEQ] = { 180 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ 181 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Channel184 // Need modify for 11b/g */ 182 0x451FE200 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ 183 0x5FDFA300 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ 184 0x67F78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* 11a // Need modify for 11b/g */ 185 0x853F5500 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g, RoberYu:20050113 */ 186 0x56AF3600 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 187 0xCE020700 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ 188 0x6EBC0800 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 189 0x221BB900 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 190 0xE0600A00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ 191 0x08031B00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) */ 192 0x00147C00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* Need modify for 11b/g */ 193 0xFFFFFD00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 194 0x00000E00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, 195 0x12BACF00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* Need modify for 11b/g */ 196 }; 197 198 static const unsigned long al7230_channel_table0[CB_MAX_CHANNEL] = { 199 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ 200 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ 201 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ 202 0x00379000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ 203 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ 204 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ 205 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ 206 0x0037A000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 */ 207 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 */ 208 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 */ 209 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 */ 210 0x0037B000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 */ 211 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 */ 212 0x0037C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ 213 214 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ 215 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ 216 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ 217 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ 218 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ 219 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ 220 0x0FF52000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ 221 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ 222 0x0FF53000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ 223 224 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 225 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 226 */ 227 228 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ 229 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ 230 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ 231 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ 232 0x0FF54000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ 233 0x0FF55000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ 234 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ 235 0x0FF56000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ 236 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 */ 237 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ 238 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ 239 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ 240 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ 241 0x0FF57000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ 242 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ 243 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ 244 0x0FF58000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ 245 0x0FF59000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ 246 247 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ 248 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ 249 0x0FF5C000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ 250 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ 251 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ 252 0x0FF5D000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ 253 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ 254 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ 255 0x0FF5E000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ 256 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ 257 0x0FF5F000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ 258 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ 259 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ 260 0x0FF60000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ 261 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ 262 0x0FF61000 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ 263 }; 264 265 static const unsigned long al7230_channel_table1[CB_MAX_CHANNEL] = { 266 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ 267 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ 268 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ 269 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ 270 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ 271 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ 272 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ 273 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ 274 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ 275 0x1B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ 276 0x03333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ 277 0x0B333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ 278 0x13333100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ 279 0x06666100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ 280 281 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ 282 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ 283 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ 284 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ 285 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ 286 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ 287 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ 288 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ 289 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ 290 291 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 292 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 293 */ 294 0x1D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ 295 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ 296 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ 297 0x08000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ 298 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ 299 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ 300 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ 301 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ 302 0x10000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ 303 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ 304 0x1AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ 305 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ 306 0x05555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ 307 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ 308 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ 309 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ 310 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ 311 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ 312 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ 313 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ 314 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ 315 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ 316 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ 317 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ 318 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ 319 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ 320 0x0AAAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ 321 0x15555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ 322 0x00000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ 323 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ 324 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ 325 0x0D555100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ 326 0x18000100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ 327 0x02AAA100 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ 328 }; 329 330 static const unsigned long al7230_channel_table2[CB_MAX_CHANNEL] = { 331 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 1, Tf = 2412MHz */ 332 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 2, Tf = 2417MHz */ 333 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 3, Tf = 2422MHz */ 334 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 4, Tf = 2427MHz */ 335 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 5, Tf = 2432MHz */ 336 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 6, Tf = 2437MHz */ 337 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 2442MHz */ 338 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 2447MHz */ 339 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 2452MHz */ 340 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 10, Tf = 2457MHz */ 341 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 2462MHz */ 342 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 2467MHz */ 343 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 13, Tf = 2472MHz */ 344 0x7FD78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 14, Tf = 2484MHz */ 345 346 /* 4.9G => Ch 183, 184, 185, 187, 188, 189, 192, 196 (Value:15 ~ 22) */ 347 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 183, Tf = 4915MHz (15) */ 348 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 184, Tf = 4920MHz (16) */ 349 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 185, Tf = 4925MHz (17) */ 350 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 187, Tf = 4935MHz (18) */ 351 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 188, Tf = 4940MHz (19) */ 352 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 189, Tf = 4945MHz (20) */ 353 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 192, Tf = 4960MHz (21) */ 354 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 196, Tf = 4980MHz (22) */ 355 356 /* 5G => Ch 7, 8, 9, 11, 12, 16, 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64, 357 * 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165 (Value 23 ~ 56) 358 */ 359 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 7, Tf = 5035MHz (23) */ 360 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 8, Tf = 5040MHz (24) */ 361 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 9, Tf = 5045MHz (25) */ 362 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 11, Tf = 5055MHz (26) */ 363 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 12, Tf = 5060MHz (27) */ 364 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 16, Tf = 5080MHz (28) */ 365 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 34, Tf = 5170MHz (29) */ 366 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 36, Tf = 5180MHz (30) */ 367 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 38, Tf = 5190MHz (31) */ 368 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 40, Tf = 5200MHz (32) */ 369 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 42, Tf = 5210MHz (33) */ 370 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 44, Tf = 5220MHz (34) */ 371 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 46, Tf = 5230MHz (35) */ 372 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 48, Tf = 5240MHz (36) */ 373 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 52, Tf = 5260MHz (37) */ 374 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 56, Tf = 5280MHz (38) */ 375 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 60, Tf = 5300MHz (39) */ 376 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 64, Tf = 5320MHz (40) */ 377 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 100, Tf = 5500MHz (41) */ 378 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 104, Tf = 5520MHz (42) */ 379 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 108, Tf = 5540MHz (43) */ 380 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 112, Tf = 5560MHz (44) */ 381 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 116, Tf = 5580MHz (45) */ 382 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 120, Tf = 5600MHz (46) */ 383 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 124, Tf = 5620MHz (47) */ 384 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 128, Tf = 5640MHz (48) */ 385 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 132, Tf = 5660MHz (49) */ 386 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 136, Tf = 5680MHz (50) */ 387 0x67D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 140, Tf = 5700MHz (51) */ 388 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 149, Tf = 5745MHz (52) */ 389 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 153, Tf = 5765MHz (53) */ 390 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 157, Tf = 5785MHz (54) */ 391 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW, /* channel = 161, Tf = 5805MHz (55) */ 392 0x77D78400 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW /* channel = 165, Tf = 5825MHz (56) */ 393 }; 394 395 /* 396 * Description: AIROHA IFRF chip init function 397 * 398 * Parameters: 399 * In: 400 * iobase - I/O base address 401 * Out: 402 * none 403 * 404 * Return Value: true if succeeded; false if failed. 405 * 406 */ 407 static bool s_bAL7230Init(struct vnt_private *priv) 408 { 409 void __iomem *iobase = priv->port_offset; 410 int ii; 411 bool ret; 412 413 ret = true; 414 415 /* 3-wire control for normal mode */ 416 VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0); 417 418 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | 419 SOFTPWRCTL_TXPEINV)); 420 bb_power_save_mode_off(priv); /* RobertYu:20050106, have DC value for Calibration */ 421 422 for (ii = 0; ii < CB_AL7230_INIT_SEQ; ii++) 423 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[ii]); 424 425 /* PLL On */ 426 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 427 428 /* Calibration */ 429 MACvTimer0MicroSDelay(priv, 150);/* 150us */ 430 /* TXDCOC:active, RCK:disable */ 431 ret &= IFRFbWriteEmbedded(priv, (0x9ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW)); 432 MACvTimer0MicroSDelay(priv, 30);/* 30us */ 433 /* TXDCOC:disable, RCK:active */ 434 ret &= IFRFbWriteEmbedded(priv, (0x3ABA8F00 + (BY_AL7230_REG_LEN << 3) + IFREGCTL_REGW)); 435 MACvTimer0MicroSDelay(priv, 30);/* 30us */ 436 /* TXDCOC:disable, RCK:disable */ 437 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[CB_AL7230_INIT_SEQ - 1]); 438 439 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | 440 SOFTPWRCTL_SWPE2 | 441 SOFTPWRCTL_SWPECTI | 442 SOFTPWRCTL_TXPEINV)); 443 444 bb_power_save_mode_on(priv); /* RobertYu:20050106 */ 445 446 /* PE1: TX_ON, PE2: RX_ON, PE3: PLLON */ 447 /* 3-wire control for power saving mode */ 448 VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ 449 450 return ret; 451 } 452 453 /* Need to Pull PLLON low when writing channel registers through 454 * 3-wire interface 455 */ 456 static bool s_bAL7230SelectChannel(struct vnt_private *priv, unsigned char byChannel) 457 { 458 void __iomem *iobase = priv->port_offset; 459 bool ret; 460 461 ret = true; 462 463 /* PLLON Off */ 464 MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 465 466 ret &= IFRFbWriteEmbedded(priv, al7230_channel_table0[byChannel - 1]); 467 ret &= IFRFbWriteEmbedded(priv, al7230_channel_table1[byChannel - 1]); 468 ret &= IFRFbWriteEmbedded(priv, al7230_channel_table2[byChannel - 1]); 469 470 /* PLLOn On */ 471 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 472 473 /* Set Channel[7] = 0 to tell H/W channel is changing now. */ 474 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F)); 475 MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL7230); 476 /* Set Channel[7] = 1 to tell H/W channel change is done. */ 477 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80)); 478 479 return ret; 480 } 481 482 /* 483 * Description: Write to IF/RF, by embedded programming 484 * 485 * Parameters: 486 * In: 487 * iobase - I/O base address 488 * dwData - data to write 489 * Out: 490 * none 491 * 492 * Return Value: true if succeeded; false if failed. 493 * 494 */ 495 bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData) 496 { 497 void __iomem *iobase = priv->port_offset; 498 unsigned short ww; 499 unsigned long dwValue; 500 501 VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData); 502 503 /* W_MAX_TIMEOUT is the timeout period */ 504 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 505 VNSvInPortD(iobase + MAC_REG_IFREGCTL, &dwValue); 506 if (dwValue & IFREGCTL_DONE) 507 break; 508 } 509 510 if (ww == W_MAX_TIMEOUT) 511 return false; 512 513 return true; 514 } 515 516 /* 517 * Description: AIROHA IFRF chip init function 518 * 519 * Parameters: 520 * In: 521 * iobase - I/O base address 522 * Out: 523 * none 524 * 525 * Return Value: true if succeeded; false if failed. 526 * 527 */ 528 static bool RFbAL2230Init(struct vnt_private *priv) 529 { 530 void __iomem *iobase = priv->port_offset; 531 int ii; 532 bool ret; 533 534 ret = true; 535 536 /* 3-wire control for normal mode */ 537 VNSvOutPortB(iobase + MAC_REG_SOFTPWRCTL, 0); 538 539 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPECTI | 540 SOFTPWRCTL_TXPEINV)); 541 /* PLL Off */ 542 MACvWordRegBitsOff(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 543 544 /* patch abnormal AL2230 frequency output */ 545 IFRFbWriteEmbedded(priv, (0x07168700 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); 546 547 for (ii = 0; ii < CB_AL2230_INIT_SEQ; ii++) 548 ret &= IFRFbWriteEmbedded(priv, al2230_init_table[ii]); 549 MACvTimer0MicroSDelay(priv, 30); /* delay 30 us */ 550 551 /* PLL On */ 552 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_SWPE3); 553 554 MACvTimer0MicroSDelay(priv, 150);/* 150us */ 555 ret &= IFRFbWriteEmbedded(priv, (0x00d80f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); 556 MACvTimer0MicroSDelay(priv, 30);/* 30us */ 557 ret &= IFRFbWriteEmbedded(priv, (0x00780f00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW)); 558 MACvTimer0MicroSDelay(priv, 30);/* 30us */ 559 ret &= IFRFbWriteEmbedded(priv, 560 al2230_init_table[CB_AL2230_INIT_SEQ - 1]); 561 562 MACvWordRegBitsOn(iobase, MAC_REG_SOFTPWRCTL, (SOFTPWRCTL_SWPE3 | 563 SOFTPWRCTL_SWPE2 | 564 SOFTPWRCTL_SWPECTI | 565 SOFTPWRCTL_TXPEINV)); 566 567 /* 3-wire control for power saving mode */ 568 VNSvOutPortB(iobase + MAC_REG_PSPWRSIG, (PSSIG_WPE3 | PSSIG_WPE2)); /* 1100 0000 */ 569 570 return ret; 571 } 572 573 static bool RFbAL2230SelectChannel(struct vnt_private *priv, unsigned char byChannel) 574 { 575 void __iomem *iobase = priv->port_offset; 576 bool ret; 577 578 ret = true; 579 580 ret &= IFRFbWriteEmbedded(priv, al2230_channel_table0[byChannel - 1]); 581 ret &= IFRFbWriteEmbedded(priv, al2230_channel_table1[byChannel - 1]); 582 583 /* Set Channel[7] = 0 to tell H/W channel is changing now. */ 584 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel & 0x7F)); 585 MACvTimer0MicroSDelay(priv, SWITCH_CHANNEL_DELAY_AL2230); 586 /* Set Channel[7] = 1 to tell H/W channel change is done. */ 587 VNSvOutPortB(iobase + MAC_REG_CHANNEL, (byChannel | 0x80)); 588 589 return ret; 590 } 591 592 /* 593 * Description: RF init function 594 * 595 * Parameters: 596 * In: 597 * byBBType 598 * byRFType 599 * Out: 600 * none 601 * 602 * Return Value: true if succeeded; false if failed. 603 * 604 */ 605 bool RFbInit(struct vnt_private *priv) 606 { 607 bool ret = true; 608 609 switch (priv->byRFType) { 610 case RF_AIROHA: 611 case RF_AL2230S: 612 priv->max_pwr_level = AL2230_PWR_IDX_LEN; 613 ret = RFbAL2230Init(priv); 614 break; 615 case RF_AIROHA7230: 616 priv->max_pwr_level = AL7230_PWR_IDX_LEN; 617 ret = s_bAL7230Init(priv); 618 break; 619 case RF_NOTHING: 620 ret = true; 621 break; 622 default: 623 ret = false; 624 break; 625 } 626 return ret; 627 } 628 629 /* 630 * Description: Select channel 631 * 632 * Parameters: 633 * In: 634 * byRFType 635 * byChannel - Channel number 636 * Out: 637 * none 638 * 639 * Return Value: true if succeeded; false if failed. 640 * 641 */ 642 bool RFbSelectChannel(struct vnt_private *priv, unsigned char byRFType, 643 u16 byChannel) 644 { 645 bool ret = true; 646 647 switch (byRFType) { 648 case RF_AIROHA: 649 case RF_AL2230S: 650 ret = RFbAL2230SelectChannel(priv, byChannel); 651 break; 652 /*{{ RobertYu: 20050104 */ 653 case RF_AIROHA7230: 654 ret = s_bAL7230SelectChannel(priv, byChannel); 655 break; 656 /*}} RobertYu */ 657 case RF_NOTHING: 658 ret = true; 659 break; 660 default: 661 ret = false; 662 break; 663 } 664 return ret; 665 } 666 667 /* 668 * Description: Write WakeProgSyn 669 * 670 * Parameters: 671 * In: 672 * priv - Device Structure 673 * rf_type - RF type 674 * channel - Channel number 675 * 676 * Return Value: true if succeeded; false if failed. 677 * 678 */ 679 bool rf_write_wake_prog_syn(struct vnt_private *priv, unsigned char rf_type, 680 u16 channel) 681 { 682 void __iomem *iobase = priv->port_offset; 683 int i; 684 unsigned char init_count = 0; 685 unsigned char sleep_count = 0; 686 unsigned short idx = MISCFIFO_SYNDATA_IDX; 687 const unsigned long *init_table; 688 689 VNSvOutPortW(iobase + MAC_REG_MISCFFNDEX, 0); 690 switch (rf_type) { 691 case RF_AIROHA: 692 case RF_AL2230S: 693 694 if (channel > CB_MAX_CHANNEL_24G) 695 return false; 696 697 /* Init Reg + Channel Reg (2) */ 698 init_count = CB_AL2230_INIT_SEQ + 2; 699 sleep_count = 0; 700 701 for (i = 0; i < CB_AL2230_INIT_SEQ; i++) 702 MACvSetMISCFifo(priv, idx++, al2230_init_table[i]); 703 704 MACvSetMISCFifo(priv, idx++, al2230_channel_table0[channel - 1]); 705 MACvSetMISCFifo(priv, idx++, al2230_channel_table1[channel - 1]); 706 break; 707 708 /* Need to check, PLLON need to be low for channel setting */ 709 case RF_AIROHA7230: 710 /* Init Reg + Channel Reg (3) */ 711 init_count = CB_AL7230_INIT_SEQ + 3; 712 sleep_count = 0; 713 714 init_table = (channel <= CB_MAX_CHANNEL_24G) ? 715 al7230_init_table : al7230_init_table_a_mode; 716 for (i = 0; i < CB_AL7230_INIT_SEQ; i++) 717 MACvSetMISCFifo(priv, idx++, init_table[i]); 718 719 MACvSetMISCFifo(priv, idx++, al7230_channel_table0[channel - 1]); 720 MACvSetMISCFifo(priv, idx++, al7230_channel_table1[channel - 1]); 721 MACvSetMISCFifo(priv, idx++, al7230_channel_table2[channel - 1]); 722 break; 723 724 case RF_NOTHING: 725 return true; 726 727 default: 728 return false; 729 } 730 731 MACvSetMISCFifo(priv, MISCFIFO_SYNINFO_IDX, (unsigned long)MAKEWORD(sleep_count, init_count)); 732 733 return true; 734 } 735 736 /* 737 * Description: Set Tx power 738 * 739 * Parameters: 740 * In: 741 * iobase - I/O base address 742 * dwRFPowerTable - RF Tx Power Setting 743 * Out: 744 * none 745 * 746 * Return Value: true if succeeded; false if failed. 747 * 748 */ 749 bool RFbSetPower(struct vnt_private *priv, unsigned int rate, u16 uCH) 750 { 751 bool ret; 752 unsigned char byPwr = 0; 753 unsigned char byDec = 0; 754 755 if (priv->dwDiagRefCount != 0) 756 return true; 757 758 if ((uCH < 1) || (uCH > CB_MAX_CHANNEL)) 759 return false; 760 761 switch (rate) { 762 case RATE_1M: 763 case RATE_2M: 764 case RATE_5M: 765 case RATE_11M: 766 if (uCH > CB_MAX_CHANNEL_24G) 767 return false; 768 769 byPwr = priv->abyCCKPwrTbl[uCH]; 770 break; 771 case RATE_6M: 772 case RATE_9M: 773 case RATE_12M: 774 case RATE_18M: 775 byPwr = priv->abyOFDMPwrTbl[uCH]; 776 if (priv->byRFType == RF_UW2452) 777 byDec = byPwr + 14; 778 else 779 byDec = byPwr + 10; 780 781 if (byDec >= priv->max_pwr_level) 782 byDec = priv->max_pwr_level - 1; 783 784 byPwr = byDec; 785 break; 786 case RATE_24M: 787 case RATE_36M: 788 case RATE_48M: 789 case RATE_54M: 790 byPwr = priv->abyOFDMPwrTbl[uCH]; 791 break; 792 } 793 794 if (priv->byCurPwr == byPwr) 795 return true; 796 797 ret = RFbRawSetPower(priv, byPwr, rate); 798 if (ret) 799 priv->byCurPwr = byPwr; 800 801 return ret; 802 } 803 804 /* 805 * Description: Set Tx power 806 * 807 * Parameters: 808 * In: 809 * iobase - I/O base address 810 * dwRFPowerTable - RF Tx Power Setting 811 * Out: 812 * none 813 * 814 * Return Value: true if succeeded; false if failed. 815 * 816 */ 817 818 bool RFbRawSetPower(struct vnt_private *priv, unsigned char byPwr, 819 unsigned int rate) 820 { 821 bool ret = true; 822 unsigned long dwMax7230Pwr = 0; 823 824 if (byPwr >= priv->max_pwr_level) 825 return false; 826 827 switch (priv->byRFType) { 828 case RF_AIROHA: 829 ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]); 830 if (rate <= RATE_11M) 831 ret &= IFRFbWriteEmbedded(priv, 0x0001B400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 832 else 833 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 834 835 break; 836 837 case RF_AL2230S: 838 ret &= IFRFbWriteEmbedded(priv, al2230_power_table[byPwr]); 839 if (rate <= RATE_11M) { 840 ret &= IFRFbWriteEmbedded(priv, 0x040C1400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 841 ret &= IFRFbWriteEmbedded(priv, 0x00299B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 842 } else { 843 ret &= IFRFbWriteEmbedded(priv, 0x0005A400 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 844 ret &= IFRFbWriteEmbedded(priv, 0x00099B00 + (BY_AL2230_REG_LEN << 3) + IFREGCTL_REGW); 845 } 846 847 break; 848 849 case RF_AIROHA7230: 850 /* 0x080F1B00 for 3 wire control TxGain(D10) 851 * and 0x31 as TX Gain value 852 */ 853 dwMax7230Pwr = 0x080C0B00 | ((byPwr) << 12) | 854 (BY_AL7230_REG_LEN << 3) | IFREGCTL_REGW; 855 856 ret &= IFRFbWriteEmbedded(priv, dwMax7230Pwr); 857 break; 858 859 default: 860 break; 861 } 862 return ret; 863 } 864 865 /* 866 * 867 * Routine Description: 868 * Translate RSSI to dBm 869 * 870 * Parameters: 871 * In: 872 * priv - The adapter to be translated 873 * byCurrRSSI - RSSI to be translated 874 * Out: 875 * pdwdbm - Translated dbm number 876 * 877 * Return Value: none 878 * 879 */ 880 void 881 RFvRSSITodBm(struct vnt_private *priv, unsigned char byCurrRSSI, long *pldBm) 882 { 883 unsigned char byIdx = (((byCurrRSSI & 0xC0) >> 6) & 0x03); 884 long b = (byCurrRSSI & 0x3F); 885 long a = 0; 886 unsigned char abyAIROHARF[4] = {0, 18, 0, 40}; 887 888 switch (priv->byRFType) { 889 case RF_AIROHA: 890 case RF_AL2230S: 891 case RF_AIROHA7230: 892 a = abyAIROHARF[byIdx]; 893 break; 894 default: 895 break; 896 } 897 898 *pldBm = -1 * (a + b * 2); 899 } 900 901 /* Post processing for the 11b/g and 11a. 902 * for save time on changing Reg2,3,5,7,10,12,15 903 */ 904 bool RFbAL7230SelectChannelPostProcess(struct vnt_private *priv, 905 u16 byOldChannel, 906 u16 byNewChannel) 907 { 908 bool ret; 909 910 ret = true; 911 912 /* if change between 11 b/g and 11a need to update the following 913 * register 914 * Channel Index 1~14 915 */ 916 if ((byOldChannel <= CB_MAX_CHANNEL_24G) && (byNewChannel > CB_MAX_CHANNEL_24G)) { 917 /* Change from 2.4G to 5G [Reg] */ 918 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[2]); 919 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[3]); 920 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[5]); 921 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[7]); 922 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[10]); 923 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[12]); 924 ret &= IFRFbWriteEmbedded(priv, al7230_init_table_a_mode[15]); 925 } else if ((byOldChannel > CB_MAX_CHANNEL_24G) && (byNewChannel <= CB_MAX_CHANNEL_24G)) { 926 /* Change from 5G to 2.4G [Reg] */ 927 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[2]); 928 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[3]); 929 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[5]); 930 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[7]); 931 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[10]); 932 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[12]); 933 ret &= IFRFbWriteEmbedded(priv, al7230_init_table[15]); 934 } 935 936 return ret; 937 } 938