1 /* 2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * 20 * File: mac.h 21 * 22 * Purpose: MAC routines 23 * 24 * Author: Tevin Chen 25 * 26 * Date: May 21, 1996 27 * 28 * Revision History: 29 * 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec. 30 * 08-25-2003 Kyle Hsu: Porting MAC functions from sim53. 31 * 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD 32 */ 33 34 #ifndef __MAC_H__ 35 #define __MAC_H__ 36 37 #include "tmacro.h" 38 #include "upc.h" 39 40 /*--------------------- Export Definitions -------------------------*/ 41 /* Registers in the MAC */ 42 #define MAC_MAX_CONTEXT_SIZE_PAGE0 256 43 #define MAC_MAX_CONTEXT_SIZE_PAGE1 128 44 45 /* Registers not related to 802.11b */ 46 #define MAC_REG_BCFG0 0x00 47 #define MAC_REG_BCFG1 0x01 48 #define MAC_REG_FCR0 0x02 49 #define MAC_REG_FCR1 0x03 50 #define MAC_REG_BISTCMD 0x04 51 #define MAC_REG_BISTSR0 0x05 52 #define MAC_REG_BISTSR1 0x06 53 #define MAC_REG_BISTSR2 0x07 54 #define MAC_REG_I2MCSR 0x08 55 #define MAC_REG_I2MTGID 0x09 56 #define MAC_REG_I2MTGAD 0x0A 57 #define MAC_REG_I2MCFG 0x0B 58 #define MAC_REG_I2MDIPT 0x0C 59 #define MAC_REG_I2MDOPT 0x0E 60 #define MAC_REG_PMC0 0x10 61 #define MAC_REG_PMC1 0x11 62 #define MAC_REG_STICKHW 0x12 63 #define MAC_REG_LOCALID 0x14 64 #define MAC_REG_TESTCFG 0x15 65 #define MAC_REG_JUMPER0 0x16 66 #define MAC_REG_JUMPER1 0x17 67 #define MAC_REG_TMCTL0 0x18 68 #define MAC_REG_TMCTL1 0x19 69 #define MAC_REG_TMDATA0 0x1C 70 71 /* MAC Parameter related */ 72 #define MAC_REG_LRT 0x20 73 #define MAC_REG_SRT 0x21 74 #define MAC_REG_SIFS 0x22 75 #define MAC_REG_DIFS 0x23 76 #define MAC_REG_EIFS 0x24 77 #define MAC_REG_SLOT 0x25 78 #define MAC_REG_BI 0x26 79 #define MAC_REG_CWMAXMIN0 0x28 80 #define MAC_REG_LINKOFFTOTM 0x2A 81 #define MAC_REG_SWTMOT 0x2B 82 #define MAC_REG_MIBCNTR 0x2C 83 #define MAC_REG_RTSOKCNT 0x2C 84 #define MAC_REG_RTSFAILCNT 0x2D 85 #define MAC_REG_ACKFAILCNT 0x2E 86 #define MAC_REG_FCSERRCNT 0x2F 87 88 /* TSF Related */ 89 #define MAC_REG_TSFCNTR 0x30 90 #define MAC_REG_NEXTTBTT 0x38 91 #define MAC_REG_TSFOFST 0x40 92 #define MAC_REG_TFTCTL 0x48 93 94 /* WMAC Control/Status Related */ 95 #define MAC_REG_ENCFG 0x4C 96 #define MAC_REG_PAGE1SEL 0x4F 97 #define MAC_REG_CFG 0x50 98 #define MAC_REG_TEST 0x52 99 #define MAC_REG_HOSTCR 0x54 100 #define MAC_REG_MACCR 0x55 101 #define MAC_REG_RCR 0x56 102 #define MAC_REG_TCR 0x57 103 #define MAC_REG_IMR 0x58 104 #define MAC_REG_ISR 0x5C 105 106 /* Power Saving Related */ 107 #define MAC_REG_PSCFG 0x60 108 #define MAC_REG_PSCTL 0x61 109 #define MAC_REG_PSPWRSIG 0x62 110 #define MAC_REG_BBCR13 0x63 111 #define MAC_REG_AIDATIM 0x64 112 #define MAC_REG_PWBT 0x66 113 #define MAC_REG_WAKEOKTMR 0x68 114 #define MAC_REG_CALTMR 0x69 115 #define MAC_REG_SYNSPACCNT 0x6A 116 #define MAC_REG_WAKSYNOPT 0x6B 117 118 /* Baseband/IF Control Group */ 119 #define MAC_REG_BBREGCTL 0x6C 120 #define MAC_REG_CHANNEL 0x6D 121 #define MAC_REG_BBREGADR 0x6E 122 #define MAC_REG_BBREGDATA 0x6F 123 #define MAC_REG_IFREGCTL 0x70 124 #define MAC_REG_IFDATA 0x71 125 #define MAC_REG_ITRTMSET 0x74 126 #define MAC_REG_PAPEDELAY 0x77 127 #define MAC_REG_SOFTPWRCTL 0x78 128 #define MAC_REG_GPIOCTL0 0x7A 129 #define MAC_REG_GPIOCTL1 0x7B 130 131 /* MAC DMA Related Group */ 132 #define MAC_REG_TXDMACTL0 0x7C 133 #define MAC_REG_TXDMAPTR0 0x80 134 #define MAC_REG_AC0DMACTL 0x84 135 #define MAC_REG_AC0DMAPTR 0x88 136 #define MAC_REG_BCNDMACTL 0x8C 137 #define MAC_REG_BCNDMAPTR 0x90 138 #define MAC_REG_RXDMACTL0 0x94 139 #define MAC_REG_RXDMAPTR0 0x98 140 #define MAC_REG_RXDMACTL1 0x9C 141 #define MAC_REG_RXDMAPTR1 0xA0 142 #define MAC_REG_SYNCDMACTL 0xA4 143 #define MAC_REG_SYNCDMAPTR 0xA8 144 #define MAC_REG_ATIMDMACTL 0xAC 145 #define MAC_REG_ATIMDMAPTR 0xB0 146 147 /* MiscFF PIO related */ 148 #define MAC_REG_MISCFFNDEX 0xB4 149 #define MAC_REG_MISCFFCTL 0xB6 150 #define MAC_REG_MISCFFDATA 0xB8 151 152 /* Extend SW Timer */ 153 #define MAC_REG_TMDATA1 0xBC 154 155 /* WOW Related Group */ 156 #define MAC_REG_WAKEUPEN0 0xC0 157 #define MAC_REG_WAKEUPEN1 0xC1 158 #define MAC_REG_WAKEUPSR0 0xC2 159 #define MAC_REG_WAKEUPSR1 0xC3 160 #define MAC_REG_WAKE128_0 0xC4 161 #define MAC_REG_WAKE128_1 0xD4 162 #define MAC_REG_WAKE128_2 0xE4 163 #define MAC_REG_WAKE128_3 0xF4 164 165 /************** Page 1 ******************/ 166 #define MAC_REG_CRC_128_0 0x04 167 #define MAC_REG_CRC_128_1 0x06 168 #define MAC_REG_CRC_128_2 0x08 169 #define MAC_REG_CRC_128_3 0x0A 170 171 /* MAC Configuration Group */ 172 #define MAC_REG_PAR0 0x0C 173 #define MAC_REG_PAR4 0x10 174 #define MAC_REG_BSSID0 0x14 175 #define MAC_REG_BSSID4 0x18 176 #define MAC_REG_MAR0 0x1C 177 #define MAC_REG_MAR4 0x20 178 179 /* MAC RSPPKT INFO Group */ 180 #define MAC_REG_RSPINF_B_1 0x24 181 #define MAC_REG_RSPINF_B_2 0x28 182 #define MAC_REG_RSPINF_B_5 0x2C 183 #define MAC_REG_RSPINF_B_11 0x30 184 #define MAC_REG_RSPINF_A_6 0x34 185 #define MAC_REG_RSPINF_A_9 0x36 186 #define MAC_REG_RSPINF_A_12 0x38 187 #define MAC_REG_RSPINF_A_18 0x3A 188 #define MAC_REG_RSPINF_A_24 0x3C 189 #define MAC_REG_RSPINF_A_36 0x3E 190 #define MAC_REG_RSPINF_A_48 0x40 191 #define MAC_REG_RSPINF_A_54 0x42 192 #define MAC_REG_RSPINF_A_72 0x44 193 194 /* 802.11h relative */ 195 #define MAC_REG_QUIETINIT 0x60 196 #define MAC_REG_QUIETGAP 0x62 197 #define MAC_REG_QUIETDUR 0x64 198 #define MAC_REG_MSRCTL 0x66 199 #define MAC_REG_MSRBBSTS 0x67 200 #define MAC_REG_MSRSTART 0x68 201 #define MAC_REG_MSRDURATION 0x70 202 #define MAC_REG_CCAFRACTION 0x72 203 #define MAC_REG_PWRCCK 0x73 204 #define MAC_REG_PWROFDM 0x7C 205 206 /* Bits in the BCFG0 register */ 207 #define BCFG0_PERROFF 0x40 208 #define BCFG0_MRDMDIS 0x20 209 #define BCFG0_MRDLDIS 0x10 210 #define BCFG0_MWMEN 0x08 211 #define BCFG0_VSERREN 0x02 212 #define BCFG0_LATMEN 0x01 213 214 /* Bits in the BCFG1 register */ 215 #define BCFG1_CFUNOPT 0x80 216 #define BCFG1_CREQOPT 0x40 217 #define BCFG1_DMA8 0x10 218 #define BCFG1_ARBITOPT 0x08 219 #define BCFG1_PCIMEN 0x04 220 #define BCFG1_MIOEN 0x02 221 #define BCFG1_CISDLYEN 0x01 222 223 /* Bits in RAMBIST registers */ 224 #define BISTCMD_TSTPAT5 0x00 225 #define BISTCMD_TSTPATA 0x80 226 #define BISTCMD_TSTERR 0x20 227 #define BISTCMD_TSTPATF 0x18 228 #define BISTCMD_TSTPAT0 0x10 229 #define BISTCMD_TSTMODE 0x04 230 #define BISTCMD_TSTITTX 0x03 231 #define BISTCMD_TSTATRX 0x02 232 #define BISTCMD_TSTATTX 0x01 233 #define BISTCMD_TSTRX 0x00 234 #define BISTSR0_BISTGO 0x01 235 #define BISTSR1_TSTSR 0x01 236 #define BISTSR2_CMDPRTEN 0x02 237 #define BISTSR2_RAMTSTEN 0x01 238 239 /* Bits in the I2MCFG EEPROM register */ 240 #define I2MCFG_BOUNDCTL 0x80 241 #define I2MCFG_WAITCTL 0x20 242 #define I2MCFG_SCLOECTL 0x10 243 #define I2MCFG_WBUSYCTL 0x08 244 #define I2MCFG_NORETRY 0x04 245 #define I2MCFG_I2MLDSEQ 0x02 246 #define I2MCFG_I2CMFAST 0x01 247 248 /* Bits in the I2MCSR EEPROM register */ 249 #define I2MCSR_EEMW 0x80 250 #define I2MCSR_EEMR 0x40 251 #define I2MCSR_AUTOLD 0x08 252 #define I2MCSR_NACK 0x02 253 #define I2MCSR_DONE 0x01 254 255 /* Bits in the PMC1 register */ 256 #define SPS_RST 0x80 257 #define PCISTIKY 0x40 258 #define PME_OVR 0x02 259 260 /* Bits in the STICKYHW register */ 261 #define STICKHW_DS1_SHADOW 0x02 262 #define STICKHW_DS0_SHADOW 0x01 263 264 /* Bits in the TMCTL register */ 265 #define TMCTL_TSUSP 0x04 266 #define TMCTL_TMD 0x02 267 #define TMCTL_TE 0x01 268 269 /* Bits in the TFTCTL register */ 270 #define TFTCTL_HWUTSF 0x80 271 #define TFTCTL_TBTTSYNC 0x40 272 #define TFTCTL_HWUTSFEN 0x20 273 #define TFTCTL_TSFCNTRRD 0x10 274 #define TFTCTL_TBTTSYNCEN 0x08 275 #define TFTCTL_TSFSYNCEN 0x04 276 #define TFTCTL_TSFCNTRST 0x02 277 #define TFTCTL_TSFCNTREN 0x01 278 279 /* Bits in the EnhanceCFG register */ 280 #define EnCFG_BarkerPream 0x00020000 281 #define EnCFG_NXTBTTCFPSTR 0x00010000 282 #define EnCFG_BcnSusClr 0x00000200 283 #define EnCFG_BcnSusInd 0x00000100 284 #define EnCFG_CFP_ProtectEn 0x00000040 285 #define EnCFG_ProtectMd 0x00000020 286 #define EnCFG_HwParCFP 0x00000010 287 #define EnCFG_CFNULRSP 0x00000004 288 #define EnCFG_BBType_MASK 0x00000003 289 #define EnCFG_BBType_g 0x00000002 290 #define EnCFG_BBType_b 0x00000001 291 #define EnCFG_BBType_a 0x00000000 292 293 /* Bits in the Page1Sel register */ 294 #define PAGE1_SEL 0x01 295 296 /* Bits in the CFG register */ 297 #define CFG_TKIPOPT 0x80 298 #define CFG_RXDMAOPT 0x40 299 #define CFG_TMOT_SW 0x20 300 #define CFG_TMOT_HWLONG 0x10 301 #define CFG_TMOT_HW 0x00 302 #define CFG_CFPENDOPT 0x08 303 #define CFG_BCNSUSEN 0x04 304 #define CFG_NOTXTIMEOUT 0x02 305 #define CFG_NOBUFOPT 0x01 306 307 /* Bits in the TEST register */ 308 #define TEST_LBEXT 0x80 309 #define TEST_LBINT 0x40 310 #define TEST_LBNONE 0x00 311 #define TEST_SOFTINT 0x20 312 #define TEST_CONTTX 0x10 313 #define TEST_TXPE 0x08 314 #define TEST_NAVDIS 0x04 315 #define TEST_NOCTS 0x02 316 #define TEST_NOACK 0x01 317 318 /* Bits in the HOSTCR register */ 319 #define HOSTCR_TXONST 0x80 320 #define HOSTCR_RXONST 0x40 321 #define HOSTCR_ADHOC 0x20 /* Network Type 1 = Ad-hoc */ 322 #define HOSTCR_AP 0x10 /* Port Type 1 = AP */ 323 #define HOSTCR_TXON 0x08 /* 0000 1000 */ 324 #define HOSTCR_RXON 0x04 /* 0000 0100 */ 325 #define HOSTCR_MACEN 0x02 /* 0000 0010 */ 326 #define HOSTCR_SOFTRST 0x01 /* 0000 0001 */ 327 328 /* Bits in the MACCR register */ 329 #define MACCR_SYNCFLUSHOK 0x04 330 #define MACCR_SYNCFLUSH 0x02 331 #define MACCR_CLRNAV 0x01 332 333 /* Bits in the MAC_REG_GPIOCTL0 register */ 334 #define LED_ACTSET 0x01 335 #define LED_RFOFF 0x02 336 #define LED_NOCONNECT 0x04 337 338 /* Bits in the RCR register */ 339 #define RCR_SSID 0x80 340 #define RCR_RXALLTYPE 0x40 341 #define RCR_UNICAST 0x20 342 #define RCR_BROADCAST 0x10 343 #define RCR_MULTICAST 0x08 344 #define RCR_WPAERR 0x04 345 #define RCR_ERRCRC 0x02 346 #define RCR_BSSID 0x01 347 348 /* Bits in the TCR register */ 349 #define TCR_SYNCDCFOPT 0x02 350 #define TCR_AUTOBCNTX 0x01 /* Beacon automatically transmit enable */ 351 352 /* Bits in the IMR register */ 353 #define IMR_MEASURESTART 0x80000000 354 #define IMR_QUIETSTART 0x20000000 355 #define IMR_RADARDETECT 0x10000000 356 #define IMR_MEASUREEND 0x08000000 357 #define IMR_SOFTTIMER1 0x00200000 358 #define IMR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ 359 #define IMR_RXNOBUF 0x00000800 360 #define IMR_MIBNEARFULL 0x00000400 361 #define IMR_SOFTINT 0x00000200 362 #define IMR_FETALERR 0x00000100 363 #define IMR_WATCHDOG 0x00000080 364 #define IMR_SOFTTIMER 0x00000040 365 #define IMR_GPIO 0x00000020 366 #define IMR_TBTT 0x00000010 367 #define IMR_RXDMA0 0x00000008 368 #define IMR_BNTX 0x00000004 369 #define IMR_AC0DMA 0x00000002 370 #define IMR_TXDMA0 0x00000001 371 372 /* Bits in the ISR register */ 373 #define ISR_MEASURESTART 0x80000000 374 #define ISR_QUIETSTART 0x20000000 375 #define ISR_RADARDETECT 0x10000000 376 #define ISR_MEASUREEND 0x08000000 377 #define ISR_SOFTTIMER1 0x00200000 378 #define ISR_RXDMA1 0x00001000 /* 0000 0000 0001 0000 0000 0000 */ 379 #define ISR_RXNOBUF 0x00000800 /* 0000 0000 0000 1000 0000 0000 */ 380 #define ISR_MIBNEARFULL 0x00000400 /* 0000 0000 0000 0100 0000 0000 */ 381 #define ISR_SOFTINT 0x00000200 382 #define ISR_FETALERR 0x00000100 383 #define ISR_WATCHDOG 0x00000080 384 #define ISR_SOFTTIMER 0x00000040 385 #define ISR_GPIO 0x00000020 386 #define ISR_TBTT 0x00000010 387 #define ISR_RXDMA0 0x00000008 388 #define ISR_BNTX 0x00000004 389 #define ISR_AC0DMA 0x00000002 390 #define ISR_TXDMA0 0x00000001 391 392 /* Bits in the PSCFG register */ 393 #define PSCFG_PHILIPMD 0x40 394 #define PSCFG_WAKECALEN 0x20 395 #define PSCFG_WAKETMREN 0x10 396 #define PSCFG_BBPSPROG 0x08 397 #define PSCFG_WAKESYN 0x04 398 #define PSCFG_SLEEPSYN 0x02 399 #define PSCFG_AUTOSLEEP 0x01 400 401 /* Bits in the PSCTL register */ 402 #define PSCTL_WAKEDONE 0x20 403 #define PSCTL_PS 0x10 404 #define PSCTL_GO2DOZE 0x08 405 #define PSCTL_LNBCN 0x04 406 #define PSCTL_ALBCN 0x02 407 #define PSCTL_PSEN 0x01 408 409 /* Bits in the PSPWSIG register */ 410 #define PSSIG_WPE3 0x80 411 #define PSSIG_WPE2 0x40 412 #define PSSIG_WPE1 0x20 413 #define PSSIG_WRADIOPE 0x10 414 #define PSSIG_SPE3 0x08 415 #define PSSIG_SPE2 0x04 416 #define PSSIG_SPE1 0x02 417 #define PSSIG_SRADIOPE 0x01 418 419 /* Bits in the BBREGCTL register */ 420 #define BBREGCTL_DONE 0x04 421 #define BBREGCTL_REGR 0x02 422 #define BBREGCTL_REGW 0x01 423 424 /* Bits in the IFREGCTL register */ 425 #define IFREGCTL_DONE 0x04 426 #define IFREGCTL_IFRF 0x02 427 #define IFREGCTL_REGW 0x01 428 429 /* Bits in the SOFTPWRCTL register */ 430 #define SOFTPWRCTL_RFLEOPT 0x0800 431 #define SOFTPWRCTL_TXPEINV 0x0200 432 #define SOFTPWRCTL_SWPECTI 0x0100 433 #define SOFTPWRCTL_SWPAPE 0x0020 434 #define SOFTPWRCTL_SWCALEN 0x0010 435 #define SOFTPWRCTL_SWRADIO_PE 0x0008 436 #define SOFTPWRCTL_SWPE2 0x0004 437 #define SOFTPWRCTL_SWPE1 0x0002 438 #define SOFTPWRCTL_SWPE3 0x0001 439 440 /* Bits in the GPIOCTL1 register */ 441 #define GPIO1_DATA1 0x20 442 #define GPIO1_MD1 0x10 443 #define GPIO1_DATA0 0x02 444 #define GPIO1_MD0 0x01 445 446 /* Bits in the DMACTL register */ 447 #define DMACTL_CLRRUN 0x00080000 448 #define DMACTL_RUN 0x00000008 449 #define DMACTL_WAKE 0x00000004 450 #define DMACTL_DEAD 0x00000002 451 #define DMACTL_ACTIVE 0x00000001 452 453 /* Bits in the RXDMACTL0 register */ 454 #define RX_PERPKT 0x00000100 455 #define RX_PERPKTCLR 0x01000000 456 457 /* Bits in the BCNDMACTL register */ 458 #define BEACON_READY 0x01 459 460 /* Bits in the MISCFFCTL register */ 461 #define MISCFFCTL_WRITE 0x0001 462 463 /* Bits in WAKEUPEN0 */ 464 #define WAKEUPEN0_DIRPKT 0x10 465 #define WAKEUPEN0_LINKOFF 0x08 466 #define WAKEUPEN0_ATIMEN 0x04 467 #define WAKEUPEN0_TIMEN 0x02 468 #define WAKEUPEN0_MAGICEN 0x01 469 470 /* Bits in WAKEUPEN1 */ 471 #define WAKEUPEN1_128_3 0x08 472 #define WAKEUPEN1_128_2 0x04 473 #define WAKEUPEN1_128_1 0x02 474 #define WAKEUPEN1_128_0 0x01 475 476 /* Bits in WAKEUPSR0 */ 477 #define WAKEUPSR0_DIRPKT 0x10 478 #define WAKEUPSR0_LINKOFF 0x08 479 #define WAKEUPSR0_ATIMEN 0x04 480 #define WAKEUPSR0_TIMEN 0x02 481 #define WAKEUPSR0_MAGICEN 0x01 482 483 /* Bits in WAKEUPSR1 */ 484 #define WAKEUPSR1_128_3 0x08 485 #define WAKEUPSR1_128_2 0x04 486 #define WAKEUPSR1_128_1 0x02 487 #define WAKEUPSR1_128_0 0x01 488 489 /* Bits in the MAC_REG_GPIOCTL register */ 490 #define GPIO0_MD 0x01 491 #define GPIO0_DATA 0x02 492 #define GPIO0_INTMD 0x04 493 #define GPIO1_MD 0x10 494 #define GPIO1_DATA 0x20 495 496 /* Bits in the MSRCTL register */ 497 #define MSRCTL_FINISH 0x80 498 #define MSRCTL_READY 0x40 499 #define MSRCTL_RADARDETECT 0x20 500 #define MSRCTL_EN 0x10 501 #define MSRCTL_QUIETTXCHK 0x08 502 #define MSRCTL_QUIETRPT 0x04 503 #define MSRCTL_QUIETINT 0x02 504 #define MSRCTL_QUIETEN 0x01 505 506 /* Bits in the MSRCTL1 register */ 507 #define MSRCTL1_TXPWR 0x08 508 #define MSRCTL1_CSAPAREN 0x04 509 #define MSRCTL1_TXPAUSE 0x01 510 511 /* Loopback mode */ 512 #define MAC_LB_EXT 0x02 513 #define MAC_LB_INTERNAL 0x01 514 #define MAC_LB_NONE 0x00 515 516 #define Default_BI 0x200 517 518 /* MiscFIFO Offset */ 519 #define MISCFIFO_KEYETRY0 32 520 #define MISCFIFO_KEYENTRYSIZE 22 521 #define MISCFIFO_SYNINFO_IDX 10 522 #define MISCFIFO_SYNDATA_IDX 11 523 #define MISCFIFO_SYNDATASIZE 21 524 525 /* enabled mask value of irq */ 526 #define IMR_MASK_VALUE (IMR_SOFTTIMER1 | \ 527 IMR_RXDMA1 | \ 528 IMR_RXNOBUF | \ 529 IMR_MIBNEARFULL | \ 530 IMR_SOFTINT | \ 531 IMR_FETALERR | \ 532 IMR_WATCHDOG | \ 533 IMR_SOFTTIMER | \ 534 IMR_GPIO | \ 535 IMR_TBTT | \ 536 IMR_RXDMA0 | \ 537 IMR_BNTX | \ 538 IMR_AC0DMA | \ 539 IMR_TXDMA0) 540 541 /* max time out delay time */ 542 #define W_MAX_TIMEOUT 0xFFF0U 543 544 /* wait time within loop */ 545 #define CB_DELAY_LOOP_WAIT 10 /* 10ms */ 546 547 /* revision id */ 548 #define REV_ID_VT3253_A0 0x00 549 #define REV_ID_VT3253_A1 0x01 550 #define REV_ID_VT3253_B0 0x08 551 #define REV_ID_VT3253_B1 0x09 552 553 /*--------------------- Export Types ------------------------------*/ 554 555 /*--------------------- Export Macros ------------------------------*/ 556 557 #define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \ 558 do { \ 559 unsigned char byData; \ 560 VNSvInPortB(dwIoBase + byRegOfs, &byData); \ 561 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ 562 } while (0) 563 564 #define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \ 565 do { \ 566 unsigned short wData; \ 567 VNSvInPortW(dwIoBase + byRegOfs, &wData); \ 568 VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \ 569 } while (0) 570 571 #define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \ 572 do { \ 573 unsigned long dwData; \ 574 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ 575 VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \ 576 } while (0) 577 578 #define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \ 579 do { \ 580 unsigned char byData; \ 581 VNSvInPortB(dwIoBase + byRegOfs, &byData); \ 582 byData &= byMask; \ 583 VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \ 584 } while (0) 585 586 #define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \ 587 do { \ 588 unsigned char byData; \ 589 VNSvInPortB(dwIoBase + byRegOfs, &byData); \ 590 VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \ 591 } while (0) 592 593 #define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \ 594 do { \ 595 unsigned short wData; \ 596 VNSvInPortW(dwIoBase + byRegOfs, &wData); \ 597 VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \ 598 } while (0) 599 600 #define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \ 601 do { \ 602 unsigned long dwData; \ 603 VNSvInPortD(dwIoBase + byRegOfs, &dwData); \ 604 VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \ 605 } while (0) 606 607 #define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \ 608 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \ 609 (unsigned long *)pdwCurrDescAddr) 610 611 #define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \ 612 VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \ 613 (unsigned long *)pdwCurrDescAddr) 614 615 #define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \ 616 VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \ 617 (unsigned long *)pdwCurrDescAddr) 618 619 #define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \ 620 VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \ 621 (unsigned long *)pdwCurrDescAddr) 622 623 #define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \ 624 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \ 625 (unsigned long *)pdwCurrDescAddr) 626 627 #define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \ 628 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \ 629 (unsigned long *)pdwCurrDescAddr) 630 631 /* set the chip with current BCN tx descriptor address */ 632 #define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \ 633 VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \ 634 dwCurrDescAddr) 635 636 /* set the chip with current BCN length */ 637 #define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \ 638 VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \ 639 wCurrBCNLength) 640 641 #define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \ 642 do { \ 643 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ 644 VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \ 645 (unsigned char *)pbyEtherAddr); \ 646 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ 647 pbyEtherAddr + 1); \ 648 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ 649 pbyEtherAddr + 2); \ 650 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ 651 pbyEtherAddr + 3); \ 652 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ 653 pbyEtherAddr + 4); \ 654 VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ 655 pbyEtherAddr + 5); \ 656 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ 657 } while (0) 658 659 #define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \ 660 do { \ 661 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ 662 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \ 663 *(pbyEtherAddr)); \ 664 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \ 665 *(pbyEtherAddr + 1)); \ 666 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \ 667 *(pbyEtherAddr + 2)); \ 668 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \ 669 *(pbyEtherAddr + 3)); \ 670 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \ 671 *(pbyEtherAddr + 4)); \ 672 VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \ 673 *(pbyEtherAddr + 5)); \ 674 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ 675 } while (0) 676 677 #define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \ 678 do { \ 679 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ 680 VNSvInPortB(dwIoBase + MAC_REG_PAR0, \ 681 (unsigned char *)pbyEtherAddr); \ 682 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \ 683 pbyEtherAddr + 1); \ 684 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \ 685 pbyEtherAddr + 2); \ 686 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \ 687 pbyEtherAddr + 3); \ 688 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \ 689 pbyEtherAddr + 4); \ 690 VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \ 691 pbyEtherAddr + 5); \ 692 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ 693 } while (0) 694 695 #define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \ 696 do { \ 697 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ 698 VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \ 699 *pbyEtherAddr); \ 700 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \ 701 *(pbyEtherAddr + 1)); \ 702 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \ 703 *(pbyEtherAddr + 2)); \ 704 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \ 705 *(pbyEtherAddr + 3)); \ 706 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \ 707 *(pbyEtherAddr + 4)); \ 708 VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \ 709 *(pbyEtherAddr + 5)); \ 710 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ 711 } while (0) 712 713 #define MACvClearISR(dwIoBase) \ 714 VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE) 715 716 #define MACvStart(dwIoBase) \ 717 VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \ 718 (HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)) 719 720 #define MACvRx0PerPktMode(dwIoBase) \ 721 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT) 722 723 #define MACvRx0BufferFillMode(dwIoBase) \ 724 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR) 725 726 #define MACvRx1PerPktMode(dwIoBase) \ 727 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT) 728 729 #define MACvRx1BufferFillMode(dwIoBase) \ 730 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR) 731 732 #define MACvRxOn(dwIoBase) \ 733 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON) 734 735 #define MACvReceive0(dwIoBase) \ 736 do { \ 737 unsigned long dwData; \ 738 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \ 739 if (dwData & DMACTL_RUN) \ 740 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \ 741 else \ 742 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \ 743 } while (0) 744 745 #define MACvReceive1(dwIoBase) \ 746 do { \ 747 unsigned long dwData; \ 748 VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \ 749 if (dwData & DMACTL_RUN) \ 750 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \ 751 else \ 752 VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \ 753 } while (0) 754 755 #define MACvTxOn(dwIoBase) \ 756 MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON) 757 758 #define MACvTransmit0(dwIoBase) \ 759 do { \ 760 unsigned long dwData; \ 761 VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \ 762 if (dwData & DMACTL_RUN) \ 763 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \ 764 else \ 765 VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \ 766 } while (0) 767 768 #define MACvTransmitAC0(dwIoBase) \ 769 do { \ 770 unsigned long dwData; \ 771 VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \ 772 if (dwData & DMACTL_RUN) \ 773 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \ 774 else \ 775 VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \ 776 } while (0) 777 778 #define MACvTransmitSYNC(dwIoBase) \ 779 do { \ 780 unsigned long dwData; \ 781 VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \ 782 if (dwData & DMACTL_RUN) \ 783 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \ 784 else \ 785 VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \ 786 } while (0) 787 788 #define MACvTransmitATIM(dwIoBase) \ 789 do { \ 790 unsigned long dwData; \ 791 VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \ 792 if (dwData & DMACTL_RUN) \ 793 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \ 794 else \ 795 VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \ 796 } while (0) 797 798 #define MACvTransmitBCN(dwIoBase) \ 799 VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY) 800 801 #define MACvClearStckDS(dwIoBase) \ 802 do { \ 803 unsigned char byOrgValue; \ 804 VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \ 805 byOrgValue = byOrgValue & 0xFC; \ 806 VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \ 807 } while (0) 808 809 #define MACvReadISR(dwIoBase, pdwValue) \ 810 VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue) 811 812 #define MACvWriteISR(dwIoBase, dwValue) \ 813 VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue) 814 815 #define MACvIntEnable(dwIoBase, dwMask) \ 816 VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask) 817 818 #define MACvIntDisable(dwIoBase) \ 819 VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0) 820 821 #define MACvSelectPage0(dwIoBase) \ 822 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0) 823 824 #define MACvSelectPage1(dwIoBase) \ 825 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1) 826 827 #define MACvReadMIBCounter(dwIoBase, pdwCounter) \ 828 VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR, pdwCounter) 829 830 #define MACvPwrEvntDisable(dwIoBase) \ 831 VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000) 832 833 #define MACvEnableProtectMD(dwIoBase) \ 834 do { \ 835 unsigned long dwOrgValue; \ 836 VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ 837 dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \ 838 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ 839 } while (0) 840 841 #define MACvDisableProtectMD(dwIoBase) \ 842 do { \ 843 unsigned long dwOrgValue; \ 844 VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ 845 dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \ 846 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ 847 } while (0) 848 849 #define MACvEnableBarkerPreambleMd(dwIoBase) \ 850 do { \ 851 unsigned long dwOrgValue; \ 852 VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ 853 dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \ 854 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ 855 } while (0) 856 857 #define MACvDisableBarkerPreambleMd(dwIoBase) \ 858 do { \ 859 unsigned long dwOrgValue; \ 860 VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ 861 dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \ 862 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ 863 } while (0) 864 865 #define MACvSetBBType(dwIoBase, byTyp) \ 866 do { \ 867 unsigned long dwOrgValue; \ 868 VNSvInPortD(dwIoBase + MAC_REG_ENCFG, &dwOrgValue); \ 869 dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \ 870 dwOrgValue = dwOrgValue | (unsigned long)byTyp; \ 871 VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \ 872 } while (0) 873 874 #define MACvReadATIMW(dwIoBase, pwCounter) \ 875 VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter) 876 877 #define MACvWriteATIMW(dwIoBase, wCounter) \ 878 VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter) 879 880 #define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \ 881 do { \ 882 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \ 883 VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \ 884 VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \ 885 } while (0) 886 887 #define MACvGPIOIn(dwIoBase, pbyValue) \ 888 VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue) 889 890 #define MACvSetRFLE_LatchBase(dwIoBase) \ 891 MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT) 892 893 bool MACbIsRegBitsOn(void __iomem *dwIoBase, unsigned char byRegOfs, 894 unsigned char byTestBits); 895 bool MACbIsRegBitsOff(void __iomem *dwIoBase, unsigned char byRegOfs, 896 unsigned char byTestBits); 897 898 bool MACbIsIntDisable(void __iomem *dwIoBase); 899 900 void MACvSetShortRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit); 901 902 void MACvSetLongRetryLimit(void __iomem *dwIoBase, unsigned char byRetryLimit); 903 void MACvGetLongRetryLimit(void __iomem *dwIoBase, 904 unsigned char *pbyRetryLimit); 905 906 void MACvSetLoopbackMode(void __iomem *dwIoBase, unsigned char byLoopbackMode); 907 908 void MACvSaveContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf); 909 void MACvRestoreContext(void __iomem *dwIoBase, unsigned char *pbyCxtBuf); 910 911 bool MACbSoftwareReset(void __iomem *dwIoBase); 912 bool MACbSafeSoftwareReset(void __iomem *dwIoBase); 913 bool MACbSafeRxOff(void __iomem *dwIoBase); 914 bool MACbSafeTxOff(void __iomem *dwIoBase); 915 bool MACbSafeStop(void __iomem *dwIoBase); 916 bool MACbShutdown(void __iomem *dwIoBase); 917 void MACvInitialize(void __iomem *dwIoBase); 918 void MACvSetCurrRx0DescAddr(void __iomem *dwIoBase, 919 unsigned long dwCurrDescAddr); 920 void MACvSetCurrRx1DescAddr(void __iomem *dwIoBase, 921 unsigned long dwCurrDescAddr); 922 void MACvSetCurrTXDescAddr(int iTxType, void __iomem *dwIoBase, 923 unsigned long dwCurrDescAddr); 924 void MACvSetCurrTx0DescAddrEx(void __iomem *dwIoBase, 925 unsigned long dwCurrDescAddr); 926 void MACvSetCurrAC0DescAddrEx(void __iomem *dwIoBase, 927 unsigned long dwCurrDescAddr); 928 void MACvSetCurrSyncDescAddrEx(void __iomem *dwIoBase, 929 unsigned long dwCurrDescAddr); 930 void MACvSetCurrATIMDescAddrEx(void __iomem *dwIoBase, 931 unsigned long dwCurrDescAddr); 932 void MACvTimer0MicroSDelay(void __iomem *dwIoBase, unsigned int uDelay); 933 void MACvOneShotTimer1MicroSec(void __iomem *dwIoBase, unsigned int uDelayTime); 934 935 void MACvSetMISCFifo(void __iomem *dwIoBase, unsigned short wOffset, 936 unsigned long dwData); 937 938 bool MACbPSWakeup(void __iomem *dwIoBase); 939 940 void MACvSetKeyEntry(void __iomem *dwIoBase, unsigned short wKeyCtl, 941 unsigned int uEntryIdx, unsigned int uKeyIdx, 942 unsigned char *pbyAddr, u32 *pdwKey, 943 unsigned char byLocalID); 944 void MACvDisableKeyEntry(void __iomem *dwIoBase, unsigned int uEntryIdx); 945 946 #endif /* __MAC_H__ */ 947