1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * File: mac.c 7 * 8 * Purpose: MAC routines 9 * 10 * Author: Tevin Chen 11 * 12 * Date: May 21, 1996 13 * 14 * Functions: 15 * MACbIsRegBitsOn - Test if All test Bits On 16 * MACbIsRegBitsOff - Test if All test Bits Off 17 * MACbIsIntDisable - Test if MAC interrupt disable 18 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit 19 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit 20 * MACvSetLoopbackMode - Set MAC Loopback Mode 21 * MACvSaveContext - Save Context of MAC Registers 22 * MACvRestoreContext - Restore Context of MAC Registers 23 * MACbSoftwareReset - Software Reset MAC 24 * MACbSafeRxOff - Turn Off MAC Rx 25 * MACbSafeTxOff - Turn Off MAC Tx 26 * MACbSafeStop - Stop MAC function 27 * MACbShutdown - Shut down MAC 28 * MACvInitialize - Initialize MAC 29 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address 30 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address 31 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address 32 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC 33 * 34 * Revision History: 35 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53 36 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()& 37 * MACvEnableBusSusEn() 38 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry 39 * 40 */ 41 42 #include "tmacro.h" 43 #include "mac.h" 44 45 /* 46 * Description: 47 * Test if all test bits on 48 * 49 * Parameters: 50 * In: 51 * io_base - Base Address for MAC 52 * byRegOfs - Offset of MAC Register 53 * byTestBits - Test bits 54 * Out: 55 * none 56 * 57 * Return Value: true if all test bits On; otherwise false 58 * 59 */ 60 bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs, 61 unsigned char byTestBits) 62 { 63 void __iomem *io_base = priv->PortOffset; 64 65 return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits; 66 } 67 68 /* 69 * Description: 70 * Test if all test bits off 71 * 72 * Parameters: 73 * In: 74 * io_base - Base Address for MAC 75 * byRegOfs - Offset of MAC Register 76 * byTestBits - Test bits 77 * Out: 78 * none 79 * 80 * Return Value: true if all test bits Off; otherwise false 81 * 82 */ 83 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs, 84 unsigned char byTestBits) 85 { 86 void __iomem *io_base = priv->PortOffset; 87 88 return !(ioread8(io_base + byRegOfs) & byTestBits); 89 } 90 91 /* 92 * Description: 93 * Test if MAC interrupt disable 94 * 95 * Parameters: 96 * In: 97 * io_base - Base Address for MAC 98 * Out: 99 * none 100 * 101 * Return Value: true if interrupt is disable; otherwise false 102 * 103 */ 104 bool MACbIsIntDisable(struct vnt_private *priv) 105 { 106 void __iomem *io_base = priv->PortOffset; 107 108 if (ioread32(io_base + MAC_REG_IMR)) 109 return false; 110 111 return true; 112 } 113 114 /* 115 * Description: 116 * Set 802.11 Short Retry Limit 117 * 118 * Parameters: 119 * In: 120 * io_base - Base Address for MAC 121 * byRetryLimit- Retry Limit 122 * Out: 123 * none 124 * 125 * Return Value: none 126 * 127 */ 128 void MACvSetShortRetryLimit(struct vnt_private *priv, 129 unsigned char byRetryLimit) 130 { 131 void __iomem *io_base = priv->PortOffset; 132 /* set SRT */ 133 iowrite8(byRetryLimit, io_base + MAC_REG_SRT); 134 } 135 136 /* 137 * Description: 138 * Set 802.11 Long Retry Limit 139 * 140 * Parameters: 141 * In: 142 * io_base - Base Address for MAC 143 * byRetryLimit- Retry Limit 144 * Out: 145 * none 146 * 147 * Return Value: none 148 * 149 */ 150 void MACvSetLongRetryLimit(struct vnt_private *priv, 151 unsigned char byRetryLimit) 152 { 153 void __iomem *io_base = priv->PortOffset; 154 /* set LRT */ 155 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); 156 } 157 158 /* 159 * Description: 160 * Set MAC Loopback mode 161 * 162 * Parameters: 163 * In: 164 * io_base - Base Address for MAC 165 * byLoopbackMode - Loopback Mode 166 * Out: 167 * none 168 * 169 * Return Value: none 170 * 171 */ 172 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode) 173 { 174 void __iomem *io_base = priv->PortOffset; 175 176 byLoopbackMode <<= 6; 177 /* set TCR */ 178 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode, 179 io_base + MAC_REG_TEST); 180 } 181 182 /* 183 * Description: 184 * Save MAC registers to context buffer 185 * 186 * Parameters: 187 * In: 188 * io_base - Base Address for MAC 189 * Out: 190 * cxt_buf - Context buffer 191 * 192 * Return Value: none 193 * 194 */ 195 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf) 196 { 197 void __iomem *io_base = priv->PortOffset; 198 199 /* read page0 register */ 200 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0); 201 202 MACvSelectPage1(io_base); 203 204 /* read page1 register */ 205 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base, 206 MAC_MAX_CONTEXT_SIZE_PAGE1); 207 208 MACvSelectPage0(io_base); 209 } 210 211 /* 212 * Description: 213 * Restore MAC registers from context buffer 214 * 215 * Parameters: 216 * In: 217 * io_base - Base Address for MAC 218 * cxt_buf - Context buffer 219 * Out: 220 * none 221 * 222 * Return Value: none 223 * 224 */ 225 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf) 226 { 227 void __iomem *io_base = priv->PortOffset; 228 229 MACvSelectPage1(io_base); 230 /* restore page1 */ 231 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, 232 MAC_MAX_CONTEXT_SIZE_PAGE1); 233 234 MACvSelectPage0(io_base); 235 236 /* restore RCR,TCR,IMR... */ 237 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR, 238 MAC_REG_ISR - MAC_REG_RCR); 239 240 /* restore MAC Config. */ 241 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT, 242 MAC_REG_PAGE1SEL - MAC_REG_LRT); 243 244 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG); 245 246 /* restore PS Config. */ 247 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG, 248 MAC_REG_BBREGCTL - MAC_REG_PSCFG); 249 250 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */ 251 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0), 252 io_base + MAC_REG_TXDMAPTR0); 253 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR), 254 io_base + MAC_REG_AC0DMAPTR); 255 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR), 256 io_base + MAC_REG_BCNDMAPTR); 257 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0), 258 io_base + MAC_REG_RXDMAPTR0); 259 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1), 260 io_base + MAC_REG_RXDMAPTR1); 261 } 262 263 /* 264 * Description: 265 * Software Reset MAC 266 * 267 * Parameters: 268 * In: 269 * io_base - Base Address for MAC 270 * Out: 271 * none 272 * 273 * Return Value: true if Reset Success; otherwise false 274 * 275 */ 276 bool MACbSoftwareReset(struct vnt_private *priv) 277 { 278 void __iomem *io_base = priv->PortOffset; 279 unsigned short ww; 280 281 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */ 282 iowrite8(0x01, io_base + MAC_REG_HOSTCR); 283 284 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 285 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST)) 286 break; 287 } 288 if (ww == W_MAX_TIMEOUT) 289 return false; 290 return true; 291 } 292 293 /* 294 * Description: 295 * save some important register's value, then do reset, then restore 296 * register's value 297 * 298 * Parameters: 299 * In: 300 * io_base - Base Address for MAC 301 * Out: 302 * none 303 * 304 * Return Value: true if success; otherwise false 305 * 306 */ 307 bool MACbSafeSoftwareReset(struct vnt_private *priv) 308 { 309 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1]; 310 bool bRetVal; 311 312 /* PATCH.... 313 * save some important register's value, then do 314 * reset, then restore register's value 315 */ 316 /* save MAC context */ 317 MACvSaveContext(priv, abyTmpRegData); 318 /* do reset */ 319 bRetVal = MACbSoftwareReset(priv); 320 /* restore MAC context, except CR0 */ 321 MACvRestoreContext(priv, abyTmpRegData); 322 323 return bRetVal; 324 } 325 326 /* 327 * Description: 328 * Turn Off MAC Rx 329 * 330 * Parameters: 331 * In: 332 * io_base - Base Address for MAC 333 * Out: 334 * none 335 * 336 * Return Value: true if success; otherwise false 337 * 338 */ 339 bool MACbSafeRxOff(struct vnt_private *priv) 340 { 341 void __iomem *io_base = priv->PortOffset; 342 unsigned short ww; 343 344 /* turn off wow temp for turn off Rx safely */ 345 346 /* Clear RX DMA0,1 */ 347 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0); 348 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1); 349 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 350 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) 351 break; 352 } 353 if (ww == W_MAX_TIMEOUT) { 354 pr_debug(" DBG_PORT80(0x10)\n"); 355 return false; 356 } 357 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 358 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) 359 break; 360 } 361 if (ww == W_MAX_TIMEOUT) { 362 pr_debug(" DBG_PORT80(0x11)\n"); 363 return false; 364 } 365 366 /* try to safe shutdown RX */ 367 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON); 368 /* W_MAX_TIMEOUT is the timeout period */ 369 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 370 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST)) 371 break; 372 } 373 if (ww == W_MAX_TIMEOUT) { 374 pr_debug(" DBG_PORT80(0x12)\n"); 375 return false; 376 } 377 return true; 378 } 379 380 /* 381 * Description: 382 * Turn Off MAC Tx 383 * 384 * Parameters: 385 * In: 386 * io_base - Base Address for MAC 387 * Out: 388 * none 389 * 390 * Return Value: true if success; otherwise false 391 * 392 */ 393 bool MACbSafeTxOff(struct vnt_private *priv) 394 { 395 void __iomem *io_base = priv->PortOffset; 396 unsigned short ww; 397 398 /* Clear TX DMA */ 399 /* Tx0 */ 400 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0); 401 /* AC0 */ 402 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL); 403 404 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 405 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) 406 break; 407 } 408 if (ww == W_MAX_TIMEOUT) { 409 pr_debug(" DBG_PORT80(0x20)\n"); 410 return false; 411 } 412 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 413 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) 414 break; 415 } 416 if (ww == W_MAX_TIMEOUT) { 417 pr_debug(" DBG_PORT80(0x21)\n"); 418 return false; 419 } 420 421 /* try to safe shutdown TX */ 422 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON); 423 424 /* W_MAX_TIMEOUT is the timeout period */ 425 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 426 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST)) 427 break; 428 } 429 if (ww == W_MAX_TIMEOUT) { 430 pr_debug(" DBG_PORT80(0x24)\n"); 431 return false; 432 } 433 return true; 434 } 435 436 /* 437 * Description: 438 * Stop MAC function 439 * 440 * Parameters: 441 * In: 442 * io_base - Base Address for MAC 443 * Out: 444 * none 445 * 446 * Return Value: true if success; otherwise false 447 * 448 */ 449 bool MACbSafeStop(struct vnt_private *priv) 450 { 451 void __iomem *io_base = priv->PortOffset; 452 453 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX); 454 455 if (!MACbSafeRxOff(priv)) { 456 pr_debug(" MACbSafeRxOff == false)\n"); 457 MACbSafeSoftwareReset(priv); 458 return false; 459 } 460 if (!MACbSafeTxOff(priv)) { 461 pr_debug(" MACbSafeTxOff == false)\n"); 462 MACbSafeSoftwareReset(priv); 463 return false; 464 } 465 466 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN); 467 468 return true; 469 } 470 471 /* 472 * Description: 473 * Shut Down MAC 474 * 475 * Parameters: 476 * In: 477 * io_base - Base Address for MAC 478 * Out: 479 * none 480 * 481 * Return Value: true if success; otherwise false 482 * 483 */ 484 bool MACbShutdown(struct vnt_private *priv) 485 { 486 void __iomem *io_base = priv->PortOffset; 487 /* disable MAC IMR */ 488 MACvIntDisable(io_base); 489 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL); 490 /* stop the adapter */ 491 if (!MACbSafeStop(priv)) { 492 MACvSetLoopbackMode(priv, MAC_LB_NONE); 493 return false; 494 } 495 MACvSetLoopbackMode(priv, MAC_LB_NONE); 496 return true; 497 } 498 499 /* 500 * Description: 501 * Initialize MAC 502 * 503 * Parameters: 504 * In: 505 * io_base - Base Address for MAC 506 * Out: 507 * none 508 * 509 * Return Value: none 510 * 511 */ 512 void MACvInitialize(struct vnt_private *priv) 513 { 514 void __iomem *io_base = priv->PortOffset; 515 /* clear sticky bits */ 516 MACvClearStckDS(io_base); 517 /* disable force PME-enable */ 518 iowrite8(PME_OVR, io_base + MAC_REG_PMC1); 519 /* only 3253 A */ 520 521 /* do reset */ 522 MACbSoftwareReset(priv); 523 524 /* reset TSF counter */ 525 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL); 526 /* enable TSF counter */ 527 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL); 528 } 529 530 /* 531 * Description: 532 * Set the chip with current rx descriptor address 533 * 534 * Parameters: 535 * In: 536 * io_base - Base Address for MAC 537 * curr_desc_addr - Descriptor Address 538 * Out: 539 * none 540 * 541 * Return Value: none 542 * 543 */ 544 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr) 545 { 546 void __iomem *io_base = priv->PortOffset; 547 unsigned short ww; 548 unsigned char org_dma_ctl; 549 550 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0); 551 if (org_dma_ctl & DMACTL_RUN) 552 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2); 553 554 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 555 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) 556 break; 557 } 558 559 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0); 560 if (org_dma_ctl & DMACTL_RUN) 561 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0); 562 } 563 564 /* 565 * Description: 566 * Set the chip with current rx descriptor address 567 * 568 * Parameters: 569 * In: 570 * io_base - Base Address for MAC 571 * curr_desc_addr - Descriptor Address 572 * Out: 573 * none 574 * 575 * Return Value: none 576 * 577 */ 578 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr) 579 { 580 void __iomem *io_base = priv->PortOffset; 581 unsigned short ww; 582 unsigned char org_dma_ctl; 583 584 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1); 585 if (org_dma_ctl & DMACTL_RUN) 586 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2); 587 588 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 589 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) 590 break; 591 } 592 593 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1); 594 if (org_dma_ctl & DMACTL_RUN) 595 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1); 596 597 } 598 599 /* 600 * Description: 601 * Set the chip with current tx0 descriptor address 602 * 603 * Parameters: 604 * In: 605 * io_base - Base Address for MAC 606 * curr_desc_addr - Descriptor Address 607 * Out: 608 * none 609 * 610 * Return Value: none 611 * 612 */ 613 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv, 614 u32 curr_desc_addr) 615 { 616 void __iomem *io_base = priv->PortOffset; 617 unsigned short ww; 618 unsigned char org_dma_ctl; 619 620 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0); 621 if (org_dma_ctl & DMACTL_RUN) 622 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2); 623 624 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 625 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) 626 break; 627 } 628 629 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0); 630 if (org_dma_ctl & DMACTL_RUN) 631 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0); 632 } 633 634 /* 635 * Description: 636 * Set the chip with current AC0 descriptor address 637 * 638 * Parameters: 639 * In: 640 * io_base - Base Address for MAC 641 * curr_desc_addr - Descriptor Address 642 * Out: 643 * none 644 * 645 * Return Value: none 646 * 647 */ 648 /* TxDMA1 = AC0DMA */ 649 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv, 650 u32 curr_desc_addr) 651 { 652 void __iomem *io_base = priv->PortOffset; 653 unsigned short ww; 654 unsigned char org_dma_ctl; 655 656 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL); 657 if (org_dma_ctl & DMACTL_RUN) 658 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2); 659 660 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 661 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) 662 break; 663 } 664 if (ww == W_MAX_TIMEOUT) 665 pr_debug(" DBG_PORT80(0x26)\n"); 666 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR); 667 if (org_dma_ctl & DMACTL_RUN) 668 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL); 669 } 670 671 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv, 672 u32 curr_desc_addr) 673 { 674 if (iTxType == TYPE_AC0DMA) 675 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr); 676 else if (iTxType == TYPE_TXDMA0) 677 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr); 678 } 679 680 /* 681 * Description: 682 * Micro Second Delay via MAC 683 * 684 * Parameters: 685 * In: 686 * io_base - Base Address for MAC 687 * uDelay - Delay time (timer resolution is 4 us) 688 * Out: 689 * none 690 * 691 * Return Value: none 692 * 693 */ 694 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay) 695 { 696 void __iomem *io_base = priv->PortOffset; 697 unsigned char byValue; 698 unsigned int uu, ii; 699 700 iowrite8(0, io_base + MAC_REG_TMCTL0); 701 iowrite32(uDelay, io_base + MAC_REG_TMDATA0); 702 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0); 703 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */ 704 for (uu = 0; uu < uDelay; uu++) { 705 byValue = ioread8(io_base + MAC_REG_TMCTL0); 706 if ((byValue == 0) || 707 (byValue & TMCTL_TSUSP)) { 708 iowrite8(0, io_base + MAC_REG_TMCTL0); 709 return; 710 } 711 } 712 } 713 iowrite8(0, io_base + MAC_REG_TMCTL0); 714 } 715 716 /* 717 * Description: 718 * Micro Second One shot timer via MAC 719 * 720 * Parameters: 721 * In: 722 * io_base - Base Address for MAC 723 * uDelay - Delay time 724 * Out: 725 * none 726 * 727 * Return Value: none 728 * 729 */ 730 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, 731 unsigned int uDelayTime) 732 { 733 void __iomem *io_base = priv->PortOffset; 734 735 iowrite8(0, io_base + MAC_REG_TMCTL1); 736 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1); 737 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1); 738 } 739 740 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset, 741 u32 data) 742 { 743 void __iomem *io_base = priv->PortOffset; 744 745 if (offset > 273) 746 return; 747 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 748 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 749 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 750 } 751 752 bool MACbPSWakeup(struct vnt_private *priv) 753 { 754 void __iomem *io_base = priv->PortOffset; 755 unsigned int ww; 756 /* Read PSCTL */ 757 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS)) 758 return true; 759 760 /* Disable PS */ 761 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN); 762 763 /* Check if SyncFlushOK */ 764 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 765 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE) 766 break; 767 } 768 if (ww == W_MAX_TIMEOUT) { 769 pr_debug(" DBG_PORT80(0x33)\n"); 770 return false; 771 } 772 return true; 773 } 774 775 /* 776 * Description: 777 * Set the Key by MISCFIFO 778 * 779 * Parameters: 780 * In: 781 * io_base - Base Address for MAC 782 * 783 * Out: 784 * none 785 * 786 * Return Value: none 787 * 788 */ 789 790 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, 791 unsigned int uEntryIdx, unsigned int uKeyIdx, 792 unsigned char *pbyAddr, u32 *pdwKey, 793 unsigned char byLocalID) 794 { 795 void __iomem *io_base = priv->PortOffset; 796 unsigned short offset; 797 u32 data; 798 int ii; 799 800 if (byLocalID <= 1) 801 return; 802 803 pr_debug("%s\n", __func__); 804 offset = MISCFIFO_KEYETRY0; 805 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); 806 807 data = 0; 808 data |= wKeyCtl; 809 data <<= 16; 810 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5)); 811 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n", 812 offset, data, wKeyCtl); 813 814 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 815 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 816 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 817 offset++; 818 819 data = 0; 820 data |= *(pbyAddr + 3); 821 data <<= 8; 822 data |= *(pbyAddr + 2); 823 data <<= 8; 824 data |= *(pbyAddr + 1); 825 data <<= 8; 826 data |= *pbyAddr; 827 pr_debug("2. offset: %d, Data: %X\n", offset, data); 828 829 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 830 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 831 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 832 offset++; 833 834 offset += (uKeyIdx * 4); 835 for (ii = 0; ii < 4; ii++) { 836 /* always push 128 bits */ 837 pr_debug("3.(%d) offset: %d, Data: %X\n", 838 ii, offset + ii, *pdwKey); 839 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX); 840 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA); 841 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 842 } 843 } 844 845 /* 846 * Description: 847 * Disable the Key Entry by MISCFIFO 848 * 849 * Parameters: 850 * In: 851 * io_base - Base Address for MAC 852 * 853 * Out: 854 * none 855 * 856 * Return Value: none 857 * 858 */ 859 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx) 860 { 861 void __iomem *io_base = priv->PortOffset; 862 unsigned short offset; 863 864 offset = MISCFIFO_KEYETRY0; 865 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); 866 867 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 868 iowrite32(0, io_base + MAC_REG_MISCFFDATA); 869 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 870 } 871