1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * Purpose: MAC routines 7 * 8 * Author: Tevin Chen 9 * 10 * Date: May 21, 1996 11 * 12 * Functions: 13 * MACbIsRegBitsOff - Test if All test Bits Off 14 * MACbIsIntDisable - Test if MAC interrupt disable 15 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit 16 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit 17 * MACvSetLoopbackMode - Set MAC Loopback Mode 18 * MACvSaveContext - Save Context of MAC Registers 19 * MACvRestoreContext - Restore Context of MAC Registers 20 * MACbSoftwareReset - Software Reset MAC 21 * MACbSafeRxOff - Turn Off MAC Rx 22 * MACbSafeTxOff - Turn Off MAC Tx 23 * MACbSafeStop - Stop MAC function 24 * MACbShutdown - Shut down MAC 25 * MACvInitialize - Initialize MAC 26 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address 27 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address 28 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address 29 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC 30 * 31 * Revision History: 32 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53 33 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()& 34 * MACvEnableBusSusEn() 35 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry 36 * 37 */ 38 39 #include "tmacro.h" 40 #include "mac.h" 41 42 /* 43 * Description: 44 * Test if all test bits off 45 * 46 * Parameters: 47 * In: 48 * io_base - Base Address for MAC 49 * byRegOfs - Offset of MAC Register 50 * byTestBits - Test bits 51 * Out: 52 * none 53 * 54 * Return Value: true if all test bits Off; otherwise false 55 * 56 */ 57 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs, 58 unsigned char byTestBits) 59 { 60 void __iomem *io_base = priv->port_offset; 61 62 return !(ioread8(io_base + byRegOfs) & byTestBits); 63 } 64 65 /* 66 * Description: 67 * Test if MAC interrupt disable 68 * 69 * Parameters: 70 * In: 71 * io_base - Base Address for MAC 72 * Out: 73 * none 74 * 75 * Return Value: true if interrupt is disable; otherwise false 76 * 77 */ 78 bool MACbIsIntDisable(struct vnt_private *priv) 79 { 80 void __iomem *io_base = priv->port_offset; 81 82 if (ioread32(io_base + MAC_REG_IMR)) 83 return false; 84 85 return true; 86 } 87 88 /* 89 * Description: 90 * Set 802.11 Short Retry Limit 91 * 92 * Parameters: 93 * In: 94 * io_base - Base Address for MAC 95 * byRetryLimit- Retry Limit 96 * Out: 97 * none 98 * 99 * Return Value: none 100 * 101 */ 102 void MACvSetShortRetryLimit(struct vnt_private *priv, 103 unsigned char byRetryLimit) 104 { 105 void __iomem *io_base = priv->port_offset; 106 /* set SRT */ 107 iowrite8(byRetryLimit, io_base + MAC_REG_SRT); 108 } 109 110 /* 111 * Description: 112 * Set 802.11 Long Retry Limit 113 * 114 * Parameters: 115 * In: 116 * io_base - Base Address for MAC 117 * byRetryLimit- Retry Limit 118 * Out: 119 * none 120 * 121 * Return Value: none 122 * 123 */ 124 void MACvSetLongRetryLimit(struct vnt_private *priv, 125 unsigned char byRetryLimit) 126 { 127 void __iomem *io_base = priv->port_offset; 128 /* set LRT */ 129 iowrite8(byRetryLimit, io_base + MAC_REG_LRT); 130 } 131 132 /* 133 * Description: 134 * Set MAC Loopback mode 135 * 136 * Parameters: 137 * In: 138 * io_base - Base Address for MAC 139 * byLoopbackMode - Loopback Mode 140 * Out: 141 * none 142 * 143 * Return Value: none 144 * 145 */ 146 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode) 147 { 148 void __iomem *io_base = priv->port_offset; 149 150 byLoopbackMode <<= 6; 151 /* set TCR */ 152 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode, 153 io_base + MAC_REG_TEST); 154 } 155 156 /* 157 * Description: 158 * Save MAC registers to context buffer 159 * 160 * Parameters: 161 * In: 162 * io_base - Base Address for MAC 163 * Out: 164 * cxt_buf - Context buffer 165 * 166 * Return Value: none 167 * 168 */ 169 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf) 170 { 171 void __iomem *io_base = priv->port_offset; 172 173 /* read page0 register */ 174 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0); 175 176 MACvSelectPage1(io_base); 177 178 /* read page1 register */ 179 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base, 180 MAC_MAX_CONTEXT_SIZE_PAGE1); 181 182 MACvSelectPage0(io_base); 183 } 184 185 /* 186 * Description: 187 * Restore MAC registers from context buffer 188 * 189 * Parameters: 190 * In: 191 * io_base - Base Address for MAC 192 * cxt_buf - Context buffer 193 * Out: 194 * none 195 * 196 * Return Value: none 197 * 198 */ 199 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf) 200 { 201 void __iomem *io_base = priv->port_offset; 202 203 MACvSelectPage1(io_base); 204 /* restore page1 */ 205 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, 206 MAC_MAX_CONTEXT_SIZE_PAGE1); 207 208 MACvSelectPage0(io_base); 209 210 /* restore RCR,TCR,IMR... */ 211 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR, 212 MAC_REG_ISR - MAC_REG_RCR); 213 214 /* restore MAC Config. */ 215 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT, 216 MAC_REG_PAGE1SEL - MAC_REG_LRT); 217 218 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG); 219 220 /* restore PS Config. */ 221 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG, 222 MAC_REG_BBREGCTL - MAC_REG_PSCFG); 223 224 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */ 225 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0), 226 io_base + MAC_REG_TXDMAPTR0); 227 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR), 228 io_base + MAC_REG_AC0DMAPTR); 229 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR), 230 io_base + MAC_REG_BCNDMAPTR); 231 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0), 232 io_base + MAC_REG_RXDMAPTR0); 233 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1), 234 io_base + MAC_REG_RXDMAPTR1); 235 } 236 237 /* 238 * Description: 239 * Software Reset MAC 240 * 241 * Parameters: 242 * In: 243 * io_base - Base Address for MAC 244 * Out: 245 * none 246 * 247 * Return Value: true if Reset Success; otherwise false 248 * 249 */ 250 bool MACbSoftwareReset(struct vnt_private *priv) 251 { 252 void __iomem *io_base = priv->port_offset; 253 unsigned short ww; 254 255 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */ 256 iowrite8(0x01, io_base + MAC_REG_HOSTCR); 257 258 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 259 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST)) 260 break; 261 } 262 if (ww == W_MAX_TIMEOUT) 263 return false; 264 return true; 265 } 266 267 /* 268 * Description: 269 * save some important register's value, then do reset, then restore 270 * register's value 271 * 272 * Parameters: 273 * In: 274 * io_base - Base Address for MAC 275 * Out: 276 * none 277 * 278 * Return Value: true if success; otherwise false 279 * 280 */ 281 bool MACbSafeSoftwareReset(struct vnt_private *priv) 282 { 283 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1]; 284 bool bRetVal; 285 286 /* PATCH.... 287 * save some important register's value, then do 288 * reset, then restore register's value 289 */ 290 /* save MAC context */ 291 MACvSaveContext(priv, abyTmpRegData); 292 /* do reset */ 293 bRetVal = MACbSoftwareReset(priv); 294 /* restore MAC context, except CR0 */ 295 MACvRestoreContext(priv, abyTmpRegData); 296 297 return bRetVal; 298 } 299 300 /* 301 * Description: 302 * Turn Off MAC Rx 303 * 304 * Parameters: 305 * In: 306 * io_base - Base Address for MAC 307 * Out: 308 * none 309 * 310 * Return Value: true if success; otherwise false 311 * 312 */ 313 bool MACbSafeRxOff(struct vnt_private *priv) 314 { 315 void __iomem *io_base = priv->port_offset; 316 unsigned short ww; 317 318 /* turn off wow temp for turn off Rx safely */ 319 320 /* Clear RX DMA0,1 */ 321 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0); 322 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1); 323 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 324 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) 325 break; 326 } 327 if (ww == W_MAX_TIMEOUT) { 328 pr_debug(" DBG_PORT80(0x10)\n"); 329 return false; 330 } 331 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 332 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) 333 break; 334 } 335 if (ww == W_MAX_TIMEOUT) { 336 pr_debug(" DBG_PORT80(0x11)\n"); 337 return false; 338 } 339 340 /* try to safe shutdown RX */ 341 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON); 342 /* W_MAX_TIMEOUT is the timeout period */ 343 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 344 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST)) 345 break; 346 } 347 if (ww == W_MAX_TIMEOUT) { 348 pr_debug(" DBG_PORT80(0x12)\n"); 349 return false; 350 } 351 return true; 352 } 353 354 /* 355 * Description: 356 * Turn Off MAC Tx 357 * 358 * Parameters: 359 * In: 360 * io_base - Base Address for MAC 361 * Out: 362 * none 363 * 364 * Return Value: true if success; otherwise false 365 * 366 */ 367 bool MACbSafeTxOff(struct vnt_private *priv) 368 { 369 void __iomem *io_base = priv->port_offset; 370 unsigned short ww; 371 372 /* Clear TX DMA */ 373 /* Tx0 */ 374 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0); 375 /* AC0 */ 376 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL); 377 378 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 379 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) 380 break; 381 } 382 if (ww == W_MAX_TIMEOUT) { 383 pr_debug(" DBG_PORT80(0x20)\n"); 384 return false; 385 } 386 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 387 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) 388 break; 389 } 390 if (ww == W_MAX_TIMEOUT) { 391 pr_debug(" DBG_PORT80(0x21)\n"); 392 return false; 393 } 394 395 /* try to safe shutdown TX */ 396 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON); 397 398 /* W_MAX_TIMEOUT is the timeout period */ 399 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 400 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST)) 401 break; 402 } 403 if (ww == W_MAX_TIMEOUT) { 404 pr_debug(" DBG_PORT80(0x24)\n"); 405 return false; 406 } 407 return true; 408 } 409 410 /* 411 * Description: 412 * Stop MAC function 413 * 414 * Parameters: 415 * In: 416 * io_base - Base Address for MAC 417 * Out: 418 * none 419 * 420 * Return Value: true if success; otherwise false 421 * 422 */ 423 bool MACbSafeStop(struct vnt_private *priv) 424 { 425 void __iomem *io_base = priv->port_offset; 426 427 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX); 428 429 if (!MACbSafeRxOff(priv)) { 430 pr_debug(" MACbSafeRxOff == false)\n"); 431 MACbSafeSoftwareReset(priv); 432 return false; 433 } 434 if (!MACbSafeTxOff(priv)) { 435 pr_debug(" MACbSafeTxOff == false)\n"); 436 MACbSafeSoftwareReset(priv); 437 return false; 438 } 439 440 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN); 441 442 return true; 443 } 444 445 /* 446 * Description: 447 * Shut Down MAC 448 * 449 * Parameters: 450 * In: 451 * io_base - Base Address for MAC 452 * Out: 453 * none 454 * 455 * Return Value: true if success; otherwise false 456 * 457 */ 458 bool MACbShutdown(struct vnt_private *priv) 459 { 460 void __iomem *io_base = priv->port_offset; 461 /* disable MAC IMR */ 462 MACvIntDisable(io_base); 463 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL); 464 /* stop the adapter */ 465 if (!MACbSafeStop(priv)) { 466 MACvSetLoopbackMode(priv, MAC_LB_NONE); 467 return false; 468 } 469 MACvSetLoopbackMode(priv, MAC_LB_NONE); 470 return true; 471 } 472 473 /* 474 * Description: 475 * Initialize MAC 476 * 477 * Parameters: 478 * In: 479 * io_base - Base Address for MAC 480 * Out: 481 * none 482 * 483 * Return Value: none 484 * 485 */ 486 void MACvInitialize(struct vnt_private *priv) 487 { 488 void __iomem *io_base = priv->port_offset; 489 /* clear sticky bits */ 490 MACvClearStckDS(io_base); 491 /* disable force PME-enable */ 492 iowrite8(PME_OVR, io_base + MAC_REG_PMC1); 493 /* only 3253 A */ 494 495 /* do reset */ 496 MACbSoftwareReset(priv); 497 498 /* reset TSF counter */ 499 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL); 500 /* enable TSF counter */ 501 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL); 502 } 503 504 /* 505 * Description: 506 * Set the chip with current rx descriptor address 507 * 508 * Parameters: 509 * In: 510 * io_base - Base Address for MAC 511 * curr_desc_addr - Descriptor Address 512 * Out: 513 * none 514 * 515 * Return Value: none 516 * 517 */ 518 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr) 519 { 520 void __iomem *io_base = priv->port_offset; 521 unsigned short ww; 522 unsigned char org_dma_ctl; 523 524 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0); 525 if (org_dma_ctl & DMACTL_RUN) 526 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2); 527 528 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 529 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN)) 530 break; 531 } 532 533 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0); 534 if (org_dma_ctl & DMACTL_RUN) 535 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0); 536 } 537 538 /* 539 * Description: 540 * Set the chip with current rx descriptor address 541 * 542 * Parameters: 543 * In: 544 * io_base - Base Address for MAC 545 * curr_desc_addr - Descriptor Address 546 * Out: 547 * none 548 * 549 * Return Value: none 550 * 551 */ 552 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr) 553 { 554 void __iomem *io_base = priv->port_offset; 555 unsigned short ww; 556 unsigned char org_dma_ctl; 557 558 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1); 559 if (org_dma_ctl & DMACTL_RUN) 560 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2); 561 562 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 563 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN)) 564 break; 565 } 566 567 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1); 568 if (org_dma_ctl & DMACTL_RUN) 569 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1); 570 } 571 572 /* 573 * Description: 574 * Set the chip with current tx0 descriptor address 575 * 576 * Parameters: 577 * In: 578 * io_base - Base Address for MAC 579 * curr_desc_addr - Descriptor Address 580 * Out: 581 * none 582 * 583 * Return Value: none 584 * 585 */ 586 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv, 587 u32 curr_desc_addr) 588 { 589 void __iomem *io_base = priv->port_offset; 590 unsigned short ww; 591 unsigned char org_dma_ctl; 592 593 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0); 594 if (org_dma_ctl & DMACTL_RUN) 595 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2); 596 597 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 598 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN)) 599 break; 600 } 601 602 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0); 603 if (org_dma_ctl & DMACTL_RUN) 604 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0); 605 } 606 607 /* 608 * Description: 609 * Set the chip with current AC0 descriptor address 610 * 611 * Parameters: 612 * In: 613 * io_base - Base Address for MAC 614 * curr_desc_addr - Descriptor Address 615 * Out: 616 * none 617 * 618 * Return Value: none 619 * 620 */ 621 /* TxDMA1 = AC0DMA */ 622 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv, 623 u32 curr_desc_addr) 624 { 625 void __iomem *io_base = priv->port_offset; 626 unsigned short ww; 627 unsigned char org_dma_ctl; 628 629 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL); 630 if (org_dma_ctl & DMACTL_RUN) 631 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2); 632 633 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 634 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN)) 635 break; 636 } 637 if (ww == W_MAX_TIMEOUT) 638 pr_debug(" DBG_PORT80(0x26)\n"); 639 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR); 640 if (org_dma_ctl & DMACTL_RUN) 641 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL); 642 } 643 644 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv, 645 u32 curr_desc_addr) 646 { 647 if (iTxType == TYPE_AC0DMA) 648 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr); 649 else if (iTxType == TYPE_TXDMA0) 650 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr); 651 } 652 653 /* 654 * Description: 655 * Micro Second Delay via MAC 656 * 657 * Parameters: 658 * In: 659 * io_base - Base Address for MAC 660 * uDelay - Delay time (timer resolution is 4 us) 661 * Out: 662 * none 663 * 664 * Return Value: none 665 * 666 */ 667 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay) 668 { 669 void __iomem *io_base = priv->port_offset; 670 unsigned char byValue; 671 unsigned int uu, ii; 672 673 iowrite8(0, io_base + MAC_REG_TMCTL0); 674 iowrite32(uDelay, io_base + MAC_REG_TMDATA0); 675 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0); 676 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */ 677 for (uu = 0; uu < uDelay; uu++) { 678 byValue = ioread8(io_base + MAC_REG_TMCTL0); 679 if ((byValue == 0) || 680 (byValue & TMCTL_TSUSP)) { 681 iowrite8(0, io_base + MAC_REG_TMCTL0); 682 return; 683 } 684 } 685 } 686 iowrite8(0, io_base + MAC_REG_TMCTL0); 687 } 688 689 /* 690 * Description: 691 * Micro Second One shot timer via MAC 692 * 693 * Parameters: 694 * In: 695 * io_base - Base Address for MAC 696 * uDelay - Delay time 697 * Out: 698 * none 699 * 700 * Return Value: none 701 * 702 */ 703 void MACvOneShotTimer1MicroSec(struct vnt_private *priv, 704 unsigned int uDelayTime) 705 { 706 void __iomem *io_base = priv->port_offset; 707 708 iowrite8(0, io_base + MAC_REG_TMCTL1); 709 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1); 710 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1); 711 } 712 713 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset, 714 u32 data) 715 { 716 void __iomem *io_base = priv->port_offset; 717 718 if (offset > 273) 719 return; 720 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 721 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 722 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 723 } 724 725 bool MACbPSWakeup(struct vnt_private *priv) 726 { 727 void __iomem *io_base = priv->port_offset; 728 unsigned int ww; 729 /* Read PSCTL */ 730 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS)) 731 return true; 732 733 /* Disable PS */ 734 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN); 735 736 /* Check if SyncFlushOK */ 737 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) { 738 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE) 739 break; 740 } 741 if (ww == W_MAX_TIMEOUT) { 742 pr_debug(" DBG_PORT80(0x33)\n"); 743 return false; 744 } 745 return true; 746 } 747 748 /* 749 * Description: 750 * Set the Key by MISCFIFO 751 * 752 * Parameters: 753 * In: 754 * io_base - Base Address for MAC 755 * 756 * Out: 757 * none 758 * 759 * Return Value: none 760 * 761 */ 762 763 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl, 764 unsigned int uEntryIdx, unsigned int uKeyIdx, 765 unsigned char *pbyAddr, u32 *pdwKey, 766 unsigned char local_id) 767 { 768 void __iomem *io_base = priv->port_offset; 769 unsigned short offset; 770 u32 data; 771 int ii; 772 773 if (local_id <= 1) 774 return; 775 776 offset = MISCFIFO_KEYETRY0; 777 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); 778 779 data = 0; 780 data |= wKeyCtl; 781 data <<= 16; 782 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5)); 783 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n", 784 offset, data, wKeyCtl); 785 786 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 787 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 788 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 789 offset++; 790 791 data = 0; 792 data |= *(pbyAddr + 3); 793 data <<= 8; 794 data |= *(pbyAddr + 2); 795 data <<= 8; 796 data |= *(pbyAddr + 1); 797 data <<= 8; 798 data |= *pbyAddr; 799 pr_debug("2. offset: %d, Data: %X\n", offset, data); 800 801 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 802 iowrite32(data, io_base + MAC_REG_MISCFFDATA); 803 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 804 offset++; 805 806 offset += (uKeyIdx * 4); 807 for (ii = 0; ii < 4; ii++) { 808 /* always push 128 bits */ 809 pr_debug("3.(%d) offset: %d, Data: %X\n", 810 ii, offset + ii, *pdwKey); 811 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX); 812 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA); 813 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 814 } 815 } 816 817 /* 818 * Description: 819 * Disable the Key Entry by MISCFIFO 820 * 821 * Parameters: 822 * In: 823 * io_base - Base Address for MAC 824 * 825 * Out: 826 * none 827 * 828 * Return Value: none 829 * 830 */ 831 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx) 832 { 833 void __iomem *io_base = priv->port_offset; 834 unsigned short offset; 835 836 offset = MISCFIFO_KEYETRY0; 837 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE); 838 839 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX); 840 iowrite32(0, io_base + MAC_REG_MISCFFDATA); 841 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL); 842 } 843