181dee67eSSudip Mukherjee #ifndef DDK750_SII164_H__ 281dee67eSSudip Mukherjee #define DDK750_SII164_H__ 381dee67eSSudip Mukherjee 481dee67eSSudip Mukherjee #define USE_DVICHIP 581dee67eSSudip Mukherjee 681dee67eSSudip Mukherjee /* Hot Plug detection mode structure */ 7259fef35SJuston Li typedef enum _sii164_hot_plug_mode_t { 881dee67eSSudip Mukherjee SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */ 981dee67eSSudip Mukherjee SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */ 1081dee67eSSudip Mukherjee SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */ 1181dee67eSSudip Mukherjee SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */ 1281dee67eSSudip Mukherjee } sii164_hot_plug_mode_t; 1381dee67eSSudip Mukherjee 1481dee67eSSudip Mukherjee 1581dee67eSSudip Mukherjee /* Silicon Image SiI164 chip prototype */ 16c9750456SMatej Dujava long sii164InitChip(unsigned char edgeSelect, 1781dee67eSSudip Mukherjee unsigned char busSelect, 1881dee67eSSudip Mukherjee unsigned char dualEdgeClkSelect, 1981dee67eSSudip Mukherjee unsigned char hsyncEnable, 2081dee67eSSudip Mukherjee unsigned char vsyncEnable, 2181dee67eSSudip Mukherjee unsigned char deskewEnable, 2281dee67eSSudip Mukherjee unsigned char deskewSetting, 2381dee67eSSudip Mukherjee unsigned char continuousSyncEnable, 2481dee67eSSudip Mukherjee unsigned char pllFilterEnable, 25c9750456SMatej Dujava unsigned char pllFilterValue); 2681dee67eSSudip Mukherjee 2781dee67eSSudip Mukherjee unsigned short sii164GetVendorID(void); 2881dee67eSSudip Mukherjee unsigned short sii164GetDeviceID(void); 2981dee67eSSudip Mukherjee 3081dee67eSSudip Mukherjee 3181dee67eSSudip Mukherjee #ifdef SII164_FULL_FUNCTIONS 3281dee67eSSudip Mukherjee void sii164ResetChip(void); 3381dee67eSSudip Mukherjee char *sii164GetChipString(void); 3481dee67eSSudip Mukherjee void sii164SetPower(unsigned char powerUp); 3581dee67eSSudip Mukherjee void sii164EnableHotPlugDetection(unsigned char enableHotPlug); 3681dee67eSSudip Mukherjee unsigned char sii164IsConnected(void); 3781dee67eSSudip Mukherjee unsigned char sii164CheckInterrupt(void); 3881dee67eSSudip Mukherjee void sii164ClearInterrupt(void); 3981dee67eSSudip Mukherjee #endif 40fbb8c963SMatej Vasek /* 41fbb8c963SMatej Vasek * below register definition is used for 42fbb8c963SMatej Vasek * Silicon Image SiI164 DVI controller chip 43fbb8c963SMatej Vasek */ 4481dee67eSSudip Mukherjee /* 4581dee67eSSudip Mukherjee * Vendor ID registers 4681dee67eSSudip Mukherjee */ 4781dee67eSSudip Mukherjee #define SII164_VENDOR_ID_LOW 0x00 4881dee67eSSudip Mukherjee #define SII164_VENDOR_ID_HIGH 0x01 4981dee67eSSudip Mukherjee 5081dee67eSSudip Mukherjee /* 5181dee67eSSudip Mukherjee * Device ID registers 5281dee67eSSudip Mukherjee */ 5381dee67eSSudip Mukherjee #define SII164_DEVICE_ID_LOW 0x02 5481dee67eSSudip Mukherjee #define SII164_DEVICE_ID_HIGH 0x03 5581dee67eSSudip Mukherjee 5681dee67eSSudip Mukherjee /* 5781dee67eSSudip Mukherjee * Device Revision 5881dee67eSSudip Mukherjee */ 5981dee67eSSudip Mukherjee #define SII164_DEVICE_REVISION 0x04 6081dee67eSSudip Mukherjee 6181dee67eSSudip Mukherjee /* 6281dee67eSSudip Mukherjee * Frequency Limitation registers 6381dee67eSSudip Mukherjee */ 6481dee67eSSudip Mukherjee #define SII164_FREQUENCY_LIMIT_LOW 0x06 6581dee67eSSudip Mukherjee #define SII164_FREQUENCY_LIMIT_HIGH 0x07 6681dee67eSSudip Mukherjee 6781dee67eSSudip Mukherjee /* 6881dee67eSSudip Mukherjee * Power Down and Input Signal Configuration registers 6981dee67eSSudip Mukherjee */ 7081dee67eSSudip Mukherjee #define SII164_CONFIGURATION 0x08 7181dee67eSSudip Mukherjee 7281dee67eSSudip Mukherjee /* Power down (PD) */ 7381dee67eSSudip Mukherjee #define SII164_CONFIGURATION_POWER_DOWN 0x00 7481dee67eSSudip Mukherjee #define SII164_CONFIGURATION_POWER_NORMAL 0x01 7581dee67eSSudip Mukherjee #define SII164_CONFIGURATION_POWER_MASK 0x01 7681dee67eSSudip Mukherjee 7781dee67eSSudip Mukherjee /* Input Edge Latch Select (EDGE) */ 7881dee67eSSudip Mukherjee #define SII164_CONFIGURATION_LATCH_FALLING 0x00 7981dee67eSSudip Mukherjee #define SII164_CONFIGURATION_LATCH_RISING 0x02 8081dee67eSSudip Mukherjee 8181dee67eSSudip Mukherjee /* Bus Select (BSEL) */ 8281dee67eSSudip Mukherjee #define SII164_CONFIGURATION_BUS_12BITS 0x00 8381dee67eSSudip Mukherjee #define SII164_CONFIGURATION_BUS_24BITS 0x04 8481dee67eSSudip Mukherjee 8581dee67eSSudip Mukherjee /* Dual Edge Clock Select (DSEL) */ 8681dee67eSSudip Mukherjee #define SII164_CONFIGURATION_CLOCK_SINGLE 0x00 8781dee67eSSudip Mukherjee #define SII164_CONFIGURATION_CLOCK_DUAL 0x08 8881dee67eSSudip Mukherjee 8981dee67eSSudip Mukherjee /* Horizontal Sync Enable (HEN) */ 9081dee67eSSudip Mukherjee #define SII164_CONFIGURATION_HSYNC_FORCE_LOW 0x00 9181dee67eSSudip Mukherjee #define SII164_CONFIGURATION_HSYNC_AS_IS 0x10 9281dee67eSSudip Mukherjee 9381dee67eSSudip Mukherjee /* Vertical Sync Enable (VEN) */ 9481dee67eSSudip Mukherjee #define SII164_CONFIGURATION_VSYNC_FORCE_LOW 0x00 9581dee67eSSudip Mukherjee #define SII164_CONFIGURATION_VSYNC_AS_IS 0x20 9681dee67eSSudip Mukherjee 9781dee67eSSudip Mukherjee /* 9881dee67eSSudip Mukherjee * Detection registers 9981dee67eSSudip Mukherjee */ 10081dee67eSSudip Mukherjee #define SII164_DETECT 0x09 10181dee67eSSudip Mukherjee 10281dee67eSSudip Mukherjee /* Monitor Detect Interrupt (MDI) */ 10381dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_STATE_CHANGE 0x00 10481dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_STATE_NO_CHANGE 0x01 10581dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_STATE_CLEAR 0x01 10681dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_STATE_MASK 0x01 10781dee67eSSudip Mukherjee 10881dee67eSSudip Mukherjee /* Hot Plug detect Input (HTPLG) */ 10981dee67eSSudip Mukherjee #define SII164_DETECT_HOT_PLUG_STATUS_OFF 0x00 11081dee67eSSudip Mukherjee #define SII164_DETECT_HOT_PLUG_STATUS_ON 0x02 11181dee67eSSudip Mukherjee #define SII164_DETECT_HOT_PLUG_STATUS_MASK 0x02 11281dee67eSSudip Mukherjee 11381dee67eSSudip Mukherjee /* Receiver Sense (RSEN) */ 11481dee67eSSudip Mukherjee #define SII164_DETECT_RECEIVER_SENSE_NOT_DETECTED 0x00 11581dee67eSSudip Mukherjee #define SII164_DETECT_RECEIVER_SENSE_DETECTED 0x04 11681dee67eSSudip Mukherjee 11781dee67eSSudip Mukherjee /* Interrupt Generation Method (TSEL) */ 11881dee67eSSudip Mukherjee #define SII164_DETECT_INTERRUPT_BY_RSEN_PIN 0x00 11981dee67eSSudip Mukherjee #define SII164_DETECT_INTERRUPT_BY_HTPLG_PIN 0x08 12081dee67eSSudip Mukherjee #define SII164_DETECT_INTERRUPT_MASK 0x08 12181dee67eSSudip Mukherjee 12281dee67eSSudip Mukherjee /* Monitor Sense Output (MSEN) */ 12381dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_SENSE_OUTPUT_HIGH 0x00 12481dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_SENSE_OUTPUT_MDI 0x10 12581dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_SENSE_OUTPUT_RSEN 0x20 12681dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_SENSE_OUTPUT_HTPLG 0x30 12781dee67eSSudip Mukherjee #define SII164_DETECT_MONITOR_SENSE_OUTPUT_FLAG 0x30 12881dee67eSSudip Mukherjee 12981dee67eSSudip Mukherjee /* 13081dee67eSSudip Mukherjee * Skewing registers 13181dee67eSSudip Mukherjee */ 13281dee67eSSudip Mukherjee #define SII164_DESKEW 0x0A 13381dee67eSSudip Mukherjee 13481dee67eSSudip Mukherjee /* General Purpose Input (CTL[3:1]) */ 13581dee67eSSudip Mukherjee #define SII164_DESKEW_GENERAL_PURPOSE_INPUT_MASK 0x0E 13681dee67eSSudip Mukherjee 13781dee67eSSudip Mukherjee /* De-skewing Enable bit (DKEN) */ 13881dee67eSSudip Mukherjee #define SII164_DESKEW_DISABLE 0x00 13981dee67eSSudip Mukherjee #define SII164_DESKEW_ENABLE 0x10 14081dee67eSSudip Mukherjee 14181dee67eSSudip Mukherjee /* De-skewing Setting (DK[3:1])*/ 14281dee67eSSudip Mukherjee #define SII164_DESKEW_1_STEP 0x00 14381dee67eSSudip Mukherjee #define SII164_DESKEW_2_STEP 0x20 14481dee67eSSudip Mukherjee #define SII164_DESKEW_3_STEP 0x40 14581dee67eSSudip Mukherjee #define SII164_DESKEW_4_STEP 0x60 14681dee67eSSudip Mukherjee #define SII164_DESKEW_5_STEP 0x80 14781dee67eSSudip Mukherjee #define SII164_DESKEW_6_STEP 0xA0 14881dee67eSSudip Mukherjee #define SII164_DESKEW_7_STEP 0xC0 14981dee67eSSudip Mukherjee #define SII164_DESKEW_8_STEP 0xE0 15081dee67eSSudip Mukherjee 15181dee67eSSudip Mukherjee /* 15281dee67eSSudip Mukherjee * User Configuration Data registers (CFG 7:0) 15381dee67eSSudip Mukherjee */ 15481dee67eSSudip Mukherjee #define SII164_USER_CONFIGURATION 0x0B 15581dee67eSSudip Mukherjee 15681dee67eSSudip Mukherjee /* 15781dee67eSSudip Mukherjee * PLL registers 15881dee67eSSudip Mukherjee */ 15981dee67eSSudip Mukherjee #define SII164_PLL 0x0C 16081dee67eSSudip Mukherjee 16181dee67eSSudip Mukherjee /* PLL Filter Value (PLLF) */ 16281dee67eSSudip Mukherjee #define SII164_PLL_FILTER_VALUE_MASK 0x0E 16381dee67eSSudip Mukherjee 16481dee67eSSudip Mukherjee /* PLL Filter Enable (PFEN) */ 16581dee67eSSudip Mukherjee #define SII164_PLL_FILTER_DISABLE 0x00 16681dee67eSSudip Mukherjee #define SII164_PLL_FILTER_ENABLE 0x01 16781dee67eSSudip Mukherjee 16881dee67eSSudip Mukherjee /* Sync Continuous (SCNT) */ 16981dee67eSSudip Mukherjee #define SII164_PLL_FILTER_SYNC_CONTINUOUS_DISABLE 0x00 17081dee67eSSudip Mukherjee #define SII164_PLL_FILTER_SYNC_CONTINUOUS_ENABLE 0x80 17181dee67eSSudip Mukherjee 17281dee67eSSudip Mukherjee #endif 173