1 #ifndef DDK750_REG_H__ 2 #define DDK750_REG_H__ 3 4 /* New register for SM750LE */ 5 #define DE_STATE1 0x100054 6 #define DE_STATE1_DE_ABORT BIT(0) 7 8 #define DE_STATE2 0x100058 9 #define DE_STATE2_DE_FIFO_EMPTY BIT(3) 10 #define DE_STATE2_DE_STATUS_BUSY BIT(2) 11 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1) 12 13 #define SYSTEM_CTRL 0x000000 14 #define SYSTEM_CTRL_DPMS_MASK (0x3 << 30) 15 #define SYSTEM_CTRL_DPMS_VPHP (0x0 << 30) 16 #define SYSTEM_CTRL_DPMS_VPHN (0x1 << 30) 17 #define SYSTEM_CTRL_DPMS_VNHP (0x2 << 30) 18 #define SYSTEM_CTRL_DPMS_VNHN (0x3 << 30) 19 #define SYSTEM_CTRL_PCI_BURST BIT(29) 20 #define SYSTEM_CTRL_PCI_MASTER BIT(25) 21 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24) 22 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23) 23 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22) 24 #define SYSTEM_CTRL_DE_MEM_FIFO_EMPTY BIT(21) 25 #define SYSTEM_CTRL_CSC_STATUS_BUSY BIT(20) 26 #define SYSTEM_CTRL_CRT_VSYNC_ACTIVE BIT(19) 27 #define SYSTEM_CTRL_PANEL_VSYNC_ACTIVE BIT(18) 28 #define SYSTEM_CTRL_CURRENT_BUFFER_FLIP_PENDING BIT(17) 29 #define SYSTEM_CTRL_DMA_STATUS_BUSY BIT(16) 30 #define SYSTEM_CTRL_PCI_BURST_READ BIT(15) 31 #define SYSTEM_CTRL_DE_ABORT BIT(13) 32 #define SYSTEM_CTRL_PCI_SUBSYS_ID_LOCK BIT(11) 33 #define SYSTEM_CTRL_PCI_RETRY_OFF BIT(7) 34 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_MASK (0x3 << 4) 35 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_1 (0x0 << 4) 36 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_2 (0x1 << 4) 37 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_4 (0x2 << 4) 38 #define SYSTEM_CTRL_PCI_SLAVE_BURST_READ_SIZE_8 (0x3 << 4) 39 #define SYSTEM_CTRL_CRT_TRISTATE BIT(3) 40 #define SYSTEM_CTRL_PCIMEM_TRISTATE BIT(2) 41 #define SYSTEM_CTRL_LOCALMEM_TRISTATE BIT(1) 42 #define SYSTEM_CTRL_PANEL_TRISTATE BIT(0) 43 44 #define MISC_CTRL 0x000004 45 #define MISC_CTRL_DRAM_RERESH_COUNT BIT(27) 46 #define MISC_CTRL_DRAM_REFRESH_TIME_MASK (0x3 << 25) 47 #define MISC_CTRL_DRAM_REFRESH_TIME_8 (0x0 << 25) 48 #define MISC_CTRL_DRAM_REFRESH_TIME_16 (0x1 << 25) 49 #define MISC_CTRL_DRAM_REFRESH_TIME_32 (0x2 << 25) 50 #define MISC_CTRL_DRAM_REFRESH_TIME_64 (0x3 << 25) 51 #define MISC_CTRL_INT_OUTPUT_INVERT BIT(24) 52 #define MISC_CTRL_PLL_CLK_COUNT BIT(23) 53 #define MISC_CTRL_DAC_POWER_OFF BIT(20) 54 #define MISC_CTRL_CLK_SELECT_TESTCLK BIT(16) 55 #define MISC_CTRL_DRAM_COLUMN_SIZE_MASK (0x3 << 14) 56 #define MISC_CTRL_DRAM_COLUMN_SIZE_256 (0x0 << 14) 57 #define MISC_CTRL_DRAM_COLUMN_SIZE_512 (0x1 << 14) 58 #define MISC_CTRL_DRAM_COLUMN_SIZE_1024 (0x2 << 14) 59 #define MISC_CTRL_LOCALMEM_SIZE_MASK (0x3 << 12) 60 #define MISC_CTRL_LOCALMEM_SIZE_8M (0x3 << 12) 61 #define MISC_CTRL_LOCALMEM_SIZE_16M (0x0 << 12) 62 #define MISC_CTRL_LOCALMEM_SIZE_32M (0x1 << 12) 63 #define MISC_CTRL_LOCALMEM_SIZE_64M (0x2 << 12) 64 #define MISC_CTRL_DRAM_TWTR BIT(11) 65 #define MISC_CTRL_DRAM_TWR BIT(10) 66 #define MISC_CTRL_DRAM_TRP BIT(9) 67 #define MISC_CTRL_DRAM_TRFC BIT(8) 68 #define MISC_CTRL_DRAM_TRAS BIT(7) 69 #define MISC_CTRL_LOCALMEM_RESET BIT(6) 70 #define MISC_CTRL_LOCALMEM_STATE_INACTIVE BIT(5) 71 #define MISC_CTRL_CPU_CAS_LATENCY BIT(4) 72 #define MISC_CTRL_DLL_OFF BIT(3) 73 #define MISC_CTRL_DRAM_OUTPUT_HIGH BIT(2) 74 #define MISC_CTRL_LOCALMEM_BUS_SIZE BIT(1) 75 #define MISC_CTRL_EMBEDDED_LOCALMEM_OFF BIT(0) 76 77 #define GPIO_MUX 0x000008 78 #define GPIO_MUX_31 BIT(31) 79 #define GPIO_MUX_30 BIT(30) 80 #define GPIO_MUX_29 BIT(29) 81 #define GPIO_MUX_28 BIT(28) 82 #define GPIO_MUX_27 BIT(27) 83 #define GPIO_MUX_26 BIT(26) 84 #define GPIO_MUX_25 BIT(25) 85 #define GPIO_MUX_24 BIT(24) 86 #define GPIO_MUX_23 BIT(23) 87 #define GPIO_MUX_22 BIT(22) 88 #define GPIO_MUX_21 BIT(21) 89 #define GPIO_MUX_20 BIT(20) 90 #define GPIO_MUX_19 BIT(19) 91 #define GPIO_MUX_18 BIT(18) 92 #define GPIO_MUX_17 BIT(17) 93 #define GPIO_MUX_16 BIT(16) 94 #define GPIO_MUX_15 BIT(15) 95 #define GPIO_MUX_14 BIT(14) 96 #define GPIO_MUX_13 BIT(13) 97 #define GPIO_MUX_12 BIT(12) 98 #define GPIO_MUX_11 BIT(11) 99 #define GPIO_MUX_10 BIT(10) 100 #define GPIO_MUX_9 BIT(9) 101 #define GPIO_MUX_8 BIT(8) 102 #define GPIO_MUX_7 BIT(7) 103 #define GPIO_MUX_6 BIT(6) 104 #define GPIO_MUX_5 BIT(5) 105 #define GPIO_MUX_4 BIT(4) 106 #define GPIO_MUX_3 BIT(3) 107 #define GPIO_MUX_2 BIT(2) 108 #define GPIO_MUX_1 BIT(1) 109 #define GPIO_MUX_0 BIT(0) 110 111 #define LOCALMEM_ARBITRATION 0x00000C 112 #define LOCALMEM_ARBITRATION_ROTATE BIT(28) 113 #define LOCALMEM_ARBITRATION_VGA_MASK (0x7 << 24) 114 #define LOCALMEM_ARBITRATION_VGA_OFF (0x0 << 24) 115 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) 116 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) 117 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) 118 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) 119 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) 120 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) 121 #define LOCALMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) 122 #define LOCALMEM_ARBITRATION_DMA_MASK (0x7 << 20) 123 #define LOCALMEM_ARBITRATION_DMA_OFF (0x0 << 20) 124 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) 125 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) 126 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) 127 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) 128 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) 129 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) 130 #define LOCALMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) 131 #define LOCALMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) 132 #define LOCALMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) 133 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) 134 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) 135 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) 136 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) 137 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) 138 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) 139 #define LOCALMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) 140 #define LOCALMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) 141 #define LOCALMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) 142 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) 143 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) 144 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) 145 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) 146 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) 147 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) 148 #define LOCALMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) 149 #define LOCALMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) 150 #define LOCALMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) 151 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) 152 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) 153 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) 154 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) 155 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) 156 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) 157 #define LOCALMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) 158 #define LOCALMEM_ARBITRATION_PANEL_MASK (0x7 << 4) 159 #define LOCALMEM_ARBITRATION_PANEL_OFF (0x0 << 4) 160 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) 161 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) 162 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) 163 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) 164 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) 165 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) 166 #define LOCALMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) 167 #define LOCALMEM_ARBITRATION_CRT_MASK 0x7 168 #define LOCALMEM_ARBITRATION_CRT_OFF 0x0 169 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_1 0x1 170 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_2 0x2 171 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_3 0x3 172 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_4 0x4 173 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_5 0x5 174 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_6 0x6 175 #define LOCALMEM_ARBITRATION_CRT_PRIORITY_7 0x7 176 177 #define PCIMEM_ARBITRATION 0x000010 178 #define PCIMEM_ARBITRATION_ROTATE BIT(28) 179 #define PCIMEM_ARBITRATION_VGA_MASK (0x7 << 24) 180 #define PCIMEM_ARBITRATION_VGA_OFF (0x0 << 24) 181 #define PCIMEM_ARBITRATION_VGA_PRIORITY_1 (0x1 << 24) 182 #define PCIMEM_ARBITRATION_VGA_PRIORITY_2 (0x2 << 24) 183 #define PCIMEM_ARBITRATION_VGA_PRIORITY_3 (0x3 << 24) 184 #define PCIMEM_ARBITRATION_VGA_PRIORITY_4 (0x4 << 24) 185 #define PCIMEM_ARBITRATION_VGA_PRIORITY_5 (0x5 << 24) 186 #define PCIMEM_ARBITRATION_VGA_PRIORITY_6 (0x6 << 24) 187 #define PCIMEM_ARBITRATION_VGA_PRIORITY_7 (0x7 << 24) 188 #define PCIMEM_ARBITRATION_DMA_MASK (0x7 << 20) 189 #define PCIMEM_ARBITRATION_DMA_OFF (0x0 << 20) 190 #define PCIMEM_ARBITRATION_DMA_PRIORITY_1 (0x1 << 20) 191 #define PCIMEM_ARBITRATION_DMA_PRIORITY_2 (0x2 << 20) 192 #define PCIMEM_ARBITRATION_DMA_PRIORITY_3 (0x3 << 20) 193 #define PCIMEM_ARBITRATION_DMA_PRIORITY_4 (0x4 << 20) 194 #define PCIMEM_ARBITRATION_DMA_PRIORITY_5 (0x5 << 20) 195 #define PCIMEM_ARBITRATION_DMA_PRIORITY_6 (0x6 << 20) 196 #define PCIMEM_ARBITRATION_DMA_PRIORITY_7 (0x7 << 20) 197 #define PCIMEM_ARBITRATION_ZVPORT1_MASK (0x7 << 16) 198 #define PCIMEM_ARBITRATION_ZVPORT1_OFF (0x0 << 16) 199 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_1 (0x1 << 16) 200 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_2 (0x2 << 16) 201 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_3 (0x3 << 16) 202 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_4 (0x4 << 16) 203 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_5 (0x5 << 16) 204 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_6 (0x6 << 16) 205 #define PCIMEM_ARBITRATION_ZVPORT1_PRIORITY_7 (0x7 << 16) 206 #define PCIMEM_ARBITRATION_ZVPORT0_MASK (0x7 << 12) 207 #define PCIMEM_ARBITRATION_ZVPORT0_OFF (0x0 << 12) 208 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_1 (0x1 << 12) 209 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_2 (0x2 << 12) 210 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_3 (0x3 << 12) 211 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_4 (0x4 << 12) 212 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_5 (0x5 << 12) 213 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_6 (0x6 << 12) 214 #define PCIMEM_ARBITRATION_ZVPORT0_PRIORITY_7 (0x7 << 12) 215 #define PCIMEM_ARBITRATION_VIDEO_MASK (0x7 << 8) 216 #define PCIMEM_ARBITRATION_VIDEO_OFF (0x0 << 8) 217 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_1 (0x1 << 8) 218 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_2 (0x2 << 8) 219 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_3 (0x3 << 8) 220 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_4 (0x4 << 8) 221 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_5 (0x5 << 8) 222 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_6 (0x6 << 8) 223 #define PCIMEM_ARBITRATION_VIDEO_PRIORITY_7 (0x7 << 8) 224 #define PCIMEM_ARBITRATION_PANEL_MASK (0x7 << 4) 225 #define PCIMEM_ARBITRATION_PANEL_OFF (0x0 << 4) 226 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_1 (0x1 << 4) 227 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_2 (0x2 << 4) 228 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_3 (0x3 << 4) 229 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_4 (0x4 << 4) 230 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_5 (0x5 << 4) 231 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_6 (0x6 << 4) 232 #define PCIMEM_ARBITRATION_PANEL_PRIORITY_7 (0x7 << 4) 233 #define PCIMEM_ARBITRATION_CRT_MASK 0x7 234 #define PCIMEM_ARBITRATION_CRT_OFF 0x0 235 #define PCIMEM_ARBITRATION_CRT_PRIORITY_1 0x1 236 #define PCIMEM_ARBITRATION_CRT_PRIORITY_2 0x2 237 #define PCIMEM_ARBITRATION_CRT_PRIORITY_3 0x3 238 #define PCIMEM_ARBITRATION_CRT_PRIORITY_4 0x4 239 #define PCIMEM_ARBITRATION_CRT_PRIORITY_5 0x5 240 #define PCIMEM_ARBITRATION_CRT_PRIORITY_6 0x6 241 #define PCIMEM_ARBITRATION_CRT_PRIORITY_7 0x7 242 243 #define RAW_INT 0x000020 244 #define RAW_INT_ZVPORT1_VSYNC BIT(4) 245 #define RAW_INT_ZVPORT0_VSYNC BIT(3) 246 #define RAW_INT_CRT_VSYNC BIT(2) 247 #define RAW_INT_PANEL_VSYNC BIT(1) 248 #define RAW_INT_VGA_VSYNC BIT(0) 249 250 #define INT_STATUS 0x000024 251 #define INT_STATUS_GPIO31 BIT(31) 252 #define INT_STATUS_GPIO30 BIT(30) 253 #define INT_STATUS_GPIO29 BIT(29) 254 #define INT_STATUS_GPIO28 BIT(28) 255 #define INT_STATUS_GPIO27 BIT(27) 256 #define INT_STATUS_GPIO26 BIT(26) 257 #define INT_STATUS_GPIO25 BIT(25) 258 #define INT_STATUS_I2C BIT(12) 259 #define INT_STATUS_PWM BIT(11) 260 #define INT_STATUS_DMA1 BIT(10) 261 #define INT_STATUS_DMA0 BIT(9) 262 #define INT_STATUS_PCI BIT(8) 263 #define INT_STATUS_SSP1 BIT(7) 264 #define INT_STATUS_SSP0 BIT(6) 265 #define INT_STATUS_DE BIT(5) 266 #define INT_STATUS_ZVPORT1_VSYNC BIT(4) 267 #define INT_STATUS_ZVPORT0_VSYNC BIT(3) 268 #define INT_STATUS_CRT_VSYNC BIT(2) 269 #define INT_STATUS_PANEL_VSYNC BIT(1) 270 #define INT_STATUS_VGA_VSYNC BIT(0) 271 272 #define INT_MASK 0x000028 273 #define INT_MASK_GPIO31 BIT(31) 274 #define INT_MASK_GPIO30 BIT(30) 275 #define INT_MASK_GPIO29 BIT(29) 276 #define INT_MASK_GPIO28 BIT(28) 277 #define INT_MASK_GPIO27 BIT(27) 278 #define INT_MASK_GPIO26 BIT(26) 279 #define INT_MASK_GPIO25 BIT(25) 280 #define INT_MASK_I2C BIT(12) 281 #define INT_MASK_PWM BIT(11) 282 #define INT_MASK_DMA1 BIT(10) 283 #define INT_MASK_DMA BIT(9) 284 #define INT_MASK_PCI BIT(8) 285 #define INT_MASK_SSP1 BIT(7) 286 #define INT_MASK_SSP0 BIT(6) 287 #define INT_MASK_DE BIT(5) 288 #define INT_MASK_ZVPORT1_VSYNC BIT(4) 289 #define INT_MASK_ZVPORT0_VSYNC BIT(3) 290 #define INT_MASK_CRT_VSYNC BIT(2) 291 #define INT_MASK_PANEL_VSYNC BIT(1) 292 #define INT_MASK_VGA_VSYNC BIT(0) 293 294 #define CURRENT_GATE 0x000040 295 #define CURRENT_GATE_MCLK_MASK (0x3 << 14) 296 #ifdef VALIDATION_CHIP 297 #define CURRENT_GATE_MCLK_112MHZ (0x0 << 14) 298 #define CURRENT_GATE_MCLK_84MHZ (0x1 << 14) 299 #define CURRENT_GATE_MCLK_56MHZ (0x2 << 14) 300 #define CURRENT_GATE_MCLK_42MHZ (0x3 << 14) 301 #else 302 #define CURRENT_GATE_MCLK_DIV_3 (0x0 << 14) 303 #define CURRENT_GATE_MCLK_DIV_4 (0x1 << 14) 304 #define CURRENT_GATE_MCLK_DIV_6 (0x2 << 14) 305 #define CURRENT_GATE_MCLK_DIV_8 (0x3 << 14) 306 #endif 307 #define CURRENT_GATE_M2XCLK_MASK (0x3 << 12) 308 #ifdef VALIDATION_CHIP 309 #define CURRENT_GATE_M2XCLK_336MHZ (0x0 << 12) 310 #define CURRENT_GATE_M2XCLK_168MHZ (0x1 << 12) 311 #define CURRENT_GATE_M2XCLK_112MHZ (0x2 << 12) 312 #define CURRENT_GATE_M2XCLK_84MHZ (0x3 << 12) 313 #else 314 #define CURRENT_GATE_M2XCLK_DIV_1 (0x0 << 12) 315 #define CURRENT_GATE_M2XCLK_DIV_2 (0x1 << 12) 316 #define CURRENT_GATE_M2XCLK_DIV_3 (0x2 << 12) 317 #define CURRENT_GATE_M2XCLK_DIV_4 (0x3 << 12) 318 #endif 319 #define CURRENT_GATE_VGA BIT(10) 320 #define CURRENT_GATE_PWM BIT(9) 321 #define CURRENT_GATE_I2C BIT(8) 322 #define CURRENT_GATE_SSP BIT(7) 323 #define CURRENT_GATE_GPIO BIT(6) 324 #define CURRENT_GATE_ZVPORT BIT(5) 325 #define CURRENT_GATE_CSC BIT(4) 326 #define CURRENT_GATE_DE BIT(3) 327 #define CURRENT_GATE_DISPLAY BIT(2) 328 #define CURRENT_GATE_LOCALMEM BIT(1) 329 #define CURRENT_GATE_DMA BIT(0) 330 331 #define MODE0_GATE 0x000044 332 #define MODE0_GATE_MCLK_MASK (0x3 << 14) 333 #define MODE0_GATE_MCLK_112MHZ (0x0 << 14) 334 #define MODE0_GATE_MCLK_84MHZ (0x1 << 14) 335 #define MODE0_GATE_MCLK_56MHZ (0x2 << 14) 336 #define MODE0_GATE_MCLK_42MHZ (0x3 << 14) 337 #define MODE0_GATE_M2XCLK_MASK (0x3 << 12) 338 #define MODE0_GATE_M2XCLK_336MHZ (0x0 << 12) 339 #define MODE0_GATE_M2XCLK_168MHZ (0x1 << 12) 340 #define MODE0_GATE_M2XCLK_112MHZ (0x2 << 12) 341 #define MODE0_GATE_M2XCLK_84MHZ (0x3 << 12) 342 #define MODE0_GATE_VGA BIT(10) 343 #define MODE0_GATE_PWM BIT(9) 344 #define MODE0_GATE_I2C BIT(8) 345 #define MODE0_GATE_SSP BIT(7) 346 #define MODE0_GATE_GPIO BIT(6) 347 #define MODE0_GATE_ZVPORT BIT(5) 348 #define MODE0_GATE_CSC BIT(4) 349 #define MODE0_GATE_DE BIT(3) 350 #define MODE0_GATE_DISPLAY BIT(2) 351 #define MODE0_GATE_LOCALMEM BIT(1) 352 #define MODE0_GATE_DMA BIT(0) 353 354 #define MODE1_GATE 0x000048 355 #define MODE1_GATE_MCLK_MASK (0x3 << 14) 356 #define MODE1_GATE_MCLK_112MHZ (0x0 << 14) 357 #define MODE1_GATE_MCLK_84MHZ (0x1 << 14) 358 #define MODE1_GATE_MCLK_56MHZ (0x2 << 14) 359 #define MODE1_GATE_MCLK_42MHZ (0x3 << 14) 360 #define MODE1_GATE_M2XCLK_MASK (0x3 << 12) 361 #define MODE1_GATE_M2XCLK_336MHZ (0x0 << 12) 362 #define MODE1_GATE_M2XCLK_168MHZ (0x1 << 12) 363 #define MODE1_GATE_M2XCLK_112MHZ (0x2 << 12) 364 #define MODE1_GATE_M2XCLK_84MHZ (0x3 << 12) 365 #define MODE1_GATE_VGA BIT(10) 366 #define MODE1_GATE_PWM BIT(9) 367 #define MODE1_GATE_I2C BIT(8) 368 #define MODE1_GATE_SSP BIT(7) 369 #define MODE1_GATE_GPIO BIT(6) 370 #define MODE1_GATE_ZVPORT BIT(5) 371 #define MODE1_GATE_CSC BIT(4) 372 #define MODE1_GATE_DE BIT(3) 373 #define MODE1_GATE_DISPLAY BIT(2) 374 #define MODE1_GATE_LOCALMEM BIT(1) 375 #define MODE1_GATE_DMA BIT(0) 376 377 #define POWER_MODE_CTRL 0x00004C 378 #ifdef VALIDATION_CHIP 379 #define POWER_MODE_CTRL_336CLK BIT(4) 380 #endif 381 #define POWER_MODE_CTRL_OSC_INPUT BIT(3) 382 #define POWER_MODE_CTRL_ACPI BIT(2) 383 #define POWER_MODE_CTRL_MODE_MASK (0x3 << 0) 384 #define POWER_MODE_CTRL_MODE_MODE0 (0x0 << 0) 385 #define POWER_MODE_CTRL_MODE_MODE1 (0x1 << 0) 386 #define POWER_MODE_CTRL_MODE_SLEEP (0x2 << 0) 387 388 #define PCI_MASTER_BASE 0x000050 389 #define PCI_MASTER_BASE_ADDRESS_MASK 0xff 390 391 #define DEVICE_ID 0x000054 392 #define DEVICE_ID_DEVICE_ID_MASK (0xffff << 16) 393 #define DEVICE_ID_REVISION_ID_MASK 0xff 394 395 #define PLL_CLK_COUNT 0x000058 396 #define PLL_CLK_COUNT_COUNTER_MASK 0xffff 397 398 #define PANEL_PLL_CTRL 0x00005C 399 #define PLL_CTRL_BYPASS BIT(18) 400 #define PLL_CTRL_POWER BIT(17) 401 #define PLL_CTRL_INPUT BIT(16) 402 #ifdef VALIDATION_CHIP 403 #define PLL_CTRL_OD_SHIFT 14 404 #define PLL_CTRL_OD_MASK (0x3 << 14) 405 #else 406 #define PLL_CTRL_POD_SHIFT 14 407 #define PLL_CTRL_POD_MASK (0x3 << 14) 408 #define PLL_CTRL_OD_SHIFT 12 409 #define PLL_CTRL_OD_MASK (0x3 << 12) 410 #endif 411 #define PLL_CTRL_N_SHIFT 8 412 #define PLL_CTRL_N_MASK (0xf << 8) 413 #define PLL_CTRL_M_SHIFT 0 414 #define PLL_CTRL_M_MASK 0xff 415 416 #define CRT_PLL_CTRL 0x000060 417 418 #define VGA_PLL0_CTRL 0x000064 419 420 #define VGA_PLL1_CTRL 0x000068 421 422 #define SCRATCH_DATA 0x00006c 423 424 #ifndef VALIDATION_CHIP 425 426 #define MXCLK_PLL_CTRL 0x000070 427 428 #define VGA_CONFIGURATION 0x000088 429 #define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4) 430 #define VGA_CONFIGURATION_PLL BIT(2) 431 #define VGA_CONFIGURATION_MODE BIT(1) 432 433 #endif 434 435 #define GPIO_DATA 0x010000 436 #define GPIO_DATA_31 BIT(31) 437 #define GPIO_DATA_30 BIT(30) 438 #define GPIO_DATA_29 BIT(29) 439 #define GPIO_DATA_28 BIT(28) 440 #define GPIO_DATA_27 BIT(27) 441 #define GPIO_DATA_26 BIT(26) 442 #define GPIO_DATA_25 BIT(25) 443 #define GPIO_DATA_24 BIT(24) 444 #define GPIO_DATA_23 BIT(23) 445 #define GPIO_DATA_22 BIT(22) 446 #define GPIO_DATA_21 BIT(21) 447 #define GPIO_DATA_20 BIT(20) 448 #define GPIO_DATA_19 BIT(19) 449 #define GPIO_DATA_18 BIT(18) 450 #define GPIO_DATA_17 BIT(17) 451 #define GPIO_DATA_16 BIT(16) 452 #define GPIO_DATA_15 BIT(15) 453 #define GPIO_DATA_14 BIT(14) 454 #define GPIO_DATA_13 BIT(13) 455 #define GPIO_DATA_12 BIT(12) 456 #define GPIO_DATA_11 BIT(11) 457 #define GPIO_DATA_10 BIT(10) 458 #define GPIO_DATA_9 BIT(9) 459 #define GPIO_DATA_8 BIT(8) 460 #define GPIO_DATA_7 BIT(7) 461 #define GPIO_DATA_6 BIT(6) 462 #define GPIO_DATA_5 BIT(5) 463 #define GPIO_DATA_4 BIT(4) 464 #define GPIO_DATA_3 BIT(3) 465 #define GPIO_DATA_2 BIT(2) 466 #define GPIO_DATA_1 BIT(1) 467 #define GPIO_DATA_0 BIT(0) 468 469 #define GPIO_DATA_DIRECTION 0x010004 470 #define GPIO_DATA_DIRECTION_31 BIT(31) 471 #define GPIO_DATA_DIRECTION_30 BIT(30) 472 #define GPIO_DATA_DIRECTION_29 BIT(29) 473 #define GPIO_DATA_DIRECTION_28 BIT(28) 474 #define GPIO_DATA_DIRECTION_27 BIT(27) 475 #define GPIO_DATA_DIRECTION_26 BIT(26) 476 #define GPIO_DATA_DIRECTION_25 BIT(25) 477 #define GPIO_DATA_DIRECTION_24 BIT(24) 478 #define GPIO_DATA_DIRECTION_23 BIT(23) 479 #define GPIO_DATA_DIRECTION_22 BIT(22) 480 #define GPIO_DATA_DIRECTION_21 BIT(21) 481 #define GPIO_DATA_DIRECTION_20 BIT(20) 482 #define GPIO_DATA_DIRECTION_19 BIT(19) 483 #define GPIO_DATA_DIRECTION_18 BIT(18) 484 #define GPIO_DATA_DIRECTION_17 BIT(17) 485 #define GPIO_DATA_DIRECTION_16 BIT(16) 486 #define GPIO_DATA_DIRECTION_15 BIT(15) 487 #define GPIO_DATA_DIRECTION_14 BIT(14) 488 #define GPIO_DATA_DIRECTION_13 BIT(13) 489 #define GPIO_DATA_DIRECTION_12 BIT(12) 490 #define GPIO_DATA_DIRECTION_11 BIT(11) 491 #define GPIO_DATA_DIRECTION_10 BIT(10) 492 #define GPIO_DATA_DIRECTION_9 BIT(9) 493 #define GPIO_DATA_DIRECTION_8 BIT(8) 494 #define GPIO_DATA_DIRECTION_7 BIT(7) 495 #define GPIO_DATA_DIRECTION_6 BIT(6) 496 #define GPIO_DATA_DIRECTION_5 BIT(5) 497 #define GPIO_DATA_DIRECTION_4 BIT(4) 498 #define GPIO_DATA_DIRECTION_3 BIT(3) 499 #define GPIO_DATA_DIRECTION_2 BIT(2) 500 #define GPIO_DATA_DIRECTION_1 BIT(1) 501 #define GPIO_DATA_DIRECTION_0 BIT(0) 502 503 #define GPIO_INTERRUPT_SETUP 0x010008 504 #define GPIO_INTERRUPT_SETUP_TRIGGER_31 BIT(22) 505 #define GPIO_INTERRUPT_SETUP_TRIGGER_30 BIT(21) 506 #define GPIO_INTERRUPT_SETUP_TRIGGER_29 BIT(20) 507 #define GPIO_INTERRUPT_SETUP_TRIGGER_28 BIT(19) 508 #define GPIO_INTERRUPT_SETUP_TRIGGER_27 BIT(18) 509 #define GPIO_INTERRUPT_SETUP_TRIGGER_26 BIT(17) 510 #define GPIO_INTERRUPT_SETUP_TRIGGER_25 BIT(16) 511 #define GPIO_INTERRUPT_SETUP_ACTIVE_31 BIT(14) 512 #define GPIO_INTERRUPT_SETUP_ACTIVE_30 BIT(13) 513 #define GPIO_INTERRUPT_SETUP_ACTIVE_29 BIT(12) 514 #define GPIO_INTERRUPT_SETUP_ACTIVE_28 BIT(11) 515 #define GPIO_INTERRUPT_SETUP_ACTIVE_27 BIT(10) 516 #define GPIO_INTERRUPT_SETUP_ACTIVE_26 BIT(9) 517 #define GPIO_INTERRUPT_SETUP_ACTIVE_25 BIT(8) 518 #define GPIO_INTERRUPT_SETUP_ENABLE_31 BIT(6) 519 #define GPIO_INTERRUPT_SETUP_ENABLE_30 BIT(5) 520 #define GPIO_INTERRUPT_SETUP_ENABLE_29 BIT(4) 521 #define GPIO_INTERRUPT_SETUP_ENABLE_28 BIT(3) 522 #define GPIO_INTERRUPT_SETUP_ENABLE_27 BIT(2) 523 #define GPIO_INTERRUPT_SETUP_ENABLE_26 BIT(1) 524 #define GPIO_INTERRUPT_SETUP_ENABLE_25 BIT(0) 525 526 #define GPIO_INTERRUPT_STATUS 0x01000C 527 #define GPIO_INTERRUPT_STATUS_31 BIT(22) 528 #define GPIO_INTERRUPT_STATUS_30 BIT(21) 529 #define GPIO_INTERRUPT_STATUS_29 BIT(20) 530 #define GPIO_INTERRUPT_STATUS_28 BIT(19) 531 #define GPIO_INTERRUPT_STATUS_27 BIT(18) 532 #define GPIO_INTERRUPT_STATUS_26 BIT(17) 533 #define GPIO_INTERRUPT_STATUS_25 BIT(16) 534 535 #define PANEL_DISPLAY_CTRL 0x080000 536 #define PANEL_DISPLAY_CTRL_RESERVED_MASK 0xc0f08000 537 #define PANEL_DISPLAY_CTRL_SELECT_SHIFT 28 538 #define PANEL_DISPLAY_CTRL_SELECT_MASK (0x3 << 28) 539 #define PANEL_DISPLAY_CTRL_SELECT_PANEL (0x0 << 28) 540 #define PANEL_DISPLAY_CTRL_SELECT_VGA (0x1 << 28) 541 #define PANEL_DISPLAY_CTRL_SELECT_CRT (0x2 << 28) 542 #define PANEL_DISPLAY_CTRL_FPEN BIT(27) 543 #define PANEL_DISPLAY_CTRL_VBIASEN BIT(26) 544 #define PANEL_DISPLAY_CTRL_DATA BIT(25) 545 #define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24) 546 #define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19) 547 #define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18) 548 #define PANEL_DISPLAY_CTRL_FIFO (0x3 << 16) 549 #define PANEL_DISPLAY_CTRL_FIFO_1 (0x0 << 16) 550 #define PANEL_DISPLAY_CTRL_FIFO_3 (0x1 << 16) 551 #define PANEL_DISPLAY_CTRL_FIFO_7 (0x2 << 16) 552 #define PANEL_DISPLAY_CTRL_FIFO_11 (0x3 << 16) 553 #define DISPLAY_CTRL_CLOCK_PHASE BIT(14) 554 #define DISPLAY_CTRL_VSYNC_PHASE BIT(13) 555 #define DISPLAY_CTRL_HSYNC_PHASE BIT(12) 556 #define PANEL_DISPLAY_CTRL_VSYNC BIT(11) 557 #define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10) 558 #define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9) 559 #define DISPLAY_CTRL_TIMING BIT(8) 560 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7) 561 #define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6) 562 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5) 563 #define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4) 564 #define DISPLAY_CTRL_GAMMA BIT(3) 565 #define DISPLAY_CTRL_PLANE BIT(2) 566 #define PANEL_DISPLAY_CTRL_FORMAT (0x3 << 0) 567 #define PANEL_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) 568 #define PANEL_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) 569 #define PANEL_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) 570 571 #define PANEL_PAN_CTRL 0x080004 572 #define PANEL_PAN_CTRL_VERTICAL_PAN_MASK (0xff << 24) 573 #define PANEL_PAN_CTRL_VERTICAL_VSYNC_MASK (0x3f << 16) 574 #define PANEL_PAN_CTRL_HORIZONTAL_PAN_MASK (0xff << 8) 575 #define PANEL_PAN_CTRL_HORIZONTAL_VSYNC_MASK 0x3f 576 577 #define PANEL_COLOR_KEY 0x080008 578 #define PANEL_COLOR_KEY_MASK_MASK (0xffff << 16) 579 #define PANEL_COLOR_KEY_VALUE_MASK 0xffff 580 581 #define PANEL_FB_ADDRESS 0x08000C 582 #define PANEL_FB_ADDRESS_STATUS BIT(31) 583 #define PANEL_FB_ADDRESS_EXT BIT(27) 584 #define PANEL_FB_ADDRESS_ADDRESS_MASK 0x1ffffff 585 586 #define PANEL_FB_WIDTH 0x080010 587 #define PANEL_FB_WIDTH_WIDTH_SHIFT 16 588 #define PANEL_FB_WIDTH_WIDTH_MASK (0x3fff << 16) 589 #define PANEL_FB_WIDTH_OFFSET_MASK 0x3fff 590 591 #define PANEL_WINDOW_WIDTH 0x080014 592 #define PANEL_WINDOW_WIDTH_WIDTH_SHIFT 16 593 #define PANEL_WINDOW_WIDTH_WIDTH_MASK (0xfff << 16) 594 #define PANEL_WINDOW_WIDTH_X_MASK 0xfff 595 596 #define PANEL_WINDOW_HEIGHT 0x080018 597 #define PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT 16 598 #define PANEL_WINDOW_HEIGHT_HEIGHT_MASK (0xfff << 16) 599 #define PANEL_WINDOW_HEIGHT_Y_MASK 0xfff 600 601 #define PANEL_PLANE_TL 0x08001C 602 #define PANEL_PLANE_TL_TOP_SHIFT 16 603 #define PANEL_PLANE_TL_TOP_MASK (0x7ff << 16) 604 #define PANEL_PLANE_TL_LEFT_MASK 0x7ff 605 606 #define PANEL_PLANE_BR 0x080020 607 #define PANEL_PLANE_BR_BOTTOM_SHIFT 16 608 #define PANEL_PLANE_BR_BOTTOM_MASK (0x7ff << 16) 609 #define PANEL_PLANE_BR_RIGHT_MASK 0x7ff 610 611 #define PANEL_HORIZONTAL_TOTAL 0x080024 612 #define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 613 #define PANEL_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) 614 #define PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff 615 616 #define PANEL_HORIZONTAL_SYNC 0x080028 617 #define PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT 16 618 #define PANEL_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) 619 #define PANEL_HORIZONTAL_SYNC_START_MASK 0xfff 620 621 #define PANEL_VERTICAL_TOTAL 0x08002C 622 #define PANEL_VERTICAL_TOTAL_TOTAL_SHIFT 16 623 #define PANEL_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) 624 #define PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK 0x7ff 625 626 #define PANEL_VERTICAL_SYNC 0x080030 627 #define PANEL_VERTICAL_SYNC_HEIGHT_SHIFT 16 628 #define PANEL_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) 629 #define PANEL_VERTICAL_SYNC_START_MASK 0x7ff 630 631 #define PANEL_CURRENT_LINE 0x080034 632 #define PANEL_CURRENT_LINE_LINE_MASK 0x7ff 633 634 /* Video Control */ 635 636 #define VIDEO_DISPLAY_CTRL 0x080040 637 #define VIDEO_DISPLAY_CTRL_LINE_BUFFER BIT(18) 638 #define VIDEO_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) 639 #define VIDEO_DISPLAY_CTRL_FIFO_1 (0x0 << 16) 640 #define VIDEO_DISPLAY_CTRL_FIFO_3 (0x1 << 16) 641 #define VIDEO_DISPLAY_CTRL_FIFO_7 (0x2 << 16) 642 #define VIDEO_DISPLAY_CTRL_FIFO_11 (0x3 << 16) 643 #define VIDEO_DISPLAY_CTRL_BUFFER BIT(15) 644 #define VIDEO_DISPLAY_CTRL_CAPTURE BIT(14) 645 #define VIDEO_DISPLAY_CTRL_DOUBLE_BUFFER BIT(13) 646 #define VIDEO_DISPLAY_CTRL_BYTE_SWAP BIT(12) 647 #define VIDEO_DISPLAY_CTRL_VERTICAL_SCALE BIT(11) 648 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_SCALE BIT(10) 649 #define VIDEO_DISPLAY_CTRL_VERTICAL_MODE BIT(9) 650 #define VIDEO_DISPLAY_CTRL_HORIZONTAL_MODE BIT(8) 651 #define VIDEO_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) 652 #define VIDEO_DISPLAY_CTRL_GAMMA BIT(3) 653 #define VIDEO_DISPLAY_CTRL_FORMAT_MASK 0x3 654 #define VIDEO_DISPLAY_CTRL_FORMAT_8 0x0 655 #define VIDEO_DISPLAY_CTRL_FORMAT_16 0x1 656 #define VIDEO_DISPLAY_CTRL_FORMAT_32 0x2 657 #define VIDEO_DISPLAY_CTRL_FORMAT_YUV 0x3 658 659 #define VIDEO_FB_0_ADDRESS 0x080044 660 #define VIDEO_FB_0_ADDRESS_STATUS BIT(31) 661 #define VIDEO_FB_0_ADDRESS_EXT BIT(27) 662 #define VIDEO_FB_0_ADDRESS_ADDRESS_MASK 0x3ffffff 663 664 #define VIDEO_FB_WIDTH 0x080048 665 #define VIDEO_FB_WIDTH_WIDTH_MASK (0x3fff << 16) 666 #define VIDEO_FB_WIDTH_OFFSET_MASK 0x3fff 667 668 #define VIDEO_FB_0_LAST_ADDRESS 0x08004C 669 #define VIDEO_FB_0_LAST_ADDRESS_EXT BIT(27) 670 #define VIDEO_FB_0_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff 671 672 #define VIDEO_PLANE_TL 0x080050 673 #define VIDEO_PLANE_TL_TOP_MASK (0x7ff << 16) 674 #define VIDEO_PLANE_TL_LEFT_MASK 0x7ff 675 676 #define VIDEO_PLANE_BR 0x080054 677 #define VIDEO_PLANE_BR_BOTTOM_MASK (0x7ff << 16) 678 #define VIDEO_PLANE_BR_RIGHT_MASK 0x7ff 679 680 #define VIDEO_SCALE 0x080058 681 #define VIDEO_SCALE_VERTICAL_MODE BIT(31) 682 #define VIDEO_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) 683 #define VIDEO_SCALE_HORIZONTAL_MODE BIT(15) 684 #define VIDEO_SCALE_HORIZONTAL_SCALE_MASK 0xfff 685 686 #define VIDEO_INITIAL_SCALE 0x08005C 687 #define VIDEO_INITIAL_SCALE_FB_1_MASK (0xfff << 16) 688 #define VIDEO_INITIAL_SCALE_FB_0_MASK 0xfff 689 690 #define VIDEO_YUV_CONSTANTS 0x080060 691 #define VIDEO_YUV_CONSTANTS_Y_MASK (0xff << 24) 692 #define VIDEO_YUV_CONSTANTS_R_MASK (0xff << 16) 693 #define VIDEO_YUV_CONSTANTS_G_MASK (0xff << 8) 694 #define VIDEO_YUV_CONSTANTS_B_MASK 0xff 695 696 #define VIDEO_FB_1_ADDRESS 0x080064 697 #define VIDEO_FB_1_ADDRESS_STATUS BIT(31) 698 #define VIDEO_FB_1_ADDRESS_EXT BIT(27) 699 #define VIDEO_FB_1_ADDRESS_ADDRESS_MASK 0x3ffffff 700 701 #define VIDEO_FB_1_LAST_ADDRESS 0x080068 702 #define VIDEO_FB_1_LAST_ADDRESS_EXT BIT(27) 703 #define VIDEO_FB_1_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff 704 705 /* Video Alpha Control */ 706 707 #define VIDEO_ALPHA_DISPLAY_CTRL 0x080080 708 #define VIDEO_ALPHA_DISPLAY_CTRL_SELECT BIT(28) 709 #define VIDEO_ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) 710 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) 711 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) 712 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) 713 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) 714 #define VIDEO_ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) 715 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_SCALE BIT(11) 716 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_SCALE BIT(10) 717 #define VIDEO_ALPHA_DISPLAY_CTRL_VERT_MODE BIT(9) 718 #define VIDEO_ALPHA_DISPLAY_CTRL_HORZ_MODE BIT(8) 719 #define VIDEO_ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) 720 #define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) 721 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 722 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0x0 723 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 724 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 725 #define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 726 727 #define VIDEO_ALPHA_FB_ADDRESS 0x080084 728 #define VIDEO_ALPHA_FB_ADDRESS_STATUS BIT(31) 729 #define VIDEO_ALPHA_FB_ADDRESS_EXT BIT(27) 730 #define VIDEO_ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff 731 732 #define VIDEO_ALPHA_FB_WIDTH 0x080088 733 #define VIDEO_ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) 734 #define VIDEO_ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff 735 736 #define VIDEO_ALPHA_FB_LAST_ADDRESS 0x08008C 737 #define VIDEO_ALPHA_FB_LAST_ADDRESS_EXT BIT(27) 738 #define VIDEO_ALPHA_FB_LAST_ADDRESS_ADDRESS_MASK 0x3ffffff 739 740 #define VIDEO_ALPHA_PLANE_TL 0x080090 741 #define VIDEO_ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) 742 #define VIDEO_ALPHA_PLANE_TL_LEFT_MASK 0x7ff 743 744 #define VIDEO_ALPHA_PLANE_BR 0x080094 745 #define VIDEO_ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) 746 #define VIDEO_ALPHA_PLANE_BR_RIGHT_MASK 0x7ff 747 748 #define VIDEO_ALPHA_SCALE 0x080098 749 #define VIDEO_ALPHA_SCALE_VERTICAL_MODE BIT(31) 750 #define VIDEO_ALPHA_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) 751 #define VIDEO_ALPHA_SCALE_HORIZONTAL_MODE BIT(15) 752 #define VIDEO_ALPHA_SCALE_HORIZONTAL_SCALE_MASK 0xfff 753 754 #define VIDEO_ALPHA_INITIAL_SCALE 0x08009C 755 #define VIDEO_ALPHA_INITIAL_SCALE_VERTICAL_MASK (0xfff << 16) 756 #define VIDEO_ALPHA_INITIAL_SCALE_HORIZONTAL_MASK 0xfff 757 758 #define VIDEO_ALPHA_CHROMA_KEY 0x0800A0 759 #define VIDEO_ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) 760 #define VIDEO_ALPHA_CHROMA_KEY_VALUE_MASK 0xffff 761 762 #define VIDEO_ALPHA_COLOR_LOOKUP_01 0x0800A4 763 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) 764 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) 765 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) 766 #define VIDEO_ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) 767 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff 768 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) 769 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) 770 #define VIDEO_ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f 771 772 #define VIDEO_ALPHA_COLOR_LOOKUP_23 0x0800A8 773 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) 774 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) 775 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) 776 #define VIDEO_ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) 777 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff 778 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) 779 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) 780 #define VIDEO_ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f 781 782 #define VIDEO_ALPHA_COLOR_LOOKUP_45 0x0800AC 783 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) 784 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) 785 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) 786 #define VIDEO_ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) 787 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff 788 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) 789 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) 790 #define VIDEO_ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f 791 792 #define VIDEO_ALPHA_COLOR_LOOKUP_67 0x0800B0 793 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) 794 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) 795 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) 796 #define VIDEO_ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) 797 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff 798 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) 799 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) 800 #define VIDEO_ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f 801 802 #define VIDEO_ALPHA_COLOR_LOOKUP_89 0x0800B4 803 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) 804 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) 805 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) 806 #define VIDEO_ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) 807 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff 808 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) 809 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) 810 #define VIDEO_ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f 811 812 #define VIDEO_ALPHA_COLOR_LOOKUP_AB 0x0800B8 813 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) 814 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) 815 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) 816 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) 817 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff 818 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) 819 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) 820 #define VIDEO_ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f 821 822 #define VIDEO_ALPHA_COLOR_LOOKUP_CD 0x0800BC 823 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) 824 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) 825 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) 826 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) 827 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff 828 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) 829 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) 830 #define VIDEO_ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f 831 832 #define VIDEO_ALPHA_COLOR_LOOKUP_EF 0x0800C0 833 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) 834 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) 835 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) 836 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) 837 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff 838 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) 839 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) 840 #define VIDEO_ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f 841 842 /* Panel Cursor Control */ 843 844 #define PANEL_HWC_ADDRESS 0x0800F0 845 #define PANEL_HWC_ADDRESS_ENABLE BIT(31) 846 #define PANEL_HWC_ADDRESS_EXT BIT(27) 847 #define PANEL_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff 848 849 #define PANEL_HWC_LOCATION 0x0800F4 850 #define PANEL_HWC_LOCATION_TOP BIT(27) 851 #define PANEL_HWC_LOCATION_Y_MASK (0x7ff << 16) 852 #define PANEL_HWC_LOCATION_LEFT BIT(11) 853 #define PANEL_HWC_LOCATION_X_MASK 0x7ff 854 855 #define PANEL_HWC_COLOR_12 0x0800F8 856 #define PANEL_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) 857 #define PANEL_HWC_COLOR_12_1_RGB565_MASK 0xffff 858 859 #define PANEL_HWC_COLOR_3 0x0800FC 860 #define PANEL_HWC_COLOR_3_RGB565_MASK 0xffff 861 862 /* Old Definitions +++ */ 863 #define PANEL_HWC_COLOR_01 0x0800F8 864 #define PANEL_HWC_COLOR_01_1_RED_MASK (0x1f << 27) 865 #define PANEL_HWC_COLOR_01_1_GREEN_MASK (0x3f << 21) 866 #define PANEL_HWC_COLOR_01_1_BLUE_MASK (0x1f << 16) 867 #define PANEL_HWC_COLOR_01_0_RED_MASK (0x1f << 11) 868 #define PANEL_HWC_COLOR_01_0_GREEN_MASK (0x3f << 5) 869 #define PANEL_HWC_COLOR_01_0_BLUE_MASK 0x1f 870 871 #define PANEL_HWC_COLOR_2 0x0800FC 872 #define PANEL_HWC_COLOR_2_RED_MASK (0x1f << 11) 873 #define PANEL_HWC_COLOR_2_GREEN_MASK (0x3f << 5) 874 #define PANEL_HWC_COLOR_2_BLUE_MASK 0x1f 875 /* Old Definitions --- */ 876 877 /* Alpha Control */ 878 879 #define ALPHA_DISPLAY_CTRL 0x080100 880 #define ALPHA_DISPLAY_CTRL_SELECT BIT(28) 881 #define ALPHA_DISPLAY_CTRL_ALPHA_MASK (0xf << 24) 882 #define ALPHA_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) 883 #define ALPHA_DISPLAY_CTRL_FIFO_1 (0x0 << 16) 884 #define ALPHA_DISPLAY_CTRL_FIFO_3 (0x1 << 16) 885 #define ALPHA_DISPLAY_CTRL_FIFO_7 (0x2 << 16) 886 #define ALPHA_DISPLAY_CTRL_FIFO_11 (0x3 << 16) 887 #define ALPHA_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) 888 #define ALPHA_DISPLAY_CTRL_CHROMA_KEY BIT(3) 889 #define ALPHA_DISPLAY_CTRL_FORMAT_MASK 0x3 890 #define ALPHA_DISPLAY_CTRL_FORMAT_16 0x1 891 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 0x2 892 #define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4_4_4 0x3 893 894 #define ALPHA_FB_ADDRESS 0x080104 895 #define ALPHA_FB_ADDRESS_STATUS BIT(31) 896 #define ALPHA_FB_ADDRESS_EXT BIT(27) 897 #define ALPHA_FB_ADDRESS_ADDRESS_MASK 0x3ffffff 898 899 #define ALPHA_FB_WIDTH 0x080108 900 #define ALPHA_FB_WIDTH_WIDTH_MASK (0x3fff << 16) 901 #define ALPHA_FB_WIDTH_OFFSET_MASK 0x3fff 902 903 #define ALPHA_PLANE_TL 0x08010C 904 #define ALPHA_PLANE_TL_TOP_MASK (0x7ff << 16) 905 #define ALPHA_PLANE_TL_LEFT_MASK 0x7ff 906 907 #define ALPHA_PLANE_BR 0x080110 908 #define ALPHA_PLANE_BR_BOTTOM_MASK (0x7ff << 16) 909 #define ALPHA_PLANE_BR_RIGHT_MASK 0x7ff 910 911 #define ALPHA_CHROMA_KEY 0x080114 912 #define ALPHA_CHROMA_KEY_MASK_MASK (0xffff << 16) 913 #define ALPHA_CHROMA_KEY_VALUE_MASK 0xffff 914 915 #define ALPHA_COLOR_LOOKUP_01 0x080118 916 #define ALPHA_COLOR_LOOKUP_01_1_MASK (0xffff << 16) 917 #define ALPHA_COLOR_LOOKUP_01_1_RED_MASK (0x1f << 27) 918 #define ALPHA_COLOR_LOOKUP_01_1_GREEN_MASK (0x3f << 21) 919 #define ALPHA_COLOR_LOOKUP_01_1_BLUE_MASK (0x1f << 16) 920 #define ALPHA_COLOR_LOOKUP_01_0_MASK 0xffff 921 #define ALPHA_COLOR_LOOKUP_01_0_RED_MASK (0x1f << 11) 922 #define ALPHA_COLOR_LOOKUP_01_0_GREEN_MASK (0x3f << 5) 923 #define ALPHA_COLOR_LOOKUP_01_0_BLUE_MASK 0x1f 924 925 #define ALPHA_COLOR_LOOKUP_23 0x08011C 926 #define ALPHA_COLOR_LOOKUP_23_3_MASK (0xffff << 16) 927 #define ALPHA_COLOR_LOOKUP_23_3_RED_MASK (0x1f << 27) 928 #define ALPHA_COLOR_LOOKUP_23_3_GREEN_MASK (0x3f << 21) 929 #define ALPHA_COLOR_LOOKUP_23_3_BLUE_MASK (0x1f << 16) 930 #define ALPHA_COLOR_LOOKUP_23_2_MASK 0xffff 931 #define ALPHA_COLOR_LOOKUP_23_2_RED_MASK (0x1f << 11) 932 #define ALPHA_COLOR_LOOKUP_23_2_GREEN_MASK (0x3f << 5) 933 #define ALPHA_COLOR_LOOKUP_23_2_BLUE_MASK 0x1f 934 935 #define ALPHA_COLOR_LOOKUP_45 0x080120 936 #define ALPHA_COLOR_LOOKUP_45_5_MASK (0xffff << 16) 937 #define ALPHA_COLOR_LOOKUP_45_5_RED_MASK (0x1f << 27) 938 #define ALPHA_COLOR_LOOKUP_45_5_GREEN_MASK (0x3f << 21) 939 #define ALPHA_COLOR_LOOKUP_45_5_BLUE_MASK (0x1f << 16) 940 #define ALPHA_COLOR_LOOKUP_45_4_MASK 0xffff 941 #define ALPHA_COLOR_LOOKUP_45_4_RED_MASK (0x1f << 11) 942 #define ALPHA_COLOR_LOOKUP_45_4_GREEN_MASK (0x3f << 5) 943 #define ALPHA_COLOR_LOOKUP_45_4_BLUE_MASK 0x1f 944 945 #define ALPHA_COLOR_LOOKUP_67 0x080124 946 #define ALPHA_COLOR_LOOKUP_67_7_MASK (0xffff << 16) 947 #define ALPHA_COLOR_LOOKUP_67_7_RED_MASK (0x1f << 27) 948 #define ALPHA_COLOR_LOOKUP_67_7_GREEN_MASK (0x3f << 21) 949 #define ALPHA_COLOR_LOOKUP_67_7_BLUE_MASK (0x1f << 16) 950 #define ALPHA_COLOR_LOOKUP_67_6_MASK 0xffff 951 #define ALPHA_COLOR_LOOKUP_67_6_RED_MASK (0x1f << 11) 952 #define ALPHA_COLOR_LOOKUP_67_6_GREEN_MASK (0x3f << 5) 953 #define ALPHA_COLOR_LOOKUP_67_6_BLUE_MASK 0x1f 954 955 #define ALPHA_COLOR_LOOKUP_89 0x080128 956 #define ALPHA_COLOR_LOOKUP_89_9_MASK (0xffff << 16) 957 #define ALPHA_COLOR_LOOKUP_89_9_RED_MASK (0x1f << 27) 958 #define ALPHA_COLOR_LOOKUP_89_9_GREEN_MASK (0x3f << 21) 959 #define ALPHA_COLOR_LOOKUP_89_9_BLUE_MASK (0x1f << 16) 960 #define ALPHA_COLOR_LOOKUP_89_8_MASK 0xffff 961 #define ALPHA_COLOR_LOOKUP_89_8_RED_MASK (0x1f << 11) 962 #define ALPHA_COLOR_LOOKUP_89_8_GREEN_MASK (0x3f << 5) 963 #define ALPHA_COLOR_LOOKUP_89_8_BLUE_MASK 0x1f 964 965 #define ALPHA_COLOR_LOOKUP_AB 0x08012C 966 #define ALPHA_COLOR_LOOKUP_AB_B_MASK (0xffff << 16) 967 #define ALPHA_COLOR_LOOKUP_AB_B_RED_MASK (0x1f << 27) 968 #define ALPHA_COLOR_LOOKUP_AB_B_GREEN_MASK (0x3f << 21) 969 #define ALPHA_COLOR_LOOKUP_AB_B_BLUE_MASK (0x1f << 16) 970 #define ALPHA_COLOR_LOOKUP_AB_A_MASK 0xffff 971 #define ALPHA_COLOR_LOOKUP_AB_A_RED_MASK (0x1f << 11) 972 #define ALPHA_COLOR_LOOKUP_AB_A_GREEN_MASK (0x3f << 5) 973 #define ALPHA_COLOR_LOOKUP_AB_A_BLUE_MASK 0x1f 974 975 #define ALPHA_COLOR_LOOKUP_CD 0x080130 976 #define ALPHA_COLOR_LOOKUP_CD_D_MASK (0xffff << 16) 977 #define ALPHA_COLOR_LOOKUP_CD_D_RED_MASK (0x1f << 27) 978 #define ALPHA_COLOR_LOOKUP_CD_D_GREEN_MASK (0x3f << 21) 979 #define ALPHA_COLOR_LOOKUP_CD_D_BLUE_MASK (0x1f << 16) 980 #define ALPHA_COLOR_LOOKUP_CD_C_MASK 0xffff 981 #define ALPHA_COLOR_LOOKUP_CD_C_RED_MASK (0x1f << 11) 982 #define ALPHA_COLOR_LOOKUP_CD_C_GREEN_MASK (0x3f << 5) 983 #define ALPHA_COLOR_LOOKUP_CD_C_BLUE_MASK 0x1f 984 985 #define ALPHA_COLOR_LOOKUP_EF 0x080134 986 #define ALPHA_COLOR_LOOKUP_EF_F_MASK (0xffff << 16) 987 #define ALPHA_COLOR_LOOKUP_EF_F_RED_MASK (0x1f << 27) 988 #define ALPHA_COLOR_LOOKUP_EF_F_GREEN_MASK (0x3f << 21) 989 #define ALPHA_COLOR_LOOKUP_EF_F_BLUE_MASK (0x1f << 16) 990 #define ALPHA_COLOR_LOOKUP_EF_E_MASK 0xffff 991 #define ALPHA_COLOR_LOOKUP_EF_E_RED_MASK (0x1f << 11) 992 #define ALPHA_COLOR_LOOKUP_EF_E_GREEN_MASK (0x3f << 5) 993 #define ALPHA_COLOR_LOOKUP_EF_E_BLUE_MASK 0x1f 994 995 /* CRT Graphics Control */ 996 997 #define CRT_DISPLAY_CTRL 0x080200 998 #define CRT_DISPLAY_CTRL_RESERVED_MASK 0xfb008200 999 1000 /* SM750LE definition */ 1001 #define CRT_DISPLAY_CTRL_DPMS_SHIFT 30 1002 #define CRT_DISPLAY_CTRL_DPMS_MASK (0x3 << 30) 1003 #define CRT_DISPLAY_CTRL_DPMS_0 (0x0 << 30) 1004 #define CRT_DISPLAY_CTRL_DPMS_1 (0x1 << 30) 1005 #define CRT_DISPLAY_CTRL_DPMS_2 (0x2 << 30) 1006 #define CRT_DISPLAY_CTRL_DPMS_3 (0x3 << 30) 1007 #define CRT_DISPLAY_CTRL_CLK_MASK (0x7 << 27) 1008 #define CRT_DISPLAY_CTRL_CLK_PLL25 (0x0 << 27) 1009 #define CRT_DISPLAY_CTRL_CLK_PLL41 (0x1 << 27) 1010 #define CRT_DISPLAY_CTRL_CLK_PLL62 (0x2 << 27) 1011 #define CRT_DISPLAY_CTRL_CLK_PLL65 (0x3 << 27) 1012 #define CRT_DISPLAY_CTRL_CLK_PLL74 (0x4 << 27) 1013 #define CRT_DISPLAY_CTRL_CLK_PLL80 (0x5 << 27) 1014 #define CRT_DISPLAY_CTRL_CLK_PLL108 (0x6 << 27) 1015 #define CRT_DISPLAY_CTRL_CLK_RESERVED (0x7 << 27) 1016 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26) 1017 1018 /* SM750LE definition */ 1019 #define CRT_DISPLAY_CTRL_CRTSELECT BIT(25) 1020 #define CRT_DISPLAY_CTRL_RGBBIT BIT(24) 1021 1022 #ifndef VALIDATION_CHIP 1023 #define CRT_DISPLAY_CTRL_CENTERING BIT(24) 1024 #endif 1025 #define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23) 1026 #define CRT_DISPLAY_CTRL_EXPANSION BIT(22) 1027 #define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21) 1028 #define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20) 1029 #define CRT_DISPLAY_CTRL_SELECT_SHIFT 18 1030 #define CRT_DISPLAY_CTRL_SELECT_MASK (0x3 << 18) 1031 #define CRT_DISPLAY_CTRL_SELECT_PANEL (0x0 << 18) 1032 #define CRT_DISPLAY_CTRL_SELECT_VGA (0x1 << 18) 1033 #define CRT_DISPLAY_CTRL_SELECT_CRT (0x2 << 18) 1034 #define CRT_DISPLAY_CTRL_FIFO_MASK (0x3 << 16) 1035 #define CRT_DISPLAY_CTRL_FIFO_1 (0x0 << 16) 1036 #define CRT_DISPLAY_CTRL_FIFO_3 (0x1 << 16) 1037 #define CRT_DISPLAY_CTRL_FIFO_7 (0x2 << 16) 1038 #define CRT_DISPLAY_CTRL_FIFO_11 (0x3 << 16) 1039 #define CRT_DISPLAY_CTRL_BLANK BIT(10) 1040 #define CRT_DISPLAY_CTRL_PIXEL_MASK (0xf << 4) 1041 #define CRT_DISPLAY_CTRL_FORMAT_MASK (0x3 << 0) 1042 #define CRT_DISPLAY_CTRL_FORMAT_8 (0x0 << 0) 1043 #define CRT_DISPLAY_CTRL_FORMAT_16 (0x1 << 0) 1044 #define CRT_DISPLAY_CTRL_FORMAT_32 (0x2 << 0) 1045 1046 #define CRT_FB_ADDRESS 0x080204 1047 #define CRT_FB_ADDRESS_STATUS BIT(31) 1048 #define CRT_FB_ADDRESS_EXT BIT(27) 1049 #define CRT_FB_ADDRESS_ADDRESS_MASK 0x3ffffff 1050 1051 #define CRT_FB_WIDTH 0x080208 1052 #define CRT_FB_WIDTH_WIDTH_SHIFT 16 1053 #define CRT_FB_WIDTH_WIDTH_MASK (0x3fff << 16) 1054 #define CRT_FB_WIDTH_OFFSET_MASK 0x3fff 1055 1056 #define CRT_HORIZONTAL_TOTAL 0x08020C 1057 #define CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT 16 1058 #define CRT_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16) 1059 #define CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff 1060 1061 #define CRT_HORIZONTAL_SYNC 0x080210 1062 #define CRT_HORIZONTAL_SYNC_WIDTH_SHIFT 16 1063 #define CRT_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16) 1064 #define CRT_HORIZONTAL_SYNC_START_MASK 0xfff 1065 1066 #define CRT_VERTICAL_TOTAL 0x080214 1067 #define CRT_VERTICAL_TOTAL_TOTAL_SHIFT 16 1068 #define CRT_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16) 1069 #define CRT_VERTICAL_TOTAL_DISPLAY_END_MASK (0x7ff) 1070 1071 #define CRT_VERTICAL_SYNC 0x080218 1072 #define CRT_VERTICAL_SYNC_HEIGHT_SHIFT 16 1073 #define CRT_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16) 1074 #define CRT_VERTICAL_SYNC_START_MASK 0x7ff 1075 1076 #define CRT_SIGNATURE_ANALYZER 0x08021C 1077 #define CRT_SIGNATURE_ANALYZER_STATUS_MASK (0xffff << 16) 1078 #define CRT_SIGNATURE_ANALYZER_ENABLE BIT(3) 1079 #define CRT_SIGNATURE_ANALYZER_RESET BIT(2) 1080 #define CRT_SIGNATURE_ANALYZER_SOURCE_MASK 0x3 1081 #define CRT_SIGNATURE_ANALYZER_SOURCE_RED 0 1082 #define CRT_SIGNATURE_ANALYZER_SOURCE_GREEN 1 1083 #define CRT_SIGNATURE_ANALYZER_SOURCE_BLUE 2 1084 1085 #define CRT_CURRENT_LINE 0x080220 1086 #define CRT_CURRENT_LINE_LINE_MASK 0x7ff 1087 1088 #define CRT_MONITOR_DETECT 0x080224 1089 #define CRT_MONITOR_DETECT_VALUE BIT(25) 1090 #define CRT_MONITOR_DETECT_ENABLE BIT(24) 1091 #define CRT_MONITOR_DETECT_RED_MASK (0xff << 16) 1092 #define CRT_MONITOR_DETECT_GREEN_MASK (0xff << 8) 1093 #define CRT_MONITOR_DETECT_BLUE_MASK 0xff 1094 1095 #define CRT_SCALE 0x080228 1096 #define CRT_SCALE_VERTICAL_MODE BIT(31) 1097 #define CRT_SCALE_VERTICAL_SCALE_MASK (0xfff << 16) 1098 #define CRT_SCALE_HORIZONTAL_MODE BIT(15) 1099 #define CRT_SCALE_HORIZONTAL_SCALE_MASK 0xfff 1100 1101 /* CRT Cursor Control */ 1102 1103 #define CRT_HWC_ADDRESS 0x080230 1104 #define CRT_HWC_ADDRESS_ENABLE BIT(31) 1105 #define CRT_HWC_ADDRESS_EXT BIT(27) 1106 #define CRT_HWC_ADDRESS_ADDRESS_MASK 0x3ffffff 1107 1108 #define CRT_HWC_LOCATION 0x080234 1109 #define CRT_HWC_LOCATION_TOP BIT(27) 1110 #define CRT_HWC_LOCATION_Y_MASK (0x7ff << 16) 1111 #define CRT_HWC_LOCATION_LEFT BIT(11) 1112 #define CRT_HWC_LOCATION_X_MASK 0x7ff 1113 1114 #define CRT_HWC_COLOR_12 0x080238 1115 #define CRT_HWC_COLOR_12_2_RGB565_MASK (0xffff << 16) 1116 #define CRT_HWC_COLOR_12_1_RGB565_MASK 0xffff 1117 1118 #define CRT_HWC_COLOR_3 0x08023C 1119 #define CRT_HWC_COLOR_3_RGB565_MASK 0xffff 1120 1121 /* This vertical expansion below start at 0x080240 ~ 0x080264 */ 1122 #define CRT_VERTICAL_EXPANSION 0x080240 1123 #ifndef VALIDATION_CHIP 1124 #define CRT_VERTICAL_CENTERING_VALUE_MASK (0xff << 24) 1125 #endif 1126 #define CRT_VERTICAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) 1127 #define CRT_VERTICAL_EXPANSION_LINE_BUFFER_MASK (0xf << 12) 1128 #define CRT_VERTICAL_EXPANSION_SCALE_FACTOR_MASK 0xfff 1129 1130 /* This horizontal expansion below start at 0x080268 ~ 0x08027C */ 1131 #define CRT_HORIZONTAL_EXPANSION 0x080268 1132 #ifndef VALIDATION_CHIP 1133 #define CRT_HORIZONTAL_CENTERING_VALUE_MASK (0xff << 24) 1134 #endif 1135 #define CRT_HORIZONTAL_EXPANSION_COMPARE_VALUE_MASK (0xff << 16) 1136 #define CRT_HORIZONTAL_EXPANSION_SCALE_FACTOR_MASK 0xfff 1137 1138 #ifndef VALIDATION_CHIP 1139 /* Auto Centering */ 1140 #define CRT_AUTO_CENTERING_TL 0x080280 1141 #define CRT_AUTO_CENTERING_TL_TOP_MASK (0x7ff << 16) 1142 #define CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7ff 1143 1144 #define CRT_AUTO_CENTERING_BR 0x080284 1145 #define CRT_AUTO_CENTERING_BR_BOTTOM_MASK (0x7ff << 16) 1146 #define CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT 16 1147 #define CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7ff 1148 #endif 1149 1150 /* sm750le new register to control panel output */ 1151 #define DISPLAY_CONTROL_750LE 0x80288 1152 /* Palette RAM */ 1153 1154 /* Panel Palette register starts at 0x080400 ~ 0x0807FC */ 1155 #define PANEL_PALETTE_RAM 0x080400 1156 1157 /* Panel Palette register starts at 0x080C00 ~ 0x080FFC */ 1158 #define CRT_PALETTE_RAM 0x080C00 1159 1160 /* Color Space Conversion registers. */ 1161 1162 #define CSC_Y_SOURCE_BASE 0x1000C8 1163 #define CSC_Y_SOURCE_BASE_EXT BIT(27) 1164 #define CSC_Y_SOURCE_BASE_CS BIT(26) 1165 #define CSC_Y_SOURCE_BASE_ADDRESS_MASK 0x3ffffff 1166 1167 #define CSC_CONSTANTS 0x1000CC 1168 #define CSC_CONSTANTS_Y_MASK (0xff << 24) 1169 #define CSC_CONSTANTS_R_MASK (0xff << 16) 1170 #define CSC_CONSTANTS_G_MASK (0xff << 8) 1171 #define CSC_CONSTANTS_B_MASK 0xff 1172 1173 #define CSC_Y_SOURCE_X 0x1000D0 1174 #define CSC_Y_SOURCE_X_INTEGER_MASK (0x7ff << 16) 1175 #define CSC_Y_SOURCE_X_FRACTION_MASK (0x1fff << 3) 1176 1177 #define CSC_Y_SOURCE_Y 0x1000D4 1178 #define CSC_Y_SOURCE_Y_INTEGER_MASK (0xfff << 16) 1179 #define CSC_Y_SOURCE_Y_FRACTION_MASK (0x1fff << 3) 1180 1181 #define CSC_U_SOURCE_BASE 0x1000D8 1182 #define CSC_U_SOURCE_BASE_EXT BIT(27) 1183 #define CSC_U_SOURCE_BASE_CS BIT(26) 1184 #define CSC_U_SOURCE_BASE_ADDRESS_MASK 0x3ffffff 1185 1186 #define CSC_V_SOURCE_BASE 0x1000DC 1187 #define CSC_V_SOURCE_BASE_EXT BIT(27) 1188 #define CSC_V_SOURCE_BASE_CS BIT(26) 1189 #define CSC_V_SOURCE_BASE_ADDRESS_MASK 0x3ffffff 1190 1191 #define CSC_SOURCE_DIMENSION 0x1000E0 1192 #define CSC_SOURCE_DIMENSION_X_MASK (0xffff << 16) 1193 #define CSC_SOURCE_DIMENSION_Y_MASK 0xffff 1194 1195 #define CSC_SOURCE_PITCH 0x1000E4 1196 #define CSC_SOURCE_PITCH_Y_MASK (0xffff << 16) 1197 #define CSC_SOURCE_PITCH_UV_MASK 0xffff 1198 1199 #define CSC_DESTINATION 0x1000E8 1200 #define CSC_DESTINATION_WRAP BIT(31) 1201 #define CSC_DESTINATION_X_MASK (0xfff << 16) 1202 #define CSC_DESTINATION_Y_MASK 0xfff 1203 1204 #define CSC_DESTINATION_DIMENSION 0x1000EC 1205 #define CSC_DESTINATION_DIMENSION_X_MASK (0xffff << 16) 1206 #define CSC_DESTINATION_DIMENSION_Y_MASK 0xffff 1207 1208 #define CSC_DESTINATION_PITCH 0x1000F0 1209 #define CSC_DESTINATION_PITCH_X_MASK (0xffff << 16) 1210 #define CSC_DESTINATION_PITCH_Y_MASK 0xffff 1211 1212 #define CSC_SCALE_FACTOR 0x1000F4 1213 #define CSC_SCALE_FACTOR_HORIZONTAL_MASK (0xffff << 16) 1214 #define CSC_SCALE_FACTOR_VERTICAL_MASK 0xffff 1215 1216 #define CSC_DESTINATION_BASE 0x1000F8 1217 #define CSC_DESTINATION_BASE_EXT BIT(27) 1218 #define CSC_DESTINATION_BASE_CS BIT(26) 1219 #define CSC_DESTINATION_BASE_ADDRESS_MASK 0x3ffffff 1220 1221 #define CSC_CONTROL 0x1000FC 1222 #define CSC_CONTROL_STATUS BIT(31) 1223 #define CSC_CONTROL_SOURCE_FORMAT_MASK (0x7 << 28) 1224 #define CSC_CONTROL_SOURCE_FORMAT_YUV422 (0x0 << 28) 1225 #define CSC_CONTROL_SOURCE_FORMAT_YUV420I (0x1 << 28) 1226 #define CSC_CONTROL_SOURCE_FORMAT_YUV420 (0x2 << 28) 1227 #define CSC_CONTROL_SOURCE_FORMAT_YVU9 (0x3 << 28) 1228 #define CSC_CONTROL_SOURCE_FORMAT_IYU1 (0x4 << 28) 1229 #define CSC_CONTROL_SOURCE_FORMAT_IYU2 (0x5 << 28) 1230 #define CSC_CONTROL_SOURCE_FORMAT_RGB565 (0x6 << 28) 1231 #define CSC_CONTROL_SOURCE_FORMAT_RGB8888 (0x7 << 28) 1232 #define CSC_CONTROL_DESTINATION_FORMAT_MASK (0x3 << 26) 1233 #define CSC_CONTROL_DESTINATION_FORMAT_RGB565 (0x0 << 26) 1234 #define CSC_CONTROL_DESTINATION_FORMAT_RGB8888 (0x1 << 26) 1235 #define CSC_CONTROL_HORIZONTAL_FILTER BIT(25) 1236 #define CSC_CONTROL_VERTICAL_FILTER BIT(24) 1237 #define CSC_CONTROL_BYTE_ORDER BIT(23) 1238 1239 #define DE_DATA_PORT 0x110000 1240 1241 #define I2C_BYTE_COUNT 0x010040 1242 #define I2C_BYTE_COUNT_COUNT_MASK 0xf 1243 1244 #define I2C_CTRL 0x010041 1245 #define I2C_CTRL_INT BIT(4) 1246 #define I2C_CTRL_DIR BIT(3) 1247 #define I2C_CTRL_CTRL BIT(2) 1248 #define I2C_CTRL_MODE BIT(1) 1249 #define I2C_CTRL_EN BIT(0) 1250 1251 #define I2C_STATUS 0x010042 1252 #define I2C_STATUS_TX BIT(3) 1253 #define I2C_STATUS_ERR BIT(2) 1254 #define I2C_STATUS_ACK BIT(1) 1255 #define I2C_STATUS_BSY BIT(0) 1256 1257 #define I2C_RESET 0x010042 1258 #define I2C_RESET_BUS_ERROR BIT(2) 1259 1260 #define I2C_SLAVE_ADDRESS 0x010043 1261 #define I2C_SLAVE_ADDRESS_ADDRESS_MASK (0x7f << 1) 1262 #define I2C_SLAVE_ADDRESS_RW BIT(0) 1263 1264 #define I2C_DATA0 0x010044 1265 #define I2C_DATA1 0x010045 1266 #define I2C_DATA2 0x010046 1267 #define I2C_DATA3 0x010047 1268 #define I2C_DATA4 0x010048 1269 #define I2C_DATA5 0x010049 1270 #define I2C_DATA6 0x01004A 1271 #define I2C_DATA7 0x01004B 1272 #define I2C_DATA8 0x01004C 1273 #define I2C_DATA9 0x01004D 1274 #define I2C_DATA10 0x01004E 1275 #define I2C_DATA11 0x01004F 1276 #define I2C_DATA12 0x010050 1277 #define I2C_DATA13 0x010051 1278 #define I2C_DATA14 0x010052 1279 #define I2C_DATA15 0x010053 1280 1281 #define ZV0_CAPTURE_CTRL 0x090000 1282 #define ZV0_CAPTURE_CTRL_FIELD_INPUT BIT(27) 1283 #define ZV0_CAPTURE_CTRL_SCAN BIT(26) 1284 #define ZV0_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) 1285 #define ZV0_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) 1286 #define ZV0_CAPTURE_CTRL_ADJ BIT(19) 1287 #define ZV0_CAPTURE_CTRL_HA BIT(18) 1288 #define ZV0_CAPTURE_CTRL_VSK BIT(17) 1289 #define ZV0_CAPTURE_CTRL_HSK BIT(16) 1290 #define ZV0_CAPTURE_CTRL_FD BIT(15) 1291 #define ZV0_CAPTURE_CTRL_VP BIT(14) 1292 #define ZV0_CAPTURE_CTRL_HP BIT(13) 1293 #define ZV0_CAPTURE_CTRL_CP BIT(12) 1294 #define ZV0_CAPTURE_CTRL_UVS BIT(11) 1295 #define ZV0_CAPTURE_CTRL_BS BIT(10) 1296 #define ZV0_CAPTURE_CTRL_CS BIT(9) 1297 #define ZV0_CAPTURE_CTRL_CF BIT(8) 1298 #define ZV0_CAPTURE_CTRL_FS BIT(7) 1299 #define ZV0_CAPTURE_CTRL_WEAVE BIT(6) 1300 #define ZV0_CAPTURE_CTRL_BOB BIT(5) 1301 #define ZV0_CAPTURE_CTRL_DB BIT(4) 1302 #define ZV0_CAPTURE_CTRL_CC BIT(3) 1303 #define ZV0_CAPTURE_CTRL_RGB BIT(2) 1304 #define ZV0_CAPTURE_CTRL_656 BIT(1) 1305 #define ZV0_CAPTURE_CTRL_CAP BIT(0) 1306 1307 #define ZV0_CAPTURE_CLIP 0x090004 1308 #define ZV0_CAPTURE_CLIP_EYCLIP_MASK (0x3ff << 16) 1309 #define ZV0_CAPTURE_CLIP_XCLIP_MASK 0x3ff 1310 1311 #define ZV0_CAPTURE_SIZE 0x090008 1312 #define ZV0_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) 1313 #define ZV0_CAPTURE_SIZE_WIDTH_MASK 0x7ff 1314 1315 #define ZV0_CAPTURE_BUF0_ADDRESS 0x09000C 1316 #define ZV0_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) 1317 #define ZV0_CAPTURE_BUF0_ADDRESS_EXT BIT(27) 1318 #define ZV0_CAPTURE_BUF0_ADDRESS_CS BIT(26) 1319 #define ZV0_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff 1320 1321 #define ZV0_CAPTURE_BUF1_ADDRESS 0x090010 1322 #define ZV0_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) 1323 #define ZV0_CAPTURE_BUF1_ADDRESS_EXT BIT(27) 1324 #define ZV0_CAPTURE_BUF1_ADDRESS_CS BIT(26) 1325 #define ZV0_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff 1326 1327 #define ZV0_CAPTURE_BUF_OFFSET 0x090014 1328 #ifndef VALIDATION_CHIP 1329 #define ZV0_CAPTURE_BUF_OFFSET_YCLIP_ODD_FIELD (0x3ff << 16) 1330 #endif 1331 #define ZV0_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff 1332 1333 #define ZV0_CAPTURE_FIFO_CTRL 0x090018 1334 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 1335 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_0 0 1336 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_1 1 1337 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_2 2 1338 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_3 3 1339 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_4 4 1340 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_5 5 1341 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_6 6 1342 #define ZV0_CAPTURE_FIFO_CTRL_FIFO_7 7 1343 1344 #define ZV0_CAPTURE_YRGB_CONST 0x09001C 1345 #define ZV0_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) 1346 #define ZV0_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) 1347 #define ZV0_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) 1348 #define ZV0_CAPTURE_YRGB_CONST_B_MASK 0xff 1349 1350 #define ZV0_CAPTURE_LINE_COMP 0x090020 1351 #define ZV0_CAPTURE_LINE_COMP_LC_MASK 0x7ff 1352 1353 /* ZV1 */ 1354 1355 #define ZV1_CAPTURE_CTRL 0x098000 1356 #define ZV1_CAPTURE_CTRL_FIELD_INPUT BIT(27) 1357 #define ZV1_CAPTURE_CTRL_SCAN BIT(26) 1358 #define ZV1_CAPTURE_CTRL_CURRENT_BUFFER BIT(25) 1359 #define ZV1_CAPTURE_CTRL_VERTICAL_SYNC BIT(24) 1360 #define ZV1_CAPTURE_CTRL_PANEL BIT(20) 1361 #define ZV1_CAPTURE_CTRL_ADJ BIT(19) 1362 #define ZV1_CAPTURE_CTRL_HA BIT(18) 1363 #define ZV1_CAPTURE_CTRL_VSK BIT(17) 1364 #define ZV1_CAPTURE_CTRL_HSK BIT(16) 1365 #define ZV1_CAPTURE_CTRL_FD BIT(15) 1366 #define ZV1_CAPTURE_CTRL_VP BIT(14) 1367 #define ZV1_CAPTURE_CTRL_HP BIT(13) 1368 #define ZV1_CAPTURE_CTRL_CP BIT(12) 1369 #define ZV1_CAPTURE_CTRL_UVS BIT(11) 1370 #define ZV1_CAPTURE_CTRL_BS BIT(10) 1371 #define ZV1_CAPTURE_CTRL_CS BIT(9) 1372 #define ZV1_CAPTURE_CTRL_CF BIT(8) 1373 #define ZV1_CAPTURE_CTRL_FS BIT(7) 1374 #define ZV1_CAPTURE_CTRL_WEAVE BIT(6) 1375 #define ZV1_CAPTURE_CTRL_BOB BIT(5) 1376 #define ZV1_CAPTURE_CTRL_DB BIT(4) 1377 #define ZV1_CAPTURE_CTRL_CC BIT(3) 1378 #define ZV1_CAPTURE_CTRL_RGB BIT(2) 1379 #define ZV1_CAPTURE_CTRL_656 BIT(1) 1380 #define ZV1_CAPTURE_CTRL_CAP BIT(0) 1381 1382 #define ZV1_CAPTURE_CLIP 0x098004 1383 #define ZV1_CAPTURE_CLIP_YCLIP_MASK (0x3ff << 16) 1384 #define ZV1_CAPTURE_CLIP_XCLIP_MASK 0x3ff 1385 1386 #define ZV1_CAPTURE_SIZE 0x098008 1387 #define ZV1_CAPTURE_SIZE_HEIGHT_MASK (0x7ff << 16) 1388 #define ZV1_CAPTURE_SIZE_WIDTH_MASK 0x7ff 1389 1390 #define ZV1_CAPTURE_BUF0_ADDRESS 0x09800C 1391 #define ZV1_CAPTURE_BUF0_ADDRESS_STATUS BIT(31) 1392 #define ZV1_CAPTURE_BUF0_ADDRESS_EXT BIT(27) 1393 #define ZV1_CAPTURE_BUF0_ADDRESS_CS BIT(26) 1394 #define ZV1_CAPTURE_BUF0_ADDRESS_ADDRESS_MASK 0x3ffffff 1395 1396 #define ZV1_CAPTURE_BUF1_ADDRESS 0x098010 1397 #define ZV1_CAPTURE_BUF1_ADDRESS_STATUS BIT(31) 1398 #define ZV1_CAPTURE_BUF1_ADDRESS_EXT BIT(27) 1399 #define ZV1_CAPTURE_BUF1_ADDRESS_CS BIT(26) 1400 #define ZV1_CAPTURE_BUF1_ADDRESS_ADDRESS_MASK 0x3ffffff 1401 1402 #define ZV1_CAPTURE_BUF_OFFSET 0x098014 1403 #define ZV1_CAPTURE_BUF_OFFSET_OFFSET_MASK 0xffff 1404 1405 #define ZV1_CAPTURE_FIFO_CTRL 0x098018 1406 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_MASK 0x7 1407 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_0 0 1408 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_1 1 1409 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_2 2 1410 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_3 3 1411 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_4 4 1412 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_5 5 1413 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_6 6 1414 #define ZV1_CAPTURE_FIFO_CTRL_FIFO_7 7 1415 1416 #define ZV1_CAPTURE_YRGB_CONST 0x09801C 1417 #define ZV1_CAPTURE_YRGB_CONST_Y_MASK (0xff << 24) 1418 #define ZV1_CAPTURE_YRGB_CONST_R_MASK (0xff << 16) 1419 #define ZV1_CAPTURE_YRGB_CONST_G_MASK (0xff << 8) 1420 #define ZV1_CAPTURE_YRGB_CONST_B_MASK 0xff 1421 1422 #define DMA_1_SOURCE 0x0D0010 1423 #define DMA_1_SOURCE_ADDRESS_EXT BIT(27) 1424 #define DMA_1_SOURCE_ADDRESS_CS BIT(26) 1425 #define DMA_1_SOURCE_ADDRESS_MASK 0x3ffffff 1426 1427 #define DMA_1_DESTINATION 0x0D0014 1428 #define DMA_1_DESTINATION_ADDRESS_EXT BIT(27) 1429 #define DMA_1_DESTINATION_ADDRESS_CS BIT(26) 1430 #define DMA_1_DESTINATION_ADDRESS_MASK 0x3ffffff 1431 1432 #define DMA_1_SIZE_CONTROL 0x0D0018 1433 #define DMA_1_SIZE_CONTROL_STATUS BIT(31) 1434 #define DMA_1_SIZE_CONTROL_SIZE_MASK 0xffffff 1435 1436 #define DMA_ABORT_INTERRUPT 0x0D0020 1437 #define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5) 1438 #define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4) 1439 #define DMA_ABORT_INTERRUPT_INT_1 BIT(1) 1440 #define DMA_ABORT_INTERRUPT_INT_0 BIT(0) 1441 1442 /* Default i2c CLK and Data GPIO. These are the default i2c pins */ 1443 #define DEFAULT_I2C_SCL 30 1444 #define DEFAULT_I2C_SDA 31 1445 1446 #define GPIO_DATA_SM750LE 0x020018 1447 #define GPIO_DATA_SM750LE_1 BIT(1) 1448 #define GPIO_DATA_SM750LE_0 BIT(0) 1449 1450 #define GPIO_DATA_DIRECTION_SM750LE 0x02001C 1451 #define GPIO_DATA_DIRECTION_SM750LE_1 BIT(1) 1452 #define GPIO_DATA_DIRECTION_SM750LE_0 BIT(0) 1453 1454 #endif 1455