1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 281dee67eSSudip Mukherjee #ifndef DDK750_MODE_H__ 381dee67eSSudip Mukherjee #define DDK750_MODE_H__ 481dee67eSSudip Mukherjee 581dee67eSSudip Mukherjee #include "ddk750_chip.h" 681dee67eSSudip Mukherjee 7ff49304bSArushi Singhal enum spolarity { 881dee67eSSudip Mukherjee POS = 0, /* positive */ 981dee67eSSudip Mukherjee NEG, /* negative */ 10ff49304bSArushi Singhal }; 1181dee67eSSudip Mukherjee 12bf760231SArushi Singhal struct mode_parameter { 1381dee67eSSudip Mukherjee /* Horizontal timing. */ 1481dee67eSSudip Mukherjee unsigned long horizontal_total; 1581dee67eSSudip Mukherjee unsigned long horizontal_display_end; 1681dee67eSSudip Mukherjee unsigned long horizontal_sync_start; 1781dee67eSSudip Mukherjee unsigned long horizontal_sync_width; 18ff49304bSArushi Singhal enum spolarity horizontal_sync_polarity; 1981dee67eSSudip Mukherjee 2081dee67eSSudip Mukherjee /* Vertical timing. */ 2181dee67eSSudip Mukherjee unsigned long vertical_total; 2281dee67eSSudip Mukherjee unsigned long vertical_display_end; 2381dee67eSSudip Mukherjee unsigned long vertical_sync_start; 2481dee67eSSudip Mukherjee unsigned long vertical_sync_height; 25ff49304bSArushi Singhal enum spolarity vertical_sync_polarity; 2681dee67eSSudip Mukherjee 2781dee67eSSudip Mukherjee /* Refresh timing. */ 2881dee67eSSudip Mukherjee unsigned long pixel_clock; 2981dee67eSSudip Mukherjee unsigned long horizontal_frequency; 3081dee67eSSudip Mukherjee unsigned long vertical_frequency; 3181dee67eSSudip Mukherjee 3281dee67eSSudip Mukherjee /* Clock Phase. This clock phase only applies to Panel. */ 33ff49304bSArushi Singhal enum spolarity clock_phase_polarity; 34bf760231SArushi Singhal }; 3581dee67eSSudip Mukherjee 3617eb0b29SChristian Luetke-Stetzkamp int ddk750_setModeTiming(struct mode_parameter *parm, enum clock_type clock); 3781dee67eSSudip Mukherjee #endif 38