181dee67eSSudip Mukherjee #ifndef DDK750_DISPLAY_H__
281dee67eSSudip Mukherjee #define DDK750_DISPLAY_H__
381dee67eSSudip Mukherjee 
481dee67eSSudip Mukherjee /* panel path select
535e4d8caSElizabeth Ferdman  *	80000[29:28]
681dee67eSSudip Mukherjee  */
781dee67eSSudip Mukherjee 
881dee67eSSudip Mukherjee #define PNL_2_OFFSET 0
981dee67eSSudip Mukherjee #define PNL_2_MASK (3 << PNL_2_OFFSET)
1081dee67eSSudip Mukherjee #define PNL_2_USAGE	(PNL_2_MASK << 16)
1181dee67eSSudip Mukherjee #define PNL_2_PRI	((0 << PNL_2_OFFSET) | PNL_2_USAGE)
1281dee67eSSudip Mukherjee #define PNL_2_SEC	((2 << PNL_2_OFFSET) | PNL_2_USAGE)
1381dee67eSSudip Mukherjee 
1481dee67eSSudip Mukherjee 
1581dee67eSSudip Mukherjee /* primary timing & plane enable bit
1635e4d8caSElizabeth Ferdman  *	1: 80000[8] & 80000[2] on
1735e4d8caSElizabeth Ferdman  *	0: both off
1881dee67eSSudip Mukherjee  */
1981dee67eSSudip Mukherjee #define PRI_TP_OFFSET 4
20a5eabae9SAmitoj Kaur Chawla #define PRI_TP_MASK BIT(PRI_TP_OFFSET)
2181dee67eSSudip Mukherjee #define PRI_TP_USAGE (PRI_TP_MASK << 16)
2281dee67eSSudip Mukherjee #define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE)
2381dee67eSSudip Mukherjee #define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE)
2481dee67eSSudip Mukherjee 
2581dee67eSSudip Mukherjee 
2681dee67eSSudip Mukherjee /* panel sequency status
2735e4d8caSElizabeth Ferdman  *	80000[27:24]
2881dee67eSSudip Mukherjee  */
2981dee67eSSudip Mukherjee #define PNL_SEQ_OFFSET 6
30a5eabae9SAmitoj Kaur Chawla #define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET)
3181dee67eSSudip Mukherjee #define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16)
32a5eabae9SAmitoj Kaur Chawla #define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
3381dee67eSSudip Mukherjee #define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE)
3481dee67eSSudip Mukherjee 
3581dee67eSSudip Mukherjee /* dual digital output
3635e4d8caSElizabeth Ferdman  *	80000[19]
3781dee67eSSudip Mukherjee  */
3881dee67eSSudip Mukherjee #define DUAL_TFT_OFFSET 8
39a5eabae9SAmitoj Kaur Chawla #define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET)
4081dee67eSSudip Mukherjee #define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16)
41a5eabae9SAmitoj Kaur Chawla #define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
4281dee67eSSudip Mukherjee #define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE)
4381dee67eSSudip Mukherjee 
4481dee67eSSudip Mukherjee /* secondary timing & plane enable bit
4535e4d8caSElizabeth Ferdman  *	1:80200[8] & 80200[2] on
4635e4d8caSElizabeth Ferdman  *	0: both off
4781dee67eSSudip Mukherjee  */
4881dee67eSSudip Mukherjee #define SEC_TP_OFFSET 5
49a5eabae9SAmitoj Kaur Chawla #define SEC_TP_MASK BIT(SEC_TP_OFFSET)
5081dee67eSSudip Mukherjee #define SEC_TP_USAGE (SEC_TP_MASK << 16)
5181dee67eSSudip Mukherjee #define SEC_TP_ON  ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE)
5281dee67eSSudip Mukherjee #define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE)
5381dee67eSSudip Mukherjee 
5481dee67eSSudip Mukherjee /* crt path select
5535e4d8caSElizabeth Ferdman  *	80200[19:18]
5681dee67eSSudip Mukherjee  */
5781dee67eSSudip Mukherjee #define CRT_2_OFFSET 2
5881dee67eSSudip Mukherjee #define CRT_2_MASK (3 << CRT_2_OFFSET)
5981dee67eSSudip Mukherjee #define CRT_2_USAGE (CRT_2_MASK << 16)
6081dee67eSSudip Mukherjee #define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE)
6181dee67eSSudip Mukherjee #define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE)
6281dee67eSSudip Mukherjee 
6381dee67eSSudip Mukherjee 
6481dee67eSSudip Mukherjee /* DAC affect both DVI and DSUB
6535e4d8caSElizabeth Ferdman  *	4[20]
6681dee67eSSudip Mukherjee  */
6781dee67eSSudip Mukherjee #define DAC_OFFSET 7
68a5eabae9SAmitoj Kaur Chawla #define DAC_MASK BIT(DAC_OFFSET)
6981dee67eSSudip Mukherjee #define DAC_USAGE (DAC_MASK << 16)
7081dee67eSSudip Mukherjee #define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE)
7181dee67eSSudip Mukherjee #define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE)
7281dee67eSSudip Mukherjee 
7381dee67eSSudip Mukherjee /* DPMS only affect D-SUB head
7435e4d8caSElizabeth Ferdman  *	0[31:30]
7581dee67eSSudip Mukherjee  */
7681dee67eSSudip Mukherjee #define DPMS_OFFSET 9
7781dee67eSSudip Mukherjee #define DPMS_MASK (3 << DPMS_OFFSET)
7881dee67eSSudip Mukherjee #define DPMS_USAGE (DPMS_MASK << 16)
7981dee67eSSudip Mukherjee #define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE)
8081dee67eSSudip Mukherjee #define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE)
8181dee67eSSudip Mukherjee 
8281dee67eSSudip Mukherjee 
8381dee67eSSudip Mukherjee 
8435e4d8caSElizabeth Ferdman /* LCD1 means panel path TFT1  & panel path DVI (so enable DAC)
8535e4d8caSElizabeth Ferdman  * CRT means crt path DSUB
8681dee67eSSudip Mukherjee  */
8781dee67eSSudip Mukherjee typedef enum _disp_output_t {
8881dee67eSSudip Mukherjee 	do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON,
8981dee67eSSudip Mukherjee 	do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON,
9081dee67eSSudip Mukherjee 	do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON,
9181dee67eSSudip Mukherjee 	do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON,
9235e4d8caSElizabeth Ferdman 	/* do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON,
9335e4d8caSElizabeth Ferdman 	 * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON,
9481dee67eSSudip Mukherjee 	 */
9581dee67eSSudip Mukherjee 	do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON,
9681dee67eSSudip Mukherjee 	do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON,
9781dee67eSSudip Mukherjee }
9881dee67eSSudip Mukherjee disp_output_t;
9981dee67eSSudip Mukherjee 
10081dee67eSSudip Mukherjee void ddk750_setLogicalDispOut(disp_output_t);
10181dee67eSSudip Mukherjee 
10281dee67eSSudip Mukherjee #endif
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