1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 281dee67eSSudip Mukherjee #ifndef DDK750_DISPLAY_H__ 381dee67eSSudip Mukherjee #define DDK750_DISPLAY_H__ 481dee67eSSudip Mukherjee 5f5016082SEric S. Stone /* 6f5016082SEric S. Stone * panel path select 735e4d8caSElizabeth Ferdman * 80000[29:28] 881dee67eSSudip Mukherjee */ 981dee67eSSudip Mukherjee 1081dee67eSSudip Mukherjee #define PNL_2_OFFSET 0 1181dee67eSSudip Mukherjee #define PNL_2_MASK (3 << PNL_2_OFFSET) 1281dee67eSSudip Mukherjee #define PNL_2_USAGE (PNL_2_MASK << 16) 1381dee67eSSudip Mukherjee #define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE) 1481dee67eSSudip Mukherjee #define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE) 1581dee67eSSudip Mukherjee 16f5016082SEric S. Stone /* 17f5016082SEric S. Stone * primary timing & plane enable bit 1835e4d8caSElizabeth Ferdman * 1: 80000[8] & 80000[2] on 1935e4d8caSElizabeth Ferdman * 0: both off 2081dee67eSSudip Mukherjee */ 2181dee67eSSudip Mukherjee #define PRI_TP_OFFSET 4 22a5eabae9SAmitoj Kaur Chawla #define PRI_TP_MASK BIT(PRI_TP_OFFSET) 2381dee67eSSudip Mukherjee #define PRI_TP_USAGE (PRI_TP_MASK << 16) 2481dee67eSSudip Mukherjee #define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE) 2581dee67eSSudip Mukherjee #define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE) 2681dee67eSSudip Mukherjee 27f5016082SEric S. Stone /* 28f5016082SEric S. Stone * panel sequency status 2935e4d8caSElizabeth Ferdman * 80000[27:24] 3081dee67eSSudip Mukherjee */ 3181dee67eSSudip Mukherjee #define PNL_SEQ_OFFSET 6 32a5eabae9SAmitoj Kaur Chawla #define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET) 3381dee67eSSudip Mukherjee #define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16) 34a5eabae9SAmitoj Kaur Chawla #define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) 3581dee67eSSudip Mukherjee #define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) 3681dee67eSSudip Mukherjee 37f5016082SEric S. Stone /* 38f5016082SEric S. Stone * dual digital output 3935e4d8caSElizabeth Ferdman * 80000[19] 4081dee67eSSudip Mukherjee */ 4181dee67eSSudip Mukherjee #define DUAL_TFT_OFFSET 8 42a5eabae9SAmitoj Kaur Chawla #define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET) 4381dee67eSSudip Mukherjee #define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16) 44a5eabae9SAmitoj Kaur Chawla #define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) 4581dee67eSSudip Mukherjee #define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) 4681dee67eSSudip Mukherjee 47f5016082SEric S. Stone /* 48f5016082SEric S. Stone * secondary timing & plane enable bit 4935e4d8caSElizabeth Ferdman * 1:80200[8] & 80200[2] on 5035e4d8caSElizabeth Ferdman * 0: both off 5181dee67eSSudip Mukherjee */ 5281dee67eSSudip Mukherjee #define SEC_TP_OFFSET 5 53a5eabae9SAmitoj Kaur Chawla #define SEC_TP_MASK BIT(SEC_TP_OFFSET) 5481dee67eSSudip Mukherjee #define SEC_TP_USAGE (SEC_TP_MASK << 16) 5581dee67eSSudip Mukherjee #define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE) 5681dee67eSSudip Mukherjee #define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE) 5781dee67eSSudip Mukherjee 58f5016082SEric S. Stone /* 59f5016082SEric S. Stone * crt path select 6035e4d8caSElizabeth Ferdman * 80200[19:18] 6181dee67eSSudip Mukherjee */ 6281dee67eSSudip Mukherjee #define CRT_2_OFFSET 2 6381dee67eSSudip Mukherjee #define CRT_2_MASK (3 << CRT_2_OFFSET) 6481dee67eSSudip Mukherjee #define CRT_2_USAGE (CRT_2_MASK << 16) 6581dee67eSSudip Mukherjee #define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE) 6681dee67eSSudip Mukherjee #define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE) 6781dee67eSSudip Mukherjee 68f5016082SEric S. Stone /* 69f5016082SEric S. Stone * DAC affect both DVI and DSUB 7035e4d8caSElizabeth Ferdman * 4[20] 7181dee67eSSudip Mukherjee */ 7281dee67eSSudip Mukherjee #define DAC_OFFSET 7 73a5eabae9SAmitoj Kaur Chawla #define DAC_MASK BIT(DAC_OFFSET) 7481dee67eSSudip Mukherjee #define DAC_USAGE (DAC_MASK << 16) 7581dee67eSSudip Mukherjee #define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE) 7681dee67eSSudip Mukherjee #define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE) 7781dee67eSSudip Mukherjee 78f5016082SEric S. Stone /* 79f5016082SEric S. Stone * DPMS only affect D-SUB head 8035e4d8caSElizabeth Ferdman * 0[31:30] 8181dee67eSSudip Mukherjee */ 8281dee67eSSudip Mukherjee #define DPMS_OFFSET 9 8381dee67eSSudip Mukherjee #define DPMS_MASK (3 << DPMS_OFFSET) 8481dee67eSSudip Mukherjee #define DPMS_USAGE (DPMS_MASK << 16) 8581dee67eSSudip Mukherjee #define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE) 8681dee67eSSudip Mukherjee #define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE) 8781dee67eSSudip Mukherjee 88f5016082SEric S. Stone /* 89f5016082SEric S. Stone * LCD1 means panel path TFT1 & panel path DVI (so enable DAC) 9035e4d8caSElizabeth Ferdman * CRT means crt path DSUB 9181dee67eSSudip Mukherjee */ 92ad7d95e9SNishka Dasgupta enum disp_output { 9381dee67eSSudip Mukherjee do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON, 9481dee67eSSudip Mukherjee do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON, 9581dee67eSSudip Mukherjee do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON, 9681dee67eSSudip Mukherjee do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON, 97f5016082SEric S. Stone /* 98f5016082SEric S. Stone * do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON, 9935e4d8caSElizabeth Ferdman * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON, 10081dee67eSSudip Mukherjee */ 10181dee67eSSudip Mukherjee do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON, 10281dee67eSSudip Mukherjee do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON, 103ad7d95e9SNishka Dasgupta }; 10481dee67eSSudip Mukherjee 10540197d07SVatsala Narang void ddk750_set_logical_disp_out(enum disp_output output); 10681dee67eSSudip Mukherjee 10781dee67eSSudip Mukherjee #endif 108