1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "rtsx_transport.h" 30 #include "rtsx_scsi.h" 31 #include "rtsx_card.h" 32 #include "xd.h" 33 34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no); 35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, 36 u8 start_page, u8 end_page); 37 38 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct xd_info *xd_card = &chip->xd_card; 41 42 xd_card->err_code = err_code; 43 } 44 45 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code) 46 { 47 struct xd_info *xd_card = &chip->xd_card; 48 49 return (xd_card->err_code == err_code); 50 } 51 52 static int xd_set_init_para(struct rtsx_chip *chip) 53 { 54 struct xd_info *xd_card = &chip->xd_card; 55 int retval; 56 57 if (chip->asic_code) 58 xd_card->xd_clock = 47; 59 else 60 xd_card->xd_clock = CLK_50; 61 62 retval = switch_clock(chip, xd_card->xd_clock); 63 if (retval != STATUS_SUCCESS) { 64 return STATUS_FAIL; 65 } 66 67 return STATUS_SUCCESS; 68 } 69 70 static int xd_switch_clock(struct rtsx_chip *chip) 71 { 72 struct xd_info *xd_card = &chip->xd_card; 73 int retval; 74 75 retval = select_card(chip, XD_CARD); 76 if (retval != STATUS_SUCCESS) { 77 return STATUS_FAIL; 78 } 79 80 retval = switch_clock(chip, xd_card->xd_clock); 81 if (retval != STATUS_SUCCESS) { 82 return STATUS_FAIL; 83 } 84 85 return STATUS_SUCCESS; 86 } 87 88 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) 89 { 90 int retval, i; 91 u8 *ptr; 92 93 rtsx_init_cmd(chip); 94 95 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); 96 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 97 XD_TRANSFER_START | XD_READ_ID); 98 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 99 XD_TRANSFER_END); 100 101 for (i = 0; i < 4; i++) 102 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); 103 104 retval = rtsx_send_cmd(chip, XD_CARD, 20); 105 if (retval < 0) { 106 return STATUS_FAIL; 107 } 108 109 ptr = rtsx_get_cmd_data(chip) + 1; 110 if (id_buf && buf_len) { 111 if (buf_len > 4) 112 buf_len = 4; 113 memcpy(id_buf, ptr, buf_len); 114 } 115 116 return STATUS_SUCCESS; 117 } 118 119 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode) 120 { 121 struct xd_info *xd_card = &chip->xd_card; 122 123 switch (mode) { 124 case XD_RW_ADDR: 125 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); 126 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); 127 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 128 0xFF, (u8)(addr >> 8)); 129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 130 0xFF, (u8)(addr >> 16)); 131 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 132 xd_card->addr_cycle | 133 XD_CALC_ECC | 134 XD_BA_NO_TRANSFORM); 135 break; 136 137 case XD_ERASE_ADDR: 138 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); 139 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 140 0xFF, (u8)(addr >> 8)); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 142 0xFF, (u8)(addr >> 16)); 143 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 144 (xd_card->addr_cycle - 1) | XD_CALC_ECC | 145 XD_BA_NO_TRANSFORM); 146 break; 147 148 default: 149 break; 150 } 151 } 152 153 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, 154 u8 *buf, int buf_len) 155 { 156 int retval, i; 157 158 rtsx_init_cmd(chip); 159 160 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 161 162 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 163 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); 164 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 165 XD_TRANSFER_END, XD_TRANSFER_END); 166 167 for (i = 0; i < 6; i++) 168 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 169 0, 0); 170 for (i = 0; i < 4; i++) 171 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 172 0, 0); 173 rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); 174 175 retval = rtsx_send_cmd(chip, XD_CARD, 500); 176 if (retval < 0) { 177 return STATUS_FAIL; 178 } 179 180 if (buf && buf_len) { 181 u8 *ptr = rtsx_get_cmd_data(chip) + 1; 182 183 if (buf_len > 11) 184 buf_len = 11; 185 memcpy(buf, ptr, buf_len); 186 } 187 188 return STATUS_SUCCESS; 189 } 190 191 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, 192 u8 *buf, int buf_len) 193 { 194 int retval, i; 195 196 if (!buf || (buf_len < 0)) { 197 return STATUS_FAIL; 198 } 199 200 rtsx_init_cmd(chip); 201 202 for (i = 0; i < buf_len; i++) 203 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 204 0, 0); 205 206 retval = rtsx_send_cmd(chip, 0, 250); 207 if (retval < 0) { 208 rtsx_clear_xd_error(chip); 209 return STATUS_FAIL; 210 } 211 212 memcpy(buf, rtsx_get_cmd_data(chip), buf_len); 213 214 return STATUS_SUCCESS; 215 } 216 217 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, 218 int buf_len) 219 { 220 int retval; 221 u8 reg; 222 223 if (!buf || (buf_len < 10)) { 224 return STATUS_FAIL; 225 } 226 227 rtsx_init_cmd(chip); 228 229 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 230 231 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 232 0x01, PINGPONG_BUFFER); 233 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 234 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 235 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 236 237 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 238 XD_TRANSFER_START | XD_READ_PAGES); 239 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 240 XD_TRANSFER_END); 241 242 retval = rtsx_send_cmd(chip, XD_CARD, 250); 243 if (retval == -ETIMEDOUT) { 244 rtsx_clear_xd_error(chip); 245 return STATUS_FAIL; 246 } 247 248 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®); 249 if (retval) { 250 return retval; 251 } 252 if (reg != XD_GPG) { 253 rtsx_clear_xd_error(chip); 254 return STATUS_FAIL; 255 } 256 257 retval = rtsx_read_register(chip, XD_CTL, ®); 258 if (retval) { 259 return retval; 260 } 261 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { 262 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); 263 if (retval != STATUS_SUCCESS) { 264 return STATUS_FAIL; 265 } 266 if (reg & XD_ECC1_ERROR) { 267 u8 ecc_bit, ecc_byte; 268 269 retval = rtsx_read_register(chip, XD_ECC_BIT1, 270 &ecc_bit); 271 if (retval) { 272 return retval; 273 } 274 retval = rtsx_read_register(chip, XD_ECC_BYTE1, 275 &ecc_byte); 276 if (retval) { 277 return retval; 278 } 279 280 dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", 281 ecc_bit, ecc_byte); 282 if (ecc_byte < buf_len) { 283 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 284 buf[ecc_byte]); 285 buf[ecc_byte] ^= (1 << ecc_bit); 286 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 287 buf[ecc_byte]); 288 } 289 } 290 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { 291 rtsx_clear_xd_error(chip); 292 293 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); 294 if (retval != STATUS_SUCCESS) { 295 return STATUS_FAIL; 296 } 297 if (reg & XD_ECC2_ERROR) { 298 u8 ecc_bit, ecc_byte; 299 300 retval = rtsx_read_register(chip, XD_ECC_BIT2, 301 &ecc_bit); 302 if (retval) { 303 return retval; 304 } 305 retval = rtsx_read_register(chip, XD_ECC_BYTE2, 306 &ecc_byte); 307 if (retval) { 308 return retval; 309 } 310 311 dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", 312 ecc_bit, ecc_byte); 313 if (ecc_byte < buf_len) { 314 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 315 buf[ecc_byte]); 316 buf[ecc_byte] ^= (1 << ecc_bit); 317 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 318 buf[ecc_byte]); 319 } 320 } 321 } else { 322 rtsx_clear_xd_error(chip); 323 return STATUS_FAIL; 324 } 325 326 return STATUS_SUCCESS; 327 } 328 329 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip) 330 { 331 if (CHECK_PID(chip, 0x5208)) { 332 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 333 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 334 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 335 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 336 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 337 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 338 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 339 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); 340 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 341 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 342 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 343 MS_D5_PD | MS_D4_PD); 344 } else if (CHECK_PID(chip, 0x5288)) { 345 if (CHECK_BARO_PKG(chip, QFN)) { 346 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 347 0xFF, 0x55); 348 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 349 0xFF, 0x55); 350 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 351 0xFF, 0x4B); 352 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 353 0xFF, 0x69); 354 } 355 } 356 } 357 358 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip) 359 { 360 if (CHECK_BARO_PKG(chip, QFN)) { 361 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55); 362 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55); 363 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B); 364 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55); 365 } 366 } 367 368 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) 369 { 370 if (CHECK_PID(chip, 0x5208)) { 371 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 372 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 373 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 374 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 375 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 376 XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU); 377 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 378 XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD); 379 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 380 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 381 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 382 MS_D5_PD | MS_D4_PD); 383 } else if (CHECK_PID(chip, 0x5288)) { 384 if (CHECK_BARO_PKG(chip, QFN)) { 385 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 386 0xFF, 0x55); 387 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 388 0xFF, 0x55); 389 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 390 0xFF, 0x53); 391 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 392 0xFF, 0xA9); 393 } 394 } 395 } 396 397 static int xd_pull_ctl_disable(struct rtsx_chip *chip) 398 { 399 int retval; 400 401 if (CHECK_PID(chip, 0x5208)) { 402 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 403 XD_D3_PD | 404 XD_D2_PD | 405 XD_D1_PD | 406 XD_D0_PD); 407 if (retval) { 408 return retval; 409 } 410 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 411 XD_D7_PD | 412 XD_D6_PD | 413 XD_D5_PD | 414 XD_D4_PD); 415 if (retval) { 416 return retval; 417 } 418 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 419 XD_WP_PD | 420 XD_CE_PD | 421 XD_CLE_PD | 422 XD_CD_PU); 423 if (retval) { 424 return retval; 425 } 426 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 427 XD_RDY_PD | 428 XD_WE_PD | 429 XD_RE_PD | 430 XD_ALE_PD); 431 if (retval) { 432 return retval; 433 } 434 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 435 MS_INS_PU | 436 SD_WP_PD | 437 SD_CD_PU | 438 SD_CMD_PD); 439 if (retval) { 440 return retval; 441 } 442 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 443 MS_D5_PD | MS_D4_PD); 444 if (retval) { 445 return retval; 446 } 447 } else if (CHECK_PID(chip, 0x5288)) { 448 if (CHECK_BARO_PKG(chip, QFN)) { 449 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 450 0xFF, 0x55); 451 if (retval) { 452 return retval; 453 } 454 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 455 0xFF, 0x55); 456 if (retval) { 457 return retval; 458 } 459 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 460 0xFF, 0x4B); 461 if (retval) { 462 return retval; 463 } 464 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 465 0xFF, 0x69); 466 if (retval) { 467 return retval; 468 } 469 } 470 } 471 472 return STATUS_SUCCESS; 473 } 474 475 static int reset_xd(struct rtsx_chip *chip) 476 { 477 struct xd_info *xd_card = &chip->xd_card; 478 int retval, i, j; 479 u8 *ptr, id_buf[4], redunt[11]; 480 481 retval = select_card(chip, XD_CARD); 482 if (retval != STATUS_SUCCESS) { 483 return STATUS_FAIL; 484 } 485 486 rtsx_init_cmd(chip); 487 488 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, 489 XD_PGSTS_NOT_FF); 490 if (chip->asic_code) { 491 if (!CHECK_PID(chip, 0x5288)) 492 xd_fill_pull_ctl_disable(chip); 493 else 494 xd_fill_pull_ctl_stage1_barossa(chip); 495 } else { 496 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 497 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 498 0x20); 499 } 500 501 if (!chip->ft2_fast_mode) 502 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, 503 XD_NO_AUTO_PWR_OFF, 0); 504 505 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); 506 507 retval = rtsx_send_cmd(chip, XD_CARD, 100); 508 if (retval < 0) { 509 return STATUS_FAIL; 510 } 511 512 if (!chip->ft2_fast_mode) { 513 retval = card_power_off(chip, XD_CARD); 514 if (retval != STATUS_SUCCESS) { 515 return STATUS_FAIL; 516 } 517 518 wait_timeout(250); 519 520 rtsx_init_cmd(chip); 521 522 if (chip->asic_code) { 523 xd_fill_pull_ctl_enable(chip); 524 } else { 525 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 526 (FPGA_XD_PULL_CTL_EN1 & 527 FPGA_XD_PULL_CTL_EN2) | 528 0x20); 529 } 530 531 retval = rtsx_send_cmd(chip, XD_CARD, 100); 532 if (retval < 0) { 533 return STATUS_FAIL; 534 } 535 536 retval = card_power_on(chip, XD_CARD); 537 if (retval != STATUS_SUCCESS) { 538 return STATUS_FAIL; 539 } 540 541 #ifdef SUPPORT_OCP 542 wait_timeout(50); 543 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 544 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 545 chip->ocp_stat); 546 return STATUS_FAIL; 547 } 548 #endif 549 } 550 551 rtsx_init_cmd(chip); 552 553 if (chip->ft2_fast_mode) { 554 if (chip->asic_code) { 555 xd_fill_pull_ctl_enable(chip); 556 } else { 557 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 558 (FPGA_XD_PULL_CTL_EN1 & 559 FPGA_XD_PULL_CTL_EN2) | 560 0x20); 561 } 562 } 563 564 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN); 565 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); 566 567 retval = rtsx_send_cmd(chip, XD_CARD, 100); 568 if (retval < 0) { 569 return STATUS_FAIL; 570 } 571 572 if (!chip->ft2_fast_mode) 573 wait_timeout(200); 574 575 retval = xd_set_init_para(chip); 576 if (retval != STATUS_SUCCESS) { 577 return STATUS_FAIL; 578 } 579 580 /* Read ID to check if the timing setting is right */ 581 for (i = 0; i < 4; i++) { 582 rtsx_init_cmd(chip); 583 584 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF, 585 XD_TIME_SETUP_STEP * 3 + 586 XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i); 587 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF, 588 XD_TIME_SETUP_STEP * 3 + 589 XD_TIME_RW_STEP * (4 + i) + 590 XD_TIME_RWN_STEP * (3 + i)); 591 592 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 593 XD_TRANSFER_START | XD_RESET); 594 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 595 XD_TRANSFER_END, XD_TRANSFER_END); 596 597 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 598 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 599 600 retval = rtsx_send_cmd(chip, XD_CARD, 100); 601 if (retval < 0) { 602 return STATUS_FAIL; 603 } 604 605 ptr = rtsx_get_cmd_data(chip) + 1; 606 607 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n", 608 ptr[0], ptr[1]); 609 610 if (((ptr[0] & READY_FLAG) != READY_STATE) || 611 !(ptr[1] & XD_RDY)) 612 continue; 613 614 retval = xd_read_id(chip, READ_ID, id_buf, 4); 615 if (retval != STATUS_SUCCESS) { 616 return STATUS_FAIL; 617 } 618 619 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n", 620 id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 621 622 xd_card->device_code = id_buf[1]; 623 624 /* Check if the xD card is supported */ 625 switch (xd_card->device_code) { 626 case XD_4M_X8_512_1: 627 case XD_4M_X8_512_2: 628 xd_card->block_shift = 4; 629 xd_card->page_off = 0x0F; 630 xd_card->addr_cycle = 3; 631 xd_card->zone_cnt = 1; 632 xd_card->capacity = 8000; 633 XD_SET_4MB(xd_card); 634 break; 635 case XD_8M_X8_512: 636 xd_card->block_shift = 4; 637 xd_card->page_off = 0x0F; 638 xd_card->addr_cycle = 3; 639 xd_card->zone_cnt = 1; 640 xd_card->capacity = 16000; 641 break; 642 case XD_16M_X8_512: 643 XD_PAGE_512(xd_card); 644 xd_card->addr_cycle = 3; 645 xd_card->zone_cnt = 1; 646 xd_card->capacity = 32000; 647 break; 648 case XD_32M_X8_512: 649 XD_PAGE_512(xd_card); 650 xd_card->addr_cycle = 3; 651 xd_card->zone_cnt = 2; 652 xd_card->capacity = 64000; 653 break; 654 case XD_64M_X8_512: 655 XD_PAGE_512(xd_card); 656 xd_card->addr_cycle = 4; 657 xd_card->zone_cnt = 4; 658 xd_card->capacity = 128000; 659 break; 660 case XD_128M_X8_512: 661 XD_PAGE_512(xd_card); 662 xd_card->addr_cycle = 4; 663 xd_card->zone_cnt = 8; 664 xd_card->capacity = 256000; 665 break; 666 case XD_256M_X8_512: 667 XD_PAGE_512(xd_card); 668 xd_card->addr_cycle = 4; 669 xd_card->zone_cnt = 16; 670 xd_card->capacity = 512000; 671 break; 672 case XD_512M_X8: 673 XD_PAGE_512(xd_card); 674 xd_card->addr_cycle = 4; 675 xd_card->zone_cnt = 32; 676 xd_card->capacity = 1024000; 677 break; 678 case xD_1G_X8_512: 679 XD_PAGE_512(xd_card); 680 xd_card->addr_cycle = 4; 681 xd_card->zone_cnt = 64; 682 xd_card->capacity = 2048000; 683 break; 684 case xD_2G_X8_512: 685 XD_PAGE_512(xd_card); 686 xd_card->addr_cycle = 4; 687 xd_card->zone_cnt = 128; 688 xd_card->capacity = 4096000; 689 break; 690 default: 691 continue; 692 } 693 694 /* Confirm timing setting */ 695 for (j = 0; j < 10; j++) { 696 retval = xd_read_id(chip, READ_ID, id_buf, 4); 697 if (retval != STATUS_SUCCESS) { 698 return STATUS_FAIL; 699 } 700 701 if (id_buf[1] != xd_card->device_code) 702 break; 703 } 704 705 if (j == 10) 706 break; 707 } 708 709 if (i == 4) { 710 xd_card->block_shift = 0; 711 xd_card->page_off = 0; 712 xd_card->addr_cycle = 0; 713 xd_card->capacity = 0; 714 715 return STATUS_FAIL; 716 } 717 718 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); 719 if (retval != STATUS_SUCCESS) { 720 return STATUS_FAIL; 721 } 722 dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", 723 id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 724 if (id_buf[2] != XD_ID_CODE) { 725 return STATUS_FAIL; 726 } 727 728 /* Search CIS block */ 729 for (i = 0; i < 24; i++) { 730 u32 page_addr; 731 732 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 733 return STATUS_FAIL; 734 } 735 736 page_addr = (u32)i << xd_card->block_shift; 737 738 for (j = 0; j < 3; j++) { 739 retval = xd_read_redundant(chip, page_addr, redunt, 11); 740 if (retval == STATUS_SUCCESS) 741 break; 742 } 743 if (j == 3) 744 continue; 745 746 if (redunt[BLOCK_STATUS] != XD_GBLK) 747 continue; 748 749 j = 0; 750 if (redunt[PAGE_STATUS] != XD_GPG) { 751 for (j = 1; j <= 8; j++) { 752 retval = xd_read_redundant(chip, page_addr + j, 753 redunt, 11); 754 if (retval == STATUS_SUCCESS) { 755 if (redunt[PAGE_STATUS] == XD_GPG) 756 break; 757 } 758 } 759 760 if (j == 9) 761 break; 762 } 763 764 /* Check CIS data */ 765 if ((redunt[BLOCK_STATUS] == XD_GBLK) && 766 (redunt[PARITY] & XD_BA1_ALL0)) { 767 u8 buf[10]; 768 769 page_addr += j; 770 771 retval = xd_read_cis(chip, page_addr, buf, 10); 772 if (retval != STATUS_SUCCESS) { 773 return STATUS_FAIL; 774 } 775 776 if ((buf[0] == 0x01) && (buf[1] == 0x03) && 777 (buf[2] == 0xD9) && 778 (buf[3] == 0x01) && (buf[4] == 0xFF) && 779 (buf[5] == 0x18) && (buf[6] == 0x02) && 780 (buf[7] == 0xDF) && (buf[8] == 0x01) && 781 (buf[9] == 0x20)) { 782 xd_card->cis_block = (u16)i; 783 } 784 } 785 786 break; 787 } 788 789 dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block); 790 if (xd_card->cis_block == 0xFFFF) 791 return STATUS_FAIL; 792 793 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; 794 795 return STATUS_SUCCESS; 796 } 797 798 static int xd_check_data_blank(u8 *redunt) 799 { 800 int i; 801 802 for (i = 0; i < 6; i++) { 803 if (redunt[PAGE_STATUS + i] != 0xFF) 804 return 0; 805 } 806 807 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 808 != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 809 return 0; 810 811 for (i = 0; i < 4; i++) { 812 if (redunt[RESERVED0 + i] != 0xFF) 813 return 0; 814 } 815 816 return 1; 817 } 818 819 static u16 xd_load_log_block_addr(u8 *redunt) 820 { 821 u16 addr = 0xFFFF; 822 823 if (redunt[PARITY] & XD_BA1_BA2_EQL) 824 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 825 redunt[BLOCK_ADDR1_L]; 826 else if (redunt[PARITY] & XD_BA1_VALID) 827 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 828 redunt[BLOCK_ADDR1_L]; 829 else if (redunt[PARITY] & XD_BA2_VALID) 830 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | 831 redunt[BLOCK_ADDR2_L]; 832 833 return addr; 834 } 835 836 static int xd_init_l2p_tbl(struct rtsx_chip *chip) 837 { 838 struct xd_info *xd_card = &chip->xd_card; 839 int size, i; 840 841 dev_dbg(rtsx_dev(chip), "%s: zone_cnt = %d\n", __func__, 842 xd_card->zone_cnt); 843 844 if (xd_card->zone_cnt < 1) { 845 return STATUS_FAIL; 846 } 847 848 size = xd_card->zone_cnt * sizeof(struct zone_entry); 849 dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size); 850 851 xd_card->zone = vmalloc(size); 852 if (!xd_card->zone) { 853 return STATUS_ERROR; 854 } 855 856 for (i = 0; i < xd_card->zone_cnt; i++) { 857 xd_card->zone[i].build_flag = 0; 858 xd_card->zone[i].l2p_table = NULL; 859 xd_card->zone[i].free_table = NULL; 860 xd_card->zone[i].get_index = 0; 861 xd_card->zone[i].set_index = 0; 862 xd_card->zone[i].unused_blk_cnt = 0; 863 } 864 865 return STATUS_SUCCESS; 866 } 867 868 static inline void free_zone(struct zone_entry *zone) 869 { 870 if (!zone) 871 return; 872 873 zone->build_flag = 0; 874 zone->set_index = 0; 875 zone->get_index = 0; 876 zone->unused_blk_cnt = 0; 877 vfree(zone->l2p_table); 878 zone->l2p_table = NULL; 879 vfree(zone->free_table); 880 zone->free_table = NULL; 881 } 882 883 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) 884 { 885 struct xd_info *xd_card = &chip->xd_card; 886 struct zone_entry *zone; 887 int zone_no; 888 889 zone_no = (int)phy_blk >> 10; 890 if (zone_no >= xd_card->zone_cnt) { 891 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n", 892 zone_no, xd_card->zone_cnt); 893 return; 894 } 895 zone = &xd_card->zone[zone_no]; 896 897 if (!zone->free_table) { 898 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) 899 return; 900 } 901 902 if ((zone->set_index >= XD_FREE_TABLE_CNT) || 903 (zone->set_index < 0)) { 904 free_zone(zone); 905 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n"); 906 return; 907 } 908 909 dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n", 910 zone->set_index); 911 912 zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff); 913 if (zone->set_index >= XD_FREE_TABLE_CNT) 914 zone->set_index = 0; 915 zone->unused_blk_cnt++; 916 } 917 918 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) 919 { 920 struct xd_info *xd_card = &chip->xd_card; 921 struct zone_entry *zone; 922 u32 phy_blk; 923 924 if (zone_no >= xd_card->zone_cnt) { 925 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n", 926 zone_no, xd_card->zone_cnt); 927 return BLK_NOT_FOUND; 928 } 929 zone = &xd_card->zone[zone_no]; 930 931 if ((zone->unused_blk_cnt == 0) || 932 (zone->set_index == zone->get_index)) { 933 free_zone(zone); 934 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n"); 935 return BLK_NOT_FOUND; 936 } 937 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) { 938 free_zone(zone); 939 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n"); 940 return BLK_NOT_FOUND; 941 } 942 943 dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n", 944 zone->get_index); 945 946 phy_blk = zone->free_table[zone->get_index]; 947 zone->free_table[zone->get_index++] = 0xFFFF; 948 if (zone->get_index >= XD_FREE_TABLE_CNT) 949 zone->get_index = 0; 950 zone->unused_blk_cnt--; 951 952 phy_blk += ((u32)(zone_no) << 10); 953 return phy_blk; 954 } 955 956 static void xd_set_l2p_tbl(struct rtsx_chip *chip, 957 int zone_no, u16 log_off, u16 phy_off) 958 { 959 struct xd_info *xd_card = &chip->xd_card; 960 struct zone_entry *zone; 961 962 zone = &xd_card->zone[zone_no]; 963 zone->l2p_table[log_off] = phy_off; 964 } 965 966 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off) 967 { 968 struct xd_info *xd_card = &chip->xd_card; 969 struct zone_entry *zone; 970 int retval; 971 972 zone = &xd_card->zone[zone_no]; 973 if (zone->l2p_table[log_off] == 0xFFFF) { 974 u32 phy_blk = 0; 975 int i; 976 977 #ifdef XD_DELAY_WRITE 978 retval = xd_delay_write(chip); 979 if (retval != STATUS_SUCCESS) { 980 dev_dbg(rtsx_dev(chip), "In %s, delay write fail!\n", 981 __func__); 982 return BLK_NOT_FOUND; 983 } 984 #endif 985 986 if (zone->unused_blk_cnt <= 0) { 987 dev_dbg(rtsx_dev(chip), "No unused block!\n"); 988 return BLK_NOT_FOUND; 989 } 990 991 for (i = 0; i < zone->unused_blk_cnt; i++) { 992 phy_blk = xd_get_unused_block(chip, zone_no); 993 if (phy_blk == BLK_NOT_FOUND) { 994 dev_dbg(rtsx_dev(chip), "No unused block available!\n"); 995 return BLK_NOT_FOUND; 996 } 997 998 retval = xd_init_page(chip, phy_blk, log_off, 999 0, xd_card->page_off + 1); 1000 if (retval == STATUS_SUCCESS) 1001 break; 1002 } 1003 if (i >= zone->unused_blk_cnt) { 1004 dev_dbg(rtsx_dev(chip), "No good unused block available!\n"); 1005 return BLK_NOT_FOUND; 1006 } 1007 1008 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF)); 1009 return phy_blk; 1010 } 1011 1012 return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10); 1013 } 1014 1015 int reset_xd_card(struct rtsx_chip *chip) 1016 { 1017 struct xd_info *xd_card = &chip->xd_card; 1018 int retval; 1019 1020 memset(xd_card, 0, sizeof(struct xd_info)); 1021 1022 xd_card->block_shift = 0; 1023 xd_card->page_off = 0; 1024 xd_card->addr_cycle = 0; 1025 xd_card->capacity = 0; 1026 xd_card->zone_cnt = 0; 1027 xd_card->cis_block = 0xFFFF; 1028 xd_card->delay_write.delay_write_flag = 0; 1029 1030 retval = enable_card_clock(chip, XD_CARD); 1031 if (retval != STATUS_SUCCESS) { 1032 return STATUS_FAIL; 1033 } 1034 1035 retval = reset_xd(chip); 1036 if (retval != STATUS_SUCCESS) { 1037 return STATUS_FAIL; 1038 } 1039 1040 retval = xd_init_l2p_tbl(chip); 1041 if (retval != STATUS_SUCCESS) { 1042 return STATUS_FAIL; 1043 } 1044 1045 return STATUS_SUCCESS; 1046 } 1047 1048 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) 1049 { 1050 struct xd_info *xd_card = &chip->xd_card; 1051 int retval; 1052 u32 page_addr; 1053 u8 reg = 0; 1054 1055 dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk); 1056 1057 if (phy_blk == BLK_NOT_FOUND) { 1058 return STATUS_FAIL; 1059 } 1060 1061 rtsx_init_cmd(chip); 1062 1063 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1064 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK); 1065 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF); 1066 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF); 1067 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF); 1068 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF); 1069 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF); 1070 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF); 1071 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF); 1072 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF); 1073 1074 page_addr = phy_blk << xd_card->block_shift; 1075 1076 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1077 1078 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1079 xd_card->page_off + 1); 1080 1081 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1082 XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1083 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1084 XD_TRANSFER_END, XD_TRANSFER_END); 1085 1086 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1087 if (retval < 0) { 1088 rtsx_clear_xd_error(chip); 1089 rtsx_read_register(chip, XD_DAT, ®); 1090 if (reg & PROGRAM_ERROR) 1091 xd_set_err_code(chip, XD_PRG_ERROR); 1092 else 1093 xd_set_err_code(chip, XD_TO_ERROR); 1094 return STATUS_FAIL; 1095 } 1096 1097 return STATUS_SUCCESS; 1098 } 1099 1100 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, 1101 u16 logoff, u8 start_page, u8 end_page) 1102 { 1103 struct xd_info *xd_card = &chip->xd_card; 1104 int retval; 1105 u32 page_addr; 1106 u8 reg = 0; 1107 1108 dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk); 1109 1110 if (start_page > end_page) { 1111 return STATUS_FAIL; 1112 } 1113 if (phy_blk == BLK_NOT_FOUND) { 1114 return STATUS_FAIL; 1115 } 1116 1117 rtsx_init_cmd(chip); 1118 1119 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF); 1120 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF); 1121 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1122 0xFF, (u8)(logoff >> 8)); 1123 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff); 1124 1125 page_addr = (phy_blk << xd_card->block_shift) + start_page; 1126 1127 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1128 1129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 1130 XD_BA_TRANSFORM, XD_BA_TRANSFORM); 1131 1132 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 1133 0xFF, (end_page - start_page)); 1134 1135 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1136 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1137 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1138 XD_TRANSFER_END, XD_TRANSFER_END); 1139 1140 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1141 if (retval < 0) { 1142 rtsx_clear_xd_error(chip); 1143 rtsx_read_register(chip, XD_DAT, ®); 1144 if (reg & PROGRAM_ERROR) { 1145 xd_mark_bad_block(chip, phy_blk); 1146 xd_set_err_code(chip, XD_PRG_ERROR); 1147 } else { 1148 xd_set_err_code(chip, XD_TO_ERROR); 1149 } 1150 return STATUS_FAIL; 1151 } 1152 1153 return STATUS_SUCCESS; 1154 } 1155 1156 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, 1157 u8 start_page, u8 end_page) 1158 { 1159 struct xd_info *xd_card = &chip->xd_card; 1160 u32 old_page, new_page; 1161 u8 i, reg = 0; 1162 int retval; 1163 1164 dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n", 1165 old_blk, new_blk); 1166 1167 if (start_page > end_page) { 1168 return STATUS_FAIL; 1169 } 1170 1171 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) { 1172 return STATUS_FAIL; 1173 } 1174 1175 old_page = (old_blk << xd_card->block_shift) + start_page; 1176 new_page = (new_blk << xd_card->block_shift) + start_page; 1177 1178 XD_CLR_BAD_NEWBLK(xd_card); 1179 1180 retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, 1181 PINGPONG_BUFFER); 1182 if (retval) { 1183 return retval; 1184 } 1185 1186 for (i = start_page; i < end_page; i++) { 1187 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1188 rtsx_clear_xd_error(chip); 1189 xd_set_err_code(chip, XD_NO_CARD); 1190 return STATUS_FAIL; 1191 } 1192 1193 rtsx_init_cmd(chip); 1194 1195 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR); 1196 1197 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1198 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1199 XD_AUTO_CHK_DATA_STATUS, 0); 1200 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1201 XD_TRANSFER_START | XD_READ_PAGES); 1202 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1203 XD_TRANSFER_END, XD_TRANSFER_END); 1204 1205 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1206 if (retval < 0) { 1207 rtsx_clear_xd_error(chip); 1208 reg = 0; 1209 rtsx_read_register(chip, XD_CTL, ®); 1210 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { 1211 mdelay(100); 1212 1213 if (detect_card_cd(chip, 1214 XD_CARD) != STATUS_SUCCESS) { 1215 xd_set_err_code(chip, XD_NO_CARD); 1216 return STATUS_FAIL; 1217 } 1218 1219 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == 1220 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) || 1221 ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == 1222 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { 1223 rtsx_write_register(chip, 1224 XD_PAGE_STATUS, 1225 0xFF, 1226 XD_BPG); 1227 rtsx_write_register(chip, 1228 XD_BLOCK_STATUS, 1229 0xFF, 1230 XD_GBLK); 1231 XD_SET_BAD_OLDBLK(xd_card); 1232 dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n", 1233 old_blk); 1234 } 1235 } else { 1236 xd_set_err_code(chip, XD_TO_ERROR); 1237 return STATUS_FAIL; 1238 } 1239 } 1240 1241 if (XD_CHK_BAD_OLDBLK(xd_card)) 1242 rtsx_clear_xd_error(chip); 1243 1244 rtsx_init_cmd(chip); 1245 1246 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR); 1247 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1248 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1249 XD_TRANSFER_START | XD_WRITE_PAGES); 1250 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1251 XD_TRANSFER_END, XD_TRANSFER_END); 1252 1253 retval = rtsx_send_cmd(chip, XD_CARD, 300); 1254 if (retval < 0) { 1255 rtsx_clear_xd_error(chip); 1256 reg = 0; 1257 rtsx_read_register(chip, XD_DAT, ®); 1258 if (reg & PROGRAM_ERROR) { 1259 xd_mark_bad_block(chip, new_blk); 1260 xd_set_err_code(chip, XD_PRG_ERROR); 1261 XD_SET_BAD_NEWBLK(xd_card); 1262 } else { 1263 xd_set_err_code(chip, XD_TO_ERROR); 1264 } 1265 return STATUS_FAIL; 1266 } 1267 1268 old_page++; 1269 new_page++; 1270 } 1271 1272 return STATUS_SUCCESS; 1273 } 1274 1275 static int xd_reset_cmd(struct rtsx_chip *chip) 1276 { 1277 int retval; 1278 u8 *ptr; 1279 1280 rtsx_init_cmd(chip); 1281 1282 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1283 0xFF, XD_TRANSFER_START | XD_RESET); 1284 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1285 XD_TRANSFER_END, XD_TRANSFER_END); 1286 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1287 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 1288 1289 retval = rtsx_send_cmd(chip, XD_CARD, 100); 1290 if (retval < 0) { 1291 return STATUS_FAIL; 1292 } 1293 1294 ptr = rtsx_get_cmd_data(chip) + 1; 1295 if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) 1296 return STATUS_SUCCESS; 1297 1298 return STATUS_FAIL; 1299 } 1300 1301 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) 1302 { 1303 struct xd_info *xd_card = &chip->xd_card; 1304 u32 page_addr; 1305 u8 reg = 0, *ptr; 1306 int i, retval; 1307 1308 if (phy_blk == BLK_NOT_FOUND) { 1309 return STATUS_FAIL; 1310 } 1311 1312 page_addr = phy_blk << xd_card->block_shift; 1313 1314 for (i = 0; i < 3; i++) { 1315 rtsx_init_cmd(chip); 1316 1317 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR); 1318 1319 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1320 XD_TRANSFER_START | XD_ERASE); 1321 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1322 XD_TRANSFER_END, XD_TRANSFER_END); 1323 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1324 1325 retval = rtsx_send_cmd(chip, XD_CARD, 250); 1326 if (retval < 0) { 1327 rtsx_clear_xd_error(chip); 1328 rtsx_read_register(chip, XD_DAT, ®); 1329 if (reg & PROGRAM_ERROR) { 1330 xd_mark_bad_block(chip, phy_blk); 1331 xd_set_err_code(chip, XD_PRG_ERROR); 1332 return STATUS_FAIL; 1333 } 1334 xd_set_err_code(chip, XD_ERASE_FAIL); 1335 retval = xd_reset_cmd(chip); 1336 if (retval != STATUS_SUCCESS) { 1337 return STATUS_FAIL; 1338 } 1339 continue; 1340 } 1341 1342 ptr = rtsx_get_cmd_data(chip) + 1; 1343 if (*ptr & PROGRAM_ERROR) { 1344 xd_mark_bad_block(chip, phy_blk); 1345 xd_set_err_code(chip, XD_PRG_ERROR); 1346 return STATUS_FAIL; 1347 } 1348 1349 return STATUS_SUCCESS; 1350 } 1351 1352 xd_mark_bad_block(chip, phy_blk); 1353 xd_set_err_code(chip, XD_ERASE_FAIL); 1354 return STATUS_FAIL; 1355 } 1356 1357 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) 1358 { 1359 struct xd_info *xd_card = &chip->xd_card; 1360 struct zone_entry *zone; 1361 int retval; 1362 u32 start, end, i; 1363 u16 max_logoff, cur_fst_page_logoff; 1364 u16 cur_lst_page_logoff, ent_lst_page_logoff; 1365 u8 redunt[11]; 1366 1367 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, zone_no); 1368 1369 if (!xd_card->zone) { 1370 retval = xd_init_l2p_tbl(chip); 1371 if (retval != STATUS_SUCCESS) 1372 return retval; 1373 } 1374 1375 if (xd_card->zone[zone_no].build_flag) { 1376 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n", 1377 zone_no); 1378 return STATUS_SUCCESS; 1379 } 1380 1381 zone = &xd_card->zone[zone_no]; 1382 1383 if (!zone->l2p_table) { 1384 zone->l2p_table = vmalloc(2000); 1385 if (!zone->l2p_table) { 1386 goto build_fail; 1387 } 1388 } 1389 memset((u8 *)(zone->l2p_table), 0xff, 2000); 1390 1391 if (!zone->free_table) { 1392 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2); 1393 if (!zone->free_table) { 1394 goto build_fail; 1395 } 1396 } 1397 memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); 1398 1399 if (zone_no == 0) { 1400 if (xd_card->cis_block == 0xFFFF) 1401 start = 0; 1402 else 1403 start = xd_card->cis_block + 1; 1404 if (XD_CHK_4MB(xd_card)) { 1405 end = 0x200; 1406 max_logoff = 499; 1407 } else { 1408 end = 0x400; 1409 max_logoff = 999; 1410 } 1411 } else { 1412 start = (u32)(zone_no) << 10; 1413 end = (u32)(zone_no + 1) << 10; 1414 max_logoff = 999; 1415 } 1416 1417 dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n", 1418 start, end); 1419 1420 zone->set_index = 0; 1421 zone->get_index = 0; 1422 zone->unused_blk_cnt = 0; 1423 1424 for (i = start; i < end; i++) { 1425 u32 page_addr = i << xd_card->block_shift; 1426 u32 phy_block; 1427 1428 retval = xd_read_redundant(chip, page_addr, redunt, 11); 1429 if (retval != STATUS_SUCCESS) 1430 continue; 1431 1432 if (redunt[BLOCK_STATUS] != 0xFF) { 1433 dev_dbg(rtsx_dev(chip), "bad block\n"); 1434 continue; 1435 } 1436 1437 if (xd_check_data_blank(redunt)) { 1438 dev_dbg(rtsx_dev(chip), "blank block\n"); 1439 xd_set_unused_block(chip, i); 1440 continue; 1441 } 1442 1443 cur_fst_page_logoff = xd_load_log_block_addr(redunt); 1444 if ((cur_fst_page_logoff == 0xFFFF) || 1445 (cur_fst_page_logoff > max_logoff)) { 1446 retval = xd_erase_block(chip, i); 1447 if (retval == STATUS_SUCCESS) 1448 xd_set_unused_block(chip, i); 1449 continue; 1450 } 1451 1452 if ((zone_no == 0) && (cur_fst_page_logoff == 0) && 1453 (redunt[PAGE_STATUS] != XD_GPG)) 1454 XD_SET_MBR_FAIL(xd_card); 1455 1456 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { 1457 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); 1458 continue; 1459 } 1460 1461 phy_block = zone->l2p_table[cur_fst_page_logoff] + 1462 ((u32)((zone_no) << 10)); 1463 1464 page_addr = ((i + 1) << xd_card->block_shift) - 1; 1465 1466 retval = xd_read_redundant(chip, page_addr, redunt, 11); 1467 if (retval != STATUS_SUCCESS) 1468 continue; 1469 1470 cur_lst_page_logoff = xd_load_log_block_addr(redunt); 1471 if (cur_lst_page_logoff == cur_fst_page_logoff) { 1472 int m; 1473 1474 page_addr = ((phy_block + 1) << 1475 xd_card->block_shift) - 1; 1476 1477 for (m = 0; m < 3; m++) { 1478 retval = xd_read_redundant(chip, page_addr, 1479 redunt, 11); 1480 if (retval == STATUS_SUCCESS) 1481 break; 1482 } 1483 1484 if (m == 3) { 1485 zone->l2p_table[cur_fst_page_logoff] = 1486 (u16)(i & 0x3FF); 1487 retval = xd_erase_block(chip, phy_block); 1488 if (retval == STATUS_SUCCESS) 1489 xd_set_unused_block(chip, phy_block); 1490 continue; 1491 } 1492 1493 ent_lst_page_logoff = xd_load_log_block_addr(redunt); 1494 if (ent_lst_page_logoff != cur_fst_page_logoff) { 1495 zone->l2p_table[cur_fst_page_logoff] = 1496 (u16)(i & 0x3FF); 1497 retval = xd_erase_block(chip, phy_block); 1498 if (retval == STATUS_SUCCESS) 1499 xd_set_unused_block(chip, phy_block); 1500 continue; 1501 } else { 1502 retval = xd_erase_block(chip, i); 1503 if (retval == STATUS_SUCCESS) 1504 xd_set_unused_block(chip, i); 1505 } 1506 } else { 1507 retval = xd_erase_block(chip, i); 1508 if (retval == STATUS_SUCCESS) 1509 xd_set_unused_block(chip, i); 1510 } 1511 } 1512 1513 if (XD_CHK_4MB(xd_card)) 1514 end = 500; 1515 else 1516 end = 1000; 1517 1518 i = 0; 1519 for (start = 0; start < end; start++) { 1520 if (zone->l2p_table[start] == 0xFFFF) 1521 i++; 1522 } 1523 1524 dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n", 1525 end, i); 1526 dev_dbg(rtsx_dev(chip), "Total unused block: %d\n", 1527 zone->unused_blk_cnt); 1528 1529 if ((zone->unused_blk_cnt - i) < 1) 1530 chip->card_wp |= XD_CARD; 1531 1532 zone->build_flag = 1; 1533 1534 return STATUS_SUCCESS; 1535 1536 build_fail: 1537 vfree(zone->l2p_table); 1538 zone->l2p_table = NULL; 1539 vfree(zone->free_table); 1540 zone->free_table = NULL; 1541 1542 return STATUS_FAIL; 1543 } 1544 1545 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) 1546 { 1547 int retval; 1548 1549 rtsx_init_cmd(chip); 1550 1551 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd); 1552 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1553 XD_TRANSFER_START | XD_SET_CMD); 1554 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1555 XD_TRANSFER_END, XD_TRANSFER_END); 1556 1557 retval = rtsx_send_cmd(chip, XD_CARD, 200); 1558 if (retval < 0) { 1559 return STATUS_FAIL; 1560 } 1561 1562 return STATUS_SUCCESS; 1563 } 1564 1565 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, 1566 u32 log_blk, u8 start_page, u8 end_page, 1567 u8 *buf, unsigned int *index, 1568 unsigned int *offset) 1569 { 1570 struct xd_info *xd_card = &chip->xd_card; 1571 u32 page_addr, new_blk; 1572 u16 log_off; 1573 u8 reg_val, page_cnt; 1574 int zone_no, retval, i; 1575 1576 if (start_page > end_page) 1577 goto status_fail; 1578 1579 page_cnt = end_page - start_page; 1580 zone_no = (int)(log_blk / 1000); 1581 log_off = (u16)(log_blk % 1000); 1582 1583 if ((phy_blk & 0x3FF) == 0x3FF) { 1584 for (i = 0; i < 256; i++) { 1585 page_addr = ((u32)i) << xd_card->block_shift; 1586 1587 retval = xd_read_redundant(chip, page_addr, NULL, 0); 1588 if (retval == STATUS_SUCCESS) 1589 break; 1590 1591 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1592 xd_set_err_code(chip, XD_NO_CARD); 1593 goto status_fail; 1594 } 1595 } 1596 } 1597 1598 page_addr = (phy_blk << xd_card->block_shift) + start_page; 1599 1600 rtsx_init_cmd(chip); 1601 1602 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1603 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE); 1604 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1605 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1606 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1607 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 1608 1609 trans_dma_enable(chip->srb->sc_data_direction, chip, 1610 page_cnt * 512, DMA_512); 1611 1612 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1613 XD_TRANSFER_START | XD_READ_PAGES); 1614 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1615 XD_TRANSFER_END | XD_PPB_EMPTY, 1616 XD_TRANSFER_END | XD_PPB_EMPTY); 1617 1618 rtsx_send_cmd_no_wait(chip); 1619 1620 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1621 scsi_sg_count(chip->srb), 1622 index, offset, DMA_FROM_DEVICE, 1623 chip->xd_timeout); 1624 if (retval < 0) { 1625 rtsx_clear_xd_error(chip); 1626 1627 if (retval == -ETIMEDOUT) { 1628 xd_set_err_code(chip, XD_TO_ERROR); 1629 goto status_fail; 1630 } else { 1631 goto fail; 1632 } 1633 } 1634 1635 return STATUS_SUCCESS; 1636 1637 fail: 1638 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val); 1639 if (retval) { 1640 return retval; 1641 } 1642 1643 if (reg_val != XD_GPG) 1644 xd_set_err_code(chip, XD_PRG_ERROR); 1645 1646 retval = rtsx_read_register(chip, XD_CTL, ®_val); 1647 if (retval) { 1648 return retval; 1649 } 1650 1651 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == 1652 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) || 1653 ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == 1654 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { 1655 wait_timeout(100); 1656 1657 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1658 xd_set_err_code(chip, XD_NO_CARD); 1659 goto status_fail; 1660 } 1661 1662 xd_set_err_code(chip, XD_ECC_ERROR); 1663 1664 new_blk = xd_get_unused_block(chip, zone_no); 1665 if (new_blk == NO_NEW_BLK) { 1666 XD_CLR_BAD_OLDBLK(xd_card); 1667 goto status_fail; 1668 } 1669 1670 retval = xd_copy_page(chip, phy_blk, new_blk, 0, 1671 xd_card->page_off + 1); 1672 if (retval != STATUS_SUCCESS) { 1673 if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1674 retval = xd_erase_block(chip, new_blk); 1675 if (retval == STATUS_SUCCESS) 1676 xd_set_unused_block(chip, new_blk); 1677 } else { 1678 XD_CLR_BAD_NEWBLK(xd_card); 1679 } 1680 XD_CLR_BAD_OLDBLK(xd_card); 1681 goto status_fail; 1682 } 1683 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1684 xd_erase_block(chip, phy_blk); 1685 xd_mark_bad_block(chip, phy_blk); 1686 XD_CLR_BAD_OLDBLK(xd_card); 1687 } 1688 1689 status_fail: 1690 return STATUS_FAIL; 1691 } 1692 1693 static int xd_finish_write(struct rtsx_chip *chip, 1694 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1695 { 1696 struct xd_info *xd_card = &chip->xd_card; 1697 int retval, zone_no; 1698 u16 log_off; 1699 1700 dev_dbg(rtsx_dev(chip), "%s ", __func__); 1701 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x, ", old_blk); 1702 dev_dbg(rtsx_dev(chip), "new_blk = 0x%x, ", new_blk); 1703 dev_dbg(rtsx_dev(chip), "log_blk = 0x%x\n", log_blk); 1704 1705 if (page_off > xd_card->page_off) { 1706 return STATUS_FAIL; 1707 } 1708 1709 zone_no = (int)(log_blk / 1000); 1710 log_off = (u16)(log_blk % 1000); 1711 1712 if (old_blk == BLK_NOT_FOUND) { 1713 retval = xd_init_page(chip, new_blk, log_off, 1714 page_off, xd_card->page_off + 1); 1715 if (retval != STATUS_SUCCESS) { 1716 retval = xd_erase_block(chip, new_blk); 1717 if (retval == STATUS_SUCCESS) 1718 xd_set_unused_block(chip, new_blk); 1719 return STATUS_FAIL; 1720 } 1721 } else { 1722 retval = xd_copy_page(chip, old_blk, new_blk, 1723 page_off, xd_card->page_off + 1); 1724 if (retval != STATUS_SUCCESS) { 1725 if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1726 retval = xd_erase_block(chip, new_blk); 1727 if (retval == STATUS_SUCCESS) 1728 xd_set_unused_block(chip, new_blk); 1729 } 1730 XD_CLR_BAD_NEWBLK(xd_card); 1731 return STATUS_FAIL; 1732 } 1733 1734 retval = xd_erase_block(chip, old_blk); 1735 if (retval == STATUS_SUCCESS) { 1736 if (XD_CHK_BAD_OLDBLK(xd_card)) { 1737 xd_mark_bad_block(chip, old_blk); 1738 XD_CLR_BAD_OLDBLK(xd_card); 1739 } else { 1740 xd_set_unused_block(chip, old_blk); 1741 } 1742 } else { 1743 xd_set_err_code(chip, XD_NO_ERROR); 1744 XD_CLR_BAD_OLDBLK(xd_card); 1745 } 1746 } 1747 1748 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1749 1750 return STATUS_SUCCESS; 1751 } 1752 1753 static int xd_prepare_write(struct rtsx_chip *chip, 1754 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1755 { 1756 int retval; 1757 1758 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n", 1759 __func__, old_blk, new_blk, log_blk, (int)page_off); 1760 1761 if (page_off) { 1762 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); 1763 if (retval != STATUS_SUCCESS) { 1764 return STATUS_FAIL; 1765 } 1766 } 1767 1768 return STATUS_SUCCESS; 1769 } 1770 1771 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, 1772 u32 new_blk, u32 log_blk, u8 start_page, 1773 u8 end_page, u8 *buf, unsigned int *index, 1774 unsigned int *offset) 1775 { 1776 struct xd_info *xd_card = &chip->xd_card; 1777 u32 page_addr; 1778 int zone_no, retval; 1779 u16 log_off; 1780 u8 page_cnt, reg_val; 1781 1782 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", 1783 __func__, old_blk, new_blk, log_blk); 1784 1785 if (start_page > end_page) 1786 goto status_fail; 1787 1788 page_cnt = end_page - start_page; 1789 zone_no = (int)(log_blk / 1000); 1790 log_off = (u16)(log_blk % 1000); 1791 1792 page_addr = (new_blk << xd_card->block_shift) + start_page; 1793 1794 retval = xd_send_cmd(chip, READ1_1); 1795 if (retval != STATUS_SUCCESS) 1796 goto status_fail; 1797 1798 rtsx_init_cmd(chip); 1799 1800 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1801 0xFF, (u8)(log_off >> 8)); 1802 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off); 1803 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK); 1804 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1805 1806 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1807 1808 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, 1809 XD_BA_TRANSFORM); 1810 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1811 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1812 1813 trans_dma_enable(chip->srb->sc_data_direction, chip, 1814 page_cnt * 512, DMA_512); 1815 1816 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1817 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES); 1818 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1819 XD_TRANSFER_END, XD_TRANSFER_END); 1820 1821 rtsx_send_cmd_no_wait(chip); 1822 1823 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1824 scsi_sg_count(chip->srb), 1825 index, offset, DMA_TO_DEVICE, chip->xd_timeout); 1826 if (retval < 0) { 1827 rtsx_clear_xd_error(chip); 1828 1829 if (retval == -ETIMEDOUT) { 1830 xd_set_err_code(chip, XD_TO_ERROR); 1831 goto status_fail; 1832 } else { 1833 goto fail; 1834 } 1835 } 1836 1837 if (end_page == (xd_card->page_off + 1)) { 1838 xd_card->delay_write.delay_write_flag = 0; 1839 1840 if (old_blk != BLK_NOT_FOUND) { 1841 retval = xd_erase_block(chip, old_blk); 1842 if (retval == STATUS_SUCCESS) { 1843 if (XD_CHK_BAD_OLDBLK(xd_card)) { 1844 xd_mark_bad_block(chip, old_blk); 1845 XD_CLR_BAD_OLDBLK(xd_card); 1846 } else { 1847 xd_set_unused_block(chip, old_blk); 1848 } 1849 } else { 1850 xd_set_err_code(chip, XD_NO_ERROR); 1851 XD_CLR_BAD_OLDBLK(xd_card); 1852 } 1853 } 1854 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1855 } 1856 1857 return STATUS_SUCCESS; 1858 1859 fail: 1860 retval = rtsx_read_register(chip, XD_DAT, ®_val); 1861 if (retval) { 1862 return retval; 1863 } 1864 if (reg_val & PROGRAM_ERROR) { 1865 xd_set_err_code(chip, XD_PRG_ERROR); 1866 xd_mark_bad_block(chip, new_blk); 1867 } 1868 1869 status_fail: 1870 return STATUS_FAIL; 1871 } 1872 1873 #ifdef XD_DELAY_WRITE 1874 int xd_delay_write(struct rtsx_chip *chip) 1875 { 1876 struct xd_info *xd_card = &chip->xd_card; 1877 struct xd_delay_write_tag *delay_write = &xd_card->delay_write; 1878 int retval; 1879 1880 if (delay_write->delay_write_flag) { 1881 dev_dbg(rtsx_dev(chip), "%s\n", __func__); 1882 retval = xd_switch_clock(chip); 1883 if (retval != STATUS_SUCCESS) { 1884 return STATUS_FAIL; 1885 } 1886 1887 delay_write->delay_write_flag = 0; 1888 retval = xd_finish_write(chip, 1889 delay_write->old_phyblock, 1890 delay_write->new_phyblock, 1891 delay_write->logblock, 1892 delay_write->pageoff); 1893 if (retval != STATUS_SUCCESS) { 1894 return STATUS_FAIL; 1895 } 1896 } 1897 1898 return STATUS_SUCCESS; 1899 } 1900 #endif 1901 1902 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 1903 u32 start_sector, u16 sector_cnt) 1904 { 1905 struct xd_info *xd_card = &chip->xd_card; 1906 unsigned int lun = SCSI_LUN(srb); 1907 #ifdef XD_DELAY_WRITE 1908 struct xd_delay_write_tag *delay_write = &xd_card->delay_write; 1909 #endif 1910 int retval, zone_no; 1911 unsigned int index = 0, offset = 0; 1912 u32 log_blk, old_blk = 0, new_blk = 0; 1913 u16 log_off, total_sec_cnt = sector_cnt; 1914 u8 start_page, end_page = 0, page_cnt; 1915 u8 *ptr; 1916 1917 xd_set_err_code(chip, XD_NO_ERROR); 1918 1919 xd_card->cleanup_counter = 0; 1920 1921 dev_dbg(rtsx_dev(chip), "%s: scsi_sg_count = %d\n", __func__, 1922 scsi_sg_count(srb)); 1923 1924 ptr = (u8 *)scsi_sglist(srb); 1925 1926 retval = xd_switch_clock(chip); 1927 if (retval != STATUS_SUCCESS) { 1928 return STATUS_FAIL; 1929 } 1930 1931 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1932 chip->card_fail |= XD_CARD; 1933 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1934 return STATUS_FAIL; 1935 } 1936 1937 log_blk = start_sector >> xd_card->block_shift; 1938 start_page = (u8)start_sector & xd_card->page_off; 1939 zone_no = (int)(log_blk / 1000); 1940 log_off = (u16)(log_blk % 1000); 1941 1942 if (xd_card->zone[zone_no].build_flag == 0) { 1943 retval = xd_build_l2p_tbl(chip, zone_no); 1944 if (retval != STATUS_SUCCESS) { 1945 chip->card_fail |= XD_CARD; 1946 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 1947 return STATUS_FAIL; 1948 } 1949 } 1950 1951 if (srb->sc_data_direction == DMA_TO_DEVICE) { 1952 #ifdef XD_DELAY_WRITE 1953 if (delay_write->delay_write_flag && 1954 (delay_write->logblock == log_blk) && 1955 (start_page > delay_write->pageoff)) { 1956 delay_write->delay_write_flag = 0; 1957 if (delay_write->old_phyblock != BLK_NOT_FOUND) { 1958 retval = xd_copy_page(chip, 1959 delay_write->old_phyblock, 1960 delay_write->new_phyblock, 1961 delay_write->pageoff, 1962 start_page); 1963 if (retval != STATUS_SUCCESS) { 1964 set_sense_type(chip, lun, 1965 SENSE_TYPE_MEDIA_WRITE_ERR); 1966 return STATUS_FAIL; 1967 } 1968 } 1969 old_blk = delay_write->old_phyblock; 1970 new_blk = delay_write->new_phyblock; 1971 } else if (delay_write->delay_write_flag && 1972 (delay_write->logblock == log_blk) && 1973 (start_page == delay_write->pageoff)) { 1974 delay_write->delay_write_flag = 0; 1975 old_blk = delay_write->old_phyblock; 1976 new_blk = delay_write->new_phyblock; 1977 } else { 1978 retval = xd_delay_write(chip); 1979 if (retval != STATUS_SUCCESS) { 1980 set_sense_type(chip, lun, 1981 SENSE_TYPE_MEDIA_WRITE_ERR); 1982 return STATUS_FAIL; 1983 } 1984 #endif 1985 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 1986 new_blk = xd_get_unused_block(chip, zone_no); 1987 if ((old_blk == BLK_NOT_FOUND) || 1988 (new_blk == BLK_NOT_FOUND)) { 1989 set_sense_type(chip, lun, 1990 SENSE_TYPE_MEDIA_WRITE_ERR); 1991 return STATUS_FAIL; 1992 } 1993 1994 retval = xd_prepare_write(chip, old_blk, new_blk, 1995 log_blk, start_page); 1996 if (retval != STATUS_SUCCESS) { 1997 if (detect_card_cd(chip, XD_CARD) != 1998 STATUS_SUCCESS) { 1999 set_sense_type(chip, lun, 2000 SENSE_TYPE_MEDIA_NOT_PRESENT); 2001 return STATUS_FAIL; 2002 } 2003 set_sense_type(chip, lun, 2004 SENSE_TYPE_MEDIA_WRITE_ERR); 2005 return STATUS_FAIL; 2006 } 2007 #ifdef XD_DELAY_WRITE 2008 } 2009 #endif 2010 } else { 2011 #ifdef XD_DELAY_WRITE 2012 retval = xd_delay_write(chip); 2013 if (retval != STATUS_SUCCESS) { 2014 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2015 set_sense_type(chip, lun, 2016 SENSE_TYPE_MEDIA_NOT_PRESENT); 2017 return STATUS_FAIL; 2018 } 2019 set_sense_type(chip, lun, 2020 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2021 return STATUS_FAIL; 2022 } 2023 #endif 2024 2025 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2026 if (old_blk == BLK_NOT_FOUND) { 2027 set_sense_type(chip, lun, 2028 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2029 return STATUS_FAIL; 2030 } 2031 } 2032 2033 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk); 2034 2035 while (total_sec_cnt) { 2036 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2037 chip->card_fail |= XD_CARD; 2038 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2039 return STATUS_FAIL; 2040 } 2041 2042 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) 2043 end_page = xd_card->page_off + 1; 2044 else 2045 end_page = start_page + (u8)total_sec_cnt; 2046 2047 page_cnt = end_page - start_page; 2048 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2049 retval = xd_read_multiple_pages(chip, old_blk, log_blk, 2050 start_page, end_page, 2051 ptr, &index, &offset); 2052 if (retval != STATUS_SUCCESS) { 2053 set_sense_type(chip, lun, 2054 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2055 return STATUS_FAIL; 2056 } 2057 } else { 2058 retval = xd_write_multiple_pages(chip, old_blk, 2059 new_blk, log_blk, 2060 start_page, end_page, 2061 ptr, &index, &offset); 2062 if (retval != STATUS_SUCCESS) { 2063 set_sense_type(chip, lun, 2064 SENSE_TYPE_MEDIA_WRITE_ERR); 2065 return STATUS_FAIL; 2066 } 2067 } 2068 2069 total_sec_cnt -= page_cnt; 2070 if (scsi_sg_count(srb) == 0) 2071 ptr += page_cnt * 512; 2072 2073 if (total_sec_cnt == 0) 2074 break; 2075 2076 log_blk++; 2077 zone_no = (int)(log_blk / 1000); 2078 log_off = (u16)(log_blk % 1000); 2079 2080 if (xd_card->zone[zone_no].build_flag == 0) { 2081 retval = xd_build_l2p_tbl(chip, zone_no); 2082 if (retval != STATUS_SUCCESS) { 2083 chip->card_fail |= XD_CARD; 2084 set_sense_type(chip, lun, 2085 SENSE_TYPE_MEDIA_NOT_PRESENT); 2086 return STATUS_FAIL; 2087 } 2088 } 2089 2090 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2091 if (old_blk == BLK_NOT_FOUND) { 2092 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2093 set_sense_type(chip, lun, 2094 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2095 else 2096 set_sense_type(chip, lun, 2097 SENSE_TYPE_MEDIA_WRITE_ERR); 2098 2099 return STATUS_FAIL; 2100 } 2101 2102 if (srb->sc_data_direction == DMA_TO_DEVICE) { 2103 new_blk = xd_get_unused_block(chip, zone_no); 2104 if (new_blk == BLK_NOT_FOUND) { 2105 set_sense_type(chip, lun, 2106 SENSE_TYPE_MEDIA_WRITE_ERR); 2107 return STATUS_FAIL; 2108 } 2109 } 2110 2111 start_page = 0; 2112 } 2113 2114 if ((srb->sc_data_direction == DMA_TO_DEVICE) && 2115 (end_page != (xd_card->page_off + 1))) { 2116 #ifdef XD_DELAY_WRITE 2117 delay_write->delay_write_flag = 1; 2118 delay_write->old_phyblock = old_blk; 2119 delay_write->new_phyblock = new_blk; 2120 delay_write->logblock = log_blk; 2121 delay_write->pageoff = end_page; 2122 #else 2123 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2124 chip->card_fail |= XD_CARD; 2125 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2126 return STATUS_FAIL; 2127 } 2128 2129 retval = xd_finish_write(chip, old_blk, new_blk, 2130 log_blk, end_page); 2131 if (retval != STATUS_SUCCESS) { 2132 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2133 set_sense_type(chip, lun, 2134 SENSE_TYPE_MEDIA_NOT_PRESENT); 2135 return STATUS_FAIL; 2136 } 2137 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 2138 return STATUS_FAIL; 2139 } 2140 #endif 2141 } 2142 2143 scsi_set_resid(srb, 0); 2144 2145 return STATUS_SUCCESS; 2146 } 2147 2148 void xd_free_l2p_tbl(struct rtsx_chip *chip) 2149 { 2150 struct xd_info *xd_card = &chip->xd_card; 2151 int i = 0; 2152 2153 if (xd_card->zone) { 2154 for (i = 0; i < xd_card->zone_cnt; i++) { 2155 vfree(xd_card->zone[i].l2p_table); 2156 xd_card->zone[i].l2p_table = NULL; 2157 vfree(xd_card->zone[i].free_table); 2158 xd_card->zone[i].free_table = NULL; 2159 } 2160 vfree(xd_card->zone); 2161 xd_card->zone = NULL; 2162 } 2163 } 2164 2165 void xd_cleanup_work(struct rtsx_chip *chip) 2166 { 2167 #ifdef XD_DELAY_WRITE 2168 struct xd_info *xd_card = &chip->xd_card; 2169 2170 if (xd_card->delay_write.delay_write_flag) { 2171 dev_dbg(rtsx_dev(chip), "xD: delay write\n"); 2172 xd_delay_write(chip); 2173 xd_card->cleanup_counter = 0; 2174 } 2175 #endif 2176 } 2177 2178 int xd_power_off_card3v3(struct rtsx_chip *chip) 2179 { 2180 int retval; 2181 2182 retval = disable_card_clock(chip, XD_CARD); 2183 if (retval != STATUS_SUCCESS) { 2184 return STATUS_FAIL; 2185 } 2186 2187 retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 2188 if (retval) { 2189 return retval; 2190 } 2191 2192 if (!chip->ft2_fast_mode) { 2193 retval = card_power_off(chip, XD_CARD); 2194 if (retval != STATUS_SUCCESS) { 2195 return STATUS_FAIL; 2196 } 2197 2198 wait_timeout(50); 2199 } 2200 2201 if (chip->asic_code) { 2202 retval = xd_pull_ctl_disable(chip); 2203 if (retval != STATUS_SUCCESS) { 2204 return STATUS_FAIL; 2205 } 2206 } else { 2207 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); 2208 if (retval) { 2209 return retval; 2210 } 2211 } 2212 2213 return STATUS_SUCCESS; 2214 } 2215 2216 int release_xd_card(struct rtsx_chip *chip) 2217 { 2218 struct xd_info *xd_card = &chip->xd_card; 2219 int retval; 2220 2221 chip->card_ready &= ~XD_CARD; 2222 chip->card_fail &= ~XD_CARD; 2223 chip->card_wp &= ~XD_CARD; 2224 2225 xd_card->delay_write.delay_write_flag = 0; 2226 2227 xd_free_l2p_tbl(chip); 2228 2229 retval = xd_power_off_card3v3(chip); 2230 if (retval != STATUS_SUCCESS) { 2231 return STATUS_FAIL; 2232 } 2233 2234 return STATUS_SUCCESS; 2235 } 2236