1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "rtsx_transport.h" 30 #include "rtsx_scsi.h" 31 #include "rtsx_card.h" 32 #include "xd.h" 33 34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no); 35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff, 36 u8 start_page, u8 end_page); 37 38 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct xd_info *xd_card = &(chip->xd_card); 41 42 xd_card->err_code = err_code; 43 } 44 45 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code) 46 { 47 struct xd_info *xd_card = &(chip->xd_card); 48 49 return (xd_card->err_code == err_code); 50 } 51 52 static int xd_set_init_para(struct rtsx_chip *chip) 53 { 54 struct xd_info *xd_card = &(chip->xd_card); 55 int retval; 56 57 if (chip->asic_code) 58 xd_card->xd_clock = 47; 59 else 60 xd_card->xd_clock = CLK_50; 61 62 retval = switch_clock(chip, xd_card->xd_clock); 63 if (retval != STATUS_SUCCESS) { 64 rtsx_trace(chip); 65 return STATUS_FAIL; 66 } 67 68 return STATUS_SUCCESS; 69 } 70 71 static int xd_switch_clock(struct rtsx_chip *chip) 72 { 73 struct xd_info *xd_card = &(chip->xd_card); 74 int retval; 75 76 retval = select_card(chip, XD_CARD); 77 if (retval != STATUS_SUCCESS) { 78 rtsx_trace(chip); 79 return STATUS_FAIL; 80 } 81 82 retval = switch_clock(chip, xd_card->xd_clock); 83 if (retval != STATUS_SUCCESS) { 84 rtsx_trace(chip); 85 return STATUS_FAIL; 86 } 87 88 return STATUS_SUCCESS; 89 } 90 91 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len) 92 { 93 int retval, i; 94 u8 *ptr; 95 96 rtsx_init_cmd(chip); 97 98 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd); 99 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 100 XD_TRANSFER_START | XD_READ_ID); 101 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 102 XD_TRANSFER_END); 103 104 for (i = 0; i < 4; i++) 105 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0); 106 107 retval = rtsx_send_cmd(chip, XD_CARD, 20); 108 if (retval < 0) { 109 rtsx_trace(chip); 110 return STATUS_FAIL; 111 } 112 113 ptr = rtsx_get_cmd_data(chip) + 1; 114 if (id_buf && buf_len) { 115 if (buf_len > 4) 116 buf_len = 4; 117 memcpy(id_buf, ptr, buf_len); 118 } 119 120 return STATUS_SUCCESS; 121 } 122 123 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode) 124 { 125 struct xd_info *xd_card = &(chip->xd_card); 126 127 switch (mode) { 128 case XD_RW_ADDR: 129 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0); 130 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr); 131 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 132 0xFF, (u8)(addr >> 8)); 133 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 134 0xFF, (u8)(addr >> 16)); 135 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 136 xd_card->addr_cycle | XD_CALC_ECC | XD_BA_NO_TRANSFORM); 137 break; 138 139 case XD_ERASE_ADDR: 140 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 142 0xFF, (u8)(addr >> 8)); 143 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 144 0xFF, (u8)(addr >> 16)); 145 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF, 146 (xd_card->addr_cycle - 1) | XD_CALC_ECC | 147 XD_BA_NO_TRANSFORM); 148 break; 149 150 default: 151 break; 152 } 153 } 154 155 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr, 156 u8 *buf, int buf_len) 157 { 158 int retval, i; 159 160 rtsx_init_cmd(chip); 161 162 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 163 164 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 165 0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT); 166 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 167 XD_TRANSFER_END, XD_TRANSFER_END); 168 169 for (i = 0; i < 6; i++) 170 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i), 171 0, 0); 172 for (i = 0; i < 4; i++) 173 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i), 174 0, 0); 175 rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0); 176 177 retval = rtsx_send_cmd(chip, XD_CARD, 500); 178 if (retval < 0) { 179 rtsx_trace(chip); 180 return STATUS_FAIL; 181 } 182 183 if (buf && buf_len) { 184 u8 *ptr = rtsx_get_cmd_data(chip) + 1; 185 186 if (buf_len > 11) 187 buf_len = 11; 188 memcpy(buf, ptr, buf_len); 189 } 190 191 return STATUS_SUCCESS; 192 } 193 194 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset, 195 u8 *buf, int buf_len) 196 { 197 int retval, i; 198 199 if (!buf || (buf_len < 0)) { 200 rtsx_trace(chip); 201 return STATUS_FAIL; 202 } 203 204 rtsx_init_cmd(chip); 205 206 for (i = 0; i < buf_len; i++) 207 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 208 0, 0); 209 210 retval = rtsx_send_cmd(chip, 0, 250); 211 if (retval < 0) { 212 rtsx_clear_xd_error(chip); 213 rtsx_trace(chip); 214 return STATUS_FAIL; 215 } 216 217 memcpy(buf, rtsx_get_cmd_data(chip), buf_len); 218 219 return STATUS_SUCCESS; 220 } 221 222 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf, 223 int buf_len) 224 { 225 int retval; 226 u8 reg; 227 228 if (!buf || (buf_len < 10)) { 229 rtsx_trace(chip); 230 return STATUS_FAIL; 231 } 232 233 rtsx_init_cmd(chip); 234 235 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 236 237 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 238 0x01, PINGPONG_BUFFER); 239 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 240 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 241 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 242 243 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 244 XD_TRANSFER_START | XD_READ_PAGES); 245 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END, 246 XD_TRANSFER_END); 247 248 retval = rtsx_send_cmd(chip, XD_CARD, 250); 249 if (retval == -ETIMEDOUT) { 250 rtsx_clear_xd_error(chip); 251 rtsx_trace(chip); 252 return STATUS_FAIL; 253 } 254 255 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®); 256 if (retval) { 257 rtsx_trace(chip); 258 return retval; 259 } 260 if (reg != XD_GPG) { 261 rtsx_clear_xd_error(chip); 262 rtsx_trace(chip); 263 return STATUS_FAIL; 264 } 265 266 retval = rtsx_read_register(chip, XD_CTL, ®); 267 if (retval) { 268 rtsx_trace(chip); 269 return retval; 270 } 271 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) { 272 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len); 273 if (retval != STATUS_SUCCESS) { 274 rtsx_trace(chip); 275 return STATUS_FAIL; 276 } 277 if (reg & XD_ECC1_ERROR) { 278 u8 ecc_bit, ecc_byte; 279 280 retval = rtsx_read_register(chip, XD_ECC_BIT1, 281 &ecc_bit); 282 if (retval) { 283 rtsx_trace(chip); 284 return retval; 285 } 286 retval = rtsx_read_register(chip, XD_ECC_BYTE1, 287 &ecc_byte); 288 if (retval) { 289 rtsx_trace(chip); 290 return retval; 291 } 292 293 dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n", 294 ecc_bit, ecc_byte); 295 if (ecc_byte < buf_len) { 296 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 297 buf[ecc_byte]); 298 buf[ecc_byte] ^= (1 << ecc_bit); 299 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 300 buf[ecc_byte]); 301 } 302 } 303 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) { 304 rtsx_clear_xd_error(chip); 305 306 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len); 307 if (retval != STATUS_SUCCESS) { 308 rtsx_trace(chip); 309 return STATUS_FAIL; 310 } 311 if (reg & XD_ECC2_ERROR) { 312 u8 ecc_bit, ecc_byte; 313 314 retval = rtsx_read_register(chip, XD_ECC_BIT2, 315 &ecc_bit); 316 if (retval) { 317 rtsx_trace(chip); 318 return retval; 319 } 320 retval = rtsx_read_register(chip, XD_ECC_BYTE2, 321 &ecc_byte); 322 if (retval) { 323 rtsx_trace(chip); 324 return retval; 325 } 326 327 dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n", 328 ecc_bit, ecc_byte); 329 if (ecc_byte < buf_len) { 330 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n", 331 buf[ecc_byte]); 332 buf[ecc_byte] ^= (1 << ecc_bit); 333 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n", 334 buf[ecc_byte]); 335 } 336 } 337 } else { 338 rtsx_clear_xd_error(chip); 339 rtsx_trace(chip); 340 return STATUS_FAIL; 341 } 342 343 return STATUS_SUCCESS; 344 } 345 346 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip) 347 { 348 if (CHECK_PID(chip, 0x5208)) { 349 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 350 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 351 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 352 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 353 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 354 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 355 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 356 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); 357 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 358 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 359 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 360 MS_D5_PD | MS_D4_PD); 361 } else if (CHECK_PID(chip, 0x5288)) { 362 if (CHECK_BARO_PKG(chip, QFN)) { 363 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 364 0xFF, 0x55); 365 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 366 0xFF, 0x55); 367 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 368 0xFF, 0x4B); 369 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 370 0xFF, 0x69); 371 } 372 } 373 } 374 375 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip) 376 { 377 if (CHECK_BARO_PKG(chip, QFN)) { 378 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55); 379 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55); 380 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B); 381 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55); 382 } 383 } 384 385 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip) 386 { 387 if (CHECK_PID(chip, 0x5208)) { 388 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 389 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 390 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 391 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 392 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 393 XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU); 394 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 395 XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD); 396 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 397 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 398 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 399 MS_D5_PD | MS_D4_PD); 400 } else if (CHECK_PID(chip, 0x5288)) { 401 if (CHECK_BARO_PKG(chip, QFN)) { 402 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 403 0xFF, 0x55); 404 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 405 0xFF, 0x55); 406 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 407 0xFF, 0x53); 408 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 409 0xFF, 0xA9); 410 } 411 } 412 } 413 414 static int xd_pull_ctl_disable(struct rtsx_chip *chip) 415 { 416 int retval; 417 418 if (CHECK_PID(chip, 0x5208)) { 419 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 420 XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD); 421 if (retval) { 422 rtsx_trace(chip); 423 return retval; 424 } 425 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 426 XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD); 427 if (retval) { 428 rtsx_trace(chip); 429 return retval; 430 } 431 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 432 XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 433 if (retval) { 434 rtsx_trace(chip); 435 return retval; 436 } 437 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 438 XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD); 439 if (retval) { 440 rtsx_trace(chip); 441 return retval; 442 } 443 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 444 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 445 if (retval) { 446 rtsx_trace(chip); 447 return retval; 448 } 449 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 450 MS_D5_PD | MS_D4_PD); 451 if (retval) { 452 rtsx_trace(chip); 453 return retval; 454 } 455 } else if (CHECK_PID(chip, 0x5288)) { 456 if (CHECK_BARO_PKG(chip, QFN)) { 457 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 458 0xFF, 0x55); 459 if (retval) { 460 rtsx_trace(chip); 461 return retval; 462 } 463 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 464 0xFF, 0x55); 465 if (retval) { 466 rtsx_trace(chip); 467 return retval; 468 } 469 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 470 0xFF, 0x4B); 471 if (retval) { 472 rtsx_trace(chip); 473 return retval; 474 } 475 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 476 0xFF, 0x69); 477 if (retval) { 478 rtsx_trace(chip); 479 return retval; 480 } 481 } 482 } 483 484 return STATUS_SUCCESS; 485 } 486 487 static int reset_xd(struct rtsx_chip *chip) 488 { 489 struct xd_info *xd_card = &(chip->xd_card); 490 int retval, i, j; 491 u8 *ptr, id_buf[4], redunt[11]; 492 493 retval = select_card(chip, XD_CARD); 494 if (retval != STATUS_SUCCESS) { 495 rtsx_trace(chip); 496 return STATUS_FAIL; 497 } 498 499 rtsx_init_cmd(chip); 500 501 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF, 502 XD_PGSTS_NOT_FF); 503 if (chip->asic_code) { 504 if (!CHECK_PID(chip, 0x5288)) 505 xd_fill_pull_ctl_disable(chip); 506 else 507 xd_fill_pull_ctl_stage1_barossa(chip); 508 } else { 509 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 510 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) | 0x20); 511 } 512 513 if (!chip->ft2_fast_mode) 514 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT, 515 XD_NO_AUTO_PWR_OFF, 0); 516 517 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0); 518 519 retval = rtsx_send_cmd(chip, XD_CARD, 100); 520 if (retval < 0) { 521 rtsx_trace(chip); 522 return STATUS_FAIL; 523 } 524 525 if (!chip->ft2_fast_mode) { 526 retval = card_power_off(chip, XD_CARD); 527 if (retval != STATUS_SUCCESS) { 528 rtsx_trace(chip); 529 return STATUS_FAIL; 530 } 531 532 wait_timeout(250); 533 534 rtsx_init_cmd(chip); 535 536 if (chip->asic_code) { 537 xd_fill_pull_ctl_enable(chip); 538 } else { 539 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 540 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 541 0x20); 542 } 543 544 retval = rtsx_send_cmd(chip, XD_CARD, 100); 545 if (retval < 0) { 546 rtsx_trace(chip); 547 return STATUS_FAIL; 548 } 549 550 retval = card_power_on(chip, XD_CARD); 551 if (retval != STATUS_SUCCESS) { 552 rtsx_trace(chip); 553 return STATUS_FAIL; 554 } 555 556 #ifdef SUPPORT_OCP 557 wait_timeout(50); 558 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 559 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 560 chip->ocp_stat); 561 rtsx_trace(chip); 562 return STATUS_FAIL; 563 } 564 #endif 565 } 566 567 rtsx_init_cmd(chip); 568 569 if (chip->ft2_fast_mode) { 570 if (chip->asic_code) { 571 xd_fill_pull_ctl_enable(chip); 572 } else { 573 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 574 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2) | 575 0x20); 576 } 577 } 578 579 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN); 580 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN); 581 582 retval = rtsx_send_cmd(chip, XD_CARD, 100); 583 if (retval < 0) { 584 rtsx_trace(chip); 585 return STATUS_FAIL; 586 } 587 588 if (!chip->ft2_fast_mode) 589 wait_timeout(200); 590 591 retval = xd_set_init_para(chip); 592 if (retval != STATUS_SUCCESS) { 593 rtsx_trace(chip); 594 return STATUS_FAIL; 595 } 596 597 /* Read ID to check if the timing setting is right */ 598 for (i = 0; i < 4; i++) { 599 rtsx_init_cmd(chip); 600 601 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF, 602 XD_TIME_SETUP_STEP * 3 + 603 XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i); 604 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF, 605 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 + i) + 606 XD_TIME_RWN_STEP * (3 + i)); 607 608 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 609 XD_TRANSFER_START | XD_RESET); 610 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 611 XD_TRANSFER_END, XD_TRANSFER_END); 612 613 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 614 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 615 616 retval = rtsx_send_cmd(chip, XD_CARD, 100); 617 if (retval < 0) { 618 rtsx_trace(chip); 619 return STATUS_FAIL; 620 } 621 622 ptr = rtsx_get_cmd_data(chip) + 1; 623 624 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n", 625 ptr[0], ptr[1]); 626 627 if (((ptr[0] & READY_FLAG) != READY_STATE) || 628 !(ptr[1] & XD_RDY)) 629 continue; 630 631 retval = xd_read_id(chip, READ_ID, id_buf, 4); 632 if (retval != STATUS_SUCCESS) { 633 rtsx_trace(chip); 634 return STATUS_FAIL; 635 } 636 637 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n", 638 id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 639 640 xd_card->device_code = id_buf[1]; 641 642 /* Check if the xD card is supported */ 643 switch (xd_card->device_code) { 644 case XD_4M_X8_512_1: 645 case XD_4M_X8_512_2: 646 xd_card->block_shift = 4; 647 xd_card->page_off = 0x0F; 648 xd_card->addr_cycle = 3; 649 xd_card->zone_cnt = 1; 650 xd_card->capacity = 8000; 651 XD_SET_4MB(xd_card); 652 break; 653 case XD_8M_X8_512: 654 xd_card->block_shift = 4; 655 xd_card->page_off = 0x0F; 656 xd_card->addr_cycle = 3; 657 xd_card->zone_cnt = 1; 658 xd_card->capacity = 16000; 659 break; 660 case XD_16M_X8_512: 661 XD_PAGE_512(xd_card); 662 xd_card->addr_cycle = 3; 663 xd_card->zone_cnt = 1; 664 xd_card->capacity = 32000; 665 break; 666 case XD_32M_X8_512: 667 XD_PAGE_512(xd_card); 668 xd_card->addr_cycle = 3; 669 xd_card->zone_cnt = 2; 670 xd_card->capacity = 64000; 671 break; 672 case XD_64M_X8_512: 673 XD_PAGE_512(xd_card); 674 xd_card->addr_cycle = 4; 675 xd_card->zone_cnt = 4; 676 xd_card->capacity = 128000; 677 break; 678 case XD_128M_X8_512: 679 XD_PAGE_512(xd_card); 680 xd_card->addr_cycle = 4; 681 xd_card->zone_cnt = 8; 682 xd_card->capacity = 256000; 683 break; 684 case XD_256M_X8_512: 685 XD_PAGE_512(xd_card); 686 xd_card->addr_cycle = 4; 687 xd_card->zone_cnt = 16; 688 xd_card->capacity = 512000; 689 break; 690 case XD_512M_X8: 691 XD_PAGE_512(xd_card); 692 xd_card->addr_cycle = 4; 693 xd_card->zone_cnt = 32; 694 xd_card->capacity = 1024000; 695 break; 696 case xD_1G_X8_512: 697 XD_PAGE_512(xd_card); 698 xd_card->addr_cycle = 4; 699 xd_card->zone_cnt = 64; 700 xd_card->capacity = 2048000; 701 break; 702 case xD_2G_X8_512: 703 XD_PAGE_512(xd_card); 704 xd_card->addr_cycle = 4; 705 xd_card->zone_cnt = 128; 706 xd_card->capacity = 4096000; 707 break; 708 default: 709 continue; 710 } 711 712 /* Confirm timing setting */ 713 for (j = 0; j < 10; j++) { 714 retval = xd_read_id(chip, READ_ID, id_buf, 4); 715 if (retval != STATUS_SUCCESS) { 716 rtsx_trace(chip); 717 return STATUS_FAIL; 718 } 719 720 if (id_buf[1] != xd_card->device_code) 721 break; 722 } 723 724 if (j == 10) 725 break; 726 } 727 728 if (i == 4) { 729 xd_card->block_shift = 0; 730 xd_card->page_off = 0; 731 xd_card->addr_cycle = 0; 732 xd_card->capacity = 0; 733 734 rtsx_trace(chip); 735 return STATUS_FAIL; 736 } 737 738 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4); 739 if (retval != STATUS_SUCCESS) { 740 rtsx_trace(chip); 741 return STATUS_FAIL; 742 } 743 dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n", 744 id_buf[0], id_buf[1], id_buf[2], id_buf[3]); 745 if (id_buf[2] != XD_ID_CODE) { 746 rtsx_trace(chip); 747 return STATUS_FAIL; 748 } 749 750 /* Search CIS block */ 751 for (i = 0; i < 24; i++) { 752 u32 page_addr; 753 754 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 755 rtsx_trace(chip); 756 return STATUS_FAIL; 757 } 758 759 page_addr = (u32)i << xd_card->block_shift; 760 761 for (j = 0; j < 3; j++) { 762 retval = xd_read_redundant(chip, page_addr, redunt, 11); 763 if (retval == STATUS_SUCCESS) 764 break; 765 } 766 if (j == 3) 767 continue; 768 769 if (redunt[BLOCK_STATUS] != XD_GBLK) 770 continue; 771 772 j = 0; 773 if (redunt[PAGE_STATUS] != XD_GPG) { 774 for (j = 1; j <= 8; j++) { 775 retval = xd_read_redundant(chip, page_addr + j, 776 redunt, 11); 777 if (retval == STATUS_SUCCESS) { 778 if (redunt[PAGE_STATUS] == XD_GPG) 779 break; 780 } 781 } 782 783 if (j == 9) 784 break; 785 } 786 787 /* Check CIS data */ 788 if ((redunt[BLOCK_STATUS] == XD_GBLK) && 789 (redunt[PARITY] & XD_BA1_ALL0)) { 790 u8 buf[10]; 791 792 page_addr += j; 793 794 retval = xd_read_cis(chip, page_addr, buf, 10); 795 if (retval != STATUS_SUCCESS) { 796 rtsx_trace(chip); 797 return STATUS_FAIL; 798 } 799 800 if ((buf[0] == 0x01) && (buf[1] == 0x03) && 801 (buf[2] == 0xD9) 802 && (buf[3] == 0x01) && (buf[4] == 0xFF) 803 && (buf[5] == 0x18) && (buf[6] == 0x02) 804 && (buf[7] == 0xDF) && (buf[8] == 0x01) 805 && (buf[9] == 0x20)) { 806 xd_card->cis_block = (u16)i; 807 } 808 } 809 810 break; 811 } 812 813 dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block); 814 if (xd_card->cis_block == 0xFFFF) { 815 rtsx_trace(chip); 816 return STATUS_FAIL; 817 } 818 819 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity; 820 821 return STATUS_SUCCESS; 822 } 823 824 static int xd_check_data_blank(u8 *redunt) 825 { 826 int i; 827 828 for (i = 0; i < 6; i++) { 829 if (redunt[PAGE_STATUS + i] != 0xFF) 830 return 0; 831 } 832 833 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 834 != (XD_ECC1_ALL1 | XD_ECC2_ALL1)) 835 return 0; 836 837 838 for (i = 0; i < 4; i++) { 839 if (redunt[RESERVED0 + i] != 0xFF) 840 return 0; 841 } 842 843 return 1; 844 } 845 846 static u16 xd_load_log_block_addr(u8 *redunt) 847 { 848 u16 addr = 0xFFFF; 849 850 if (redunt[PARITY] & XD_BA1_BA2_EQL) 851 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 852 redunt[BLOCK_ADDR1_L]; 853 else if (redunt[PARITY] & XD_BA1_VALID) 854 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) | 855 redunt[BLOCK_ADDR1_L]; 856 else if (redunt[PARITY] & XD_BA2_VALID) 857 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) | 858 redunt[BLOCK_ADDR2_L]; 859 860 return addr; 861 } 862 863 static int xd_init_l2p_tbl(struct rtsx_chip *chip) 864 { 865 struct xd_info *xd_card = &(chip->xd_card); 866 int size, i; 867 868 dev_dbg(rtsx_dev(chip), "xd_init_l2p_tbl: zone_cnt = %d\n", 869 xd_card->zone_cnt); 870 871 if (xd_card->zone_cnt < 1) { 872 rtsx_trace(chip); 873 return STATUS_FAIL; 874 } 875 876 size = xd_card->zone_cnt * sizeof(struct zone_entry); 877 dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size); 878 879 xd_card->zone = vmalloc(size); 880 if (!xd_card->zone) { 881 rtsx_trace(chip); 882 return STATUS_ERROR; 883 } 884 885 for (i = 0; i < xd_card->zone_cnt; i++) { 886 xd_card->zone[i].build_flag = 0; 887 xd_card->zone[i].l2p_table = NULL; 888 xd_card->zone[i].free_table = NULL; 889 xd_card->zone[i].get_index = 0; 890 xd_card->zone[i].set_index = 0; 891 xd_card->zone[i].unused_blk_cnt = 0; 892 } 893 894 return STATUS_SUCCESS; 895 } 896 897 static inline void free_zone(struct zone_entry *zone) 898 { 899 if (!zone) 900 return; 901 902 zone->build_flag = 0; 903 zone->set_index = 0; 904 zone->get_index = 0; 905 zone->unused_blk_cnt = 0; 906 if (zone->l2p_table) { 907 vfree(zone->l2p_table); 908 zone->l2p_table = NULL; 909 } 910 if (zone->free_table) { 911 vfree(zone->free_table); 912 zone->free_table = NULL; 913 } 914 } 915 916 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk) 917 { 918 struct xd_info *xd_card = &(chip->xd_card); 919 struct zone_entry *zone; 920 int zone_no; 921 922 zone_no = (int)phy_blk >> 10; 923 if (zone_no >= xd_card->zone_cnt) { 924 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n", 925 zone_no, xd_card->zone_cnt); 926 return; 927 } 928 zone = &(xd_card->zone[zone_no]); 929 930 if (zone->free_table == NULL) { 931 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS) 932 return; 933 } 934 935 if ((zone->set_index >= XD_FREE_TABLE_CNT) 936 || (zone->set_index < 0)) { 937 free_zone(zone); 938 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n"); 939 return; 940 } 941 942 dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n", 943 zone->set_index); 944 945 zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff); 946 if (zone->set_index >= XD_FREE_TABLE_CNT) 947 zone->set_index = 0; 948 zone->unused_blk_cnt++; 949 } 950 951 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no) 952 { 953 struct xd_info *xd_card = &(chip->xd_card); 954 struct zone_entry *zone; 955 u32 phy_blk; 956 957 if (zone_no >= xd_card->zone_cnt) { 958 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n", 959 zone_no, xd_card->zone_cnt); 960 return BLK_NOT_FOUND; 961 } 962 zone = &(xd_card->zone[zone_no]); 963 964 if ((zone->unused_blk_cnt == 0) || 965 (zone->set_index == zone->get_index)) { 966 free_zone(zone); 967 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n"); 968 return BLK_NOT_FOUND; 969 } 970 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) { 971 free_zone(zone); 972 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n"); 973 return BLK_NOT_FOUND; 974 } 975 976 dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n", 977 zone->get_index); 978 979 phy_blk = zone->free_table[zone->get_index]; 980 zone->free_table[zone->get_index++] = 0xFFFF; 981 if (zone->get_index >= XD_FREE_TABLE_CNT) 982 zone->get_index = 0; 983 zone->unused_blk_cnt--; 984 985 phy_blk += ((u32)(zone_no) << 10); 986 return phy_blk; 987 } 988 989 static void xd_set_l2p_tbl(struct rtsx_chip *chip, 990 int zone_no, u16 log_off, u16 phy_off) 991 { 992 struct xd_info *xd_card = &(chip->xd_card); 993 struct zone_entry *zone; 994 995 zone = &(xd_card->zone[zone_no]); 996 zone->l2p_table[log_off] = phy_off; 997 } 998 999 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off) 1000 { 1001 struct xd_info *xd_card = &(chip->xd_card); 1002 struct zone_entry *zone; 1003 int retval; 1004 1005 zone = &(xd_card->zone[zone_no]); 1006 if (zone->l2p_table[log_off] == 0xFFFF) { 1007 u32 phy_blk = 0; 1008 int i; 1009 1010 #ifdef XD_DELAY_WRITE 1011 retval = xd_delay_write(chip); 1012 if (retval != STATUS_SUCCESS) { 1013 dev_dbg(rtsx_dev(chip), "In xd_get_l2p_tbl, delay write fail!\n"); 1014 return BLK_NOT_FOUND; 1015 } 1016 #endif 1017 1018 if (zone->unused_blk_cnt <= 0) { 1019 dev_dbg(rtsx_dev(chip), "No unused block!\n"); 1020 return BLK_NOT_FOUND; 1021 } 1022 1023 for (i = 0; i < zone->unused_blk_cnt; i++) { 1024 phy_blk = xd_get_unused_block(chip, zone_no); 1025 if (phy_blk == BLK_NOT_FOUND) { 1026 dev_dbg(rtsx_dev(chip), "No unused block available!\n"); 1027 return BLK_NOT_FOUND; 1028 } 1029 1030 retval = xd_init_page(chip, phy_blk, log_off, 1031 0, xd_card->page_off + 1); 1032 if (retval == STATUS_SUCCESS) 1033 break; 1034 } 1035 if (i >= zone->unused_blk_cnt) { 1036 dev_dbg(rtsx_dev(chip), "No good unused block available!\n"); 1037 return BLK_NOT_FOUND; 1038 } 1039 1040 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF)); 1041 return phy_blk; 1042 } 1043 1044 return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10); 1045 } 1046 1047 int reset_xd_card(struct rtsx_chip *chip) 1048 { 1049 struct xd_info *xd_card = &(chip->xd_card); 1050 int retval; 1051 1052 memset(xd_card, 0, sizeof(struct xd_info)); 1053 1054 xd_card->block_shift = 0; 1055 xd_card->page_off = 0; 1056 xd_card->addr_cycle = 0; 1057 xd_card->capacity = 0; 1058 xd_card->zone_cnt = 0; 1059 xd_card->cis_block = 0xFFFF; 1060 xd_card->delay_write.delay_write_flag = 0; 1061 1062 retval = enable_card_clock(chip, XD_CARD); 1063 if (retval != STATUS_SUCCESS) { 1064 rtsx_trace(chip); 1065 return STATUS_FAIL; 1066 } 1067 1068 retval = reset_xd(chip); 1069 if (retval != STATUS_SUCCESS) { 1070 rtsx_trace(chip); 1071 return STATUS_FAIL; 1072 } 1073 1074 retval = xd_init_l2p_tbl(chip); 1075 if (retval != STATUS_SUCCESS) { 1076 rtsx_trace(chip); 1077 return STATUS_FAIL; 1078 } 1079 1080 return STATUS_SUCCESS; 1081 } 1082 1083 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk) 1084 { 1085 struct xd_info *xd_card = &(chip->xd_card); 1086 int retval; 1087 u32 page_addr; 1088 u8 reg = 0; 1089 1090 dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk); 1091 1092 if (phy_blk == BLK_NOT_FOUND) { 1093 rtsx_trace(chip); 1094 return STATUS_FAIL; 1095 } 1096 1097 rtsx_init_cmd(chip); 1098 1099 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1100 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK); 1101 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF); 1102 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF); 1103 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF); 1104 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF); 1105 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF); 1106 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF); 1107 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF); 1108 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF); 1109 1110 page_addr = phy_blk << xd_card->block_shift; 1111 1112 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1113 1114 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1115 xd_card->page_off + 1); 1116 1117 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1118 XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1119 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1120 XD_TRANSFER_END, XD_TRANSFER_END); 1121 1122 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1123 if (retval < 0) { 1124 rtsx_clear_xd_error(chip); 1125 rtsx_read_register(chip, XD_DAT, ®); 1126 if (reg & PROGRAM_ERROR) 1127 xd_set_err_code(chip, XD_PRG_ERROR); 1128 else 1129 xd_set_err_code(chip, XD_TO_ERROR); 1130 rtsx_trace(chip); 1131 return STATUS_FAIL; 1132 } 1133 1134 return STATUS_SUCCESS; 1135 } 1136 1137 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, 1138 u16 logoff, u8 start_page, u8 end_page) 1139 { 1140 struct xd_info *xd_card = &(chip->xd_card); 1141 int retval; 1142 u32 page_addr; 1143 u8 reg = 0; 1144 1145 dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk); 1146 1147 if (start_page > end_page) { 1148 rtsx_trace(chip); 1149 return STATUS_FAIL; 1150 } 1151 if (phy_blk == BLK_NOT_FOUND) { 1152 rtsx_trace(chip); 1153 return STATUS_FAIL; 1154 } 1155 1156 rtsx_init_cmd(chip); 1157 1158 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF); 1159 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF); 1160 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1161 0xFF, (u8)(logoff >> 8)); 1162 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff); 1163 1164 page_addr = (phy_blk << xd_card->block_shift) + start_page; 1165 1166 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1167 1168 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 1169 XD_BA_TRANSFORM, XD_BA_TRANSFORM); 1170 1171 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 1172 0xFF, (end_page - start_page)); 1173 1174 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1175 0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT); 1176 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1177 XD_TRANSFER_END, XD_TRANSFER_END); 1178 1179 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1180 if (retval < 0) { 1181 rtsx_clear_xd_error(chip); 1182 rtsx_read_register(chip, XD_DAT, ®); 1183 if (reg & PROGRAM_ERROR) { 1184 xd_mark_bad_block(chip, phy_blk); 1185 xd_set_err_code(chip, XD_PRG_ERROR); 1186 } else { 1187 xd_set_err_code(chip, XD_TO_ERROR); 1188 } 1189 rtsx_trace(chip); 1190 return STATUS_FAIL; 1191 } 1192 1193 return STATUS_SUCCESS; 1194 } 1195 1196 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk, 1197 u8 start_page, u8 end_page) 1198 { 1199 struct xd_info *xd_card = &(chip->xd_card); 1200 u32 old_page, new_page; 1201 u8 i, reg = 0; 1202 int retval; 1203 1204 dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n", 1205 old_blk, new_blk); 1206 1207 if (start_page > end_page) { 1208 rtsx_trace(chip); 1209 return STATUS_FAIL; 1210 } 1211 1212 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) { 1213 rtsx_trace(chip); 1214 return STATUS_FAIL; 1215 } 1216 1217 old_page = (old_blk << xd_card->block_shift) + start_page; 1218 new_page = (new_blk << xd_card->block_shift) + start_page; 1219 1220 XD_CLR_BAD_NEWBLK(xd_card); 1221 1222 retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01, 1223 PINGPONG_BUFFER); 1224 if (retval) { 1225 rtsx_trace(chip); 1226 return retval; 1227 } 1228 1229 for (i = start_page; i < end_page; i++) { 1230 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1231 rtsx_clear_xd_error(chip); 1232 xd_set_err_code(chip, XD_NO_CARD); 1233 rtsx_trace(chip); 1234 return STATUS_FAIL; 1235 } 1236 1237 rtsx_init_cmd(chip); 1238 1239 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR); 1240 1241 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1242 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1243 XD_AUTO_CHK_DATA_STATUS, 0); 1244 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1245 XD_TRANSFER_START | XD_READ_PAGES); 1246 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1247 XD_TRANSFER_END, XD_TRANSFER_END); 1248 1249 retval = rtsx_send_cmd(chip, XD_CARD, 500); 1250 if (retval < 0) { 1251 rtsx_clear_xd_error(chip); 1252 reg = 0; 1253 rtsx_read_register(chip, XD_CTL, ®); 1254 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) { 1255 wait_timeout(100); 1256 1257 if (detect_card_cd(chip, 1258 XD_CARD) != STATUS_SUCCESS) { 1259 xd_set_err_code(chip, XD_NO_CARD); 1260 rtsx_trace(chip); 1261 return STATUS_FAIL; 1262 } 1263 1264 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) == 1265 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) 1266 || ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) == 1267 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { 1268 rtsx_write_register(chip, 1269 XD_PAGE_STATUS, 0xFF, 1270 XD_BPG); 1271 rtsx_write_register(chip, 1272 XD_BLOCK_STATUS, 0xFF, 1273 XD_GBLK); 1274 XD_SET_BAD_OLDBLK(xd_card); 1275 dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n", 1276 old_blk); 1277 } 1278 } else { 1279 xd_set_err_code(chip, XD_TO_ERROR); 1280 rtsx_trace(chip); 1281 return STATUS_FAIL; 1282 } 1283 } 1284 1285 if (XD_CHK_BAD_OLDBLK(xd_card)) 1286 rtsx_clear_xd_error(chip); 1287 1288 rtsx_init_cmd(chip); 1289 1290 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR); 1291 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1); 1292 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1293 XD_TRANSFER_START | XD_WRITE_PAGES); 1294 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1295 XD_TRANSFER_END, XD_TRANSFER_END); 1296 1297 retval = rtsx_send_cmd(chip, XD_CARD, 300); 1298 if (retval < 0) { 1299 rtsx_clear_xd_error(chip); 1300 reg = 0; 1301 rtsx_read_register(chip, XD_DAT, ®); 1302 if (reg & PROGRAM_ERROR) { 1303 xd_mark_bad_block(chip, new_blk); 1304 xd_set_err_code(chip, XD_PRG_ERROR); 1305 XD_SET_BAD_NEWBLK(xd_card); 1306 } else { 1307 xd_set_err_code(chip, XD_TO_ERROR); 1308 } 1309 rtsx_trace(chip); 1310 return STATUS_FAIL; 1311 } 1312 1313 old_page++; 1314 new_page++; 1315 } 1316 1317 return STATUS_SUCCESS; 1318 } 1319 1320 static int xd_reset_cmd(struct rtsx_chip *chip) 1321 { 1322 int retval; 1323 u8 *ptr; 1324 1325 rtsx_init_cmd(chip); 1326 1327 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1328 0xFF, XD_TRANSFER_START | XD_RESET); 1329 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1330 XD_TRANSFER_END, XD_TRANSFER_END); 1331 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1332 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0); 1333 1334 retval = rtsx_send_cmd(chip, XD_CARD, 100); 1335 if (retval < 0) { 1336 rtsx_trace(chip); 1337 return STATUS_FAIL; 1338 } 1339 1340 ptr = rtsx_get_cmd_data(chip) + 1; 1341 if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY)) 1342 return STATUS_SUCCESS; 1343 1344 rtsx_trace(chip); 1345 return STATUS_FAIL; 1346 } 1347 1348 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk) 1349 { 1350 struct xd_info *xd_card = &(chip->xd_card); 1351 u32 page_addr; 1352 u8 reg = 0, *ptr; 1353 int i, retval; 1354 1355 if (phy_blk == BLK_NOT_FOUND) { 1356 rtsx_trace(chip); 1357 return STATUS_FAIL; 1358 } 1359 1360 page_addr = phy_blk << xd_card->block_shift; 1361 1362 for (i = 0; i < 3; i++) { 1363 rtsx_init_cmd(chip); 1364 1365 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR); 1366 1367 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1368 XD_TRANSFER_START | XD_ERASE); 1369 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1370 XD_TRANSFER_END, XD_TRANSFER_END); 1371 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0); 1372 1373 retval = rtsx_send_cmd(chip, XD_CARD, 250); 1374 if (retval < 0) { 1375 rtsx_clear_xd_error(chip); 1376 rtsx_read_register(chip, XD_DAT, ®); 1377 if (reg & PROGRAM_ERROR) { 1378 xd_mark_bad_block(chip, phy_blk); 1379 xd_set_err_code(chip, XD_PRG_ERROR); 1380 rtsx_trace(chip); 1381 return STATUS_FAIL; 1382 } 1383 xd_set_err_code(chip, XD_ERASE_FAIL); 1384 retval = xd_reset_cmd(chip); 1385 if (retval != STATUS_SUCCESS) { 1386 rtsx_trace(chip); 1387 return STATUS_FAIL; 1388 } 1389 continue; 1390 } 1391 1392 ptr = rtsx_get_cmd_data(chip) + 1; 1393 if (*ptr & PROGRAM_ERROR) { 1394 xd_mark_bad_block(chip, phy_blk); 1395 xd_set_err_code(chip, XD_PRG_ERROR); 1396 rtsx_trace(chip); 1397 return STATUS_FAIL; 1398 } 1399 1400 return STATUS_SUCCESS; 1401 } 1402 1403 xd_mark_bad_block(chip, phy_blk); 1404 xd_set_err_code(chip, XD_ERASE_FAIL); 1405 rtsx_trace(chip); 1406 return STATUS_FAIL; 1407 } 1408 1409 1410 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no) 1411 { 1412 struct xd_info *xd_card = &(chip->xd_card); 1413 struct zone_entry *zone; 1414 int retval; 1415 u32 start, end, i; 1416 u16 max_logoff, cur_fst_page_logoff; 1417 u16 cur_lst_page_logoff, ent_lst_page_logoff; 1418 u8 redunt[11]; 1419 1420 dev_dbg(rtsx_dev(chip), "xd_build_l2p_tbl: %d\n", zone_no); 1421 1422 if (xd_card->zone == NULL) { 1423 retval = xd_init_l2p_tbl(chip); 1424 if (retval != STATUS_SUCCESS) 1425 return retval; 1426 } 1427 1428 if (xd_card->zone[zone_no].build_flag) { 1429 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n", 1430 zone_no); 1431 return STATUS_SUCCESS; 1432 } 1433 1434 zone = &(xd_card->zone[zone_no]); 1435 1436 if (zone->l2p_table == NULL) { 1437 zone->l2p_table = vmalloc(2000); 1438 if (zone->l2p_table == NULL) { 1439 rtsx_trace(chip); 1440 goto Build_Fail; 1441 } 1442 } 1443 memset((u8 *)(zone->l2p_table), 0xff, 2000); 1444 1445 if (zone->free_table == NULL) { 1446 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2); 1447 if (zone->free_table == NULL) { 1448 rtsx_trace(chip); 1449 goto Build_Fail; 1450 } 1451 } 1452 memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2); 1453 1454 if (zone_no == 0) { 1455 if (xd_card->cis_block == 0xFFFF) 1456 start = 0; 1457 else 1458 start = xd_card->cis_block + 1; 1459 if (XD_CHK_4MB(xd_card)) { 1460 end = 0x200; 1461 max_logoff = 499; 1462 } else { 1463 end = 0x400; 1464 max_logoff = 999; 1465 } 1466 } else { 1467 start = (u32)(zone_no) << 10; 1468 end = (u32)(zone_no + 1) << 10; 1469 max_logoff = 999; 1470 } 1471 1472 dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n", 1473 start, end); 1474 1475 zone->set_index = zone->get_index = 0; 1476 zone->unused_blk_cnt = 0; 1477 1478 for (i = start; i < end; i++) { 1479 u32 page_addr = i << xd_card->block_shift; 1480 u32 phy_block; 1481 1482 retval = xd_read_redundant(chip, page_addr, redunt, 11); 1483 if (retval != STATUS_SUCCESS) 1484 continue; 1485 1486 if (redunt[BLOCK_STATUS] != 0xFF) { 1487 dev_dbg(rtsx_dev(chip), "bad block\n"); 1488 continue; 1489 } 1490 1491 if (xd_check_data_blank(redunt)) { 1492 dev_dbg(rtsx_dev(chip), "blank block\n"); 1493 xd_set_unused_block(chip, i); 1494 continue; 1495 } 1496 1497 cur_fst_page_logoff = xd_load_log_block_addr(redunt); 1498 if ((cur_fst_page_logoff == 0xFFFF) || 1499 (cur_fst_page_logoff > max_logoff)) { 1500 retval = xd_erase_block(chip, i); 1501 if (retval == STATUS_SUCCESS) 1502 xd_set_unused_block(chip, i); 1503 continue; 1504 } 1505 1506 if ((zone_no == 0) && (cur_fst_page_logoff == 0) && 1507 (redunt[PAGE_STATUS] != XD_GPG)) 1508 XD_SET_MBR_FAIL(xd_card); 1509 1510 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) { 1511 zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF); 1512 continue; 1513 } 1514 1515 phy_block = zone->l2p_table[cur_fst_page_logoff] + 1516 ((u32)((zone_no) << 10)); 1517 1518 page_addr = ((i + 1) << xd_card->block_shift) - 1; 1519 1520 retval = xd_read_redundant(chip, page_addr, redunt, 11); 1521 if (retval != STATUS_SUCCESS) 1522 continue; 1523 1524 cur_lst_page_logoff = xd_load_log_block_addr(redunt); 1525 if (cur_lst_page_logoff == cur_fst_page_logoff) { 1526 int m; 1527 1528 page_addr = ((phy_block + 1) << 1529 xd_card->block_shift) - 1; 1530 1531 for (m = 0; m < 3; m++) { 1532 retval = xd_read_redundant(chip, page_addr, 1533 redunt, 11); 1534 if (retval == STATUS_SUCCESS) 1535 break; 1536 } 1537 1538 if (m == 3) { 1539 zone->l2p_table[cur_fst_page_logoff] = 1540 (u16)(i & 0x3FF); 1541 retval = xd_erase_block(chip, phy_block); 1542 if (retval == STATUS_SUCCESS) 1543 xd_set_unused_block(chip, phy_block); 1544 continue; 1545 } 1546 1547 ent_lst_page_logoff = xd_load_log_block_addr(redunt); 1548 if (ent_lst_page_logoff != cur_fst_page_logoff) { 1549 zone->l2p_table[cur_fst_page_logoff] = 1550 (u16)(i & 0x3FF); 1551 retval = xd_erase_block(chip, phy_block); 1552 if (retval == STATUS_SUCCESS) 1553 xd_set_unused_block(chip, phy_block); 1554 continue; 1555 } else { 1556 retval = xd_erase_block(chip, i); 1557 if (retval == STATUS_SUCCESS) 1558 xd_set_unused_block(chip, i); 1559 } 1560 } else { 1561 retval = xd_erase_block(chip, i); 1562 if (retval == STATUS_SUCCESS) 1563 xd_set_unused_block(chip, i); 1564 } 1565 } 1566 1567 if (XD_CHK_4MB(xd_card)) 1568 end = 500; 1569 else 1570 end = 1000; 1571 1572 i = 0; 1573 for (start = 0; start < end; start++) { 1574 if (zone->l2p_table[start] == 0xFFFF) 1575 i++; 1576 } 1577 1578 dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n", 1579 end, i); 1580 dev_dbg(rtsx_dev(chip), "Total unused block: %d\n", 1581 zone->unused_blk_cnt); 1582 1583 if ((zone->unused_blk_cnt - i) < 1) 1584 chip->card_wp |= XD_CARD; 1585 1586 zone->build_flag = 1; 1587 1588 return STATUS_SUCCESS; 1589 1590 Build_Fail: 1591 if (zone->l2p_table) { 1592 vfree(zone->l2p_table); 1593 zone->l2p_table = NULL; 1594 } 1595 if (zone->free_table) { 1596 vfree(zone->free_table); 1597 zone->free_table = NULL; 1598 } 1599 1600 return STATUS_FAIL; 1601 } 1602 1603 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd) 1604 { 1605 int retval; 1606 1607 rtsx_init_cmd(chip); 1608 1609 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd); 1610 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1611 XD_TRANSFER_START | XD_SET_CMD); 1612 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1613 XD_TRANSFER_END, XD_TRANSFER_END); 1614 1615 retval = rtsx_send_cmd(chip, XD_CARD, 200); 1616 if (retval < 0) { 1617 rtsx_trace(chip); 1618 return STATUS_FAIL; 1619 } 1620 1621 return STATUS_SUCCESS; 1622 } 1623 1624 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk, 1625 u32 log_blk, u8 start_page, u8 end_page, 1626 u8 *buf, unsigned int *index, 1627 unsigned int *offset) 1628 { 1629 struct xd_info *xd_card = &(chip->xd_card); 1630 u32 page_addr, new_blk; 1631 u16 log_off; 1632 u8 reg_val, page_cnt; 1633 int zone_no, retval, i; 1634 1635 if (start_page > end_page) { 1636 rtsx_trace(chip); 1637 return STATUS_FAIL; 1638 } 1639 1640 page_cnt = end_page - start_page; 1641 zone_no = (int)(log_blk / 1000); 1642 log_off = (u16)(log_blk % 1000); 1643 1644 if ((phy_blk & 0x3FF) == 0x3FF) { 1645 for (i = 0; i < 256; i++) { 1646 page_addr = ((u32)i) << xd_card->block_shift; 1647 1648 retval = xd_read_redundant(chip, page_addr, NULL, 0); 1649 if (retval == STATUS_SUCCESS) 1650 break; 1651 1652 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1653 xd_set_err_code(chip, XD_NO_CARD); 1654 rtsx_trace(chip); 1655 return STATUS_FAIL; 1656 } 1657 } 1658 } 1659 1660 page_addr = (phy_blk << xd_card->block_shift) + start_page; 1661 1662 rtsx_init_cmd(chip); 1663 1664 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1665 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE); 1666 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1667 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1668 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 1669 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS); 1670 1671 trans_dma_enable(chip->srb->sc_data_direction, chip, 1672 page_cnt * 512, DMA_512); 1673 1674 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF, 1675 XD_TRANSFER_START | XD_READ_PAGES); 1676 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1677 XD_TRANSFER_END | XD_PPB_EMPTY, XD_TRANSFER_END | XD_PPB_EMPTY); 1678 1679 rtsx_send_cmd_no_wait(chip); 1680 1681 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1682 scsi_sg_count(chip->srb), 1683 index, offset, DMA_FROM_DEVICE, 1684 chip->xd_timeout); 1685 if (retval < 0) { 1686 rtsx_clear_xd_error(chip); 1687 1688 if (retval == -ETIMEDOUT) { 1689 xd_set_err_code(chip, XD_TO_ERROR); 1690 rtsx_trace(chip); 1691 return STATUS_FAIL; 1692 } else { 1693 rtsx_trace(chip); 1694 goto Fail; 1695 } 1696 } 1697 1698 return STATUS_SUCCESS; 1699 1700 Fail: 1701 retval = rtsx_read_register(chip, XD_PAGE_STATUS, ®_val); 1702 if (retval) { 1703 rtsx_trace(chip); 1704 return retval; 1705 } 1706 1707 if (reg_val != XD_GPG) 1708 xd_set_err_code(chip, XD_PRG_ERROR); 1709 1710 retval = rtsx_read_register(chip, XD_CTL, ®_val); 1711 if (retval) { 1712 rtsx_trace(chip); 1713 return retval; 1714 } 1715 1716 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) 1717 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) 1718 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) 1719 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) { 1720 wait_timeout(100); 1721 1722 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 1723 xd_set_err_code(chip, XD_NO_CARD); 1724 rtsx_trace(chip); 1725 return STATUS_FAIL; 1726 } 1727 1728 xd_set_err_code(chip, XD_ECC_ERROR); 1729 1730 new_blk = xd_get_unused_block(chip, zone_no); 1731 if (new_blk == NO_NEW_BLK) { 1732 XD_CLR_BAD_OLDBLK(xd_card); 1733 rtsx_trace(chip); 1734 return STATUS_FAIL; 1735 } 1736 1737 retval = xd_copy_page(chip, phy_blk, new_blk, 0, 1738 xd_card->page_off + 1); 1739 if (retval != STATUS_SUCCESS) { 1740 if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1741 retval = xd_erase_block(chip, new_blk); 1742 if (retval == STATUS_SUCCESS) 1743 xd_set_unused_block(chip, new_blk); 1744 } else { 1745 XD_CLR_BAD_NEWBLK(xd_card); 1746 } 1747 XD_CLR_BAD_OLDBLK(xd_card); 1748 rtsx_trace(chip); 1749 return STATUS_FAIL; 1750 } 1751 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1752 xd_erase_block(chip, phy_blk); 1753 xd_mark_bad_block(chip, phy_blk); 1754 XD_CLR_BAD_OLDBLK(xd_card); 1755 } 1756 1757 rtsx_trace(chip); 1758 return STATUS_FAIL; 1759 } 1760 1761 static int xd_finish_write(struct rtsx_chip *chip, 1762 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1763 { 1764 struct xd_info *xd_card = &(chip->xd_card); 1765 int retval, zone_no; 1766 u16 log_off; 1767 1768 dev_dbg(rtsx_dev(chip), "xd_finish_write, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", 1769 old_blk, new_blk, log_blk); 1770 1771 if (page_off > xd_card->page_off) { 1772 rtsx_trace(chip); 1773 return STATUS_FAIL; 1774 } 1775 1776 zone_no = (int)(log_blk / 1000); 1777 log_off = (u16)(log_blk % 1000); 1778 1779 if (old_blk == BLK_NOT_FOUND) { 1780 retval = xd_init_page(chip, new_blk, log_off, 1781 page_off, xd_card->page_off + 1); 1782 if (retval != STATUS_SUCCESS) { 1783 retval = xd_erase_block(chip, new_blk); 1784 if (retval == STATUS_SUCCESS) 1785 xd_set_unused_block(chip, new_blk); 1786 rtsx_trace(chip); 1787 return STATUS_FAIL; 1788 } 1789 } else { 1790 retval = xd_copy_page(chip, old_blk, new_blk, 1791 page_off, xd_card->page_off + 1); 1792 if (retval != STATUS_SUCCESS) { 1793 if (!XD_CHK_BAD_NEWBLK(xd_card)) { 1794 retval = xd_erase_block(chip, new_blk); 1795 if (retval == STATUS_SUCCESS) 1796 xd_set_unused_block(chip, new_blk); 1797 } 1798 XD_CLR_BAD_NEWBLK(xd_card); 1799 rtsx_trace(chip); 1800 return STATUS_FAIL; 1801 } 1802 1803 retval = xd_erase_block(chip, old_blk); 1804 if (retval == STATUS_SUCCESS) { 1805 if (XD_CHK_BAD_OLDBLK(xd_card)) { 1806 xd_mark_bad_block(chip, old_blk); 1807 XD_CLR_BAD_OLDBLK(xd_card); 1808 } else { 1809 xd_set_unused_block(chip, old_blk); 1810 } 1811 } else { 1812 xd_set_err_code(chip, XD_NO_ERROR); 1813 XD_CLR_BAD_OLDBLK(xd_card); 1814 } 1815 } 1816 1817 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1818 1819 return STATUS_SUCCESS; 1820 } 1821 1822 static int xd_prepare_write(struct rtsx_chip *chip, 1823 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off) 1824 { 1825 int retval; 1826 1827 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n", 1828 __func__, old_blk, new_blk, log_blk, (int)page_off); 1829 1830 if (page_off) { 1831 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off); 1832 if (retval != STATUS_SUCCESS) { 1833 rtsx_trace(chip); 1834 return STATUS_FAIL; 1835 } 1836 } 1837 1838 return STATUS_SUCCESS; 1839 } 1840 1841 1842 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk, 1843 u32 new_blk, u32 log_blk, u8 start_page, 1844 u8 end_page, u8 *buf, unsigned int *index, 1845 unsigned int *offset) 1846 { 1847 struct xd_info *xd_card = &(chip->xd_card); 1848 u32 page_addr; 1849 int zone_no, retval; 1850 u16 log_off; 1851 u8 page_cnt, reg_val; 1852 1853 dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n", 1854 __func__, old_blk, new_blk, log_blk); 1855 1856 if (start_page > end_page) { 1857 rtsx_trace(chip); 1858 return STATUS_FAIL; 1859 } 1860 1861 page_cnt = end_page - start_page; 1862 zone_no = (int)(log_blk / 1000); 1863 log_off = (u16)(log_blk % 1000); 1864 1865 page_addr = (new_blk << xd_card->block_shift) + start_page; 1866 1867 retval = xd_send_cmd(chip, READ1_1); 1868 if (retval != STATUS_SUCCESS) { 1869 rtsx_trace(chip); 1870 return STATUS_FAIL; 1871 } 1872 1873 rtsx_init_cmd(chip); 1874 1875 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 1876 0xFF, (u8)(log_off >> 8)); 1877 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off); 1878 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK); 1879 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG); 1880 1881 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR); 1882 1883 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM, 1884 XD_BA_TRANSFORM); 1885 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt); 1886 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 1887 1888 trans_dma_enable(chip->srb->sc_data_direction, chip, 1889 page_cnt * 512, DMA_512); 1890 1891 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 1892 0xFF, XD_TRANSFER_START | XD_WRITE_PAGES); 1893 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, 1894 XD_TRANSFER_END, XD_TRANSFER_END); 1895 1896 rtsx_send_cmd_no_wait(chip); 1897 1898 retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512, 1899 scsi_sg_count(chip->srb), 1900 index, offset, DMA_TO_DEVICE, chip->xd_timeout); 1901 if (retval < 0) { 1902 rtsx_clear_xd_error(chip); 1903 1904 if (retval == -ETIMEDOUT) { 1905 xd_set_err_code(chip, XD_TO_ERROR); 1906 rtsx_trace(chip); 1907 return STATUS_FAIL; 1908 } else { 1909 rtsx_trace(chip); 1910 goto Fail; 1911 } 1912 } 1913 1914 if (end_page == (xd_card->page_off + 1)) { 1915 xd_card->delay_write.delay_write_flag = 0; 1916 1917 if (old_blk != BLK_NOT_FOUND) { 1918 retval = xd_erase_block(chip, old_blk); 1919 if (retval == STATUS_SUCCESS) { 1920 if (XD_CHK_BAD_OLDBLK(xd_card)) { 1921 xd_mark_bad_block(chip, old_blk); 1922 XD_CLR_BAD_OLDBLK(xd_card); 1923 } else { 1924 xd_set_unused_block(chip, old_blk); 1925 } 1926 } else { 1927 xd_set_err_code(chip, XD_NO_ERROR); 1928 XD_CLR_BAD_OLDBLK(xd_card); 1929 } 1930 } 1931 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF)); 1932 } 1933 1934 return STATUS_SUCCESS; 1935 1936 Fail: 1937 retval = rtsx_read_register(chip, XD_DAT, ®_val); 1938 if (retval) { 1939 rtsx_trace(chip); 1940 return retval; 1941 } 1942 if (reg_val & PROGRAM_ERROR) { 1943 xd_set_err_code(chip, XD_PRG_ERROR); 1944 xd_mark_bad_block(chip, new_blk); 1945 } 1946 1947 rtsx_trace(chip); 1948 return STATUS_FAIL; 1949 } 1950 1951 #ifdef XD_DELAY_WRITE 1952 int xd_delay_write(struct rtsx_chip *chip) 1953 { 1954 struct xd_info *xd_card = &(chip->xd_card); 1955 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write); 1956 int retval; 1957 1958 if (delay_write->delay_write_flag) { 1959 dev_dbg(rtsx_dev(chip), "xd_delay_write\n"); 1960 retval = xd_switch_clock(chip); 1961 if (retval != STATUS_SUCCESS) { 1962 rtsx_trace(chip); 1963 return STATUS_FAIL; 1964 } 1965 1966 delay_write->delay_write_flag = 0; 1967 retval = xd_finish_write(chip, 1968 delay_write->old_phyblock, 1969 delay_write->new_phyblock, 1970 delay_write->logblock, delay_write->pageoff); 1971 if (retval != STATUS_SUCCESS) { 1972 rtsx_trace(chip); 1973 return STATUS_FAIL; 1974 } 1975 } 1976 1977 return STATUS_SUCCESS; 1978 } 1979 #endif 1980 1981 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 1982 u32 start_sector, u16 sector_cnt) 1983 { 1984 struct xd_info *xd_card = &(chip->xd_card); 1985 unsigned int lun = SCSI_LUN(srb); 1986 #ifdef XD_DELAY_WRITE 1987 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write); 1988 #endif 1989 int retval, zone_no; 1990 unsigned int index = 0, offset = 0; 1991 u32 log_blk, old_blk = 0, new_blk = 0; 1992 u16 log_off, total_sec_cnt = sector_cnt; 1993 u8 start_page, end_page = 0, page_cnt; 1994 u8 *ptr; 1995 1996 xd_set_err_code(chip, XD_NO_ERROR); 1997 1998 xd_card->cleanup_counter = 0; 1999 2000 dev_dbg(rtsx_dev(chip), "xd_rw: scsi_sg_count = %d\n", 2001 scsi_sg_count(srb)); 2002 2003 ptr = (u8 *)scsi_sglist(srb); 2004 2005 retval = xd_switch_clock(chip); 2006 if (retval != STATUS_SUCCESS) { 2007 rtsx_trace(chip); 2008 return STATUS_FAIL; 2009 } 2010 2011 2012 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2013 chip->card_fail |= XD_CARD; 2014 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2015 rtsx_trace(chip); 2016 return STATUS_FAIL; 2017 } 2018 2019 log_blk = start_sector >> xd_card->block_shift; 2020 start_page = (u8)start_sector & xd_card->page_off; 2021 zone_no = (int)(log_blk / 1000); 2022 log_off = (u16)(log_blk % 1000); 2023 2024 if (xd_card->zone[zone_no].build_flag == 0) { 2025 retval = xd_build_l2p_tbl(chip, zone_no); 2026 if (retval != STATUS_SUCCESS) { 2027 chip->card_fail |= XD_CARD; 2028 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2029 rtsx_trace(chip); 2030 return STATUS_FAIL; 2031 } 2032 } 2033 2034 if (srb->sc_data_direction == DMA_TO_DEVICE) { 2035 #ifdef XD_DELAY_WRITE 2036 if (delay_write->delay_write_flag && 2037 (delay_write->logblock == log_blk) && 2038 (start_page > delay_write->pageoff)) { 2039 delay_write->delay_write_flag = 0; 2040 if (delay_write->old_phyblock != BLK_NOT_FOUND) { 2041 retval = xd_copy_page(chip, 2042 delay_write->old_phyblock, 2043 delay_write->new_phyblock, 2044 delay_write->pageoff, start_page); 2045 if (retval != STATUS_SUCCESS) { 2046 set_sense_type(chip, lun, 2047 SENSE_TYPE_MEDIA_WRITE_ERR); 2048 rtsx_trace(chip); 2049 return STATUS_FAIL; 2050 } 2051 } 2052 old_blk = delay_write->old_phyblock; 2053 new_blk = delay_write->new_phyblock; 2054 } else if (delay_write->delay_write_flag && 2055 (delay_write->logblock == log_blk) && 2056 (start_page == delay_write->pageoff)) { 2057 delay_write->delay_write_flag = 0; 2058 old_blk = delay_write->old_phyblock; 2059 new_blk = delay_write->new_phyblock; 2060 } else { 2061 retval = xd_delay_write(chip); 2062 if (retval != STATUS_SUCCESS) { 2063 set_sense_type(chip, lun, 2064 SENSE_TYPE_MEDIA_WRITE_ERR); 2065 rtsx_trace(chip); 2066 return STATUS_FAIL; 2067 } 2068 #endif 2069 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2070 new_blk = xd_get_unused_block(chip, zone_no); 2071 if ((old_blk == BLK_NOT_FOUND) || 2072 (new_blk == BLK_NOT_FOUND)) { 2073 set_sense_type(chip, lun, 2074 SENSE_TYPE_MEDIA_WRITE_ERR); 2075 rtsx_trace(chip); 2076 return STATUS_FAIL; 2077 } 2078 2079 retval = xd_prepare_write(chip, old_blk, new_blk, 2080 log_blk, start_page); 2081 if (retval != STATUS_SUCCESS) { 2082 if (detect_card_cd(chip, XD_CARD) != 2083 STATUS_SUCCESS) { 2084 set_sense_type(chip, lun, 2085 SENSE_TYPE_MEDIA_NOT_PRESENT); 2086 rtsx_trace(chip); 2087 return STATUS_FAIL; 2088 } 2089 set_sense_type(chip, lun, 2090 SENSE_TYPE_MEDIA_WRITE_ERR); 2091 rtsx_trace(chip); 2092 return STATUS_FAIL; 2093 } 2094 #ifdef XD_DELAY_WRITE 2095 } 2096 #endif 2097 } else { 2098 #ifdef XD_DELAY_WRITE 2099 retval = xd_delay_write(chip); 2100 if (retval != STATUS_SUCCESS) { 2101 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2102 set_sense_type(chip, lun, 2103 SENSE_TYPE_MEDIA_NOT_PRESENT); 2104 rtsx_trace(chip); 2105 return STATUS_FAIL; 2106 } 2107 set_sense_type(chip, lun, 2108 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2109 rtsx_trace(chip); 2110 return STATUS_FAIL; 2111 } 2112 #endif 2113 2114 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2115 if (old_blk == BLK_NOT_FOUND) { 2116 set_sense_type(chip, lun, 2117 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2118 rtsx_trace(chip); 2119 return STATUS_FAIL; 2120 } 2121 } 2122 2123 dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk); 2124 2125 while (total_sec_cnt) { 2126 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2127 chip->card_fail |= XD_CARD; 2128 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2129 rtsx_trace(chip); 2130 return STATUS_FAIL; 2131 } 2132 2133 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1)) 2134 end_page = xd_card->page_off + 1; 2135 else 2136 end_page = start_page + (u8)total_sec_cnt; 2137 2138 page_cnt = end_page - start_page; 2139 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2140 retval = xd_read_multiple_pages(chip, old_blk, log_blk, 2141 start_page, end_page, ptr, 2142 &index, &offset); 2143 if (retval != STATUS_SUCCESS) { 2144 set_sense_type(chip, lun, 2145 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2146 rtsx_trace(chip); 2147 return STATUS_FAIL; 2148 } 2149 } else { 2150 retval = xd_write_multiple_pages(chip, old_blk, 2151 new_blk, log_blk, 2152 start_page, end_page, ptr, 2153 &index, &offset); 2154 if (retval != STATUS_SUCCESS) { 2155 set_sense_type(chip, lun, 2156 SENSE_TYPE_MEDIA_WRITE_ERR); 2157 rtsx_trace(chip); 2158 return STATUS_FAIL; 2159 } 2160 } 2161 2162 total_sec_cnt -= page_cnt; 2163 if (scsi_sg_count(srb) == 0) 2164 ptr += page_cnt * 512; 2165 2166 if (total_sec_cnt == 0) 2167 break; 2168 2169 log_blk++; 2170 zone_no = (int)(log_blk / 1000); 2171 log_off = (u16)(log_blk % 1000); 2172 2173 if (xd_card->zone[zone_no].build_flag == 0) { 2174 retval = xd_build_l2p_tbl(chip, zone_no); 2175 if (retval != STATUS_SUCCESS) { 2176 chip->card_fail |= XD_CARD; 2177 set_sense_type(chip, lun, 2178 SENSE_TYPE_MEDIA_NOT_PRESENT); 2179 rtsx_trace(chip); 2180 return STATUS_FAIL; 2181 } 2182 } 2183 2184 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off); 2185 if (old_blk == BLK_NOT_FOUND) { 2186 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2187 set_sense_type(chip, lun, 2188 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 2189 else 2190 set_sense_type(chip, lun, 2191 SENSE_TYPE_MEDIA_WRITE_ERR); 2192 2193 rtsx_trace(chip); 2194 return STATUS_FAIL; 2195 } 2196 2197 if (srb->sc_data_direction == DMA_TO_DEVICE) { 2198 new_blk = xd_get_unused_block(chip, zone_no); 2199 if (new_blk == BLK_NOT_FOUND) { 2200 set_sense_type(chip, lun, 2201 SENSE_TYPE_MEDIA_WRITE_ERR); 2202 rtsx_trace(chip); 2203 return STATUS_FAIL; 2204 } 2205 } 2206 2207 start_page = 0; 2208 } 2209 2210 if ((srb->sc_data_direction == DMA_TO_DEVICE) && 2211 (end_page != (xd_card->page_off + 1))) { 2212 #ifdef XD_DELAY_WRITE 2213 delay_write->delay_write_flag = 1; 2214 delay_write->old_phyblock = old_blk; 2215 delay_write->new_phyblock = new_blk; 2216 delay_write->logblock = log_blk; 2217 delay_write->pageoff = end_page; 2218 #else 2219 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2220 chip->card_fail |= XD_CARD; 2221 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 2222 rtsx_trace(chip); 2223 return STATUS_FAIL; 2224 } 2225 2226 retval = xd_finish_write(chip, old_blk, new_blk, 2227 log_blk, end_page); 2228 if (retval != STATUS_SUCCESS) { 2229 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) { 2230 set_sense_type(chip, lun, 2231 SENSE_TYPE_MEDIA_NOT_PRESENT); 2232 rtsx_trace(chip); 2233 return STATUS_FAIL; 2234 } 2235 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 2236 rtsx_trace(chip); 2237 return STATUS_FAIL; 2238 } 2239 #endif 2240 } 2241 2242 scsi_set_resid(srb, 0); 2243 2244 return STATUS_SUCCESS; 2245 } 2246 2247 void xd_free_l2p_tbl(struct rtsx_chip *chip) 2248 { 2249 struct xd_info *xd_card = &(chip->xd_card); 2250 int i = 0; 2251 2252 if (xd_card->zone != NULL) { 2253 for (i = 0; i < xd_card->zone_cnt; i++) { 2254 if (xd_card->zone[i].l2p_table != NULL) { 2255 vfree(xd_card->zone[i].l2p_table); 2256 xd_card->zone[i].l2p_table = NULL; 2257 } 2258 if (xd_card->zone[i].free_table != NULL) { 2259 vfree(xd_card->zone[i].free_table); 2260 xd_card->zone[i].free_table = NULL; 2261 } 2262 } 2263 vfree(xd_card->zone); 2264 xd_card->zone = NULL; 2265 } 2266 } 2267 2268 void xd_cleanup_work(struct rtsx_chip *chip) 2269 { 2270 #ifdef XD_DELAY_WRITE 2271 struct xd_info *xd_card = &(chip->xd_card); 2272 2273 if (xd_card->delay_write.delay_write_flag) { 2274 dev_dbg(rtsx_dev(chip), "xD: delay write\n"); 2275 xd_delay_write(chip); 2276 xd_card->cleanup_counter = 0; 2277 } 2278 #endif 2279 } 2280 2281 int xd_power_off_card3v3(struct rtsx_chip *chip) 2282 { 2283 int retval; 2284 2285 retval = disable_card_clock(chip, XD_CARD); 2286 if (retval != STATUS_SUCCESS) { 2287 rtsx_trace(chip); 2288 return STATUS_FAIL; 2289 } 2290 2291 retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 2292 if (retval) { 2293 rtsx_trace(chip); 2294 return retval; 2295 } 2296 2297 if (!chip->ft2_fast_mode) { 2298 retval = card_power_off(chip, XD_CARD); 2299 if (retval != STATUS_SUCCESS) { 2300 rtsx_trace(chip); 2301 return STATUS_FAIL; 2302 } 2303 2304 wait_timeout(50); 2305 } 2306 2307 if (chip->asic_code) { 2308 retval = xd_pull_ctl_disable(chip); 2309 if (retval != STATUS_SUCCESS) { 2310 rtsx_trace(chip); 2311 return STATUS_FAIL; 2312 } 2313 } else { 2314 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF); 2315 if (retval) { 2316 rtsx_trace(chip); 2317 return retval; 2318 } 2319 } 2320 2321 return STATUS_SUCCESS; 2322 } 2323 2324 int release_xd_card(struct rtsx_chip *chip) 2325 { 2326 struct xd_info *xd_card = &(chip->xd_card); 2327 int retval; 2328 2329 chip->card_ready &= ~XD_CARD; 2330 chip->card_fail &= ~XD_CARD; 2331 chip->card_wp &= ~XD_CARD; 2332 2333 xd_card->delay_write.delay_write_flag = 0; 2334 2335 xd_free_l2p_tbl(chip); 2336 2337 retval = xd_power_off_card3v3(chip); 2338 if (retval != STATUS_SUCCESS) { 2339 rtsx_trace(chip); 2340 return STATUS_FAIL; 2341 } 2342 2343 return STATUS_SUCCESS; 2344 } 2345