1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 27 #include "rtsx.h" 28 #include "spi.h" 29 30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) 31 { 32 struct spi_info *spi = &chip->spi; 33 34 spi->err_code = err_code; 35 } 36 37 static int spi_init(struct rtsx_chip *chip) 38 { 39 int retval; 40 41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 42 CS_POLARITY_LOW | DTO_MSB_FIRST 43 | SPI_MASTER | SPI_MODE0 | SPI_AUTO); 44 if (retval) { 45 rtsx_trace(chip); 46 return retval; 47 } 48 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 49 SAMPLE_DELAY_HALF); 50 if (retval) { 51 rtsx_trace(chip); 52 return retval; 53 } 54 55 return STATUS_SUCCESS; 56 } 57 58 static int spi_set_init_para(struct rtsx_chip *chip) 59 { 60 struct spi_info *spi = &chip->spi; 61 int retval; 62 63 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 64 (u8)(spi->clk_div >> 8)); 65 if (retval) { 66 rtsx_trace(chip); 67 return retval; 68 } 69 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 70 (u8)(spi->clk_div)); 71 if (retval) { 72 rtsx_trace(chip); 73 return retval; 74 } 75 76 retval = switch_clock(chip, spi->spi_clock); 77 if (retval != STATUS_SUCCESS) { 78 rtsx_trace(chip); 79 return STATUS_FAIL; 80 } 81 82 retval = select_card(chip, SPI_CARD); 83 if (retval != STATUS_SUCCESS) { 84 rtsx_trace(chip); 85 return STATUS_FAIL; 86 } 87 88 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 89 SPI_CLK_EN); 90 if (retval) { 91 rtsx_trace(chip); 92 return retval; 93 } 94 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 95 SPI_OUTPUT_EN); 96 if (retval) { 97 rtsx_trace(chip); 98 return retval; 99 } 100 101 wait_timeout(10); 102 103 retval = spi_init(chip); 104 if (retval != STATUS_SUCCESS) { 105 rtsx_trace(chip); 106 return STATUS_FAIL; 107 } 108 109 return STATUS_SUCCESS; 110 } 111 112 static int sf_polling_status(struct rtsx_chip *chip, int msec) 113 { 114 int retval; 115 116 rtsx_init_cmd(chip); 117 118 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); 119 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 120 SPI_TRANSFER0_START | SPI_POLLING_MODE0); 121 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 122 SPI_TRANSFER0_END); 123 124 retval = rtsx_send_cmd(chip, 0, msec); 125 if (retval < 0) { 126 rtsx_clear_spi_error(chip); 127 spi_set_err_code(chip, SPI_BUSY_ERR); 128 rtsx_trace(chip); 129 return STATUS_FAIL; 130 } 131 132 return STATUS_SUCCESS; 133 } 134 135 static int sf_enable_write(struct rtsx_chip *chip, u8 ins) 136 { 137 struct spi_info *spi = &chip->spi; 138 int retval; 139 140 if (!spi->write_en) 141 return STATUS_SUCCESS; 142 143 rtsx_init_cmd(chip); 144 145 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 146 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 147 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 148 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 149 SPI_TRANSFER0_START | SPI_C_MODE0); 150 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 151 SPI_TRANSFER0_END); 152 153 retval = rtsx_send_cmd(chip, 0, 100); 154 if (retval < 0) { 155 rtsx_clear_spi_error(chip); 156 spi_set_err_code(chip, SPI_HW_ERR); 157 rtsx_trace(chip); 158 return STATUS_FAIL; 159 } 160 161 return STATUS_SUCCESS; 162 } 163 164 static int sf_disable_write(struct rtsx_chip *chip, u8 ins) 165 { 166 struct spi_info *spi = &chip->spi; 167 int retval; 168 169 if (!spi->write_en) 170 return STATUS_SUCCESS; 171 172 rtsx_init_cmd(chip); 173 174 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 175 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 176 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 177 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 178 SPI_TRANSFER0_START | SPI_C_MODE0); 179 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 180 SPI_TRANSFER0_END); 181 182 retval = rtsx_send_cmd(chip, 0, 100); 183 if (retval < 0) { 184 rtsx_clear_spi_error(chip); 185 spi_set_err_code(chip, SPI_HW_ERR); 186 rtsx_trace(chip); 187 return STATUS_FAIL; 188 } 189 190 return STATUS_SUCCESS; 191 } 192 193 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr, 194 u16 len) 195 { 196 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 197 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 198 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 199 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len); 200 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8)); 201 if (addr_mode) { 202 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 203 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 204 (u8)(addr >> 8)); 205 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 206 (u8)(addr >> 16)); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 208 SPI_TRANSFER0_START | SPI_CADO_MODE0); 209 } else { 210 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 211 SPI_TRANSFER0_START | SPI_CDO_MODE0); 212 } 213 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 214 SPI_TRANSFER0_END); 215 } 216 217 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr) 218 { 219 int retval; 220 221 rtsx_init_cmd(chip); 222 223 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 224 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 225 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 226 if (addr_mode) { 227 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 228 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 229 (u8)(addr >> 8)); 230 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 231 (u8)(addr >> 16)); 232 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 233 SPI_TRANSFER0_START | SPI_CA_MODE0); 234 } else { 235 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 236 SPI_TRANSFER0_START | SPI_C_MODE0); 237 } 238 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 239 SPI_TRANSFER0_END); 240 241 retval = rtsx_send_cmd(chip, 0, 100); 242 if (retval < 0) { 243 rtsx_clear_spi_error(chip); 244 spi_set_err_code(chip, SPI_HW_ERR); 245 rtsx_trace(chip); 246 return STATUS_FAIL; 247 } 248 249 return STATUS_SUCCESS; 250 } 251 252 static int spi_init_eeprom(struct rtsx_chip *chip) 253 { 254 int retval; 255 int clk; 256 257 if (chip->asic_code) 258 clk = 30; 259 else 260 clk = CLK_30; 261 262 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); 263 if (retval) { 264 rtsx_trace(chip); 265 return retval; 266 } 267 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); 268 if (retval) { 269 rtsx_trace(chip); 270 return retval; 271 } 272 273 retval = switch_clock(chip, clk); 274 if (retval != STATUS_SUCCESS) { 275 rtsx_trace(chip); 276 return STATUS_FAIL; 277 } 278 279 retval = select_card(chip, SPI_CARD); 280 if (retval != STATUS_SUCCESS) { 281 rtsx_trace(chip); 282 return STATUS_FAIL; 283 } 284 285 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 286 SPI_CLK_EN); 287 if (retval) { 288 rtsx_trace(chip); 289 return retval; 290 } 291 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 292 SPI_OUTPUT_EN); 293 if (retval) { 294 rtsx_trace(chip); 295 return retval; 296 } 297 298 wait_timeout(10); 299 300 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 301 CS_POLARITY_HIGH | SPI_EEPROM_AUTO); 302 if (retval) { 303 rtsx_trace(chip); 304 return retval; 305 } 306 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 307 SAMPLE_DELAY_HALF); 308 if (retval) { 309 rtsx_trace(chip); 310 return retval; 311 } 312 313 return STATUS_SUCCESS; 314 } 315 316 static int spi_eeprom_program_enable(struct rtsx_chip *chip) 317 { 318 int retval; 319 320 rtsx_init_cmd(chip); 321 322 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86); 323 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13); 324 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 325 SPI_TRANSFER0_START | SPI_CA_MODE0); 326 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 327 SPI_TRANSFER0_END); 328 329 retval = rtsx_send_cmd(chip, 0, 100); 330 if (retval < 0) { 331 rtsx_trace(chip); 332 return STATUS_FAIL; 333 } 334 335 return STATUS_SUCCESS; 336 } 337 338 int spi_erase_eeprom_chip(struct rtsx_chip *chip) 339 { 340 int retval; 341 342 retval = spi_init_eeprom(chip); 343 if (retval != STATUS_SUCCESS) { 344 rtsx_trace(chip); 345 return STATUS_FAIL; 346 } 347 348 retval = spi_eeprom_program_enable(chip); 349 if (retval != STATUS_SUCCESS) { 350 rtsx_trace(chip); 351 return STATUS_FAIL; 352 } 353 354 rtsx_init_cmd(chip); 355 356 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 357 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 358 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12); 359 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84); 360 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 361 SPI_TRANSFER0_START | SPI_CA_MODE0); 362 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 363 SPI_TRANSFER0_END); 364 365 retval = rtsx_send_cmd(chip, 0, 100); 366 if (retval < 0) { 367 rtsx_trace(chip); 368 return STATUS_FAIL; 369 } 370 371 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 372 if (retval) { 373 rtsx_trace(chip); 374 return retval; 375 } 376 377 return STATUS_SUCCESS; 378 } 379 380 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) 381 { 382 int retval; 383 384 retval = spi_init_eeprom(chip); 385 if (retval != STATUS_SUCCESS) { 386 rtsx_trace(chip); 387 return STATUS_FAIL; 388 } 389 390 retval = spi_eeprom_program_enable(chip); 391 if (retval != STATUS_SUCCESS) { 392 rtsx_trace(chip); 393 return STATUS_FAIL; 394 } 395 396 rtsx_init_cmd(chip); 397 398 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 399 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 400 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07); 401 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 402 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 403 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 404 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 405 SPI_TRANSFER0_START | SPI_CA_MODE0); 406 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 407 SPI_TRANSFER0_END); 408 409 retval = rtsx_send_cmd(chip, 0, 100); 410 if (retval < 0) { 411 rtsx_trace(chip); 412 return STATUS_FAIL; 413 } 414 415 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 416 if (retval) { 417 rtsx_trace(chip); 418 return retval; 419 } 420 421 return STATUS_SUCCESS; 422 } 423 424 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) 425 { 426 int retval; 427 u8 data; 428 429 retval = spi_init_eeprom(chip); 430 if (retval != STATUS_SUCCESS) { 431 rtsx_trace(chip); 432 return STATUS_FAIL; 433 } 434 435 rtsx_init_cmd(chip); 436 437 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 438 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 439 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06); 440 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 441 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 442 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 443 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 444 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 445 SPI_TRANSFER0_START | SPI_CADI_MODE0); 446 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 447 SPI_TRANSFER0_END); 448 449 retval = rtsx_send_cmd(chip, 0, 100); 450 if (retval < 0) { 451 rtsx_trace(chip); 452 return STATUS_FAIL; 453 } 454 455 wait_timeout(5); 456 retval = rtsx_read_register(chip, SPI_DATA, &data); 457 if (retval) { 458 rtsx_trace(chip); 459 return retval; 460 } 461 462 if (val) 463 *val = data; 464 465 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 466 if (retval) { 467 rtsx_trace(chip); 468 return retval; 469 } 470 471 return STATUS_SUCCESS; 472 } 473 474 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) 475 { 476 int retval; 477 478 retval = spi_init_eeprom(chip); 479 if (retval != STATUS_SUCCESS) { 480 rtsx_trace(chip); 481 return STATUS_FAIL; 482 } 483 484 retval = spi_eeprom_program_enable(chip); 485 if (retval != STATUS_SUCCESS) { 486 rtsx_trace(chip); 487 return STATUS_FAIL; 488 } 489 490 rtsx_init_cmd(chip); 491 492 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 493 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 494 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05); 495 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); 496 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr); 497 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8)); 498 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E); 499 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 500 SPI_TRANSFER0_START | SPI_CA_MODE0); 501 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 502 SPI_TRANSFER0_END); 503 504 retval = rtsx_send_cmd(chip, 0, 100); 505 if (retval < 0) { 506 rtsx_trace(chip); 507 return STATUS_FAIL; 508 } 509 510 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 511 if (retval) { 512 rtsx_trace(chip); 513 return retval; 514 } 515 516 return STATUS_SUCCESS; 517 } 518 519 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 520 { 521 struct spi_info *spi = &chip->spi; 522 523 dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__, 524 spi->err_code); 525 rtsx_stor_set_xfer_buf(&spi->err_code, 526 min_t(int, scsi_bufflen(srb), 1), srb); 527 scsi_set_resid(srb, scsi_bufflen(srb) - 1); 528 529 return STATUS_SUCCESS; 530 } 531 532 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) 533 { 534 struct spi_info *spi = &chip->spi; 535 536 spi_set_err_code(chip, SPI_NO_ERR); 537 538 if (chip->asic_code) 539 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; 540 else 541 spi->spi_clock = srb->cmnd[3]; 542 543 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 544 spi->write_en = srb->cmnd[6]; 545 546 dev_dbg(rtsx_dev(chip), "%s: ", __func__); 547 dev_dbg(rtsx_dev(chip), "spi_clock = %d, ", spi->spi_clock); 548 dev_dbg(rtsx_dev(chip), "clk_div = %d, ", spi->clk_div); 549 dev_dbg(rtsx_dev(chip), "write_en = %d\n", spi->write_en); 550 551 return STATUS_SUCCESS; 552 } 553 554 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 555 { 556 int retval; 557 u16 len; 558 u8 *buf; 559 560 spi_set_err_code(chip, SPI_NO_ERR); 561 562 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 563 if (len > 512) { 564 spi_set_err_code(chip, SPI_INVALID_COMMAND); 565 rtsx_trace(chip); 566 return STATUS_FAIL; 567 } 568 569 retval = spi_set_init_para(chip); 570 if (retval != STATUS_SUCCESS) { 571 spi_set_err_code(chip, SPI_HW_ERR); 572 rtsx_trace(chip); 573 return STATUS_FAIL; 574 } 575 576 rtsx_init_cmd(chip); 577 578 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 579 PINGPONG_BUFFER); 580 581 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]); 582 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]); 583 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]); 584 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]); 585 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 586 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 587 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]); 588 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]); 589 590 if (len == 0) { 591 if (srb->cmnd[9]) { 592 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 593 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0); 594 } else { 595 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 596 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); 597 } 598 } else { 599 if (srb->cmnd[9]) { 600 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 601 SPI_TRANSFER0_START | SPI_CADI_MODE0); 602 } else { 603 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 604 SPI_TRANSFER0_START | SPI_CDI_MODE0); 605 } 606 } 607 608 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 609 SPI_TRANSFER0_END); 610 611 retval = rtsx_send_cmd(chip, 0, 100); 612 if (retval < 0) { 613 rtsx_clear_spi_error(chip); 614 spi_set_err_code(chip, SPI_HW_ERR); 615 rtsx_trace(chip); 616 return STATUS_FAIL; 617 } 618 619 if (len) { 620 buf = kmalloc(len, GFP_KERNEL); 621 if (!buf) { 622 rtsx_trace(chip); 623 return STATUS_ERROR; 624 } 625 626 retval = rtsx_read_ppbuf(chip, buf, len); 627 if (retval != STATUS_SUCCESS) { 628 spi_set_err_code(chip, SPI_READ_ERR); 629 kfree(buf); 630 rtsx_trace(chip); 631 return STATUS_FAIL; 632 } 633 634 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 635 scsi_set_resid(srb, 0); 636 637 kfree(buf); 638 } 639 640 return STATUS_SUCCESS; 641 } 642 643 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 644 { 645 int retval; 646 unsigned int index = 0, offset = 0; 647 u8 ins, slow_read; 648 u32 addr; 649 u16 len; 650 u8 *buf; 651 652 spi_set_err_code(chip, SPI_NO_ERR); 653 654 ins = srb->cmnd[3]; 655 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 656 << 8) | srb->cmnd[6]; 657 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 658 slow_read = srb->cmnd[9]; 659 660 retval = spi_set_init_para(chip); 661 if (retval != STATUS_SUCCESS) { 662 spi_set_err_code(chip, SPI_HW_ERR); 663 rtsx_trace(chip); 664 return STATUS_FAIL; 665 } 666 667 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 668 if (!buf) { 669 rtsx_trace(chip); 670 return STATUS_ERROR; 671 } 672 673 while (len) { 674 u16 pagelen = SF_PAGE_LEN - (u8)addr; 675 676 if (pagelen > len) 677 pagelen = len; 678 679 rtsx_init_cmd(chip); 680 681 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256); 682 683 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 684 685 if (slow_read) { 686 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, 687 (u8)addr); 688 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 689 (u8)(addr >> 8)); 690 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 691 (u8)(addr >> 16)); 692 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 693 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 694 } else { 695 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 696 (u8)addr); 697 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 698 (u8)(addr >> 8)); 699 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF, 700 (u8)(addr >> 16)); 701 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 702 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32); 703 } 704 705 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 706 (u8)(pagelen >> 8)); 707 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 708 (u8)pagelen); 709 710 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 711 SPI_TRANSFER0_START | SPI_CADI_MODE0); 712 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, 713 SPI_TRANSFER0_END, SPI_TRANSFER0_END); 714 715 rtsx_send_cmd_no_wait(chip); 716 717 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 718 DMA_FROM_DEVICE, 10000); 719 if (retval < 0) { 720 kfree(buf); 721 rtsx_clear_spi_error(chip); 722 spi_set_err_code(chip, SPI_HW_ERR); 723 rtsx_trace(chip); 724 return STATUS_FAIL; 725 } 726 727 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset, 728 TO_XFER_BUF); 729 730 addr += pagelen; 731 len -= pagelen; 732 } 733 734 scsi_set_resid(srb, 0); 735 kfree(buf); 736 737 return STATUS_SUCCESS; 738 } 739 740 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 741 { 742 int retval; 743 u8 ins, program_mode; 744 u32 addr; 745 u16 len; 746 u8 *buf; 747 unsigned int index = 0, offset = 0; 748 749 spi_set_err_code(chip, SPI_NO_ERR); 750 751 ins = srb->cmnd[3]; 752 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 753 << 8) | srb->cmnd[6]; 754 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 755 program_mode = srb->cmnd[9]; 756 757 retval = spi_set_init_para(chip); 758 if (retval != STATUS_SUCCESS) { 759 spi_set_err_code(chip, SPI_HW_ERR); 760 rtsx_trace(chip); 761 return STATUS_FAIL; 762 } 763 764 if (program_mode == BYTE_PROGRAM) { 765 buf = kmalloc(4, GFP_KERNEL); 766 if (!buf) { 767 rtsx_trace(chip); 768 return STATUS_ERROR; 769 } 770 771 while (len) { 772 retval = sf_enable_write(chip, SPI_WREN); 773 if (retval != STATUS_SUCCESS) { 774 kfree(buf); 775 rtsx_trace(chip); 776 return STATUS_FAIL; 777 } 778 779 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 780 FROM_XFER_BUF); 781 782 rtsx_init_cmd(chip); 783 784 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 785 0x01, PINGPONG_BUFFER); 786 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 787 buf[0]); 788 sf_program(chip, ins, 1, addr, 1); 789 790 retval = rtsx_send_cmd(chip, 0, 100); 791 if (retval < 0) { 792 kfree(buf); 793 rtsx_clear_spi_error(chip); 794 spi_set_err_code(chip, SPI_HW_ERR); 795 rtsx_trace(chip); 796 return STATUS_FAIL; 797 } 798 799 retval = sf_polling_status(chip, 100); 800 if (retval != STATUS_SUCCESS) { 801 kfree(buf); 802 rtsx_trace(chip); 803 return STATUS_FAIL; 804 } 805 806 addr++; 807 len--; 808 } 809 810 kfree(buf); 811 812 } else if (program_mode == AAI_PROGRAM) { 813 int first_byte = 1; 814 815 retval = sf_enable_write(chip, SPI_WREN); 816 if (retval != STATUS_SUCCESS) { 817 rtsx_trace(chip); 818 return STATUS_FAIL; 819 } 820 821 buf = kmalloc(4, GFP_KERNEL); 822 if (!buf) { 823 rtsx_trace(chip); 824 return STATUS_ERROR; 825 } 826 827 while (len) { 828 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 829 FROM_XFER_BUF); 830 831 rtsx_init_cmd(chip); 832 833 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 834 0x01, PINGPONG_BUFFER); 835 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 836 buf[0]); 837 if (first_byte) { 838 sf_program(chip, ins, 1, addr, 1); 839 first_byte = 0; 840 } else { 841 sf_program(chip, ins, 0, 0, 1); 842 } 843 844 retval = rtsx_send_cmd(chip, 0, 100); 845 if (retval < 0) { 846 kfree(buf); 847 rtsx_clear_spi_error(chip); 848 spi_set_err_code(chip, SPI_HW_ERR); 849 rtsx_trace(chip); 850 return STATUS_FAIL; 851 } 852 853 retval = sf_polling_status(chip, 100); 854 if (retval != STATUS_SUCCESS) { 855 kfree(buf); 856 rtsx_trace(chip); 857 return STATUS_FAIL; 858 } 859 860 len--; 861 } 862 863 kfree(buf); 864 865 retval = sf_disable_write(chip, SPI_WRDI); 866 if (retval != STATUS_SUCCESS) { 867 rtsx_trace(chip); 868 return STATUS_FAIL; 869 } 870 871 retval = sf_polling_status(chip, 100); 872 if (retval != STATUS_SUCCESS) { 873 rtsx_trace(chip); 874 return STATUS_FAIL; 875 } 876 } else if (program_mode == PAGE_PROGRAM) { 877 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 878 if (!buf) { 879 rtsx_trace(chip); 880 return STATUS_NOMEM; 881 } 882 883 while (len) { 884 u16 pagelen = SF_PAGE_LEN - (u8)addr; 885 886 if (pagelen > len) 887 pagelen = len; 888 889 retval = sf_enable_write(chip, SPI_WREN); 890 if (retval != STATUS_SUCCESS) { 891 kfree(buf); 892 rtsx_trace(chip); 893 return STATUS_FAIL; 894 } 895 896 rtsx_init_cmd(chip); 897 898 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256); 899 sf_program(chip, ins, 1, addr, pagelen); 900 901 rtsx_send_cmd_no_wait(chip); 902 903 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, 904 &offset, FROM_XFER_BUF); 905 906 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 907 DMA_TO_DEVICE, 100); 908 if (retval < 0) { 909 kfree(buf); 910 rtsx_clear_spi_error(chip); 911 spi_set_err_code(chip, SPI_HW_ERR); 912 rtsx_trace(chip); 913 return STATUS_FAIL; 914 } 915 916 retval = sf_polling_status(chip, 100); 917 if (retval != STATUS_SUCCESS) { 918 kfree(buf); 919 rtsx_trace(chip); 920 return STATUS_FAIL; 921 } 922 923 addr += pagelen; 924 len -= pagelen; 925 } 926 927 kfree(buf); 928 } else { 929 spi_set_err_code(chip, SPI_INVALID_COMMAND); 930 rtsx_trace(chip); 931 return STATUS_FAIL; 932 } 933 934 return STATUS_SUCCESS; 935 } 936 937 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 938 { 939 int retval; 940 u8 ins, erase_mode; 941 u32 addr; 942 943 spi_set_err_code(chip, SPI_NO_ERR); 944 945 ins = srb->cmnd[3]; 946 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 947 << 8) | srb->cmnd[6]; 948 erase_mode = srb->cmnd[9]; 949 950 retval = spi_set_init_para(chip); 951 if (retval != STATUS_SUCCESS) { 952 spi_set_err_code(chip, SPI_HW_ERR); 953 rtsx_trace(chip); 954 return STATUS_FAIL; 955 } 956 957 if (erase_mode == PAGE_ERASE) { 958 retval = sf_enable_write(chip, SPI_WREN); 959 if (retval != STATUS_SUCCESS) { 960 rtsx_trace(chip); 961 return STATUS_FAIL; 962 } 963 964 retval = sf_erase(chip, ins, 1, addr); 965 if (retval != STATUS_SUCCESS) { 966 rtsx_trace(chip); 967 return STATUS_FAIL; 968 } 969 } else if (erase_mode == CHIP_ERASE) { 970 retval = sf_enable_write(chip, SPI_WREN); 971 if (retval != STATUS_SUCCESS) { 972 rtsx_trace(chip); 973 return STATUS_FAIL; 974 } 975 976 retval = sf_erase(chip, ins, 0, 0); 977 if (retval != STATUS_SUCCESS) { 978 rtsx_trace(chip); 979 return STATUS_FAIL; 980 } 981 } else { 982 spi_set_err_code(chip, SPI_INVALID_COMMAND); 983 rtsx_trace(chip); 984 return STATUS_FAIL; 985 } 986 987 return STATUS_SUCCESS; 988 } 989 990 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 991 { 992 int retval; 993 u8 ins, status, ewsr; 994 995 ins = srb->cmnd[3]; 996 status = srb->cmnd[4]; 997 ewsr = srb->cmnd[5]; 998 999 retval = spi_set_init_para(chip); 1000 if (retval != STATUS_SUCCESS) { 1001 spi_set_err_code(chip, SPI_HW_ERR); 1002 rtsx_trace(chip); 1003 return STATUS_FAIL; 1004 } 1005 1006 retval = sf_enable_write(chip, ewsr); 1007 if (retval != STATUS_SUCCESS) { 1008 rtsx_trace(chip); 1009 return STATUS_FAIL; 1010 } 1011 1012 rtsx_init_cmd(chip); 1013 1014 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 1015 PINGPONG_BUFFER); 1016 1017 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 1018 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 1019 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 1020 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0); 1021 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 1022 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); 1023 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 1024 SPI_TRANSFER0_START | SPI_CDO_MODE0); 1025 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 1026 SPI_TRANSFER0_END); 1027 1028 retval = rtsx_send_cmd(chip, 0, 100); 1029 if (retval != STATUS_SUCCESS) { 1030 rtsx_clear_spi_error(chip); 1031 spi_set_err_code(chip, SPI_HW_ERR); 1032 rtsx_trace(chip); 1033 return STATUS_FAIL; 1034 } 1035 1036 return STATUS_SUCCESS; 1037 } 1038