1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 27 #include "rtsx.h" 28 #include "spi.h" 29 30 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code) 31 { 32 struct spi_info *spi = &chip->spi; 33 34 spi->err_code = err_code; 35 } 36 37 static int spi_init(struct rtsx_chip *chip) 38 { 39 int retval; 40 41 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 42 CS_POLARITY_LOW | DTO_MSB_FIRST 43 | SPI_MASTER | SPI_MODE0 | SPI_AUTO); 44 if (retval) 45 return retval; 46 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 47 SAMPLE_DELAY_HALF); 48 if (retval) 49 return retval; 50 51 return STATUS_SUCCESS; 52 } 53 54 static int spi_set_init_para(struct rtsx_chip *chip) 55 { 56 struct spi_info *spi = &chip->spi; 57 int retval; 58 59 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 60 (u8)(spi->clk_div >> 8)); 61 if (retval) 62 return retval; 63 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 64 (u8)(spi->clk_div)); 65 if (retval) 66 return retval; 67 68 retval = switch_clock(chip, spi->spi_clock); 69 if (retval != STATUS_SUCCESS) 70 return STATUS_FAIL; 71 72 retval = select_card(chip, SPI_CARD); 73 if (retval != STATUS_SUCCESS) 74 return STATUS_FAIL; 75 76 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 77 SPI_CLK_EN); 78 if (retval) 79 return retval; 80 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 81 SPI_OUTPUT_EN); 82 if (retval) 83 return retval; 84 85 wait_timeout(10); 86 87 retval = spi_init(chip); 88 if (retval != STATUS_SUCCESS) 89 return STATUS_FAIL; 90 91 return STATUS_SUCCESS; 92 } 93 94 static int sf_polling_status(struct rtsx_chip *chip, int msec) 95 { 96 int retval; 97 98 rtsx_init_cmd(chip); 99 100 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR); 101 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 102 SPI_TRANSFER0_START | SPI_POLLING_MODE0); 103 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 104 SPI_TRANSFER0_END); 105 106 retval = rtsx_send_cmd(chip, 0, msec); 107 if (retval < 0) { 108 rtsx_clear_spi_error(chip); 109 spi_set_err_code(chip, SPI_BUSY_ERR); 110 return STATUS_FAIL; 111 } 112 113 return STATUS_SUCCESS; 114 } 115 116 static int sf_enable_write(struct rtsx_chip *chip, u8 ins) 117 { 118 struct spi_info *spi = &chip->spi; 119 int retval; 120 121 if (!spi->write_en) 122 return STATUS_SUCCESS; 123 124 rtsx_init_cmd(chip); 125 126 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 127 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 128 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 129 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 130 SPI_TRANSFER0_START | SPI_C_MODE0); 131 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 132 SPI_TRANSFER0_END); 133 134 retval = rtsx_send_cmd(chip, 0, 100); 135 if (retval < 0) { 136 rtsx_clear_spi_error(chip); 137 spi_set_err_code(chip, SPI_HW_ERR); 138 return STATUS_FAIL; 139 } 140 141 return STATUS_SUCCESS; 142 } 143 144 static int sf_disable_write(struct rtsx_chip *chip, u8 ins) 145 { 146 struct spi_info *spi = &chip->spi; 147 int retval; 148 149 if (!spi->write_en) 150 return STATUS_SUCCESS; 151 152 rtsx_init_cmd(chip); 153 154 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 155 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 156 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 157 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 158 SPI_TRANSFER0_START | SPI_C_MODE0); 159 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 160 SPI_TRANSFER0_END); 161 162 retval = rtsx_send_cmd(chip, 0, 100); 163 if (retval < 0) { 164 rtsx_clear_spi_error(chip); 165 spi_set_err_code(chip, SPI_HW_ERR); 166 return STATUS_FAIL; 167 } 168 169 return STATUS_SUCCESS; 170 } 171 172 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr, 173 u16 len) 174 { 175 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 176 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 177 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 178 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len); 179 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8)); 180 if (addr_mode) { 181 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 182 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 183 (u8)(addr >> 8)); 184 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 185 (u8)(addr >> 16)); 186 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 187 SPI_TRANSFER0_START | SPI_CADO_MODE0); 188 } else { 189 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 190 SPI_TRANSFER0_START | SPI_CDO_MODE0); 191 } 192 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 193 SPI_TRANSFER0_END); 194 } 195 196 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr) 197 { 198 int retval; 199 200 rtsx_init_cmd(chip); 201 202 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 203 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 204 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 205 if (addr_mode) { 206 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 208 (u8)(addr >> 8)); 209 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 210 (u8)(addr >> 16)); 211 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 212 SPI_TRANSFER0_START | SPI_CA_MODE0); 213 } else { 214 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 215 SPI_TRANSFER0_START | SPI_C_MODE0); 216 } 217 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 218 SPI_TRANSFER0_END); 219 220 retval = rtsx_send_cmd(chip, 0, 100); 221 if (retval < 0) { 222 rtsx_clear_spi_error(chip); 223 spi_set_err_code(chip, SPI_HW_ERR); 224 return STATUS_FAIL; 225 } 226 227 return STATUS_SUCCESS; 228 } 229 230 static int spi_init_eeprom(struct rtsx_chip *chip) 231 { 232 int retval; 233 int clk; 234 235 if (chip->asic_code) 236 clk = 30; 237 else 238 clk = CLK_30; 239 240 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00); 241 if (retval) 242 return retval; 243 retval = rtsx_write_register(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27); 244 if (retval) 245 return retval; 246 247 retval = switch_clock(chip, clk); 248 if (retval != STATUS_SUCCESS) 249 return STATUS_FAIL; 250 251 retval = select_card(chip, SPI_CARD); 252 if (retval != STATUS_SUCCESS) 253 return STATUS_FAIL; 254 255 retval = rtsx_write_register(chip, CARD_CLK_EN, SPI_CLK_EN, 256 SPI_CLK_EN); 257 if (retval) 258 return retval; 259 retval = rtsx_write_register(chip, CARD_OE, SPI_OUTPUT_EN, 260 SPI_OUTPUT_EN); 261 if (retval) 262 return retval; 263 264 wait_timeout(10); 265 266 retval = rtsx_write_register(chip, SPI_CONTROL, 0xFF, 267 CS_POLARITY_HIGH | SPI_EEPROM_AUTO); 268 if (retval) 269 return retval; 270 retval = rtsx_write_register(chip, SPI_TCTL, EDO_TIMING_MASK, 271 SAMPLE_DELAY_HALF); 272 if (retval) 273 return retval; 274 275 return STATUS_SUCCESS; 276 } 277 278 static int spi_eeprom_program_enable(struct rtsx_chip *chip) 279 { 280 int retval; 281 282 rtsx_init_cmd(chip); 283 284 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86); 285 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13); 286 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 287 SPI_TRANSFER0_START | SPI_CA_MODE0); 288 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 289 SPI_TRANSFER0_END); 290 291 retval = rtsx_send_cmd(chip, 0, 100); 292 if (retval < 0) 293 return STATUS_FAIL; 294 295 return STATUS_SUCCESS; 296 } 297 298 int spi_erase_eeprom_chip(struct rtsx_chip *chip) 299 { 300 int retval; 301 302 retval = spi_init_eeprom(chip); 303 if (retval != STATUS_SUCCESS) 304 return STATUS_FAIL; 305 306 retval = spi_eeprom_program_enable(chip); 307 if (retval != STATUS_SUCCESS) 308 return STATUS_FAIL; 309 310 rtsx_init_cmd(chip); 311 312 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 313 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 314 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12); 315 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84); 316 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 317 SPI_TRANSFER0_START | SPI_CA_MODE0); 318 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 319 SPI_TRANSFER0_END); 320 321 retval = rtsx_send_cmd(chip, 0, 100); 322 if (retval < 0) 323 return STATUS_FAIL; 324 325 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 326 if (retval) 327 return retval; 328 329 return STATUS_SUCCESS; 330 } 331 332 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr) 333 { 334 int retval; 335 336 retval = spi_init_eeprom(chip); 337 if (retval != STATUS_SUCCESS) 338 return STATUS_FAIL; 339 340 retval = spi_eeprom_program_enable(chip); 341 if (retval != STATUS_SUCCESS) 342 return STATUS_FAIL; 343 344 rtsx_init_cmd(chip); 345 346 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 347 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 348 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07); 349 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 350 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 351 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 352 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 353 SPI_TRANSFER0_START | SPI_CA_MODE0); 354 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 355 SPI_TRANSFER0_END); 356 357 retval = rtsx_send_cmd(chip, 0, 100); 358 if (retval < 0) 359 return STATUS_FAIL; 360 361 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 362 if (retval) 363 return retval; 364 365 return STATUS_SUCCESS; 366 } 367 368 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val) 369 { 370 int retval; 371 u8 data; 372 373 retval = spi_init_eeprom(chip); 374 if (retval != STATUS_SUCCESS) 375 return STATUS_FAIL; 376 377 rtsx_init_cmd(chip); 378 379 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 380 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 381 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06); 382 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr); 383 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8)); 384 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46); 385 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 386 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 387 SPI_TRANSFER0_START | SPI_CADI_MODE0); 388 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 389 SPI_TRANSFER0_END); 390 391 retval = rtsx_send_cmd(chip, 0, 100); 392 if (retval < 0) 393 return STATUS_FAIL; 394 395 wait_timeout(5); 396 retval = rtsx_read_register(chip, SPI_DATA, &data); 397 if (retval) 398 return retval; 399 400 if (val) 401 *val = data; 402 403 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 404 if (retval) 405 return retval; 406 407 return STATUS_SUCCESS; 408 } 409 410 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val) 411 { 412 int retval; 413 414 retval = spi_init_eeprom(chip); 415 if (retval != STATUS_SUCCESS) 416 return STATUS_FAIL; 417 418 retval = spi_eeprom_program_enable(chip); 419 if (retval != STATUS_SUCCESS) 420 return STATUS_FAIL; 421 422 rtsx_init_cmd(chip); 423 424 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0); 425 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 426 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05); 427 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val); 428 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr); 429 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8)); 430 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E); 431 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 432 SPI_TRANSFER0_START | SPI_CA_MODE0); 433 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 434 SPI_TRANSFER0_END); 435 436 retval = rtsx_send_cmd(chip, 0, 100); 437 if (retval < 0) 438 return STATUS_FAIL; 439 440 retval = rtsx_write_register(chip, CARD_GPIO_DIR, 0x01, 0x01); 441 if (retval) 442 return retval; 443 444 return STATUS_SUCCESS; 445 } 446 447 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 448 { 449 struct spi_info *spi = &chip->spi; 450 451 dev_dbg(rtsx_dev(chip), "%s: err_code = 0x%x\n", __func__, 452 spi->err_code); 453 rtsx_stor_set_xfer_buf(&spi->err_code, 454 min_t(int, scsi_bufflen(srb), 1), srb); 455 scsi_set_resid(srb, scsi_bufflen(srb) - 1); 456 457 return STATUS_SUCCESS; 458 } 459 460 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip) 461 { 462 struct spi_info *spi = &chip->spi; 463 464 spi_set_err_code(chip, SPI_NO_ERR); 465 466 if (chip->asic_code) 467 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9]; 468 else 469 spi->spi_clock = srb->cmnd[3]; 470 471 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5]; 472 spi->write_en = srb->cmnd[6]; 473 474 dev_dbg(rtsx_dev(chip), "%s: ", __func__); 475 dev_dbg(rtsx_dev(chip), "spi_clock = %d, ", spi->spi_clock); 476 dev_dbg(rtsx_dev(chip), "clk_div = %d, ", spi->clk_div); 477 dev_dbg(rtsx_dev(chip), "write_en = %d\n", spi->write_en); 478 479 return STATUS_SUCCESS; 480 } 481 482 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 483 { 484 int retval; 485 u16 len; 486 u8 *buf; 487 488 spi_set_err_code(chip, SPI_NO_ERR); 489 490 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 491 if (len > 512) { 492 spi_set_err_code(chip, SPI_INVALID_COMMAND); 493 return STATUS_FAIL; 494 } 495 496 retval = spi_set_init_para(chip); 497 if (retval != STATUS_SUCCESS) { 498 spi_set_err_code(chip, SPI_HW_ERR); 499 return STATUS_FAIL; 500 } 501 502 rtsx_init_cmd(chip); 503 504 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 505 PINGPONG_BUFFER); 506 507 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]); 508 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]); 509 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]); 510 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]); 511 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 512 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 513 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]); 514 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]); 515 516 if (len == 0) { 517 if (srb->cmnd[9]) { 518 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 519 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0); 520 } else { 521 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 522 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0); 523 } 524 } else { 525 if (srb->cmnd[9]) { 526 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 527 SPI_TRANSFER0_START | SPI_CADI_MODE0); 528 } else { 529 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 530 SPI_TRANSFER0_START | SPI_CDI_MODE0); 531 } 532 } 533 534 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 535 SPI_TRANSFER0_END); 536 537 retval = rtsx_send_cmd(chip, 0, 100); 538 if (retval < 0) { 539 rtsx_clear_spi_error(chip); 540 spi_set_err_code(chip, SPI_HW_ERR); 541 return STATUS_FAIL; 542 } 543 544 if (len) { 545 buf = kmalloc(len, GFP_KERNEL); 546 if (!buf) 547 return STATUS_ERROR; 548 549 retval = rtsx_read_ppbuf(chip, buf, len); 550 if (retval != STATUS_SUCCESS) { 551 spi_set_err_code(chip, SPI_READ_ERR); 552 kfree(buf); 553 return STATUS_FAIL; 554 } 555 556 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb); 557 scsi_set_resid(srb, 0); 558 559 kfree(buf); 560 } 561 562 return STATUS_SUCCESS; 563 } 564 565 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 566 { 567 int retval; 568 unsigned int index = 0, offset = 0; 569 u8 ins, slow_read; 570 u32 addr; 571 u16 len; 572 u8 *buf; 573 574 spi_set_err_code(chip, SPI_NO_ERR); 575 576 ins = srb->cmnd[3]; 577 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 578 << 8) | srb->cmnd[6]; 579 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 580 slow_read = srb->cmnd[9]; 581 582 retval = spi_set_init_para(chip); 583 if (retval != STATUS_SUCCESS) { 584 spi_set_err_code(chip, SPI_HW_ERR); 585 return STATUS_FAIL; 586 } 587 588 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 589 if (!buf) 590 return STATUS_ERROR; 591 592 while (len) { 593 u16 pagelen = SF_PAGE_LEN - (u8)addr; 594 595 if (pagelen > len) 596 pagelen = len; 597 598 rtsx_init_cmd(chip); 599 600 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256); 601 602 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 603 604 if (slow_read) { 605 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, 606 (u8)addr); 607 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 608 (u8)(addr >> 8)); 609 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 610 (u8)(addr >> 16)); 611 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 612 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 613 } else { 614 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, 615 (u8)addr); 616 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, 617 (u8)(addr >> 8)); 618 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF, 619 (u8)(addr >> 16)); 620 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 621 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32); 622 } 623 624 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 625 (u8)(pagelen >> 8)); 626 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 627 (u8)pagelen); 628 629 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 630 SPI_TRANSFER0_START | SPI_CADI_MODE0); 631 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, 632 SPI_TRANSFER0_END, SPI_TRANSFER0_END); 633 634 rtsx_send_cmd_no_wait(chip); 635 636 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 637 DMA_FROM_DEVICE, 10000); 638 if (retval < 0) { 639 kfree(buf); 640 rtsx_clear_spi_error(chip); 641 spi_set_err_code(chip, SPI_HW_ERR); 642 return STATUS_FAIL; 643 } 644 645 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset, 646 TO_XFER_BUF); 647 648 addr += pagelen; 649 len -= pagelen; 650 } 651 652 scsi_set_resid(srb, 0); 653 kfree(buf); 654 655 return STATUS_SUCCESS; 656 } 657 658 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 659 { 660 int retval; 661 u8 ins, program_mode; 662 u32 addr; 663 u16 len; 664 u8 *buf; 665 unsigned int index = 0, offset = 0; 666 667 spi_set_err_code(chip, SPI_NO_ERR); 668 669 ins = srb->cmnd[3]; 670 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 671 << 8) | srb->cmnd[6]; 672 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8]; 673 program_mode = srb->cmnd[9]; 674 675 retval = spi_set_init_para(chip); 676 if (retval != STATUS_SUCCESS) { 677 spi_set_err_code(chip, SPI_HW_ERR); 678 return STATUS_FAIL; 679 } 680 681 if (program_mode == BYTE_PROGRAM) { 682 buf = kmalloc(4, GFP_KERNEL); 683 if (!buf) 684 return STATUS_ERROR; 685 686 while (len) { 687 retval = sf_enable_write(chip, SPI_WREN); 688 if (retval != STATUS_SUCCESS) { 689 kfree(buf); 690 return STATUS_FAIL; 691 } 692 693 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 694 FROM_XFER_BUF); 695 696 rtsx_init_cmd(chip); 697 698 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 699 0x01, PINGPONG_BUFFER); 700 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 701 buf[0]); 702 sf_program(chip, ins, 1, addr, 1); 703 704 retval = rtsx_send_cmd(chip, 0, 100); 705 if (retval < 0) { 706 kfree(buf); 707 rtsx_clear_spi_error(chip); 708 spi_set_err_code(chip, SPI_HW_ERR); 709 return STATUS_FAIL; 710 } 711 712 retval = sf_polling_status(chip, 100); 713 if (retval != STATUS_SUCCESS) { 714 kfree(buf); 715 return STATUS_FAIL; 716 } 717 718 addr++; 719 len--; 720 } 721 722 kfree(buf); 723 724 } else if (program_mode == AAI_PROGRAM) { 725 int first_byte = 1; 726 727 retval = sf_enable_write(chip, SPI_WREN); 728 if (retval != STATUS_SUCCESS) 729 return STATUS_FAIL; 730 731 buf = kmalloc(4, GFP_KERNEL); 732 if (!buf) 733 return STATUS_ERROR; 734 735 while (len) { 736 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset, 737 FROM_XFER_BUF); 738 739 rtsx_init_cmd(chip); 740 741 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 742 0x01, PINGPONG_BUFFER); 743 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, 744 buf[0]); 745 if (first_byte) { 746 sf_program(chip, ins, 1, addr, 1); 747 first_byte = 0; 748 } else { 749 sf_program(chip, ins, 0, 0, 1); 750 } 751 752 retval = rtsx_send_cmd(chip, 0, 100); 753 if (retval < 0) { 754 kfree(buf); 755 rtsx_clear_spi_error(chip); 756 spi_set_err_code(chip, SPI_HW_ERR); 757 return STATUS_FAIL; 758 } 759 760 retval = sf_polling_status(chip, 100); 761 if (retval != STATUS_SUCCESS) { 762 kfree(buf); 763 return STATUS_FAIL; 764 } 765 766 len--; 767 } 768 769 kfree(buf); 770 771 retval = sf_disable_write(chip, SPI_WRDI); 772 if (retval != STATUS_SUCCESS) 773 return STATUS_FAIL; 774 775 retval = sf_polling_status(chip, 100); 776 if (retval != STATUS_SUCCESS) 777 return STATUS_FAIL; 778 } else if (program_mode == PAGE_PROGRAM) { 779 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL); 780 if (!buf) 781 return STATUS_NOMEM; 782 783 while (len) { 784 u16 pagelen = SF_PAGE_LEN - (u8)addr; 785 786 if (pagelen > len) 787 pagelen = len; 788 789 retval = sf_enable_write(chip, SPI_WREN); 790 if (retval != STATUS_SUCCESS) { 791 kfree(buf); 792 return STATUS_FAIL; 793 } 794 795 rtsx_init_cmd(chip); 796 797 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256); 798 sf_program(chip, ins, 1, addr, pagelen); 799 800 rtsx_send_cmd_no_wait(chip); 801 802 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, 803 &offset, FROM_XFER_BUF); 804 805 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, 806 DMA_TO_DEVICE, 100); 807 if (retval < 0) { 808 kfree(buf); 809 rtsx_clear_spi_error(chip); 810 spi_set_err_code(chip, SPI_HW_ERR); 811 return STATUS_FAIL; 812 } 813 814 retval = sf_polling_status(chip, 100); 815 if (retval != STATUS_SUCCESS) { 816 kfree(buf); 817 return STATUS_FAIL; 818 } 819 820 addr += pagelen; 821 len -= pagelen; 822 } 823 824 kfree(buf); 825 } else { 826 spi_set_err_code(chip, SPI_INVALID_COMMAND); 827 return STATUS_FAIL; 828 } 829 830 return STATUS_SUCCESS; 831 } 832 833 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip) 834 { 835 int retval; 836 u8 ins, erase_mode; 837 u32 addr; 838 839 spi_set_err_code(chip, SPI_NO_ERR); 840 841 ins = srb->cmnd[3]; 842 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5]) 843 << 8) | srb->cmnd[6]; 844 erase_mode = srb->cmnd[9]; 845 846 retval = spi_set_init_para(chip); 847 if (retval != STATUS_SUCCESS) { 848 spi_set_err_code(chip, SPI_HW_ERR); 849 return STATUS_FAIL; 850 } 851 852 if (erase_mode == PAGE_ERASE) { 853 retval = sf_enable_write(chip, SPI_WREN); 854 if (retval != STATUS_SUCCESS) 855 return STATUS_FAIL; 856 857 retval = sf_erase(chip, ins, 1, addr); 858 if (retval != STATUS_SUCCESS) 859 return STATUS_FAIL; 860 } else if (erase_mode == CHIP_ERASE) { 861 retval = sf_enable_write(chip, SPI_WREN); 862 if (retval != STATUS_SUCCESS) 863 return STATUS_FAIL; 864 865 retval = sf_erase(chip, ins, 0, 0); 866 if (retval != STATUS_SUCCESS) 867 return STATUS_FAIL; 868 } else { 869 spi_set_err_code(chip, SPI_INVALID_COMMAND); 870 return STATUS_FAIL; 871 } 872 873 return STATUS_SUCCESS; 874 } 875 876 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip) 877 { 878 int retval; 879 u8 ins, status, ewsr; 880 881 ins = srb->cmnd[3]; 882 status = srb->cmnd[4]; 883 ewsr = srb->cmnd[5]; 884 885 retval = spi_set_init_para(chip); 886 if (retval != STATUS_SUCCESS) { 887 spi_set_err_code(chip, SPI_HW_ERR); 888 return STATUS_FAIL; 889 } 890 891 retval = sf_enable_write(chip, ewsr); 892 if (retval != STATUS_SUCCESS) 893 return STATUS_FAIL; 894 895 rtsx_init_cmd(chip); 896 897 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 898 PINGPONG_BUFFER); 899 900 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins); 901 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 902 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24); 903 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0); 904 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1); 905 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status); 906 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF, 907 SPI_TRANSFER0_START | SPI_CDO_MODE0); 908 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END, 909 SPI_TRANSFER0_END); 910 911 retval = rtsx_send_cmd(chip, 0, 100); 912 if (retval != STATUS_SUCCESS) { 913 rtsx_clear_spi_error(chip); 914 spi_set_err_code(chip, SPI_HW_ERR); 915 return STATUS_FAIL; 916 } 917 918 return STATUS_SUCCESS; 919 } 920