1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 27 #include "rtsx.h" 28 #include "sd.h" 29 30 #define SD_MAX_RETRY_COUNT 3 31 32 static u16 REG_SD_CFG1; 33 static u16 REG_SD_CFG2; 34 static u16 REG_SD_CFG3; 35 static u16 REG_SD_STAT1; 36 static u16 REG_SD_STAT2; 37 static u16 REG_SD_BUS_STAT; 38 static u16 REG_SD_PAD_CTL; 39 static u16 REG_SD_SAMPLE_POINT_CTL; 40 static u16 REG_SD_PUSH_POINT_CTL; 41 static u16 REG_SD_CMD0; 42 static u16 REG_SD_CMD1; 43 static u16 REG_SD_CMD2; 44 static u16 REG_SD_CMD3; 45 static u16 REG_SD_CMD4; 46 static u16 REG_SD_CMD5; 47 static u16 REG_SD_BYTE_CNT_L; 48 static u16 REG_SD_BYTE_CNT_H; 49 static u16 REG_SD_BLOCK_CNT_L; 50 static u16 REG_SD_BLOCK_CNT_H; 51 static u16 REG_SD_TRANSFER; 52 static u16 REG_SD_VPCLK0_CTL; 53 static u16 REG_SD_VPCLK1_CTL; 54 static u16 REG_SD_DCMPS0_CTL; 55 static u16 REG_SD_DCMPS1_CTL; 56 57 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code) 58 { 59 struct sd_info *sd_card = &(chip->sd_card); 60 61 sd_card->err_code |= err_code; 62 } 63 64 static inline void sd_clr_err_code(struct rtsx_chip *chip) 65 { 66 struct sd_info *sd_card = &(chip->sd_card); 67 68 sd_card->err_code = 0; 69 } 70 71 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code) 72 { 73 struct sd_info *sd_card = &(chip->sd_card); 74 75 return sd_card->err_code & err_code; 76 } 77 78 static void sd_init_reg_addr(struct rtsx_chip *chip) 79 { 80 REG_SD_CFG1 = 0xFD31; 81 REG_SD_CFG2 = 0xFD33; 82 REG_SD_CFG3 = 0xFD3E; 83 REG_SD_STAT1 = 0xFD30; 84 REG_SD_STAT2 = 0; 85 REG_SD_BUS_STAT = 0; 86 REG_SD_PAD_CTL = 0; 87 REG_SD_SAMPLE_POINT_CTL = 0; 88 REG_SD_PUSH_POINT_CTL = 0; 89 REG_SD_CMD0 = 0xFD34; 90 REG_SD_CMD1 = 0xFD35; 91 REG_SD_CMD2 = 0xFD36; 92 REG_SD_CMD3 = 0xFD37; 93 REG_SD_CMD4 = 0xFD38; 94 REG_SD_CMD5 = 0xFD5A; 95 REG_SD_BYTE_CNT_L = 0xFD39; 96 REG_SD_BYTE_CNT_H = 0xFD3A; 97 REG_SD_BLOCK_CNT_L = 0xFD3B; 98 REG_SD_BLOCK_CNT_H = 0xFD3C; 99 REG_SD_TRANSFER = 0xFD32; 100 REG_SD_VPCLK0_CTL = 0; 101 REG_SD_VPCLK1_CTL = 0; 102 REG_SD_DCMPS0_CTL = 0; 103 REG_SD_DCMPS1_CTL = 0; 104 } 105 106 static int sd_check_data0_status(struct rtsx_chip *chip) 107 { 108 int retval; 109 u8 stat; 110 111 retval = rtsx_read_register(chip, REG_SD_STAT1, &stat); 112 if (retval) { 113 rtsx_trace(chip); 114 return retval; 115 } 116 117 if (!(stat & SD_DAT0_STATUS)) { 118 sd_set_err_code(chip, SD_BUSY); 119 rtsx_trace(chip); 120 return STATUS_FAIL; 121 } 122 123 return STATUS_SUCCESS; 124 } 125 126 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 127 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len) 128 { 129 struct sd_info *sd_card = &(chip->sd_card); 130 int retval; 131 int timeout = 100; 132 u16 reg_addr; 133 u8 *ptr; 134 int stat_idx = 0; 135 int rty_cnt = 0; 136 137 sd_clr_err_code(chip); 138 139 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg); 140 141 if (rsp_type == SD_RSP_TYPE_R1b) 142 timeout = 3000; 143 144 RTY_SEND_CMD: 145 146 rtsx_init_cmd(chip); 147 148 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); 149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); 150 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); 151 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); 152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); 153 154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 155 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 156 0x01, PINGPONG_BUFFER); 157 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 158 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 159 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 160 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END | SD_STAT_IDLE); 161 162 if (rsp_type == SD_RSP_TYPE_R2) { 163 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 164 reg_addr++) 165 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 166 167 stat_idx = 16; 168 } else if (rsp_type != SD_RSP_TYPE_R0) { 169 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 170 reg_addr++) 171 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 172 173 stat_idx = 5; 174 } 175 176 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); 177 178 retval = rtsx_send_cmd(chip, SD_CARD, timeout); 179 if (retval < 0) { 180 u8 val; 181 182 rtsx_read_register(chip, REG_SD_STAT1, &val); 183 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val); 184 185 rtsx_read_register(chip, REG_SD_CFG3, &val); 186 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val); 187 188 if (retval == -ETIMEDOUT) { 189 if (rsp_type & SD_WAIT_BUSY_END) { 190 retval = sd_check_data0_status(chip); 191 if (retval != STATUS_SUCCESS) { 192 rtsx_clear_sd_error(chip); 193 rtsx_trace(chip); 194 return retval; 195 } 196 } else { 197 sd_set_err_code(chip, SD_TO_ERR); 198 } 199 retval = STATUS_TIMEDOUT; 200 } else { 201 retval = STATUS_FAIL; 202 } 203 rtsx_clear_sd_error(chip); 204 205 rtsx_trace(chip); 206 return retval; 207 } 208 209 if (rsp_type == SD_RSP_TYPE_R0) 210 return STATUS_SUCCESS; 211 212 ptr = rtsx_get_cmd_data(chip) + 1; 213 214 if ((ptr[0] & 0xC0) != 0) { 215 sd_set_err_code(chip, SD_STS_ERR); 216 rtsx_trace(chip); 217 return STATUS_FAIL; 218 } 219 220 if (!(rsp_type & SD_NO_CHECK_CRC7)) { 221 if (ptr[stat_idx] & SD_CRC7_ERR) { 222 if (cmd_idx == WRITE_MULTIPLE_BLOCK) { 223 sd_set_err_code(chip, SD_CRC_ERR); 224 rtsx_trace(chip); 225 return STATUS_FAIL; 226 } 227 if (rty_cnt < SD_MAX_RETRY_COUNT) { 228 wait_timeout(20); 229 rty_cnt++; 230 goto RTY_SEND_CMD; 231 } else { 232 sd_set_err_code(chip, SD_CRC_ERR); 233 rtsx_trace(chip); 234 return STATUS_FAIL; 235 } 236 } 237 } 238 239 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) { 240 if ((cmd_idx != SEND_RELATIVE_ADDR) && 241 (cmd_idx != SEND_IF_COND)) { 242 if (cmd_idx != STOP_TRANSMISSION) { 243 if (ptr[1] & 0x80) { 244 rtsx_trace(chip); 245 return STATUS_FAIL; 246 } 247 } 248 #ifdef SUPPORT_SD_LOCK 249 if (ptr[1] & 0x7D) { 250 #else 251 if (ptr[1] & 0x7F) { 252 #endif 253 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n", 254 ptr[1]); 255 rtsx_trace(chip); 256 return STATUS_FAIL; 257 } 258 if (ptr[2] & 0xFF) { 259 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n", 260 ptr[2]); 261 rtsx_trace(chip); 262 return STATUS_FAIL; 263 } 264 if (ptr[3] & 0x80) { 265 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n", 266 ptr[3]); 267 rtsx_trace(chip); 268 return STATUS_FAIL; 269 } 270 if (ptr[3] & 0x01) 271 sd_card->sd_data_buf_ready = 1; 272 else 273 sd_card->sd_data_buf_ready = 0; 274 } 275 } 276 277 if (rsp && rsp_len) 278 memcpy(rsp, ptr, rsp_len); 279 280 return STATUS_SUCCESS; 281 } 282 283 static int sd_read_data(struct rtsx_chip *chip, 284 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt, 285 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len, 286 int timeout) 287 { 288 struct sd_info *sd_card = &(chip->sd_card); 289 int retval; 290 int i; 291 292 sd_clr_err_code(chip); 293 294 if (!buf) 295 buf_len = 0; 296 297 if (buf_len > 512) { 298 rtsx_trace(chip); 299 return STATUS_FAIL; 300 } 301 302 rtsx_init_cmd(chip); 303 304 if (cmd_len) { 305 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40); 306 for (i = 0; i < (min(cmd_len, 6)); i++) 307 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i, 308 0xFF, cmd[i]); 309 } 310 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 311 (u8)byte_cnt); 312 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 313 (u8)(byte_cnt >> 8)); 314 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 315 (u8)blk_cnt); 316 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 317 (u8)(blk_cnt >> 8)); 318 319 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 320 321 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 322 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| 323 SD_CHECK_CRC7 | SD_RSP_LEN_6); 324 if (trans_mode != SD_TM_AUTO_TUNING) 325 rtsx_add_cmd(chip, WRITE_REG_CMD, 326 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 327 328 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 329 trans_mode | SD_TRANSFER_START); 330 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 331 SD_TRANSFER_END); 332 333 retval = rtsx_send_cmd(chip, SD_CARD, timeout); 334 if (retval < 0) { 335 if (retval == -ETIMEDOUT) { 336 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 337 SD_RSP_TYPE_R1, NULL, 0); 338 } 339 340 rtsx_trace(chip); 341 return STATUS_FAIL; 342 } 343 344 if (buf && buf_len) { 345 retval = rtsx_read_ppbuf(chip, buf, buf_len); 346 if (retval != STATUS_SUCCESS) { 347 rtsx_trace(chip); 348 return STATUS_FAIL; 349 } 350 } 351 352 return STATUS_SUCCESS; 353 } 354 355 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode, 356 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt, u8 bus_width, 357 u8 *buf, int buf_len, int timeout) 358 { 359 struct sd_info *sd_card = &(chip->sd_card); 360 int retval; 361 int i; 362 363 sd_clr_err_code(chip); 364 365 if (!buf) 366 buf_len = 0; 367 368 if (buf_len > 512) { 369 /* This function can't write data more than one page */ 370 rtsx_trace(chip); 371 return STATUS_FAIL; 372 } 373 374 if (buf && buf_len) { 375 retval = rtsx_write_ppbuf(chip, buf, buf_len); 376 if (retval != STATUS_SUCCESS) { 377 rtsx_trace(chip); 378 return STATUS_FAIL; 379 } 380 } 381 382 rtsx_init_cmd(chip); 383 384 if (cmd_len) { 385 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40); 386 for (i = 0; i < (min(cmd_len, 6)); i++) { 387 rtsx_add_cmd(chip, WRITE_REG_CMD, 388 REG_SD_CMD0 + i, 0xFF, cmd[i]); 389 } 390 } 391 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 392 (u8)byte_cnt); 393 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 394 (u8)(byte_cnt >> 8)); 395 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 396 (u8)blk_cnt); 397 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 398 (u8)(blk_cnt >> 8)); 399 400 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 401 402 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 403 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END | 404 SD_CHECK_CRC7 | SD_RSP_LEN_6); 405 406 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 407 trans_mode | SD_TRANSFER_START); 408 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 409 SD_TRANSFER_END); 410 411 retval = rtsx_send_cmd(chip, SD_CARD, timeout); 412 if (retval < 0) { 413 if (retval == -ETIMEDOUT) { 414 sd_send_cmd_get_rsp(chip, SEND_STATUS, 415 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); 416 } 417 418 rtsx_trace(chip); 419 return STATUS_FAIL; 420 } 421 422 return STATUS_SUCCESS; 423 } 424 425 static int sd_check_csd(struct rtsx_chip *chip, char check_wp) 426 { 427 struct sd_info *sd_card = &(chip->sd_card); 428 int retval; 429 int i; 430 u8 csd_ver, trans_speed; 431 u8 rsp[16]; 432 433 for (i = 0; i < 6; i++) { 434 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 435 sd_set_err_code(chip, SD_NO_CARD); 436 rtsx_trace(chip); 437 return STATUS_FAIL; 438 } 439 440 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr, 441 SD_RSP_TYPE_R2, rsp, 16); 442 if (retval == STATUS_SUCCESS) 443 break; 444 } 445 446 if (i == 6) { 447 rtsx_trace(chip); 448 return STATUS_FAIL; 449 } 450 451 memcpy(sd_card->raw_csd, rsp + 1, 15); 452 453 dev_dbg(rtsx_dev(chip), "CSD Response:\n"); 454 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd); 455 456 csd_ver = (rsp[1] & 0xc0) >> 6; 457 dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver); 458 459 trans_speed = rsp[4]; 460 if ((trans_speed & 0x07) == 0x02) { 461 if ((trans_speed & 0xf8) >= 0x30) { 462 if (chip->asic_code) 463 sd_card->sd_clock = 47; 464 else 465 sd_card->sd_clock = CLK_50; 466 467 } else if ((trans_speed & 0xf8) == 0x28) { 468 if (chip->asic_code) 469 sd_card->sd_clock = 39; 470 else 471 sd_card->sd_clock = CLK_40; 472 473 } else if ((trans_speed & 0xf8) == 0x20) { 474 if (chip->asic_code) 475 sd_card->sd_clock = 29; 476 else 477 sd_card->sd_clock = CLK_30; 478 479 } else if ((trans_speed & 0xf8) >= 0x10) { 480 if (chip->asic_code) 481 sd_card->sd_clock = 23; 482 else 483 sd_card->sd_clock = CLK_20; 484 485 } else if ((trans_speed & 0x08) >= 0x08) { 486 if (chip->asic_code) 487 sd_card->sd_clock = 19; 488 else 489 sd_card->sd_clock = CLK_20; 490 } else { 491 rtsx_trace(chip); 492 return STATUS_FAIL; 493 } 494 } else { 495 rtsx_trace(chip); 496 return STATUS_FAIL; 497 } 498 499 if (CHK_MMC_SECTOR_MODE(sd_card)) { 500 sd_card->capacity = 0; 501 } else { 502 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) { 503 u8 blk_size, c_size_mult; 504 u16 c_size; 505 506 blk_size = rsp[6] & 0x0F; 507 c_size = ((u16)(rsp[7] & 0x03) << 10) 508 + ((u16)rsp[8] << 2) 509 + ((u16)(rsp[9] & 0xC0) >> 6); 510 c_size_mult = (u8)((rsp[10] & 0x03) << 1); 511 c_size_mult += (rsp[11] & 0x80) >> 7; 512 sd_card->capacity = (((u32)(c_size + 1)) * 513 (1 << (c_size_mult + 2))) 514 << (blk_size - 9); 515 } else { 516 u32 total_sector = 0; 517 518 total_sector = (((u32)rsp[8] & 0x3f) << 16) | 519 ((u32)rsp[9] << 8) | (u32)rsp[10]; 520 sd_card->capacity = (total_sector + 1) << 10; 521 } 522 } 523 524 if (check_wp) { 525 if (rsp[15] & 0x30) 526 chip->card_wp |= SD_CARD; 527 528 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]); 529 } 530 531 return STATUS_SUCCESS; 532 } 533 534 static int sd_set_sample_push_timing(struct rtsx_chip *chip) 535 { 536 int retval; 537 struct sd_info *sd_card = &(chip->sd_card); 538 u8 val = 0; 539 540 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY) 541 val |= 0x10; 542 543 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) { 544 if (chip->asic_code) { 545 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) { 546 if (val & 0x10) 547 val |= 0x04; 548 else 549 val |= 0x08; 550 } 551 } else { 552 if (val & 0x10) 553 val |= 0x04; 554 else 555 val |= 0x08; 556 } 557 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == 558 SD_SAMPLE_POINT_DELAY) { 559 if (val & 0x10) 560 val |= 0x04; 561 else 562 val |= 0x08; 563 } 564 565 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val); 566 if (retval) { 567 rtsx_trace(chip); 568 return retval; 569 } 570 571 return STATUS_SUCCESS; 572 } 573 574 static void sd_choose_proper_clock(struct rtsx_chip *chip) 575 { 576 struct sd_info *sd_card = &(chip->sd_card); 577 578 if (CHK_SD_SDR104(sd_card)) { 579 if (chip->asic_code) 580 sd_card->sd_clock = chip->asic_sd_sdr104_clk; 581 else 582 sd_card->sd_clock = chip->fpga_sd_sdr104_clk; 583 584 } else if (CHK_SD_DDR50(sd_card)) { 585 if (chip->asic_code) 586 sd_card->sd_clock = chip->asic_sd_ddr50_clk; 587 else 588 sd_card->sd_clock = chip->fpga_sd_ddr50_clk; 589 590 } else if (CHK_SD_SDR50(sd_card)) { 591 if (chip->asic_code) 592 sd_card->sd_clock = chip->asic_sd_sdr50_clk; 593 else 594 sd_card->sd_clock = chip->fpga_sd_sdr50_clk; 595 596 } else if (CHK_SD_HS(sd_card)) { 597 if (chip->asic_code) 598 sd_card->sd_clock = chip->asic_sd_hs_clk; 599 else 600 sd_card->sd_clock = chip->fpga_sd_hs_clk; 601 602 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) { 603 if (chip->asic_code) 604 sd_card->sd_clock = chip->asic_mmc_52m_clk; 605 else 606 sd_card->sd_clock = chip->fpga_mmc_52m_clk; 607 608 } else if (CHK_MMC_26M(sd_card)) { 609 if (chip->asic_code) 610 sd_card->sd_clock = 48; 611 else 612 sd_card->sd_clock = CLK_50; 613 } 614 } 615 616 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div) 617 { 618 int retval; 619 u8 mask = 0, val = 0; 620 621 mask = 0x60; 622 if (clk_div == SD_CLK_DIVIDE_0) 623 val = 0x00; 624 else if (clk_div == SD_CLK_DIVIDE_128) 625 val = 0x40; 626 else if (clk_div == SD_CLK_DIVIDE_256) 627 val = 0x20; 628 629 retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val); 630 if (retval) { 631 rtsx_trace(chip); 632 return retval; 633 } 634 635 return STATUS_SUCCESS; 636 } 637 638 static int sd_set_init_para(struct rtsx_chip *chip) 639 { 640 struct sd_info *sd_card = &(chip->sd_card); 641 int retval; 642 643 retval = sd_set_sample_push_timing(chip); 644 if (retval != STATUS_SUCCESS) { 645 rtsx_trace(chip); 646 return STATUS_FAIL; 647 } 648 649 sd_choose_proper_clock(chip); 650 651 retval = switch_clock(chip, sd_card->sd_clock); 652 if (retval != STATUS_SUCCESS) { 653 rtsx_trace(chip); 654 return STATUS_FAIL; 655 } 656 657 return STATUS_SUCCESS; 658 } 659 660 int sd_select_card(struct rtsx_chip *chip, int select) 661 { 662 struct sd_info *sd_card = &(chip->sd_card); 663 int retval; 664 u8 cmd_idx, cmd_type; 665 u32 addr; 666 667 if (select) { 668 cmd_idx = SELECT_CARD; 669 cmd_type = SD_RSP_TYPE_R1; 670 addr = sd_card->sd_addr; 671 } else { 672 cmd_idx = DESELECT_CARD; 673 cmd_type = SD_RSP_TYPE_R0; 674 addr = 0; 675 } 676 677 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0); 678 if (retval != STATUS_SUCCESS) { 679 rtsx_trace(chip); 680 return STATUS_FAIL; 681 } 682 683 return STATUS_SUCCESS; 684 } 685 686 #ifdef SUPPORT_SD_LOCK 687 static int sd_update_lock_status(struct rtsx_chip *chip) 688 { 689 struct sd_info *sd_card = &(chip->sd_card); 690 int retval; 691 u8 rsp[5]; 692 693 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 694 SD_RSP_TYPE_R1, rsp, 5); 695 if (retval != STATUS_SUCCESS) { 696 rtsx_trace(chip); 697 return STATUS_FAIL; 698 } 699 700 if (rsp[1] & 0x02) 701 sd_card->sd_lock_status |= SD_LOCKED; 702 else 703 sd_card->sd_lock_status &= ~SD_LOCKED; 704 705 dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n", 706 sd_card->sd_lock_status); 707 708 if (rsp[1] & 0x01) { 709 rtsx_trace(chip); 710 return STATUS_FAIL; 711 } 712 713 return STATUS_SUCCESS; 714 } 715 #endif 716 717 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state, 718 u8 data_ready, int polling_cnt) 719 { 720 struct sd_info *sd_card = &(chip->sd_card); 721 int retval, i; 722 u8 rsp[5]; 723 724 for (i = 0; i < polling_cnt; i++) { 725 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 726 sd_card->sd_addr, SD_RSP_TYPE_R1, rsp, 727 5); 728 if (retval != STATUS_SUCCESS) { 729 rtsx_trace(chip); 730 return STATUS_FAIL; 731 } 732 733 if (((rsp[3] & 0x1E) == state) && 734 ((rsp[3] & 0x01) == data_ready)) 735 return STATUS_SUCCESS; 736 } 737 738 rtsx_trace(chip); 739 return STATUS_FAIL; 740 } 741 742 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage) 743 { 744 int retval; 745 746 if (voltage == SD_IO_3V3) { 747 if (chip->asic_code) { 748 retval = rtsx_write_phy_register(chip, 0x08, 749 0x4FC0 | 750 chip->phy_voltage); 751 if (retval != STATUS_SUCCESS) { 752 rtsx_trace(chip); 753 return STATUS_FAIL; 754 } 755 } else { 756 retval = rtsx_write_register(chip, SD_PAD_CTL, 757 SD_IO_USING_1V8, 0); 758 if (retval) { 759 rtsx_trace(chip); 760 return retval; 761 } 762 } 763 } else if (voltage == SD_IO_1V8) { 764 if (chip->asic_code) { 765 retval = rtsx_write_phy_register(chip, 0x08, 766 0x4C40 | 767 chip->phy_voltage); 768 if (retval != STATUS_SUCCESS) { 769 rtsx_trace(chip); 770 return STATUS_FAIL; 771 } 772 } else { 773 retval = rtsx_write_register(chip, SD_PAD_CTL, 774 SD_IO_USING_1V8, 775 SD_IO_USING_1V8); 776 if (retval) { 777 rtsx_trace(chip); 778 return retval; 779 } 780 } 781 } else { 782 rtsx_trace(chip); 783 return STATUS_FAIL; 784 } 785 786 return STATUS_SUCCESS; 787 } 788 789 static int sd_voltage_switch(struct rtsx_chip *chip) 790 { 791 int retval; 792 u8 stat; 793 794 retval = rtsx_write_register(chip, SD_BUS_STAT, 795 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 796 SD_CLK_TOGGLE_EN); 797 if (retval) { 798 rtsx_trace(chip); 799 return retval; 800 } 801 802 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1, 803 NULL, 0); 804 if (retval != STATUS_SUCCESS) { 805 rtsx_trace(chip); 806 return STATUS_FAIL; 807 } 808 809 udelay(chip->sd_voltage_switch_delay); 810 811 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); 812 if (retval) { 813 rtsx_trace(chip); 814 return retval; 815 } 816 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 817 SD_DAT1_STATUS | SD_DAT0_STATUS)) { 818 rtsx_trace(chip); 819 return STATUS_FAIL; 820 } 821 822 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, 823 SD_CLK_FORCE_STOP); 824 if (retval) { 825 rtsx_trace(chip); 826 return retval; 827 } 828 retval = sd_change_bank_voltage(chip, SD_IO_1V8); 829 if (retval != STATUS_SUCCESS) { 830 rtsx_trace(chip); 831 return STATUS_FAIL; 832 } 833 834 wait_timeout(50); 835 836 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF, 837 SD_CLK_TOGGLE_EN); 838 if (retval) { 839 rtsx_trace(chip); 840 return retval; 841 } 842 wait_timeout(10); 843 844 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat); 845 if (retval) { 846 rtsx_trace(chip); 847 return retval; 848 } 849 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 850 SD_DAT1_STATUS | SD_DAT0_STATUS)) != 851 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 852 SD_DAT1_STATUS | SD_DAT0_STATUS)) { 853 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat); 854 rtsx_write_register(chip, SD_BUS_STAT, 855 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 856 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0); 857 rtsx_trace(chip); 858 return STATUS_FAIL; 859 } 860 861 retval = rtsx_write_register(chip, SD_BUS_STAT, 862 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 863 if (retval) { 864 rtsx_trace(chip); 865 return retval; 866 } 867 868 return STATUS_SUCCESS; 869 } 870 871 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir) 872 { 873 int retval; 874 875 if (tune_dir == TUNE_RX) { 876 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, 877 DCM_RESET | DCM_RX); 878 if (retval) { 879 rtsx_trace(chip); 880 return retval; 881 } 882 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX); 883 if (retval) { 884 rtsx_trace(chip); 885 return retval; 886 } 887 } else { 888 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, 889 DCM_RESET | DCM_TX); 890 if (retval) { 891 rtsx_trace(chip); 892 return retval; 893 } 894 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX); 895 if (retval) { 896 rtsx_trace(chip); 897 return retval; 898 } 899 } 900 901 return STATUS_SUCCESS; 902 } 903 904 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir) 905 { 906 struct sd_info *sd_card = &(chip->sd_card); 907 u16 SD_VP_CTL, SD_DCMPS_CTL; 908 u8 val; 909 int retval; 910 bool ddr_rx = false; 911 912 dev_dbg(rtsx_dev(chip), "sd_change_phase (sample_point = %d, tune_dir = %d)\n", 913 sample_point, tune_dir); 914 915 if (tune_dir == TUNE_RX) { 916 SD_VP_CTL = SD_VPRX_CTL; 917 SD_DCMPS_CTL = SD_DCMPS_RX_CTL; 918 if (CHK_SD_DDR50(sd_card)) 919 ddr_rx = true; 920 } else { 921 SD_VP_CTL = SD_VPTX_CTL; 922 SD_DCMPS_CTL = SD_DCMPS_TX_CTL; 923 } 924 925 if (chip->asic_code) { 926 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 927 CHANGE_CLK); 928 if (retval) { 929 rtsx_trace(chip); 930 return retval; 931 } 932 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F, 933 sample_point); 934 if (retval) { 935 rtsx_trace(chip); 936 return retval; 937 } 938 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 939 PHASE_NOT_RESET, 0); 940 if (retval) { 941 rtsx_trace(chip); 942 return retval; 943 } 944 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 945 PHASE_NOT_RESET, PHASE_NOT_RESET); 946 if (retval) { 947 rtsx_trace(chip); 948 return retval; 949 } 950 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0); 951 if (retval) { 952 rtsx_trace(chip); 953 return retval; 954 } 955 } else { 956 rtsx_read_register(chip, SD_VP_CTL, &val); 957 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); 958 rtsx_read_register(chip, SD_DCMPS_CTL, &val); 959 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); 960 961 if (ddr_rx) { 962 retval = rtsx_write_register(chip, SD_VP_CTL, 963 PHASE_CHANGE, 964 PHASE_CHANGE); 965 if (retval) { 966 rtsx_trace(chip); 967 return retval; 968 } 969 udelay(50); 970 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, 971 PHASE_CHANGE | PHASE_NOT_RESET | sample_point); 972 if (retval) { 973 rtsx_trace(chip); 974 return retval; 975 } 976 } else { 977 retval = rtsx_write_register(chip, CLK_CTL, 978 CHANGE_CLK, CHANGE_CLK); 979 if (retval) { 980 rtsx_trace(chip); 981 return retval; 982 } 983 udelay(50); 984 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF, 985 PHASE_NOT_RESET | sample_point); 986 if (retval) { 987 rtsx_trace(chip); 988 return retval; 989 } 990 } 991 udelay(100); 992 993 rtsx_init_cmd(chip); 994 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE, 995 DCMPS_CHANGE); 996 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL, 997 DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE); 998 retval = rtsx_send_cmd(chip, SD_CARD, 100); 999 if (retval != STATUS_SUCCESS) { 1000 rtsx_trace(chip); 1001 goto Fail; 1002 } 1003 1004 val = *rtsx_get_cmd_data(chip); 1005 if (val & DCMPS_ERROR) { 1006 rtsx_trace(chip); 1007 goto Fail; 1008 } 1009 1010 if ((val & DCMPS_CURRENT_PHASE) != sample_point) { 1011 rtsx_trace(chip); 1012 goto Fail; 1013 } 1014 1015 retval = rtsx_write_register(chip, SD_DCMPS_CTL, 1016 DCMPS_CHANGE, 0); 1017 if (retval) { 1018 rtsx_trace(chip); 1019 return retval; 1020 } 1021 if (ddr_rx) { 1022 retval = rtsx_write_register(chip, SD_VP_CTL, 1023 PHASE_CHANGE, 0); 1024 if (retval) { 1025 rtsx_trace(chip); 1026 return retval; 1027 } 1028 } else { 1029 retval = rtsx_write_register(chip, CLK_CTL, 1030 CHANGE_CLK, 0); 1031 if (retval) { 1032 rtsx_trace(chip); 1033 return retval; 1034 } 1035 } 1036 1037 udelay(50); 1038 } 1039 1040 retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 1041 if (retval) { 1042 rtsx_trace(chip); 1043 return retval; 1044 } 1045 1046 return STATUS_SUCCESS; 1047 1048 Fail: 1049 rtsx_read_register(chip, SD_VP_CTL, &val); 1050 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val); 1051 rtsx_read_register(chip, SD_DCMPS_CTL, &val); 1052 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val); 1053 1054 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0); 1055 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0); 1056 wait_timeout(10); 1057 sd_reset_dcm(chip, tune_dir); 1058 return STATUS_FAIL; 1059 } 1060 1061 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width) 1062 { 1063 struct sd_info *sd_card = &(chip->sd_card); 1064 int retval; 1065 u8 cmd[5], buf[8]; 1066 1067 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 1068 SD_RSP_TYPE_R1, NULL, 0); 1069 if (retval != STATUS_SUCCESS) { 1070 rtsx_trace(chip); 1071 return STATUS_FAIL; 1072 } 1073 1074 cmd[0] = 0x40 | SEND_SCR; 1075 cmd[1] = 0; 1076 cmd[2] = 0; 1077 cmd[3] = 0; 1078 cmd[4] = 0; 1079 1080 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width, 1081 buf, 8, 250); 1082 if (retval != STATUS_SUCCESS) { 1083 rtsx_clear_sd_error(chip); 1084 rtsx_trace(chip); 1085 return STATUS_FAIL; 1086 } 1087 1088 memcpy(sd_card->raw_scr, buf, 8); 1089 1090 if ((buf[0] & 0x0F) == 0) { 1091 rtsx_trace(chip); 1092 return STATUS_FAIL; 1093 } 1094 1095 return STATUS_SUCCESS; 1096 } 1097 1098 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group, 1099 u8 func_to_switch, u8 *buf, int buf_len) 1100 { 1101 u8 support_mask = 0, query_switch = 0, switch_busy = 0; 1102 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0; 1103 1104 if (func_group == SD_FUNC_GROUP_1) { 1105 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET; 1106 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET; 1107 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET; 1108 1109 switch (func_to_switch) { 1110 case HS_SUPPORT: 1111 support_mask = HS_SUPPORT_MASK; 1112 query_switch = HS_QUERY_SWITCH_OK; 1113 switch_busy = HS_SWITCH_BUSY; 1114 break; 1115 1116 case SDR50_SUPPORT: 1117 support_mask = SDR50_SUPPORT_MASK; 1118 query_switch = SDR50_QUERY_SWITCH_OK; 1119 switch_busy = SDR50_SWITCH_BUSY; 1120 break; 1121 1122 case SDR104_SUPPORT: 1123 support_mask = SDR104_SUPPORT_MASK; 1124 query_switch = SDR104_QUERY_SWITCH_OK; 1125 switch_busy = SDR104_SWITCH_BUSY; 1126 break; 1127 1128 case DDR50_SUPPORT: 1129 support_mask = DDR50_SUPPORT_MASK; 1130 query_switch = DDR50_QUERY_SWITCH_OK; 1131 switch_busy = DDR50_SWITCH_BUSY; 1132 break; 1133 1134 default: 1135 rtsx_trace(chip); 1136 return STATUS_FAIL; 1137 } 1138 } else if (func_group == SD_FUNC_GROUP_3) { 1139 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET; 1140 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET; 1141 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET; 1142 1143 switch (func_to_switch) { 1144 case DRIVING_TYPE_A: 1145 support_mask = DRIVING_TYPE_A_MASK; 1146 query_switch = TYPE_A_QUERY_SWITCH_OK; 1147 switch_busy = TYPE_A_SWITCH_BUSY; 1148 break; 1149 1150 case DRIVING_TYPE_C: 1151 support_mask = DRIVING_TYPE_C_MASK; 1152 query_switch = TYPE_C_QUERY_SWITCH_OK; 1153 switch_busy = TYPE_C_SWITCH_BUSY; 1154 break; 1155 1156 case DRIVING_TYPE_D: 1157 support_mask = DRIVING_TYPE_D_MASK; 1158 query_switch = TYPE_D_QUERY_SWITCH_OK; 1159 switch_busy = TYPE_D_SWITCH_BUSY; 1160 break; 1161 1162 default: 1163 rtsx_trace(chip); 1164 return STATUS_FAIL; 1165 } 1166 } else if (func_group == SD_FUNC_GROUP_4) { 1167 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET; 1168 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET; 1169 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET; 1170 1171 switch (func_to_switch) { 1172 case CURRENT_LIMIT_400: 1173 support_mask = CURRENT_LIMIT_400_MASK; 1174 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK; 1175 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY; 1176 break; 1177 1178 case CURRENT_LIMIT_600: 1179 support_mask = CURRENT_LIMIT_600_MASK; 1180 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK; 1181 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY; 1182 break; 1183 1184 case CURRENT_LIMIT_800: 1185 support_mask = CURRENT_LIMIT_800_MASK; 1186 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK; 1187 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY; 1188 break; 1189 1190 default: 1191 rtsx_trace(chip); 1192 return STATUS_FAIL; 1193 } 1194 } else { 1195 rtsx_trace(chip); 1196 return STATUS_FAIL; 1197 } 1198 1199 if (func_group == SD_FUNC_GROUP_1) { 1200 if (!(buf[support_offset] & support_mask) || 1201 ((buf[query_switch_offset] & 0x0F) != query_switch)) { 1202 rtsx_trace(chip); 1203 return STATUS_FAIL; 1204 } 1205 } 1206 1207 /* Check 'Busy Status' */ 1208 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) && 1209 ((buf[check_busy_offset] & switch_busy) == switch_busy)) { 1210 rtsx_trace(chip); 1211 return STATUS_FAIL; 1212 } 1213 1214 return STATUS_SUCCESS; 1215 } 1216 1217 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, 1218 u8 func_group, u8 func_to_switch, u8 bus_width) 1219 { 1220 struct sd_info *sd_card = &(chip->sd_card); 1221 int retval; 1222 u8 cmd[5], buf[64]; 1223 1224 dev_dbg(rtsx_dev(chip), "sd_check_switch_mode (mode = %d, func_group = %d, func_to_switch = %d)\n", 1225 mode, func_group, func_to_switch); 1226 1227 cmd[0] = 0x40 | SWITCH; 1228 cmd[1] = mode; 1229 1230 if (func_group == SD_FUNC_GROUP_1) { 1231 cmd[2] = 0xFF; 1232 cmd[3] = 0xFF; 1233 cmd[4] = 0xF0 + func_to_switch; 1234 } else if (func_group == SD_FUNC_GROUP_3) { 1235 cmd[2] = 0xFF; 1236 cmd[3] = 0xF0 + func_to_switch; 1237 cmd[4] = 0xFF; 1238 } else if (func_group == SD_FUNC_GROUP_4) { 1239 cmd[2] = 0xFF; 1240 cmd[3] = 0x0F + (func_to_switch << 4); 1241 cmd[4] = 0xFF; 1242 } else { 1243 cmd[1] = SD_CHECK_MODE; 1244 cmd[2] = 0xFF; 1245 cmd[3] = 0xFF; 1246 cmd[4] = 0xFF; 1247 } 1248 1249 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width, 1250 buf, 64, 250); 1251 if (retval != STATUS_SUCCESS) { 1252 rtsx_clear_sd_error(chip); 1253 rtsx_trace(chip); 1254 return STATUS_FAIL; 1255 } 1256 1257 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf); 1258 1259 if (func_group == NO_ARGUMENT) { 1260 sd_card->func_group1_mask = buf[0x0D]; 1261 sd_card->func_group2_mask = buf[0x0B]; 1262 sd_card->func_group3_mask = buf[0x09]; 1263 sd_card->func_group4_mask = buf[0x07]; 1264 1265 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n", 1266 buf[0x0D]); 1267 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n", 1268 buf[0x0B]); 1269 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n", 1270 buf[0x09]); 1271 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n", 1272 buf[0x07]); 1273 } else { 1274 /* Maximum current consumption, check whether current is 1275 * acceptable; bit[511:496] = 0x0000 means some error happened. 1276 */ 1277 u16 cc = ((u16)buf[0] << 8) | buf[1]; 1278 1279 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n", 1280 cc); 1281 if ((cc == 0) || (cc > 800)) { 1282 rtsx_trace(chip); 1283 return STATUS_FAIL; 1284 } 1285 1286 retval = sd_query_switch_result(chip, func_group, 1287 func_to_switch, buf, 64); 1288 if (retval != STATUS_SUCCESS) { 1289 rtsx_trace(chip); 1290 return STATUS_FAIL; 1291 } 1292 1293 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) { 1294 retval = rtsx_write_register(chip, OCPPARA2, 1295 SD_OCP_THD_MASK, 1296 chip->sd_800mA_ocp_thd); 1297 if (retval) { 1298 rtsx_trace(chip); 1299 return retval; 1300 } 1301 retval = rtsx_write_register(chip, CARD_PWR_CTL, 1302 PMOS_STRG_MASK, 1303 PMOS_STRG_800mA); 1304 if (retval) { 1305 rtsx_trace(chip); 1306 return retval; 1307 } 1308 } 1309 } 1310 1311 return STATUS_SUCCESS; 1312 } 1313 1314 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch) 1315 { 1316 if (func_group == SD_FUNC_GROUP_1) { 1317 if (func_to_switch > HS_SUPPORT) 1318 func_to_switch--; 1319 1320 } else if (func_group == SD_FUNC_GROUP_4) { 1321 if (func_to_switch > CURRENT_LIMIT_200) 1322 func_to_switch--; 1323 } 1324 1325 return func_to_switch; 1326 } 1327 1328 static int sd_check_switch(struct rtsx_chip *chip, 1329 u8 func_group, u8 func_to_switch, u8 bus_width) 1330 { 1331 int retval; 1332 int i; 1333 bool switch_good = false; 1334 1335 for (i = 0; i < 3; i++) { 1336 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1337 sd_set_err_code(chip, SD_NO_CARD); 1338 rtsx_trace(chip); 1339 return STATUS_FAIL; 1340 } 1341 1342 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group, 1343 func_to_switch, bus_width); 1344 if (retval == STATUS_SUCCESS) { 1345 u8 stat; 1346 1347 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE, 1348 func_group, func_to_switch, bus_width); 1349 if (retval == STATUS_SUCCESS) { 1350 switch_good = true; 1351 break; 1352 } 1353 1354 retval = rtsx_read_register(chip, SD_STAT1, &stat); 1355 if (retval) { 1356 rtsx_trace(chip); 1357 return retval; 1358 } 1359 if (stat & SD_CRC16_ERR) { 1360 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n"); 1361 rtsx_trace(chip); 1362 return STATUS_FAIL; 1363 } 1364 } 1365 1366 func_to_switch = downgrade_switch_mode(func_group, 1367 func_to_switch); 1368 1369 wait_timeout(20); 1370 } 1371 1372 if (!switch_good) { 1373 rtsx_trace(chip); 1374 return STATUS_FAIL; 1375 } 1376 1377 return STATUS_SUCCESS; 1378 } 1379 1380 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width) 1381 { 1382 struct sd_info *sd_card = &(chip->sd_card); 1383 int retval; 1384 int i; 1385 u8 func_to_switch = 0; 1386 1387 /* Get supported functions */ 1388 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, 1389 NO_ARGUMENT, NO_ARGUMENT, bus_width); 1390 if (retval != STATUS_SUCCESS) { 1391 rtsx_trace(chip); 1392 return STATUS_FAIL; 1393 } 1394 1395 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail); 1396 1397 /* Function Group 1: Access Mode */ 1398 for (i = 0; i < 4; i++) { 1399 switch ((u8)(chip->sd_speed_prior >> (i*8))) { 1400 case SDR104_SUPPORT: 1401 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) 1402 && chip->sdr104_en) { 1403 func_to_switch = SDR104_SUPPORT; 1404 } 1405 break; 1406 1407 case DDR50_SUPPORT: 1408 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) 1409 && chip->ddr50_en) { 1410 func_to_switch = DDR50_SUPPORT; 1411 } 1412 break; 1413 1414 case SDR50_SUPPORT: 1415 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) 1416 && chip->sdr50_en) { 1417 func_to_switch = SDR50_SUPPORT; 1418 } 1419 break; 1420 1421 case HS_SUPPORT: 1422 if (sd_card->func_group1_mask & HS_SUPPORT_MASK) 1423 func_to_switch = HS_SUPPORT; 1424 1425 break; 1426 1427 default: 1428 continue; 1429 } 1430 1431 1432 if (func_to_switch) 1433 break; 1434 1435 } 1436 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x", 1437 func_to_switch); 1438 1439 #ifdef SUPPORT_SD_LOCK 1440 if ((sd_card->sd_lock_status & SD_SDR_RST) 1441 && (DDR50_SUPPORT == func_to_switch) 1442 && (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) { 1443 func_to_switch = SDR50_SUPPORT; 1444 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n"); 1445 } 1446 #endif 1447 1448 if (func_to_switch) { 1449 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch, 1450 bus_width); 1451 if (retval != STATUS_SUCCESS) { 1452 if (func_to_switch == SDR104_SUPPORT) { 1453 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK; 1454 } else if (func_to_switch == DDR50_SUPPORT) { 1455 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 1456 DDR50_SUPPORT_MASK; 1457 } else if (func_to_switch == SDR50_SUPPORT) { 1458 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 1459 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; 1460 } 1461 rtsx_trace(chip); 1462 return STATUS_FAIL; 1463 } 1464 1465 if (func_to_switch == SDR104_SUPPORT) 1466 SET_SD_SDR104(sd_card); 1467 else if (func_to_switch == DDR50_SUPPORT) 1468 SET_SD_DDR50(sd_card); 1469 else if (func_to_switch == SDR50_SUPPORT) 1470 SET_SD_SDR50(sd_card); 1471 else 1472 SET_SD_HS(sd_card); 1473 } 1474 1475 if (CHK_SD_DDR50(sd_card)) { 1476 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 1477 0x04); 1478 if (retval) { 1479 rtsx_trace(chip); 1480 return retval; 1481 } 1482 retval = sd_set_sample_push_timing(chip); 1483 if (retval != STATUS_SUCCESS) { 1484 rtsx_trace(chip); 1485 return STATUS_FAIL; 1486 } 1487 } 1488 1489 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) { 1490 /* Do not try to switch current limit if the card doesn't 1491 * support UHS mode or we don't want it to support UHS mode 1492 */ 1493 return STATUS_SUCCESS; 1494 } 1495 1496 /* Function Group 4: Current Limit */ 1497 func_to_switch = 0xFF; 1498 1499 for (i = 0; i < 4; i++) { 1500 switch ((u8)(chip->sd_current_prior >> (i*8))) { 1501 case CURRENT_LIMIT_800: 1502 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK) 1503 func_to_switch = CURRENT_LIMIT_800; 1504 1505 break; 1506 1507 case CURRENT_LIMIT_600: 1508 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK) 1509 func_to_switch = CURRENT_LIMIT_600; 1510 1511 break; 1512 1513 case CURRENT_LIMIT_400: 1514 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK) 1515 func_to_switch = CURRENT_LIMIT_400; 1516 1517 break; 1518 1519 case CURRENT_LIMIT_200: 1520 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK) 1521 func_to_switch = CURRENT_LIMIT_200; 1522 1523 break; 1524 1525 default: 1526 continue; 1527 } 1528 1529 if (func_to_switch != 0xFF) 1530 break; 1531 } 1532 1533 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x", 1534 func_to_switch); 1535 1536 if (func_to_switch <= CURRENT_LIMIT_800) { 1537 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch, 1538 bus_width); 1539 if (retval != STATUS_SUCCESS) { 1540 if (sd_check_err_code(chip, SD_NO_CARD)) { 1541 rtsx_trace(chip); 1542 return STATUS_FAIL; 1543 } 1544 } 1545 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n", 1546 retval); 1547 } 1548 1549 if (CHK_SD_DDR50(sd_card)) { 1550 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0); 1551 if (retval) { 1552 rtsx_trace(chip); 1553 return retval; 1554 } 1555 } 1556 1557 return STATUS_SUCCESS; 1558 } 1559 1560 static int sd_wait_data_idle(struct rtsx_chip *chip) 1561 { 1562 int retval = STATUS_TIMEDOUT; 1563 int i; 1564 u8 val = 0; 1565 1566 for (i = 0; i < 100; i++) { 1567 retval = rtsx_read_register(chip, SD_DATA_STATE, &val); 1568 if (retval) { 1569 rtsx_trace(chip); 1570 return retval; 1571 } 1572 if (val & SD_DATA_IDLE) { 1573 retval = STATUS_SUCCESS; 1574 break; 1575 } 1576 udelay(100); 1577 } 1578 dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val); 1579 1580 return retval; 1581 } 1582 1583 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1584 { 1585 int retval; 1586 u8 cmd[5]; 1587 1588 retval = sd_change_phase(chip, sample_point, TUNE_RX); 1589 if (retval != STATUS_SUCCESS) { 1590 rtsx_trace(chip); 1591 return STATUS_FAIL; 1592 } 1593 1594 cmd[0] = 0x40 | SEND_TUNING_PATTERN; 1595 cmd[1] = 0; 1596 cmd[2] = 0; 1597 cmd[3] = 0; 1598 cmd[4] = 0; 1599 1600 retval = sd_read_data(chip, SD_TM_AUTO_TUNING, 1601 cmd, 5, 0x40, 1, SD_BUS_WIDTH_4, NULL, 0, 100); 1602 if (retval != STATUS_SUCCESS) { 1603 (void)sd_wait_data_idle(chip); 1604 1605 rtsx_clear_sd_error(chip); 1606 rtsx_trace(chip); 1607 return STATUS_FAIL; 1608 } 1609 1610 return STATUS_SUCCESS; 1611 } 1612 1613 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1614 { 1615 struct sd_info *sd_card = &(chip->sd_card); 1616 int retval; 1617 u8 cmd[5]; 1618 1619 retval = sd_change_phase(chip, sample_point, TUNE_RX); 1620 if (retval != STATUS_SUCCESS) { 1621 rtsx_trace(chip); 1622 return STATUS_FAIL; 1623 } 1624 1625 dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n"); 1626 1627 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 1628 SD_RSP_TYPE_R1, NULL, 0); 1629 if (retval != STATUS_SUCCESS) { 1630 rtsx_trace(chip); 1631 return STATUS_FAIL; 1632 } 1633 1634 cmd[0] = 0x40 | SD_STATUS; 1635 cmd[1] = 0; 1636 cmd[2] = 0; 1637 cmd[3] = 0; 1638 cmd[4] = 0; 1639 1640 retval = sd_read_data(chip, SD_TM_NORMAL_READ, 1641 cmd, 5, 64, 1, SD_BUS_WIDTH_4, NULL, 0, 100); 1642 if (retval != STATUS_SUCCESS) { 1643 (void)sd_wait_data_idle(chip); 1644 1645 rtsx_clear_sd_error(chip); 1646 rtsx_trace(chip); 1647 return STATUS_FAIL; 1648 } 1649 1650 return STATUS_SUCCESS; 1651 } 1652 1653 static int mmc_ddr_tunning_rx_cmd(struct rtsx_chip *chip, u8 sample_point) 1654 { 1655 struct sd_info *sd_card = &(chip->sd_card); 1656 int retval; 1657 u8 cmd[5], bus_width; 1658 1659 if (CHK_MMC_8BIT(sd_card)) 1660 bus_width = SD_BUS_WIDTH_8; 1661 else if (CHK_MMC_4BIT(sd_card)) 1662 bus_width = SD_BUS_WIDTH_4; 1663 else 1664 bus_width = SD_BUS_WIDTH_1; 1665 1666 retval = sd_change_phase(chip, sample_point, TUNE_RX); 1667 if (retval != STATUS_SUCCESS) { 1668 rtsx_trace(chip); 1669 return STATUS_FAIL; 1670 } 1671 1672 dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n"); 1673 1674 cmd[0] = 0x40 | SEND_EXT_CSD; 1675 cmd[1] = 0; 1676 cmd[2] = 0; 1677 cmd[3] = 0; 1678 cmd[4] = 0; 1679 1680 retval = sd_read_data(chip, SD_TM_NORMAL_READ, 1681 cmd, 5, 0x200, 1, bus_width, NULL, 0, 100); 1682 if (retval != STATUS_SUCCESS) { 1683 (void)sd_wait_data_idle(chip); 1684 1685 rtsx_clear_sd_error(chip); 1686 rtsx_trace(chip); 1687 return STATUS_FAIL; 1688 } 1689 1690 return STATUS_SUCCESS; 1691 } 1692 1693 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) 1694 { 1695 struct sd_info *sd_card = &(chip->sd_card); 1696 int retval; 1697 1698 retval = sd_change_phase(chip, sample_point, TUNE_TX); 1699 if (retval != STATUS_SUCCESS) { 1700 rtsx_trace(chip); 1701 return STATUS_FAIL; 1702 } 1703 1704 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1705 SD_RSP_80CLK_TIMEOUT_EN); 1706 if (retval) { 1707 rtsx_trace(chip); 1708 return retval; 1709 } 1710 1711 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 1712 SD_RSP_TYPE_R1, NULL, 0); 1713 if (retval != STATUS_SUCCESS) { 1714 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) { 1715 rtsx_write_register(chip, SD_CFG3, 1716 SD_RSP_80CLK_TIMEOUT_EN, 0); 1717 rtsx_trace(chip); 1718 return STATUS_FAIL; 1719 } 1720 } 1721 1722 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1723 0); 1724 if (retval) { 1725 rtsx_trace(chip); 1726 return retval; 1727 } 1728 1729 return STATUS_SUCCESS; 1730 } 1731 1732 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point) 1733 { 1734 struct sd_info *sd_card = &(chip->sd_card); 1735 int retval; 1736 u8 cmd[5], bus_width; 1737 1738 retval = sd_change_phase(chip, sample_point, TUNE_TX); 1739 if (retval != STATUS_SUCCESS) { 1740 rtsx_trace(chip); 1741 return STATUS_FAIL; 1742 } 1743 1744 if (CHK_SD(sd_card)) { 1745 bus_width = SD_BUS_WIDTH_4; 1746 } else { 1747 if (CHK_MMC_8BIT(sd_card)) 1748 bus_width = SD_BUS_WIDTH_8; 1749 else if (CHK_MMC_4BIT(sd_card)) 1750 bus_width = SD_BUS_WIDTH_4; 1751 else 1752 bus_width = SD_BUS_WIDTH_1; 1753 } 1754 1755 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 1756 if (retval != STATUS_SUCCESS) { 1757 rtsx_trace(chip); 1758 return STATUS_FAIL; 1759 } 1760 1761 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1762 SD_RSP_80CLK_TIMEOUT_EN); 1763 if (retval) { 1764 rtsx_trace(chip); 1765 return retval; 1766 } 1767 1768 cmd[0] = 0x40 | PROGRAM_CSD; 1769 cmd[1] = 0; 1770 cmd[2] = 0; 1771 cmd[3] = 0; 1772 cmd[4] = 0; 1773 1774 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, 1775 cmd, 5, 16, 1, bus_width, sd_card->raw_csd, 16, 100); 1776 if (retval != STATUS_SUCCESS) { 1777 rtsx_clear_sd_error(chip); 1778 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 1779 rtsx_trace(chip); 1780 return STATUS_FAIL; 1781 } 1782 1783 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1784 0); 1785 if (retval) { 1786 rtsx_trace(chip); 1787 return retval; 1788 } 1789 1790 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1, 1791 NULL, 0); 1792 1793 return STATUS_SUCCESS; 1794 } 1795 1796 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map, 1797 u8 tune_dir) 1798 { 1799 struct sd_info *sd_card = &(chip->sd_card); 1800 struct timing_phase_path path[MAX_PHASE + 1]; 1801 int i, j, cont_path_cnt; 1802 bool new_block; 1803 int max_len, final_path_idx; 1804 u8 final_phase = 0xFF; 1805 1806 if (phase_map == 0xFFFFFFFF) { 1807 if (tune_dir == TUNE_RX) 1808 final_phase = (u8)chip->sd_default_rx_phase; 1809 else 1810 final_phase = (u8)chip->sd_default_tx_phase; 1811 1812 goto Search_Finish; 1813 } 1814 1815 cont_path_cnt = 0; 1816 new_block = true; 1817 j = 0; 1818 for (i = 0; i < MAX_PHASE + 1; i++) { 1819 if (phase_map & (1 << i)) { 1820 if (new_block) { 1821 new_block = false; 1822 j = cont_path_cnt++; 1823 path[j].start = i; 1824 path[j].end = i; 1825 } else { 1826 path[j].end = i; 1827 } 1828 } else { 1829 new_block = true; 1830 if (cont_path_cnt) { 1831 int idx = cont_path_cnt - 1; 1832 1833 path[idx].len = path[idx].end - 1834 path[idx].start + 1; 1835 path[idx].mid = path[idx].start + 1836 path[idx].len / 2; 1837 } 1838 } 1839 } 1840 1841 if (cont_path_cnt == 0) { 1842 dev_dbg(rtsx_dev(chip), "No continuous phase path\n"); 1843 goto Search_Finish; 1844 } else { 1845 int idx = cont_path_cnt - 1; 1846 1847 path[idx].len = path[idx].end - path[idx].start + 1; 1848 path[idx].mid = path[idx].start + path[idx].len / 2; 1849 } 1850 1851 if ((path[0].start == 0) && 1852 (path[cont_path_cnt - 1].end == MAX_PHASE)) { 1853 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1; 1854 path[0].len += path[cont_path_cnt - 1].len; 1855 path[0].mid = path[0].start + path[0].len / 2; 1856 if (path[0].mid < 0) 1857 path[0].mid += MAX_PHASE + 1; 1858 1859 cont_path_cnt--; 1860 } 1861 1862 max_len = 0; 1863 final_phase = 0; 1864 final_path_idx = 0; 1865 for (i = 0; i < cont_path_cnt; i++) { 1866 if (path[i].len > max_len) { 1867 max_len = path[i].len; 1868 final_phase = (u8)path[i].mid; 1869 final_path_idx = i; 1870 } 1871 1872 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n", 1873 i, path[i].start); 1874 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end); 1875 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len); 1876 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid); 1877 dev_dbg(rtsx_dev(chip), "\n"); 1878 } 1879 1880 if (tune_dir == TUNE_TX) { 1881 if (CHK_SD_SDR104(sd_card)) { 1882 if (max_len > 15) { 1883 int temp_mid = (max_len - 16) / 2; 1884 int temp_final_phase = 1885 path[final_path_idx].end - 1886 (max_len - (6 + temp_mid)); 1887 1888 if (temp_final_phase < 0) 1889 final_phase = (u8)(temp_final_phase + 1890 MAX_PHASE + 1); 1891 else 1892 final_phase = (u8)temp_final_phase; 1893 } 1894 } else if (CHK_SD_SDR50(sd_card)) { 1895 if (max_len > 12) { 1896 int temp_mid = (max_len - 13) / 2; 1897 int temp_final_phase = 1898 path[final_path_idx].end - 1899 (max_len - (3 + temp_mid)); 1900 1901 if (temp_final_phase < 0) 1902 final_phase = (u8)(temp_final_phase + 1903 MAX_PHASE + 1); 1904 else 1905 final_phase = (u8)temp_final_phase; 1906 } 1907 } 1908 } 1909 1910 Search_Finish: 1911 dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase); 1912 return final_phase; 1913 } 1914 1915 static int sd_tuning_rx(struct rtsx_chip *chip) 1916 { 1917 struct sd_info *sd_card = &(chip->sd_card); 1918 int retval; 1919 int i, j; 1920 u32 raw_phase_map[3], phase_map; 1921 u8 final_phase; 1922 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); 1923 1924 if (CHK_SD(sd_card)) { 1925 if (CHK_SD_DDR50(sd_card)) 1926 tuning_cmd = sd_ddr_tuning_rx_cmd; 1927 else 1928 tuning_cmd = sd_sdr_tuning_rx_cmd; 1929 1930 } else { 1931 if (CHK_MMC_DDR52(sd_card)) { 1932 tuning_cmd = mmc_ddr_tunning_rx_cmd; 1933 } else { 1934 rtsx_trace(chip); 1935 return STATUS_FAIL; 1936 } 1937 } 1938 1939 for (i = 0; i < 3; i++) { 1940 raw_phase_map[i] = 0; 1941 for (j = MAX_PHASE; j >= 0; j--) { 1942 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1943 sd_set_err_code(chip, SD_NO_CARD); 1944 rtsx_trace(chip); 1945 return STATUS_FAIL; 1946 } 1947 1948 retval = tuning_cmd(chip, (u8)j); 1949 if (retval == STATUS_SUCCESS) 1950 raw_phase_map[i] |= 1 << j; 1951 } 1952 } 1953 1954 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; 1955 for (i = 0; i < 3; i++) 1956 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n", 1957 i, raw_phase_map[i]); 1958 1959 dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map); 1960 1961 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX); 1962 if (final_phase == 0xFF) { 1963 rtsx_trace(chip); 1964 return STATUS_FAIL; 1965 } 1966 1967 retval = sd_change_phase(chip, final_phase, TUNE_RX); 1968 if (retval != STATUS_SUCCESS) { 1969 rtsx_trace(chip); 1970 return STATUS_FAIL; 1971 } 1972 1973 return STATUS_SUCCESS; 1974 } 1975 1976 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip) 1977 { 1978 struct sd_info *sd_card = &(chip->sd_card); 1979 int retval; 1980 int i; 1981 u32 phase_map; 1982 u8 final_phase; 1983 1984 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 1985 SD_RSP_80CLK_TIMEOUT_EN); 1986 if (retval) { 1987 rtsx_trace(chip); 1988 return retval; 1989 } 1990 1991 phase_map = 0; 1992 for (i = MAX_PHASE; i >= 0; i--) { 1993 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 1994 sd_set_err_code(chip, SD_NO_CARD); 1995 rtsx_write_register(chip, SD_CFG3, 1996 SD_RSP_80CLK_TIMEOUT_EN, 0); 1997 rtsx_trace(chip); 1998 return STATUS_FAIL; 1999 } 2000 2001 retval = sd_change_phase(chip, (u8)i, TUNE_TX); 2002 if (retval != STATUS_SUCCESS) 2003 continue; 2004 2005 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 2006 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 2007 0); 2008 if ((retval == STATUS_SUCCESS) || 2009 !sd_check_err_code(chip, SD_RSP_TIMEOUT)) 2010 phase_map |= 1 << i; 2011 } 2012 2013 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 2014 0); 2015 if (retval) { 2016 rtsx_trace(chip); 2017 return retval; 2018 } 2019 2020 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n", 2021 phase_map); 2022 2023 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); 2024 if (final_phase == 0xFF) { 2025 rtsx_trace(chip); 2026 return STATUS_FAIL; 2027 } 2028 2029 retval = sd_change_phase(chip, final_phase, TUNE_TX); 2030 if (retval != STATUS_SUCCESS) { 2031 rtsx_trace(chip); 2032 return STATUS_FAIL; 2033 } 2034 2035 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n", 2036 (int)final_phase); 2037 2038 return STATUS_SUCCESS; 2039 } 2040 2041 static int sd_tuning_tx(struct rtsx_chip *chip) 2042 { 2043 struct sd_info *sd_card = &(chip->sd_card); 2044 int retval; 2045 int i, j; 2046 u32 raw_phase_map[3], phase_map; 2047 u8 final_phase; 2048 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point); 2049 2050 if (CHK_SD(sd_card)) { 2051 if (CHK_SD_DDR50(sd_card)) 2052 tuning_cmd = sd_ddr_tuning_tx_cmd; 2053 else 2054 tuning_cmd = sd_sdr_tuning_tx_cmd; 2055 2056 } else { 2057 if (CHK_MMC_DDR52(sd_card)) { 2058 tuning_cmd = sd_ddr_tuning_tx_cmd; 2059 } else { 2060 rtsx_trace(chip); 2061 return STATUS_FAIL; 2062 } 2063 } 2064 2065 for (i = 0; i < 3; i++) { 2066 raw_phase_map[i] = 0; 2067 for (j = MAX_PHASE; j >= 0; j--) { 2068 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2069 sd_set_err_code(chip, SD_NO_CARD); 2070 rtsx_write_register(chip, SD_CFG3, 2071 SD_RSP_80CLK_TIMEOUT_EN, 0); 2072 rtsx_trace(chip); 2073 return STATUS_FAIL; 2074 } 2075 2076 retval = tuning_cmd(chip, (u8)j); 2077 if (retval == STATUS_SUCCESS) 2078 raw_phase_map[i] |= 1 << j; 2079 } 2080 } 2081 2082 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2]; 2083 for (i = 0; i < 3; i++) 2084 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n", 2085 i, raw_phase_map[i]); 2086 2087 dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map); 2088 2089 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX); 2090 if (final_phase == 0xFF) { 2091 rtsx_trace(chip); 2092 return STATUS_FAIL; 2093 } 2094 2095 retval = sd_change_phase(chip, final_phase, TUNE_TX); 2096 if (retval != STATUS_SUCCESS) { 2097 rtsx_trace(chip); 2098 return STATUS_FAIL; 2099 } 2100 2101 return STATUS_SUCCESS; 2102 } 2103 2104 static int sd_sdr_tuning(struct rtsx_chip *chip) 2105 { 2106 int retval; 2107 2108 retval = sd_tuning_tx(chip); 2109 if (retval != STATUS_SUCCESS) { 2110 rtsx_trace(chip); 2111 return STATUS_FAIL; 2112 } 2113 2114 retval = sd_tuning_rx(chip); 2115 if (retval != STATUS_SUCCESS) { 2116 rtsx_trace(chip); 2117 return STATUS_FAIL; 2118 } 2119 2120 return STATUS_SUCCESS; 2121 } 2122 2123 static int sd_ddr_tuning(struct rtsx_chip *chip) 2124 { 2125 int retval; 2126 2127 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { 2128 retval = sd_ddr_pre_tuning_tx(chip); 2129 if (retval != STATUS_SUCCESS) { 2130 rtsx_trace(chip); 2131 return STATUS_FAIL; 2132 } 2133 } else { 2134 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase, 2135 TUNE_TX); 2136 if (retval != STATUS_SUCCESS) { 2137 rtsx_trace(chip); 2138 return STATUS_FAIL; 2139 } 2140 } 2141 2142 retval = sd_tuning_rx(chip); 2143 if (retval != STATUS_SUCCESS) { 2144 rtsx_trace(chip); 2145 return STATUS_FAIL; 2146 } 2147 2148 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) { 2149 retval = sd_tuning_tx(chip); 2150 if (retval != STATUS_SUCCESS) { 2151 rtsx_trace(chip); 2152 return STATUS_FAIL; 2153 } 2154 } 2155 2156 return STATUS_SUCCESS; 2157 } 2158 2159 static int mmc_ddr_tuning(struct rtsx_chip *chip) 2160 { 2161 int retval; 2162 2163 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { 2164 retval = sd_ddr_pre_tuning_tx(chip); 2165 if (retval != STATUS_SUCCESS) { 2166 rtsx_trace(chip); 2167 return STATUS_FAIL; 2168 } 2169 } else { 2170 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase, 2171 TUNE_TX); 2172 if (retval != STATUS_SUCCESS) { 2173 rtsx_trace(chip); 2174 return STATUS_FAIL; 2175 } 2176 } 2177 2178 retval = sd_tuning_rx(chip); 2179 if (retval != STATUS_SUCCESS) { 2180 rtsx_trace(chip); 2181 return STATUS_FAIL; 2182 } 2183 2184 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) { 2185 retval = sd_tuning_tx(chip); 2186 if (retval != STATUS_SUCCESS) { 2187 rtsx_trace(chip); 2188 return STATUS_FAIL; 2189 } 2190 } 2191 2192 return STATUS_SUCCESS; 2193 } 2194 2195 int sd_switch_clock(struct rtsx_chip *chip) 2196 { 2197 struct sd_info *sd_card = &(chip->sd_card); 2198 int retval; 2199 int re_tuning = 0; 2200 2201 retval = select_card(chip, SD_CARD); 2202 if (retval != STATUS_SUCCESS) { 2203 rtsx_trace(chip); 2204 return STATUS_FAIL; 2205 } 2206 2207 retval = switch_clock(chip, sd_card->sd_clock); 2208 if (retval != STATUS_SUCCESS) { 2209 rtsx_trace(chip); 2210 return STATUS_FAIL; 2211 } 2212 2213 if (re_tuning) { 2214 if (CHK_SD(sd_card)) { 2215 if (CHK_SD_DDR50(sd_card)) 2216 retval = sd_ddr_tuning(chip); 2217 else 2218 retval = sd_sdr_tuning(chip); 2219 } else { 2220 if (CHK_MMC_DDR52(sd_card)) 2221 retval = mmc_ddr_tuning(chip); 2222 } 2223 2224 if (retval != STATUS_SUCCESS) { 2225 rtsx_trace(chip); 2226 return STATUS_FAIL; 2227 } 2228 } 2229 2230 return STATUS_SUCCESS; 2231 } 2232 2233 static int sd_prepare_reset(struct rtsx_chip *chip) 2234 { 2235 struct sd_info *sd_card = &(chip->sd_card); 2236 int retval; 2237 2238 if (chip->asic_code) 2239 sd_card->sd_clock = 29; 2240 else 2241 sd_card->sd_clock = CLK_30; 2242 2243 sd_card->sd_type = 0; 2244 sd_card->seq_mode = 0; 2245 sd_card->sd_data_buf_ready = 0; 2246 sd_card->capacity = 0; 2247 2248 #ifdef SUPPORT_SD_LOCK 2249 sd_card->sd_lock_status = 0; 2250 sd_card->sd_erase_status = 0; 2251 #endif 2252 2253 chip->capacity[chip->card2lun[SD_CARD]] = 0; 2254 chip->sd_io = 0; 2255 2256 retval = sd_set_init_para(chip); 2257 if (retval != STATUS_SUCCESS) { 2258 rtsx_trace(chip); 2259 return retval; 2260 } 2261 2262 retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40); 2263 if (retval) { 2264 rtsx_trace(chip); 2265 return retval; 2266 } 2267 2268 retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 2269 SD_STOP | SD_CLR_ERR); 2270 if (retval) { 2271 rtsx_trace(chip); 2272 return retval; 2273 } 2274 2275 retval = select_card(chip, SD_CARD); 2276 if (retval != STATUS_SUCCESS) { 2277 rtsx_trace(chip); 2278 return STATUS_FAIL; 2279 } 2280 2281 return STATUS_SUCCESS; 2282 } 2283 2284 static int sd_pull_ctl_disable(struct rtsx_chip *chip) 2285 { 2286 int retval; 2287 2288 if (CHECK_PID(chip, 0x5208)) { 2289 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 2290 XD_D3_PD | SD_D7_PD | SD_CLK_PD | SD_D5_PD); 2291 if (retval) { 2292 rtsx_trace(chip); 2293 return retval; 2294 } 2295 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 2296 SD_D6_PD | SD_D0_PD | SD_D1_PD | XD_D5_PD); 2297 if (retval) { 2298 rtsx_trace(chip); 2299 return retval; 2300 } 2301 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 2302 SD_D4_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 2303 if (retval) { 2304 rtsx_trace(chip); 2305 return retval; 2306 } 2307 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 2308 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 2309 if (retval) { 2310 rtsx_trace(chip); 2311 return retval; 2312 } 2313 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 2314 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 2315 if (retval) { 2316 rtsx_trace(chip); 2317 return retval; 2318 } 2319 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 2320 MS_D5_PD | MS_D4_PD); 2321 if (retval) { 2322 rtsx_trace(chip); 2323 return retval; 2324 } 2325 } else if (CHECK_PID(chip, 0x5288)) { 2326 if (CHECK_BARO_PKG(chip, QFN)) { 2327 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 2328 0xFF, 0x55); 2329 if (retval) { 2330 rtsx_trace(chip); 2331 return retval; 2332 } 2333 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 2334 0xFF, 0x55); 2335 if (retval) { 2336 rtsx_trace(chip); 2337 return retval; 2338 } 2339 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 2340 0xFF, 0x4B); 2341 if (retval) { 2342 rtsx_trace(chip); 2343 return retval; 2344 } 2345 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 2346 0xFF, 0x69); 2347 if (retval) { 2348 rtsx_trace(chip); 2349 return retval; 2350 } 2351 } 2352 } 2353 2354 return STATUS_SUCCESS; 2355 } 2356 2357 int sd_pull_ctl_enable(struct rtsx_chip *chip) 2358 { 2359 int retval; 2360 2361 rtsx_init_cmd(chip); 2362 2363 if (CHECK_PID(chip, 0x5208)) { 2364 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 2365 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU); 2366 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 2367 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD); 2368 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 2369 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 2370 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 2371 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD); 2372 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 2373 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU); 2374 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 2375 MS_D5_PD | MS_D4_PD); 2376 } else if (CHECK_PID(chip, 0x5288)) { 2377 if (CHECK_BARO_PKG(chip, QFN)) { 2378 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 2379 0xA8); 2380 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 2381 0x5A); 2382 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 2383 0x95); 2384 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 2385 0xAA); 2386 } 2387 } 2388 2389 retval = rtsx_send_cmd(chip, SD_CARD, 100); 2390 if (retval < 0) { 2391 rtsx_trace(chip); 2392 return STATUS_FAIL; 2393 } 2394 2395 return STATUS_SUCCESS; 2396 } 2397 2398 static int sd_init_power(struct rtsx_chip *chip) 2399 { 2400 int retval; 2401 2402 retval = sd_power_off_card3v3(chip); 2403 if (retval != STATUS_SUCCESS) { 2404 rtsx_trace(chip); 2405 return STATUS_FAIL; 2406 } 2407 2408 if (!chip->ft2_fast_mode) 2409 wait_timeout(250); 2410 2411 retval = enable_card_clock(chip, SD_CARD); 2412 if (retval != STATUS_SUCCESS) { 2413 rtsx_trace(chip); 2414 return STATUS_FAIL; 2415 } 2416 2417 if (chip->asic_code) { 2418 retval = sd_pull_ctl_enable(chip); 2419 if (retval != STATUS_SUCCESS) { 2420 rtsx_trace(chip); 2421 return STATUS_FAIL; 2422 } 2423 } else { 2424 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 2425 FPGA_SD_PULL_CTL_BIT | 0x20, 0); 2426 if (retval) { 2427 rtsx_trace(chip); 2428 return retval; 2429 } 2430 } 2431 2432 if (!chip->ft2_fast_mode) { 2433 retval = card_power_on(chip, SD_CARD); 2434 if (retval != STATUS_SUCCESS) { 2435 rtsx_trace(chip); 2436 return STATUS_FAIL; 2437 } 2438 2439 wait_timeout(260); 2440 2441 #ifdef SUPPORT_OCP 2442 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) { 2443 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 2444 chip->ocp_stat); 2445 rtsx_trace(chip); 2446 return STATUS_FAIL; 2447 } 2448 #endif 2449 } 2450 2451 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 2452 SD_OUTPUT_EN); 2453 if (retval) { 2454 rtsx_trace(chip); 2455 return retval; 2456 } 2457 2458 return STATUS_SUCCESS; 2459 } 2460 2461 static int sd_dummy_clock(struct rtsx_chip *chip) 2462 { 2463 int retval; 2464 2465 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01); 2466 if (retval) { 2467 rtsx_trace(chip); 2468 return retval; 2469 } 2470 wait_timeout(5); 2471 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0); 2472 if (retval) { 2473 rtsx_trace(chip); 2474 return retval; 2475 } 2476 2477 return STATUS_SUCCESS; 2478 } 2479 2480 static int sd_read_lba0(struct rtsx_chip *chip) 2481 { 2482 struct sd_info *sd_card = &(chip->sd_card); 2483 int retval; 2484 u8 cmd[5], bus_width; 2485 2486 cmd[0] = 0x40 | READ_SINGLE_BLOCK; 2487 cmd[1] = 0; 2488 cmd[2] = 0; 2489 cmd[3] = 0; 2490 cmd[4] = 0; 2491 2492 if (CHK_SD(sd_card)) { 2493 bus_width = SD_BUS_WIDTH_4; 2494 } else { 2495 if (CHK_MMC_8BIT(sd_card)) 2496 bus_width = SD_BUS_WIDTH_8; 2497 else if (CHK_MMC_4BIT(sd_card)) 2498 bus_width = SD_BUS_WIDTH_4; 2499 else 2500 bus_width = SD_BUS_WIDTH_1; 2501 } 2502 2503 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 2504 5, 512, 1, bus_width, NULL, 0, 100); 2505 if (retval != STATUS_SUCCESS) { 2506 rtsx_clear_sd_error(chip); 2507 rtsx_trace(chip); 2508 return STATUS_FAIL; 2509 } 2510 2511 return STATUS_SUCCESS; 2512 } 2513 2514 static int sd_check_wp_state(struct rtsx_chip *chip) 2515 { 2516 struct sd_info *sd_card = &(chip->sd_card); 2517 int retval; 2518 u32 val; 2519 u16 sd_card_type; 2520 u8 cmd[5], buf[64]; 2521 2522 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 2523 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); 2524 if (retval != STATUS_SUCCESS) { 2525 rtsx_trace(chip); 2526 return STATUS_FAIL; 2527 } 2528 2529 cmd[0] = 0x40 | SD_STATUS; 2530 cmd[1] = 0; 2531 cmd[2] = 0; 2532 cmd[3] = 0; 2533 cmd[4] = 0; 2534 2535 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, 2536 SD_BUS_WIDTH_4, buf, 64, 250); 2537 if (retval != STATUS_SUCCESS) { 2538 rtsx_clear_sd_error(chip); 2539 2540 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2541 SD_RSP_TYPE_R1, NULL, 0); 2542 rtsx_trace(chip); 2543 return STATUS_FAIL; 2544 } 2545 2546 dev_dbg(rtsx_dev(chip), "ACMD13:\n"); 2547 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf); 2548 2549 sd_card_type = ((u16)buf[2] << 8) | buf[3]; 2550 dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type); 2551 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) { 2552 /* ROM card or OTP */ 2553 chip->card_wp |= SD_CARD; 2554 } 2555 2556 /* Check SD Machanical Write-Protect Switch */ 2557 val = rtsx_readl(chip, RTSX_BIPR); 2558 if (val & SD_WRITE_PROTECT) 2559 chip->card_wp |= SD_CARD; 2560 2561 return STATUS_SUCCESS; 2562 } 2563 2564 static int reset_sd(struct rtsx_chip *chip) 2565 { 2566 struct sd_info *sd_card = &(chip->sd_card); 2567 bool hi_cap_flow = false; 2568 int retval, i = 0, j = 0, k = 0; 2569 bool sd_dont_switch = false; 2570 bool support_1v8 = false; 2571 bool try_sdio = true; 2572 u8 rsp[16]; 2573 u8 switch_bus_width; 2574 u32 voltage = 0; 2575 bool sd20_mode = false; 2576 2577 SET_SD(sd_card); 2578 2579 Switch_Fail: 2580 2581 i = 0; 2582 j = 0; 2583 k = 0; 2584 hi_cap_flow = false; 2585 2586 #ifdef SUPPORT_SD_LOCK 2587 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) 2588 goto SD_UNLOCK_ENTRY; 2589 #endif 2590 2591 retval = sd_prepare_reset(chip); 2592 if (retval != STATUS_SUCCESS) { 2593 rtsx_trace(chip); 2594 return STATUS_FAIL; 2595 } 2596 2597 retval = sd_dummy_clock(chip); 2598 if (retval != STATUS_SUCCESS) { 2599 rtsx_trace(chip); 2600 return STATUS_FAIL; 2601 } 2602 2603 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) { 2604 int rty_cnt = 0; 2605 2606 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) { 2607 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2608 sd_set_err_code(chip, SD_NO_CARD); 2609 rtsx_trace(chip); 2610 return STATUS_FAIL; 2611 } 2612 2613 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0, 2614 SD_RSP_TYPE_R4, rsp, 5); 2615 if (retval == STATUS_SUCCESS) { 2616 int func_num = (rsp[1] >> 4) & 0x07; 2617 2618 if (func_num) { 2619 dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n", 2620 func_num); 2621 chip->sd_io = 1; 2622 rtsx_trace(chip); 2623 return STATUS_FAIL; 2624 } 2625 2626 break; 2627 } 2628 2629 sd_init_power(chip); 2630 2631 sd_dummy_clock(chip); 2632 } 2633 2634 dev_dbg(rtsx_dev(chip), "Normal card!\n"); 2635 } 2636 2637 /* Start Initialization Process of SD Card */ 2638 RTY_SD_RST: 2639 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, 2640 NULL, 0); 2641 if (retval != STATUS_SUCCESS) { 2642 rtsx_trace(chip); 2643 return STATUS_FAIL; 2644 } 2645 2646 wait_timeout(20); 2647 2648 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA, 2649 SD_RSP_TYPE_R7, rsp, 5); 2650 if (retval == STATUS_SUCCESS) { 2651 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) { 2652 hi_cap_flow = true; 2653 voltage = SUPPORT_VOLTAGE | 0x40000000; 2654 } 2655 } 2656 2657 if (!hi_cap_flow) { 2658 voltage = SUPPORT_VOLTAGE; 2659 2660 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, 2661 SD_RSP_TYPE_R0, NULL, 0); 2662 if (retval != STATUS_SUCCESS) { 2663 rtsx_trace(chip); 2664 return STATUS_FAIL; 2665 } 2666 2667 wait_timeout(20); 2668 } 2669 2670 do { 2671 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1, 2672 NULL, 0); 2673 if (retval != STATUS_SUCCESS) { 2674 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 2675 sd_set_err_code(chip, SD_NO_CARD); 2676 rtsx_trace(chip); 2677 return STATUS_FAIL; 2678 } 2679 2680 j++; 2681 if (j < 3) { 2682 goto RTY_SD_RST; 2683 } else { 2684 rtsx_trace(chip); 2685 return STATUS_FAIL; 2686 } 2687 } 2688 2689 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage, 2690 SD_RSP_TYPE_R3, rsp, 5); 2691 if (retval != STATUS_SUCCESS) { 2692 k++; 2693 if (k < 3) { 2694 goto RTY_SD_RST; 2695 } else { 2696 rtsx_trace(chip); 2697 return STATUS_FAIL; 2698 } 2699 } 2700 2701 i++; 2702 wait_timeout(20); 2703 } while (!(rsp[1] & 0x80) && (i < 255)); 2704 2705 if (i == 255) { 2706 rtsx_trace(chip); 2707 return STATUS_FAIL; 2708 } 2709 2710 if (hi_cap_flow) { 2711 if (rsp[1] & 0x40) 2712 SET_SD_HCXC(sd_card); 2713 else 2714 CLR_SD_HCXC(sd_card); 2715 2716 support_1v8 = false; 2717 } else { 2718 CLR_SD_HCXC(sd_card); 2719 support_1v8 = false; 2720 } 2721 dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8); 2722 2723 if (support_1v8) { 2724 retval = sd_voltage_switch(chip); 2725 if (retval != STATUS_SUCCESS) { 2726 rtsx_trace(chip); 2727 return STATUS_FAIL; 2728 } 2729 } 2730 2731 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, 2732 NULL, 0); 2733 if (retval != STATUS_SUCCESS) { 2734 rtsx_trace(chip); 2735 return STATUS_FAIL; 2736 } 2737 2738 for (i = 0; i < 3; i++) { 2739 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0, 2740 SD_RSP_TYPE_R6, rsp, 5); 2741 if (retval != STATUS_SUCCESS) { 2742 rtsx_trace(chip); 2743 return STATUS_FAIL; 2744 } 2745 2746 sd_card->sd_addr = (u32)rsp[1] << 24; 2747 sd_card->sd_addr += (u32)rsp[2] << 16; 2748 2749 if (sd_card->sd_addr) 2750 break; 2751 } 2752 2753 retval = sd_check_csd(chip, 1); 2754 if (retval != STATUS_SUCCESS) { 2755 rtsx_trace(chip); 2756 return STATUS_FAIL; 2757 } 2758 2759 retval = sd_select_card(chip, 1); 2760 if (retval != STATUS_SUCCESS) { 2761 rtsx_trace(chip); 2762 return STATUS_FAIL; 2763 } 2764 2765 #ifdef SUPPORT_SD_LOCK 2766 SD_UNLOCK_ENTRY: 2767 retval = sd_update_lock_status(chip); 2768 if (retval != STATUS_SUCCESS) { 2769 rtsx_trace(chip); 2770 return STATUS_FAIL; 2771 } 2772 2773 if (sd_card->sd_lock_status & SD_LOCKED) { 2774 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST); 2775 return STATUS_SUCCESS; 2776 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) { 2777 sd_card->sd_lock_status &= ~SD_PWD_EXIST; 2778 } 2779 #endif 2780 2781 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2782 SD_RSP_TYPE_R1, NULL, 0); 2783 if (retval != STATUS_SUCCESS) { 2784 rtsx_trace(chip); 2785 return STATUS_FAIL; 2786 } 2787 2788 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0, 2789 SD_RSP_TYPE_R1, NULL, 0); 2790 if (retval != STATUS_SUCCESS) { 2791 rtsx_trace(chip); 2792 return STATUS_FAIL; 2793 } 2794 2795 if (support_1v8) { 2796 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2797 SD_RSP_TYPE_R1, NULL, 0); 2798 if (retval != STATUS_SUCCESS) { 2799 rtsx_trace(chip); 2800 return STATUS_FAIL; 2801 } 2802 2803 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, 2804 SD_RSP_TYPE_R1, NULL, 0); 2805 if (retval != STATUS_SUCCESS) { 2806 rtsx_trace(chip); 2807 return STATUS_FAIL; 2808 } 2809 2810 switch_bus_width = SD_BUS_WIDTH_4; 2811 } else { 2812 switch_bus_width = SD_BUS_WIDTH_1; 2813 } 2814 2815 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, 2816 NULL, 0); 2817 if (retval != STATUS_SUCCESS) { 2818 rtsx_trace(chip); 2819 return STATUS_FAIL; 2820 } 2821 2822 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 2823 if (retval != STATUS_SUCCESS) { 2824 rtsx_trace(chip); 2825 return STATUS_FAIL; 2826 } 2827 2828 if (!(sd_card->raw_csd[4] & 0x40)) 2829 sd_dont_switch = true; 2830 2831 if (!sd_dont_switch) { 2832 if (sd20_mode) { 2833 /* Set sd_switch_fail here, because we needn't 2834 * switch to UHS mode 2835 */ 2836 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK | 2837 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK; 2838 } 2839 2840 /* Check the card whether follow SD1.1 spec or higher */ 2841 retval = sd_check_spec(chip, switch_bus_width); 2842 if (retval == STATUS_SUCCESS) { 2843 retval = sd_switch_function(chip, switch_bus_width); 2844 if (retval != STATUS_SUCCESS) { 2845 sd_init_power(chip); 2846 sd_dont_switch = true; 2847 try_sdio = false; 2848 2849 goto Switch_Fail; 2850 } 2851 } else { 2852 if (support_1v8) { 2853 sd_init_power(chip); 2854 sd_dont_switch = true; 2855 try_sdio = false; 2856 2857 goto Switch_Fail; 2858 } 2859 } 2860 } 2861 2862 if (!support_1v8) { 2863 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr, 2864 SD_RSP_TYPE_R1, NULL, 0); 2865 if (retval != STATUS_SUCCESS) { 2866 rtsx_trace(chip); 2867 return STATUS_FAIL; 2868 } 2869 2870 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2, 2871 SD_RSP_TYPE_R1, NULL, 0); 2872 if (retval != STATUS_SUCCESS) { 2873 rtsx_trace(chip); 2874 return STATUS_FAIL; 2875 } 2876 } 2877 2878 #ifdef SUPPORT_SD_LOCK 2879 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 2880 #endif 2881 2882 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) { 2883 int read_lba0 = 1; 2884 2885 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07, 2886 chip->sd30_drive_sel_1v8); 2887 if (retval) { 2888 rtsx_trace(chip); 2889 return retval; 2890 } 2891 2892 retval = sd_set_init_para(chip); 2893 if (retval != STATUS_SUCCESS) { 2894 rtsx_trace(chip); 2895 return STATUS_FAIL; 2896 } 2897 2898 if (CHK_SD_DDR50(sd_card)) 2899 retval = sd_ddr_tuning(chip); 2900 else 2901 retval = sd_sdr_tuning(chip); 2902 2903 if (retval != STATUS_SUCCESS) { 2904 if (sd20_mode) { 2905 rtsx_trace(chip); 2906 return STATUS_FAIL; 2907 } else { 2908 retval = sd_init_power(chip); 2909 if (retval != STATUS_SUCCESS) { 2910 rtsx_trace(chip); 2911 return STATUS_FAIL; 2912 } 2913 2914 try_sdio = false; 2915 sd20_mode = true; 2916 goto Switch_Fail; 2917 } 2918 } 2919 2920 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 2921 SD_RSP_TYPE_R1, NULL, 0); 2922 2923 if (CHK_SD_DDR50(sd_card)) { 2924 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 2925 if (retval != STATUS_SUCCESS) 2926 read_lba0 = 0; 2927 } 2928 2929 if (read_lba0) { 2930 retval = sd_read_lba0(chip); 2931 if (retval != STATUS_SUCCESS) { 2932 if (sd20_mode) { 2933 rtsx_trace(chip); 2934 return STATUS_FAIL; 2935 } else { 2936 retval = sd_init_power(chip); 2937 if (retval != STATUS_SUCCESS) { 2938 rtsx_trace(chip); 2939 return STATUS_FAIL; 2940 } 2941 2942 try_sdio = false; 2943 sd20_mode = true; 2944 goto Switch_Fail; 2945 } 2946 } 2947 } 2948 } 2949 2950 retval = sd_check_wp_state(chip); 2951 if (retval != STATUS_SUCCESS) { 2952 rtsx_trace(chip); 2953 return STATUS_FAIL; 2954 } 2955 2956 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; 2957 2958 #ifdef SUPPORT_SD_LOCK 2959 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { 2960 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, 2961 0x02); 2962 if (retval) { 2963 rtsx_trace(chip); 2964 return retval; 2965 } 2966 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, 2967 0x00); 2968 if (retval) { 2969 rtsx_trace(chip); 2970 return retval; 2971 } 2972 } 2973 #endif 2974 2975 return STATUS_SUCCESS; 2976 } 2977 2978 2979 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width) 2980 { 2981 struct sd_info *sd_card = &(chip->sd_card); 2982 int retval; 2983 u8 buf[8] = {0}, bus_width, *ptr; 2984 u16 byte_cnt; 2985 int len; 2986 2987 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL, 2988 0); 2989 if (retval != STATUS_SUCCESS) { 2990 rtsx_trace(chip); 2991 return SWITCH_FAIL; 2992 } 2993 2994 if (width == MMC_8BIT_BUS) { 2995 buf[0] = 0x55; 2996 buf[1] = 0xAA; 2997 len = 8; 2998 byte_cnt = 8; 2999 bus_width = SD_BUS_WIDTH_8; 3000 } else { 3001 buf[0] = 0x5A; 3002 len = 4; 3003 byte_cnt = 4; 3004 bus_width = SD_BUS_WIDTH_4; 3005 } 3006 3007 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02); 3008 if (retval != STATUS_SUCCESS) { 3009 rtsx_trace(chip); 3010 return SWITCH_ERR; 3011 } 3012 3013 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, 3014 NULL, 0, byte_cnt, 1, bus_width, buf, len, 100); 3015 if (retval != STATUS_SUCCESS) { 3016 rtsx_clear_sd_error(chip); 3017 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); 3018 rtsx_trace(chip); 3019 return SWITCH_ERR; 3020 } 3021 3022 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0); 3023 if (retval != STATUS_SUCCESS) { 3024 rtsx_trace(chip); 3025 return SWITCH_ERR; 3026 } 3027 3028 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R); 3029 3030 rtsx_init_cmd(chip); 3031 3032 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R); 3033 3034 if (width == MMC_8BIT_BUS) 3035 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 3036 0xFF, 0x08); 3037 else 3038 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 3039 0xFF, 0x04); 3040 3041 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); 3042 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); 3043 3044 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3045 SD_CALCULATE_CRC7 | SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| 3046 SD_CHECK_CRC7 | SD_RSP_LEN_6); 3047 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 3048 PINGPONG_BUFFER); 3049 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3050 SD_TM_NORMAL_READ | SD_TRANSFER_START); 3051 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 3052 SD_TRANSFER_END); 3053 3054 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0); 3055 if (width == MMC_8BIT_BUS) 3056 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0); 3057 3058 retval = rtsx_send_cmd(chip, SD_CARD, 100); 3059 if (retval < 0) { 3060 rtsx_clear_sd_error(chip); 3061 rtsx_trace(chip); 3062 return SWITCH_ERR; 3063 } 3064 3065 ptr = rtsx_get_cmd_data(chip) + 1; 3066 3067 if (width == MMC_8BIT_BUS) { 3068 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n", 3069 ptr[0], ptr[1]); 3070 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) { 3071 u8 rsp[5]; 3072 u32 arg; 3073 3074 if (CHK_MMC_DDR52(sd_card)) 3075 arg = 0x03B70600; 3076 else 3077 arg = 0x03B70200; 3078 3079 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, 3080 SD_RSP_TYPE_R1b, rsp, 5); 3081 if ((retval == STATUS_SUCCESS) && 3082 !(rsp[4] & MMC_SWITCH_ERR)) 3083 return SWITCH_SUCCESS; 3084 } 3085 } else { 3086 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]); 3087 if (ptr[0] == 0xA5) { 3088 u8 rsp[5]; 3089 u32 arg; 3090 3091 if (CHK_MMC_DDR52(sd_card)) 3092 arg = 0x03B70500; 3093 else 3094 arg = 0x03B70100; 3095 3096 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg, 3097 SD_RSP_TYPE_R1b, rsp, 5); 3098 if ((retval == STATUS_SUCCESS) && 3099 !(rsp[4] & MMC_SWITCH_ERR)) 3100 return SWITCH_SUCCESS; 3101 } 3102 } 3103 3104 rtsx_trace(chip); 3105 return SWITCH_FAIL; 3106 } 3107 3108 3109 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr) 3110 { 3111 struct sd_info *sd_card = &(chip->sd_card); 3112 int retval; 3113 u8 *ptr, card_type, card_type_mask = 0; 3114 3115 CLR_MMC_HS(sd_card); 3116 3117 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD); 3118 3119 rtsx_init_cmd(chip); 3120 3121 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 3122 0x40 | SEND_EXT_CSD); 3123 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0); 3124 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0); 3125 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0); 3126 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0); 3127 3128 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0); 3129 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2); 3130 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1); 3131 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0); 3132 3133 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3134 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END| 3135 SD_CHECK_CRC7 | SD_RSP_LEN_6); 3136 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 3137 PINGPONG_BUFFER); 3138 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3139 SD_TM_NORMAL_READ | SD_TRANSFER_START); 3140 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 3141 SD_TRANSFER_END); 3142 3143 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0); 3144 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0); 3145 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0); 3146 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0); 3147 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0); 3148 3149 retval = rtsx_send_cmd(chip, SD_CARD, 1000); 3150 if (retval < 0) { 3151 if (retval == -ETIMEDOUT) { 3152 rtsx_clear_sd_error(chip); 3153 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3154 SD_RSP_TYPE_R1, NULL, 0); 3155 } 3156 rtsx_trace(chip); 3157 return STATUS_FAIL; 3158 } 3159 3160 ptr = rtsx_get_cmd_data(chip); 3161 if (ptr[0] & SD_TRANSFER_ERR) { 3162 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3163 SD_RSP_TYPE_R1, NULL, 0); 3164 rtsx_trace(chip); 3165 return STATUS_FAIL; 3166 } 3167 3168 if (CHK_MMC_SECTOR_MODE(sd_card)) { 3169 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) | 3170 ((u32)ptr[3] << 8) | ((u32)ptr[2]); 3171 } 3172 3173 card_type_mask = 0x03; 3174 card_type = ptr[1] & card_type_mask; 3175 if (card_type) { 3176 u8 rsp[5]; 3177 3178 if (card_type & 0x04) { 3179 if (switch_ddr) 3180 SET_MMC_DDR52(sd_card); 3181 else 3182 SET_MMC_52M(sd_card); 3183 } else if (card_type & 0x02) { 3184 SET_MMC_52M(sd_card); 3185 } else { 3186 SET_MMC_26M(sd_card); 3187 } 3188 3189 retval = sd_send_cmd_get_rsp(chip, SWITCH, 3190 0x03B90100, SD_RSP_TYPE_R1b, rsp, 5); 3191 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR)) 3192 CLR_MMC_HS(sd_card); 3193 } 3194 3195 sd_choose_proper_clock(chip); 3196 retval = switch_clock(chip, sd_card->sd_clock); 3197 if (retval != STATUS_SUCCESS) { 3198 rtsx_trace(chip); 3199 return STATUS_FAIL; 3200 } 3201 3202 /* Test Bus Procedure */ 3203 retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS); 3204 if (retval == SWITCH_SUCCESS) { 3205 SET_MMC_8BIT(sd_card); 3206 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8; 3207 #ifdef SUPPORT_SD_LOCK 3208 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 3209 #endif 3210 } else if (retval == SWITCH_FAIL) { 3211 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS); 3212 if (retval == SWITCH_SUCCESS) { 3213 SET_MMC_4BIT(sd_card); 3214 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4; 3215 #ifdef SUPPORT_SD_LOCK 3216 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE; 3217 #endif 3218 } else if (retval == SWITCH_FAIL) { 3219 CLR_MMC_8BIT(sd_card); 3220 CLR_MMC_4BIT(sd_card); 3221 } else { 3222 rtsx_trace(chip); 3223 return STATUS_FAIL; 3224 } 3225 } else { 3226 rtsx_trace(chip); 3227 return STATUS_FAIL; 3228 } 3229 3230 return STATUS_SUCCESS; 3231 } 3232 3233 3234 static int reset_mmc(struct rtsx_chip *chip) 3235 { 3236 struct sd_info *sd_card = &(chip->sd_card); 3237 int retval, i = 0, j = 0, k = 0; 3238 bool switch_ddr = true; 3239 u8 rsp[16]; 3240 u8 spec_ver = 0; 3241 u32 temp; 3242 3243 #ifdef SUPPORT_SD_LOCK 3244 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) 3245 goto MMC_UNLOCK_ENTRY; 3246 #endif 3247 3248 Switch_Fail: 3249 retval = sd_prepare_reset(chip); 3250 if (retval != STATUS_SUCCESS) { 3251 rtsx_trace(chip); 3252 return retval; 3253 } 3254 3255 SET_MMC(sd_card); 3256 3257 RTY_MMC_RST: 3258 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0, 3259 NULL, 0); 3260 if (retval != STATUS_SUCCESS) { 3261 rtsx_trace(chip); 3262 return STATUS_FAIL; 3263 } 3264 3265 do { 3266 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3267 sd_set_err_code(chip, SD_NO_CARD); 3268 rtsx_trace(chip); 3269 return STATUS_FAIL; 3270 } 3271 3272 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND, 3273 (SUPPORT_VOLTAGE | 0x40000000), 3274 SD_RSP_TYPE_R3, rsp, 5); 3275 if (retval != STATUS_SUCCESS) { 3276 if (sd_check_err_code(chip, SD_BUSY) || 3277 sd_check_err_code(chip, SD_TO_ERR)) { 3278 k++; 3279 if (k < 20) { 3280 sd_clr_err_code(chip); 3281 goto RTY_MMC_RST; 3282 } else { 3283 rtsx_trace(chip); 3284 return STATUS_FAIL; 3285 } 3286 } else { 3287 j++; 3288 if (j < 100) { 3289 sd_clr_err_code(chip); 3290 goto RTY_MMC_RST; 3291 } else { 3292 rtsx_trace(chip); 3293 return STATUS_FAIL; 3294 } 3295 } 3296 } 3297 3298 wait_timeout(20); 3299 i++; 3300 } while (!(rsp[1] & 0x80) && (i < 255)); 3301 3302 if (i == 255) { 3303 rtsx_trace(chip); 3304 return STATUS_FAIL; 3305 } 3306 3307 if ((rsp[1] & 0x60) == 0x40) 3308 SET_MMC_SECTOR_MODE(sd_card); 3309 else 3310 CLR_MMC_SECTOR_MODE(sd_card); 3311 3312 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2, 3313 NULL, 0); 3314 if (retval != STATUS_SUCCESS) { 3315 rtsx_trace(chip); 3316 return STATUS_FAIL; 3317 } 3318 3319 sd_card->sd_addr = 0x00100000; 3320 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr, 3321 SD_RSP_TYPE_R6, rsp, 5); 3322 if (retval != STATUS_SUCCESS) { 3323 rtsx_trace(chip); 3324 return STATUS_FAIL; 3325 } 3326 3327 retval = sd_check_csd(chip, 1); 3328 if (retval != STATUS_SUCCESS) { 3329 rtsx_trace(chip); 3330 return STATUS_FAIL; 3331 } 3332 3333 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2; 3334 3335 retval = sd_select_card(chip, 1); 3336 if (retval != STATUS_SUCCESS) { 3337 rtsx_trace(chip); 3338 return STATUS_FAIL; 3339 } 3340 3341 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1, 3342 NULL, 0); 3343 if (retval != STATUS_SUCCESS) { 3344 rtsx_trace(chip); 3345 return STATUS_FAIL; 3346 } 3347 3348 #ifdef SUPPORT_SD_LOCK 3349 MMC_UNLOCK_ENTRY: 3350 retval = sd_update_lock_status(chip); 3351 if (retval != STATUS_SUCCESS) { 3352 rtsx_trace(chip); 3353 return STATUS_FAIL; 3354 } 3355 #endif 3356 3357 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 3358 if (retval != STATUS_SUCCESS) { 3359 rtsx_trace(chip); 3360 return STATUS_FAIL; 3361 } 3362 3363 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1; 3364 3365 if (!sd_card->mmc_dont_switch_bus) { 3366 if (spec_ver == 4) { 3367 /* MMC 4.x Cards */ 3368 retval = mmc_switch_timing_bus(chip, switch_ddr); 3369 if (retval != STATUS_SUCCESS) { 3370 retval = sd_init_power(chip); 3371 if (retval != STATUS_SUCCESS) { 3372 rtsx_trace(chip); 3373 return STATUS_FAIL; 3374 } 3375 sd_card->mmc_dont_switch_bus = 1; 3376 rtsx_trace(chip); 3377 goto Switch_Fail; 3378 } 3379 } 3380 3381 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) { 3382 rtsx_trace(chip); 3383 return STATUS_FAIL; 3384 } 3385 3386 if (switch_ddr && CHK_MMC_DDR52(sd_card)) { 3387 retval = sd_set_init_para(chip); 3388 if (retval != STATUS_SUCCESS) { 3389 rtsx_trace(chip); 3390 return STATUS_FAIL; 3391 } 3392 3393 retval = mmc_ddr_tuning(chip); 3394 if (retval != STATUS_SUCCESS) { 3395 retval = sd_init_power(chip); 3396 if (retval != STATUS_SUCCESS) { 3397 rtsx_trace(chip); 3398 return STATUS_FAIL; 3399 } 3400 3401 switch_ddr = false; 3402 rtsx_trace(chip); 3403 goto Switch_Fail; 3404 } 3405 3406 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 3407 if (retval == STATUS_SUCCESS) { 3408 retval = sd_read_lba0(chip); 3409 if (retval != STATUS_SUCCESS) { 3410 retval = sd_init_power(chip); 3411 if (retval != STATUS_SUCCESS) { 3412 rtsx_trace(chip); 3413 return STATUS_FAIL; 3414 } 3415 3416 switch_ddr = false; 3417 rtsx_trace(chip); 3418 goto Switch_Fail; 3419 } 3420 } 3421 } 3422 } 3423 3424 #ifdef SUPPORT_SD_LOCK 3425 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) { 3426 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF, 3427 0x02); 3428 if (retval) { 3429 rtsx_trace(chip); 3430 return retval; 3431 } 3432 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF, 3433 0x00); 3434 if (retval) { 3435 rtsx_trace(chip); 3436 return retval; 3437 } 3438 } 3439 #endif 3440 3441 temp = rtsx_readl(chip, RTSX_BIPR); 3442 if (temp & SD_WRITE_PROTECT) 3443 chip->card_wp |= SD_CARD; 3444 3445 return STATUS_SUCCESS; 3446 } 3447 3448 int reset_sd_card(struct rtsx_chip *chip) 3449 { 3450 struct sd_info *sd_card = &(chip->sd_card); 3451 int retval; 3452 3453 sd_init_reg_addr(chip); 3454 3455 memset(sd_card, 0, sizeof(struct sd_info)); 3456 chip->capacity[chip->card2lun[SD_CARD]] = 0; 3457 3458 retval = enable_card_clock(chip, SD_CARD); 3459 if (retval != STATUS_SUCCESS) { 3460 rtsx_trace(chip); 3461 return STATUS_FAIL; 3462 } 3463 3464 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) && 3465 !CHK_SDIO_IGNORED(chip)) { 3466 if (chip->asic_code) { 3467 retval = sd_pull_ctl_enable(chip); 3468 if (retval != STATUS_SUCCESS) { 3469 rtsx_trace(chip); 3470 return STATUS_FAIL; 3471 } 3472 } else { 3473 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 3474 FPGA_SD_PULL_CTL_BIT | 0x20, 0); 3475 if (retval != STATUS_SUCCESS) { 3476 rtsx_trace(chip); 3477 return STATUS_FAIL; 3478 } 3479 } 3480 retval = card_share_mode(chip, SD_CARD); 3481 if (retval != STATUS_SUCCESS) { 3482 rtsx_trace(chip); 3483 return STATUS_FAIL; 3484 } 3485 3486 chip->sd_io = 1; 3487 rtsx_trace(chip); 3488 return STATUS_FAIL; 3489 } 3490 3491 retval = sd_init_power(chip); 3492 if (retval != STATUS_SUCCESS) { 3493 rtsx_trace(chip); 3494 return STATUS_FAIL; 3495 } 3496 3497 if (chip->sd_ctl & RESET_MMC_FIRST) { 3498 retval = reset_mmc(chip); 3499 if (retval != STATUS_SUCCESS) { 3500 if (sd_check_err_code(chip, SD_NO_CARD)) { 3501 rtsx_trace(chip); 3502 return STATUS_FAIL; 3503 } 3504 3505 retval = reset_sd(chip); 3506 if (retval != STATUS_SUCCESS) { 3507 rtsx_trace(chip); 3508 return STATUS_FAIL; 3509 } 3510 } 3511 } else { 3512 retval = reset_sd(chip); 3513 if (retval != STATUS_SUCCESS) { 3514 if (sd_check_err_code(chip, SD_NO_CARD)) { 3515 rtsx_trace(chip); 3516 return STATUS_FAIL; 3517 } 3518 3519 if (chip->sd_io) { 3520 rtsx_trace(chip); 3521 return STATUS_FAIL; 3522 } 3523 retval = reset_mmc(chip); 3524 if (retval != STATUS_SUCCESS) { 3525 rtsx_trace(chip); 3526 return STATUS_FAIL; 3527 } 3528 } 3529 } 3530 3531 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 3532 if (retval != STATUS_SUCCESS) { 3533 rtsx_trace(chip); 3534 return STATUS_FAIL; 3535 } 3536 3537 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); 3538 if (retval) { 3539 rtsx_trace(chip); 3540 return retval; 3541 } 3542 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); 3543 if (retval) { 3544 rtsx_trace(chip); 3545 return retval; 3546 } 3547 3548 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; 3549 3550 retval = sd_set_init_para(chip); 3551 if (retval != STATUS_SUCCESS) { 3552 rtsx_trace(chip); 3553 return STATUS_FAIL; 3554 } 3555 3556 dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type); 3557 3558 return STATUS_SUCCESS; 3559 } 3560 3561 static int reset_mmc_only(struct rtsx_chip *chip) 3562 { 3563 struct sd_info *sd_card = &(chip->sd_card); 3564 int retval; 3565 3566 sd_card->sd_type = 0; 3567 sd_card->seq_mode = 0; 3568 sd_card->sd_data_buf_ready = 0; 3569 sd_card->capacity = 0; 3570 sd_card->sd_switch_fail = 0; 3571 3572 #ifdef SUPPORT_SD_LOCK 3573 sd_card->sd_lock_status = 0; 3574 sd_card->sd_erase_status = 0; 3575 #endif 3576 3577 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0; 3578 3579 retval = enable_card_clock(chip, SD_CARD); 3580 if (retval != STATUS_SUCCESS) { 3581 rtsx_trace(chip); 3582 return STATUS_FAIL; 3583 } 3584 3585 retval = sd_init_power(chip); 3586 if (retval != STATUS_SUCCESS) { 3587 rtsx_trace(chip); 3588 return STATUS_FAIL; 3589 } 3590 3591 retval = reset_mmc(chip); 3592 if (retval != STATUS_SUCCESS) { 3593 rtsx_trace(chip); 3594 return STATUS_FAIL; 3595 } 3596 3597 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0); 3598 if (retval != STATUS_SUCCESS) { 3599 rtsx_trace(chip); 3600 return STATUS_FAIL; 3601 } 3602 3603 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0); 3604 if (retval) { 3605 rtsx_trace(chip); 3606 return retval; 3607 } 3608 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2); 3609 if (retval) { 3610 rtsx_trace(chip); 3611 return retval; 3612 } 3613 3614 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity; 3615 3616 retval = sd_set_init_para(chip); 3617 if (retval != STATUS_SUCCESS) { 3618 rtsx_trace(chip); 3619 return STATUS_FAIL; 3620 } 3621 3622 dev_dbg(rtsx_dev(chip), "In reset_mmc_only, sd_card->sd_type = 0x%x\n", 3623 sd_card->sd_type); 3624 3625 return STATUS_SUCCESS; 3626 } 3627 3628 #define WAIT_DATA_READY_RTY_CNT 255 3629 3630 static int wait_data_buf_ready(struct rtsx_chip *chip) 3631 { 3632 struct sd_info *sd_card = &(chip->sd_card); 3633 int i, retval; 3634 3635 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) { 3636 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3637 sd_set_err_code(chip, SD_NO_CARD); 3638 rtsx_trace(chip); 3639 return STATUS_FAIL; 3640 } 3641 3642 sd_card->sd_data_buf_ready = 0; 3643 3644 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, 3645 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); 3646 if (retval != STATUS_SUCCESS) { 3647 rtsx_trace(chip); 3648 return STATUS_FAIL; 3649 } 3650 3651 if (sd_card->sd_data_buf_ready) { 3652 return sd_send_cmd_get_rsp(chip, SEND_STATUS, 3653 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0); 3654 } 3655 } 3656 3657 sd_set_err_code(chip, SD_TO_ERR); 3658 3659 rtsx_trace(chip); 3660 return STATUS_FAIL; 3661 } 3662 3663 void sd_stop_seq_mode(struct rtsx_chip *chip) 3664 { 3665 struct sd_info *sd_card = &(chip->sd_card); 3666 int retval; 3667 3668 if (sd_card->seq_mode) { 3669 retval = sd_switch_clock(chip); 3670 if (retval != STATUS_SUCCESS) 3671 return; 3672 3673 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 3674 SD_RSP_TYPE_R1b, NULL, 0); 3675 if (retval != STATUS_SUCCESS) 3676 sd_set_err_code(chip, SD_STS_ERR); 3677 3678 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000); 3679 if (retval != STATUS_SUCCESS) 3680 sd_set_err_code(chip, SD_STS_ERR); 3681 3682 sd_card->seq_mode = 0; 3683 3684 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3685 } 3686 } 3687 3688 static inline int sd_auto_tune_clock(struct rtsx_chip *chip) 3689 { 3690 struct sd_info *sd_card = &(chip->sd_card); 3691 int retval; 3692 3693 if (chip->asic_code) { 3694 if (sd_card->sd_clock > 30) 3695 sd_card->sd_clock -= 20; 3696 } else { 3697 switch (sd_card->sd_clock) { 3698 case CLK_200: 3699 sd_card->sd_clock = CLK_150; 3700 break; 3701 3702 case CLK_150: 3703 sd_card->sd_clock = CLK_120; 3704 break; 3705 3706 case CLK_120: 3707 sd_card->sd_clock = CLK_100; 3708 break; 3709 3710 case CLK_100: 3711 sd_card->sd_clock = CLK_80; 3712 break; 3713 3714 case CLK_80: 3715 sd_card->sd_clock = CLK_60; 3716 break; 3717 3718 case CLK_60: 3719 sd_card->sd_clock = CLK_50; 3720 break; 3721 3722 default: 3723 break; 3724 } 3725 } 3726 3727 retval = sd_switch_clock(chip); 3728 if (retval != STATUS_SUCCESS) { 3729 rtsx_trace(chip); 3730 return STATUS_FAIL; 3731 } 3732 3733 return STATUS_SUCCESS; 3734 } 3735 3736 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector, 3737 u16 sector_cnt) 3738 { 3739 struct sd_info *sd_card = &(chip->sd_card); 3740 u32 data_addr; 3741 u8 cfg2; 3742 int retval; 3743 3744 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3745 dev_dbg(rtsx_dev(chip), "sd_rw: Read %d %s from 0x%x\n", 3746 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector", 3747 start_sector); 3748 } else { 3749 dev_dbg(rtsx_dev(chip), "sd_rw: Write %d %s to 0x%x\n", 3750 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector", 3751 start_sector); 3752 } 3753 3754 sd_card->cleanup_counter = 0; 3755 3756 if (!(chip->card_ready & SD_CARD)) { 3757 sd_card->seq_mode = 0; 3758 3759 retval = reset_sd_card(chip); 3760 if (retval == STATUS_SUCCESS) { 3761 chip->card_ready |= SD_CARD; 3762 chip->card_fail &= ~SD_CARD; 3763 } else { 3764 chip->card_ready &= ~SD_CARD; 3765 chip->card_fail |= SD_CARD; 3766 chip->capacity[chip->card2lun[SD_CARD]] = 0; 3767 chip->rw_need_retry = 1; 3768 rtsx_trace(chip); 3769 return STATUS_FAIL; 3770 } 3771 } 3772 3773 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card)) 3774 data_addr = start_sector << 9; 3775 else 3776 data_addr = start_sector; 3777 3778 sd_clr_err_code(chip); 3779 3780 retval = sd_switch_clock(chip); 3781 if (retval != STATUS_SUCCESS) { 3782 sd_set_err_code(chip, SD_IO_ERR); 3783 rtsx_trace(chip); 3784 goto RW_FAIL; 3785 } 3786 3787 if (sd_card->seq_mode && 3788 ((sd_card->pre_dir != srb->sc_data_direction) || 3789 ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) != 3790 start_sector))) { 3791 if ((sd_card->pre_sec_cnt < 0x80) 3792 && (sd_card->pre_dir == DMA_FROM_DEVICE) 3793 && !CHK_SD30_SPEED(sd_card) 3794 && !CHK_SD_HS(sd_card) 3795 && !CHK_MMC_HS(sd_card)) { 3796 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3797 SD_RSP_TYPE_R1, NULL, 0); 3798 } 3799 3800 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 3801 0, SD_RSP_TYPE_R1b, NULL, 0); 3802 if (retval != STATUS_SUCCESS) { 3803 chip->rw_need_retry = 1; 3804 sd_set_err_code(chip, SD_STS_ERR); 3805 rtsx_trace(chip); 3806 goto RW_FAIL; 3807 } 3808 3809 sd_card->seq_mode = 0; 3810 3811 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3812 if (retval != STATUS_SUCCESS) { 3813 sd_set_err_code(chip, SD_IO_ERR); 3814 rtsx_trace(chip); 3815 goto RW_FAIL; 3816 } 3817 3818 if ((sd_card->pre_sec_cnt < 0x80) 3819 && !CHK_SD30_SPEED(sd_card) 3820 && !CHK_SD_HS(sd_card) 3821 && !CHK_MMC_HS(sd_card)) { 3822 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, 3823 SD_RSP_TYPE_R1, NULL, 0); 3824 } 3825 } 3826 3827 rtsx_init_cmd(chip); 3828 3829 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00); 3830 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02); 3831 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 3832 (u8)sector_cnt); 3833 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 3834 (u8)(sector_cnt >> 8)); 3835 3836 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 3837 3838 if (CHK_MMC_8BIT(sd_card)) 3839 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3840 0x03, SD_BUS_WIDTH_8); 3841 else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card)) 3842 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3843 0x03, SD_BUS_WIDTH_4); 3844 else 3845 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 3846 0x03, SD_BUS_WIDTH_1); 3847 3848 if (sd_card->seq_mode) { 3849 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16| 3850 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | 3851 SD_RSP_LEN_0; 3852 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2); 3853 3854 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512, 3855 DMA_512); 3856 3857 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3858 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3859 SD_TM_AUTO_READ_3 | SD_TRANSFER_START); 3860 } else { 3861 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3862 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 3863 } 3864 3865 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3866 SD_TRANSFER_END, SD_TRANSFER_END); 3867 3868 rtsx_send_cmd_no_wait(chip); 3869 } else { 3870 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3871 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", 3872 READ_MULTIPLE_BLOCK); 3873 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 3874 0x40 | READ_MULTIPLE_BLOCK); 3875 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 3876 (u8)(data_addr >> 24)); 3877 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 3878 (u8)(data_addr >> 16)); 3879 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 3880 (u8)(data_addr >> 8)); 3881 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 3882 (u8)data_addr); 3883 3884 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 3885 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | 3886 SD_RSP_LEN_6; 3887 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3888 cfg2); 3889 3890 trans_dma_enable(srb->sc_data_direction, chip, 3891 sector_cnt * 512, DMA_512); 3892 3893 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3894 SD_TM_AUTO_READ_2 | SD_TRANSFER_START); 3895 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3896 SD_TRANSFER_END, SD_TRANSFER_END); 3897 3898 rtsx_send_cmd_no_wait(chip); 3899 } else { 3900 retval = rtsx_send_cmd(chip, SD_CARD, 50); 3901 if (retval < 0) { 3902 rtsx_clear_sd_error(chip); 3903 3904 chip->rw_need_retry = 1; 3905 sd_set_err_code(chip, SD_TO_ERR); 3906 rtsx_trace(chip); 3907 goto RW_FAIL; 3908 } 3909 3910 retval = wait_data_buf_ready(chip); 3911 if (retval != STATUS_SUCCESS) { 3912 chip->rw_need_retry = 1; 3913 sd_set_err_code(chip, SD_TO_ERR); 3914 rtsx_trace(chip); 3915 goto RW_FAIL; 3916 } 3917 3918 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK, 3919 data_addr, SD_RSP_TYPE_R1, NULL, 0); 3920 if (retval != STATUS_SUCCESS) { 3921 chip->rw_need_retry = 1; 3922 rtsx_trace(chip); 3923 goto RW_FAIL; 3924 } 3925 3926 rtsx_init_cmd(chip); 3927 3928 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 3929 SD_NO_WAIT_BUSY_END | 3930 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 3931 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, 3932 cfg2); 3933 3934 trans_dma_enable(srb->sc_data_direction, chip, 3935 sector_cnt * 512, DMA_512); 3936 3937 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 3938 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 3939 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 3940 SD_TRANSFER_END, SD_TRANSFER_END); 3941 3942 rtsx_send_cmd_no_wait(chip); 3943 } 3944 3945 sd_card->seq_mode = 1; 3946 } 3947 3948 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 3949 scsi_bufflen(srb), scsi_sg_count(srb), 3950 srb->sc_data_direction, chip->sd_timeout); 3951 if (retval < 0) { 3952 u8 stat = 0; 3953 int err; 3954 3955 sd_card->seq_mode = 0; 3956 3957 if (retval == -ETIMEDOUT) 3958 err = STATUS_TIMEDOUT; 3959 else 3960 err = STATUS_FAIL; 3961 3962 rtsx_read_register(chip, REG_SD_STAT1, &stat); 3963 rtsx_clear_sd_error(chip); 3964 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 3965 chip->rw_need_retry = 0; 3966 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n"); 3967 rtsx_trace(chip); 3968 return STATUS_FAIL; 3969 } 3970 3971 chip->rw_need_retry = 1; 3972 3973 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0, 3974 SD_RSP_TYPE_R1b, NULL, 0); 3975 if (retval != STATUS_SUCCESS) { 3976 sd_set_err_code(chip, SD_STS_ERR); 3977 rtsx_trace(chip); 3978 goto RW_FAIL; 3979 } 3980 3981 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) { 3982 dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n"); 3983 sd_set_err_code(chip, SD_CRC_ERR); 3984 rtsx_trace(chip); 3985 goto RW_FAIL; 3986 } 3987 3988 if (err == STATUS_TIMEDOUT) { 3989 sd_set_err_code(chip, SD_TO_ERR); 3990 rtsx_trace(chip); 3991 goto RW_FAIL; 3992 } 3993 3994 rtsx_trace(chip); 3995 return err; 3996 } 3997 3998 sd_card->pre_sec_addr = start_sector; 3999 sd_card->pre_sec_cnt = sector_cnt; 4000 sd_card->pre_dir = srb->sc_data_direction; 4001 4002 return STATUS_SUCCESS; 4003 4004 RW_FAIL: 4005 sd_card->seq_mode = 0; 4006 4007 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) { 4008 chip->rw_need_retry = 0; 4009 dev_dbg(rtsx_dev(chip), "No card exist, exit sd_rw\n"); 4010 rtsx_trace(chip); 4011 return STATUS_FAIL; 4012 } 4013 4014 if (sd_check_err_code(chip, SD_CRC_ERR)) { 4015 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) { 4016 sd_card->mmc_dont_switch_bus = 1; 4017 reset_mmc_only(chip); 4018 sd_card->mmc_dont_switch_bus = 0; 4019 } else { 4020 sd_card->need_retune = 1; 4021 sd_auto_tune_clock(chip); 4022 } 4023 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) { 4024 retval = reset_sd_card(chip); 4025 if (retval != STATUS_SUCCESS) { 4026 chip->card_ready &= ~SD_CARD; 4027 chip->card_fail |= SD_CARD; 4028 chip->capacity[chip->card2lun[SD_CARD]] = 0; 4029 } 4030 } 4031 4032 rtsx_trace(chip); 4033 return STATUS_FAIL; 4034 } 4035 4036 #ifdef SUPPORT_CPRM 4037 int soft_reset_sd_card(struct rtsx_chip *chip) 4038 { 4039 return reset_sd(chip); 4040 } 4041 4042 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, 4043 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len, bool special_check) 4044 { 4045 int retval; 4046 int timeout = 100; 4047 u16 reg_addr; 4048 u8 *ptr; 4049 int stat_idx = 0; 4050 int rty_cnt = 0; 4051 4052 dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx); 4053 4054 if (rsp_type == SD_RSP_TYPE_R1b) 4055 timeout = 3000; 4056 4057 RTY_SEND_CMD: 4058 4059 rtsx_init_cmd(chip); 4060 4061 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx); 4062 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24)); 4063 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16)); 4064 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8)); 4065 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg); 4066 4067 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 4068 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4069 0x01, PINGPONG_BUFFER); 4070 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 4071 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 4072 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END, 4073 SD_TRANSFER_END); 4074 4075 if (rsp_type == SD_RSP_TYPE_R2) { 4076 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 4077 reg_addr++) 4078 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 4079 4080 stat_idx = 17; 4081 } else if (rsp_type != SD_RSP_TYPE_R0) { 4082 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 4083 reg_addr++) 4084 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 4085 4086 stat_idx = 6; 4087 } 4088 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0); 4089 4090 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0); 4091 4092 retval = rtsx_send_cmd(chip, SD_CARD, timeout); 4093 if (retval < 0) { 4094 if (retval == -ETIMEDOUT) { 4095 rtsx_clear_sd_error(chip); 4096 4097 if (rsp_type & SD_WAIT_BUSY_END) { 4098 retval = sd_check_data0_status(chip); 4099 if (retval != STATUS_SUCCESS) { 4100 rtsx_trace(chip); 4101 return retval; 4102 } 4103 } else { 4104 sd_set_err_code(chip, SD_TO_ERR); 4105 } 4106 } 4107 rtsx_trace(chip); 4108 return STATUS_FAIL; 4109 } 4110 4111 if (rsp_type == SD_RSP_TYPE_R0) 4112 return STATUS_SUCCESS; 4113 4114 ptr = rtsx_get_cmd_data(chip) + 1; 4115 4116 if ((ptr[0] & 0xC0) != 0) { 4117 sd_set_err_code(chip, SD_STS_ERR); 4118 rtsx_trace(chip); 4119 return STATUS_FAIL; 4120 } 4121 4122 if (!(rsp_type & SD_NO_CHECK_CRC7)) { 4123 if (ptr[stat_idx] & SD_CRC7_ERR) { 4124 if (cmd_idx == WRITE_MULTIPLE_BLOCK) { 4125 sd_set_err_code(chip, SD_CRC_ERR); 4126 rtsx_trace(chip); 4127 return STATUS_FAIL; 4128 } 4129 if (rty_cnt < SD_MAX_RETRY_COUNT) { 4130 wait_timeout(20); 4131 rty_cnt++; 4132 goto RTY_SEND_CMD; 4133 } else { 4134 sd_set_err_code(chip, SD_CRC_ERR); 4135 rtsx_trace(chip); 4136 return STATUS_FAIL; 4137 } 4138 } 4139 } 4140 4141 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) || 4142 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) { 4143 if ((cmd_idx != STOP_TRANSMISSION) && !special_check) { 4144 if (ptr[1] & 0x80) { 4145 rtsx_trace(chip); 4146 return STATUS_FAIL; 4147 } 4148 } 4149 #ifdef SUPPORT_SD_LOCK 4150 if (ptr[1] & 0x7D) { 4151 #else 4152 if (ptr[1] & 0x7F) { 4153 #endif 4154 rtsx_trace(chip); 4155 return STATUS_FAIL; 4156 } 4157 if (ptr[2] & 0xF8) { 4158 rtsx_trace(chip); 4159 return STATUS_FAIL; 4160 } 4161 4162 if (cmd_idx == SELECT_CARD) { 4163 if (rsp_type == SD_RSP_TYPE_R2) { 4164 if ((ptr[3] & 0x1E) != 0x04) { 4165 rtsx_trace(chip); 4166 return STATUS_FAIL; 4167 } 4168 4169 } else if (rsp_type == SD_RSP_TYPE_R0) { 4170 if ((ptr[3] & 0x1E) != 0x03) { 4171 rtsx_trace(chip); 4172 return STATUS_FAIL; 4173 } 4174 } 4175 } 4176 } 4177 4178 if (rsp && rsp_len) 4179 memcpy(rsp, ptr, rsp_len); 4180 4181 return STATUS_SUCCESS; 4182 } 4183 4184 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type) 4185 { 4186 int retval, rsp_len; 4187 u16 reg_addr; 4188 4189 if (rsp_type == SD_RSP_TYPE_R0) 4190 return STATUS_SUCCESS; 4191 4192 rtsx_init_cmd(chip); 4193 4194 if (rsp_type == SD_RSP_TYPE_R2) { 4195 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16; 4196 reg_addr++) 4197 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); 4198 4199 rsp_len = 17; 4200 } else if (rsp_type != SD_RSP_TYPE_R0) { 4201 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4; 4202 reg_addr++) 4203 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0); 4204 4205 rsp_len = 6; 4206 } 4207 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0); 4208 4209 retval = rtsx_send_cmd(chip, SD_CARD, 100); 4210 if (retval != STATUS_SUCCESS) { 4211 rtsx_trace(chip); 4212 return STATUS_FAIL; 4213 } 4214 4215 if (rsp) { 4216 int min_len = (rsp_len < len) ? rsp_len : len; 4217 4218 memcpy(rsp, rtsx_get_cmd_data(chip), min_len); 4219 4220 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len); 4221 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n", 4222 rsp[0], rsp[1], rsp[2], rsp[3]); 4223 } 4224 4225 return STATUS_SUCCESS; 4226 } 4227 4228 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4229 { 4230 struct sd_info *sd_card = &(chip->sd_card); 4231 unsigned int lun = SCSI_LUN(srb); 4232 int len; 4233 u8 buf[18] = { 4234 0x00, 4235 0x00, 4236 0x00, 4237 0x0E, 4238 0x00, 4239 0x00, 4240 0x00, 4241 0x00, 4242 0x53, 4243 0x44, 4244 0x20, 4245 0x43, 4246 0x61, 4247 0x72, 4248 0x64, 4249 0x00, 4250 0x00, 4251 0x00, 4252 }; 4253 4254 sd_card->pre_cmd_err = 0; 4255 4256 if (!(CHK_BIT(chip->lun_mc, lun))) { 4257 SET_BIT(chip->lun_mc, lun); 4258 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4259 rtsx_trace(chip); 4260 return TRANSPORT_FAILED; 4261 } 4262 4263 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) || 4264 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) || 4265 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) || 4266 (srb->cmnd[8] != 0x64)) { 4267 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4268 rtsx_trace(chip); 4269 return TRANSPORT_FAILED; 4270 } 4271 4272 switch (srb->cmnd[1] & 0x0F) { 4273 case 0: 4274 sd_card->sd_pass_thru_en = 0; 4275 break; 4276 4277 case 1: 4278 sd_card->sd_pass_thru_en = 1; 4279 break; 4280 4281 default: 4282 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4283 rtsx_trace(chip); 4284 return TRANSPORT_FAILED; 4285 } 4286 4287 buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02; 4288 if (chip->card_wp & SD_CARD) 4289 buf[5] |= 0x80; 4290 4291 buf[6] = (u8)(sd_card->sd_addr >> 16); 4292 buf[7] = (u8)(sd_card->sd_addr >> 24); 4293 4294 buf[15] = chip->max_lun; 4295 4296 len = min_t(int, 18, scsi_bufflen(srb)); 4297 rtsx_stor_set_xfer_buf(buf, len, srb); 4298 4299 return TRANSPORT_GOOD; 4300 } 4301 4302 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type, 4303 int *rsp_len) 4304 { 4305 if (!rsp_type || !rsp_len) 4306 return STATUS_FAIL; 4307 4308 switch (srb->cmnd[10]) { 4309 case 0x03: 4310 *rsp_type = SD_RSP_TYPE_R0; 4311 *rsp_len = 0; 4312 break; 4313 4314 case 0x04: 4315 *rsp_type = SD_RSP_TYPE_R1; 4316 *rsp_len = 6; 4317 break; 4318 4319 case 0x05: 4320 *rsp_type = SD_RSP_TYPE_R1b; 4321 *rsp_len = 6; 4322 break; 4323 4324 case 0x06: 4325 *rsp_type = SD_RSP_TYPE_R2; 4326 *rsp_len = 17; 4327 break; 4328 4329 case 0x07: 4330 *rsp_type = SD_RSP_TYPE_R3; 4331 *rsp_len = 6; 4332 break; 4333 4334 default: 4335 return STATUS_FAIL; 4336 } 4337 4338 return STATUS_SUCCESS; 4339 } 4340 4341 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4342 { 4343 struct sd_info *sd_card = &(chip->sd_card); 4344 unsigned int lun = SCSI_LUN(srb); 4345 int retval, rsp_len; 4346 u8 cmd_idx, rsp_type; 4347 bool standby = false, acmd = false; 4348 u32 arg; 4349 4350 if (!sd_card->sd_pass_thru_en) { 4351 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4352 rtsx_trace(chip); 4353 return TRANSPORT_FAILED; 4354 } 4355 4356 retval = sd_switch_clock(chip); 4357 if (retval != STATUS_SUCCESS) { 4358 rtsx_trace(chip); 4359 return TRANSPORT_FAILED; 4360 } 4361 4362 if (sd_card->pre_cmd_err) { 4363 sd_card->pre_cmd_err = 0; 4364 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4365 rtsx_trace(chip); 4366 return TRANSPORT_FAILED; 4367 } 4368 4369 cmd_idx = srb->cmnd[2] & 0x3F; 4370 if (srb->cmnd[1] & 0x02) 4371 standby = true; 4372 4373 if (srb->cmnd[1] & 0x01) 4374 acmd = true; 4375 4376 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | 4377 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; 4378 4379 retval = get_rsp_type(srb, &rsp_type, &rsp_len); 4380 if (retval != STATUS_SUCCESS) { 4381 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4382 rtsx_trace(chip); 4383 return TRANSPORT_FAILED; 4384 } 4385 sd_card->last_rsp_type = rsp_type; 4386 4387 retval = sd_switch_clock(chip); 4388 if (retval != STATUS_SUCCESS) { 4389 rtsx_trace(chip); 4390 return TRANSPORT_FAILED; 4391 } 4392 4393 #ifdef SUPPORT_SD_LOCK 4394 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 4395 if (CHK_MMC_8BIT(sd_card)) { 4396 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4397 SD_BUS_WIDTH_8); 4398 if (retval != STATUS_SUCCESS) { 4399 rtsx_trace(chip); 4400 return TRANSPORT_FAILED; 4401 } 4402 4403 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { 4404 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4405 SD_BUS_WIDTH_4); 4406 if (retval != STATUS_SUCCESS) { 4407 rtsx_trace(chip); 4408 return TRANSPORT_FAILED; 4409 } 4410 } 4411 } 4412 #else 4413 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); 4414 if (retval != STATUS_SUCCESS) { 4415 rtsx_trace(chip); 4416 return TRANSPORT_FAILED; 4417 } 4418 #endif 4419 4420 if (standby) { 4421 retval = sd_select_card(chip, 0); 4422 if (retval != STATUS_SUCCESS) { 4423 rtsx_trace(chip); 4424 goto SD_Execute_Cmd_Failed; 4425 } 4426 } 4427 4428 if (acmd) { 4429 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 4430 sd_card->sd_addr, 4431 SD_RSP_TYPE_R1, NULL, 0, false); 4432 if (retval != STATUS_SUCCESS) { 4433 rtsx_trace(chip); 4434 goto SD_Execute_Cmd_Failed; 4435 } 4436 } 4437 4438 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, 4439 sd_card->rsp, rsp_len, false); 4440 if (retval != STATUS_SUCCESS) { 4441 rtsx_trace(chip); 4442 goto SD_Execute_Cmd_Failed; 4443 } 4444 4445 if (standby) { 4446 retval = sd_select_card(chip, 1); 4447 if (retval != STATUS_SUCCESS) { 4448 rtsx_trace(chip); 4449 goto SD_Execute_Cmd_Failed; 4450 } 4451 } 4452 4453 #ifdef SUPPORT_SD_LOCK 4454 retval = sd_update_lock_status(chip); 4455 if (retval != STATUS_SUCCESS) { 4456 rtsx_trace(chip); 4457 goto SD_Execute_Cmd_Failed; 4458 } 4459 #endif 4460 4461 scsi_set_resid(srb, 0); 4462 return TRANSPORT_GOOD; 4463 4464 SD_Execute_Cmd_Failed: 4465 sd_card->pre_cmd_err = 1; 4466 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 4467 release_sd_card(chip); 4468 do_reset_sd_card(chip); 4469 if (!(chip->card_ready & SD_CARD)) 4470 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4471 4472 rtsx_trace(chip); 4473 return TRANSPORT_FAILED; 4474 } 4475 4476 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4477 { 4478 struct sd_info *sd_card = &(chip->sd_card); 4479 unsigned int lun = SCSI_LUN(srb); 4480 int retval, rsp_len, i; 4481 bool read_err = false, cmd13_checkbit = false; 4482 u8 cmd_idx, rsp_type, bus_width; 4483 bool standby = false, send_cmd12 = false, acmd = false; 4484 u32 data_len; 4485 4486 if (!sd_card->sd_pass_thru_en) { 4487 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4488 rtsx_trace(chip); 4489 return TRANSPORT_FAILED; 4490 } 4491 4492 if (sd_card->pre_cmd_err) { 4493 sd_card->pre_cmd_err = 0; 4494 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4495 rtsx_trace(chip); 4496 return TRANSPORT_FAILED; 4497 } 4498 4499 retval = sd_switch_clock(chip); 4500 if (retval != STATUS_SUCCESS) { 4501 rtsx_trace(chip); 4502 return TRANSPORT_FAILED; 4503 } 4504 4505 cmd_idx = srb->cmnd[2] & 0x3F; 4506 if (srb->cmnd[1] & 0x04) 4507 send_cmd12 = true; 4508 4509 if (srb->cmnd[1] & 0x02) 4510 standby = true; 4511 4512 if (srb->cmnd[1] & 0x01) 4513 acmd = true; 4514 4515 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] 4516 << 8) | srb->cmnd[9]; 4517 4518 retval = get_rsp_type(srb, &rsp_type, &rsp_len); 4519 if (retval != STATUS_SUCCESS) { 4520 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4521 rtsx_trace(chip); 4522 return TRANSPORT_FAILED; 4523 } 4524 sd_card->last_rsp_type = rsp_type; 4525 4526 retval = sd_switch_clock(chip); 4527 if (retval != STATUS_SUCCESS) { 4528 rtsx_trace(chip); 4529 return TRANSPORT_FAILED; 4530 } 4531 4532 #ifdef SUPPORT_SD_LOCK 4533 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 4534 if (CHK_MMC_8BIT(sd_card)) 4535 bus_width = SD_BUS_WIDTH_8; 4536 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) 4537 bus_width = SD_BUS_WIDTH_4; 4538 else 4539 bus_width = SD_BUS_WIDTH_1; 4540 } else { 4541 bus_width = SD_BUS_WIDTH_4; 4542 } 4543 dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width); 4544 #else 4545 bus_width = SD_BUS_WIDTH_4; 4546 #endif 4547 4548 if (data_len < 512) { 4549 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, 4550 SD_RSP_TYPE_R1, NULL, 0, false); 4551 if (retval != STATUS_SUCCESS) { 4552 rtsx_trace(chip); 4553 goto SD_Execute_Read_Cmd_Failed; 4554 } 4555 } 4556 4557 if (standby) { 4558 retval = sd_select_card(chip, 0); 4559 if (retval != STATUS_SUCCESS) { 4560 rtsx_trace(chip); 4561 goto SD_Execute_Read_Cmd_Failed; 4562 } 4563 } 4564 4565 if (acmd) { 4566 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 4567 sd_card->sd_addr, 4568 SD_RSP_TYPE_R1, NULL, 0, false); 4569 if (retval != STATUS_SUCCESS) { 4570 rtsx_trace(chip); 4571 goto SD_Execute_Read_Cmd_Failed; 4572 } 4573 } 4574 4575 if (data_len <= 512) { 4576 int min_len; 4577 u8 *buf; 4578 u16 byte_cnt, blk_cnt; 4579 u8 cmd[5]; 4580 4581 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9]; 4582 blk_cnt = 1; 4583 4584 cmd[0] = 0x40 | cmd_idx; 4585 cmd[1] = srb->cmnd[3]; 4586 cmd[2] = srb->cmnd[4]; 4587 cmd[3] = srb->cmnd[5]; 4588 cmd[4] = srb->cmnd[6]; 4589 4590 buf = kmalloc(data_len, GFP_KERNEL); 4591 if (!buf) { 4592 rtsx_trace(chip); 4593 return TRANSPORT_ERROR; 4594 } 4595 4596 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt, 4597 blk_cnt, bus_width, buf, data_len, 2000); 4598 if (retval != STATUS_SUCCESS) { 4599 read_err = true; 4600 kfree(buf); 4601 rtsx_clear_sd_error(chip); 4602 rtsx_trace(chip); 4603 goto SD_Execute_Read_Cmd_Failed; 4604 } 4605 4606 min_len = min(data_len, scsi_bufflen(srb)); 4607 rtsx_stor_set_xfer_buf(buf, min_len, srb); 4608 4609 kfree(buf); 4610 } else if (!(data_len & 0x1FF)) { 4611 rtsx_init_cmd(chip); 4612 4613 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512); 4614 4615 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4616 0x02); 4617 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4618 0x00); 4619 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 4620 0xFF, (srb->cmnd[7] & 0xFE) >> 1); 4621 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 4622 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); 4623 4624 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 4625 0x40 | cmd_idx); 4626 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 4627 srb->cmnd[3]); 4628 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 4629 srb->cmnd[4]); 4630 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 4631 srb->cmnd[5]); 4632 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 4633 srb->cmnd[6]); 4634 4635 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width); 4636 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type); 4637 4638 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 4639 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START); 4640 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4641 SD_TRANSFER_END, SD_TRANSFER_END); 4642 4643 rtsx_send_cmd_no_wait(chip); 4644 4645 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 4646 scsi_bufflen(srb), scsi_sg_count(srb), 4647 DMA_FROM_DEVICE, 10000); 4648 if (retval < 0) { 4649 read_err = true; 4650 rtsx_clear_sd_error(chip); 4651 rtsx_trace(chip); 4652 goto SD_Execute_Read_Cmd_Failed; 4653 } 4654 4655 } else { 4656 rtsx_trace(chip); 4657 goto SD_Execute_Read_Cmd_Failed; 4658 } 4659 4660 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type); 4661 if (retval != STATUS_SUCCESS) { 4662 rtsx_trace(chip); 4663 goto SD_Execute_Read_Cmd_Failed; 4664 } 4665 4666 if (standby) { 4667 retval = sd_select_card(chip, 1); 4668 if (retval != STATUS_SUCCESS) { 4669 rtsx_trace(chip); 4670 goto SD_Execute_Read_Cmd_Failed; 4671 } 4672 } 4673 4674 if (send_cmd12) { 4675 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 4676 0, SD_RSP_TYPE_R1b, NULL, 0, false); 4677 if (retval != STATUS_SUCCESS) { 4678 rtsx_trace(chip); 4679 goto SD_Execute_Read_Cmd_Failed; 4680 } 4681 } 4682 4683 if (data_len < 512) { 4684 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, 4685 SD_RSP_TYPE_R1, NULL, 0, false); 4686 if (retval != STATUS_SUCCESS) { 4687 rtsx_trace(chip); 4688 goto SD_Execute_Read_Cmd_Failed; 4689 } 4690 4691 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); 4692 if (retval != STATUS_SUCCESS) { 4693 rtsx_trace(chip); 4694 goto SD_Execute_Read_Cmd_Failed; 4695 } 4696 4697 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); 4698 if (retval != STATUS_SUCCESS) { 4699 rtsx_trace(chip); 4700 goto SD_Execute_Read_Cmd_Failed; 4701 } 4702 } 4703 4704 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) 4705 cmd13_checkbit = true; 4706 4707 for (i = 0; i < 3; i++) { 4708 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, 4709 sd_card->sd_addr, 4710 SD_RSP_TYPE_R1, NULL, 0, 4711 cmd13_checkbit); 4712 if (retval == STATUS_SUCCESS) 4713 break; 4714 } 4715 if (retval != STATUS_SUCCESS) { 4716 rtsx_trace(chip); 4717 goto SD_Execute_Read_Cmd_Failed; 4718 } 4719 4720 scsi_set_resid(srb, 0); 4721 return TRANSPORT_GOOD; 4722 4723 SD_Execute_Read_Cmd_Failed: 4724 sd_card->pre_cmd_err = 1; 4725 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 4726 if (read_err) 4727 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4728 4729 release_sd_card(chip); 4730 do_reset_sd_card(chip); 4731 if (!(chip->card_ready & SD_CARD)) 4732 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 4733 4734 rtsx_trace(chip); 4735 return TRANSPORT_FAILED; 4736 } 4737 4738 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4739 { 4740 struct sd_info *sd_card = &(chip->sd_card); 4741 unsigned int lun = SCSI_LUN(srb); 4742 int retval, rsp_len, i; 4743 bool write_err = false, cmd13_checkbit = false; 4744 u8 cmd_idx, rsp_type; 4745 bool standby = false, send_cmd12 = false, acmd = false; 4746 u32 data_len, arg; 4747 #ifdef SUPPORT_SD_LOCK 4748 int lock_cmd_fail = 0; 4749 u8 sd_lock_state = 0; 4750 u8 lock_cmd_type = 0; 4751 #endif 4752 4753 if (!sd_card->sd_pass_thru_en) { 4754 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4755 rtsx_trace(chip); 4756 return TRANSPORT_FAILED; 4757 } 4758 4759 if (sd_card->pre_cmd_err) { 4760 sd_card->pre_cmd_err = 0; 4761 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 4762 rtsx_trace(chip); 4763 return TRANSPORT_FAILED; 4764 } 4765 4766 retval = sd_switch_clock(chip); 4767 if (retval != STATUS_SUCCESS) { 4768 rtsx_trace(chip); 4769 return TRANSPORT_FAILED; 4770 } 4771 4772 cmd_idx = srb->cmnd[2] & 0x3F; 4773 if (srb->cmnd[1] & 0x04) 4774 send_cmd12 = true; 4775 4776 if (srb->cmnd[1] & 0x02) 4777 standby = true; 4778 4779 if (srb->cmnd[1] & 0x01) 4780 acmd = true; 4781 4782 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8] 4783 << 8) | srb->cmnd[9]; 4784 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) | 4785 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6]; 4786 4787 #ifdef SUPPORT_SD_LOCK 4788 if (cmd_idx == LOCK_UNLOCK) { 4789 sd_lock_state = sd_card->sd_lock_status; 4790 sd_lock_state &= SD_LOCKED; 4791 } 4792 #endif 4793 4794 retval = get_rsp_type(srb, &rsp_type, &rsp_len); 4795 if (retval != STATUS_SUCCESS) { 4796 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4797 rtsx_trace(chip); 4798 return TRANSPORT_FAILED; 4799 } 4800 sd_card->last_rsp_type = rsp_type; 4801 4802 retval = sd_switch_clock(chip); 4803 if (retval != STATUS_SUCCESS) { 4804 rtsx_trace(chip); 4805 return TRANSPORT_FAILED; 4806 } 4807 4808 #ifdef SUPPORT_SD_LOCK 4809 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) { 4810 if (CHK_MMC_8BIT(sd_card)) { 4811 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4812 SD_BUS_WIDTH_8); 4813 if (retval != STATUS_SUCCESS) { 4814 rtsx_trace(chip); 4815 return TRANSPORT_FAILED; 4816 } 4817 4818 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) { 4819 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, 4820 SD_BUS_WIDTH_4); 4821 if (retval != STATUS_SUCCESS) { 4822 rtsx_trace(chip); 4823 return TRANSPORT_FAILED; 4824 } 4825 } 4826 } 4827 #else 4828 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4); 4829 if (retval != STATUS_SUCCESS) { 4830 rtsx_trace(chip); 4831 return TRANSPORT_FAILED; 4832 } 4833 #endif 4834 4835 if (data_len < 512) { 4836 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len, 4837 SD_RSP_TYPE_R1, NULL, 0, false); 4838 if (retval != STATUS_SUCCESS) { 4839 rtsx_trace(chip); 4840 goto SD_Execute_Write_Cmd_Failed; 4841 } 4842 } 4843 4844 if (standby) { 4845 retval = sd_select_card(chip, 0); 4846 if (retval != STATUS_SUCCESS) { 4847 rtsx_trace(chip); 4848 goto SD_Execute_Write_Cmd_Failed; 4849 } 4850 } 4851 4852 if (acmd) { 4853 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD, 4854 sd_card->sd_addr, 4855 SD_RSP_TYPE_R1, NULL, 0, false); 4856 if (retval != STATUS_SUCCESS) { 4857 rtsx_trace(chip); 4858 goto SD_Execute_Write_Cmd_Failed; 4859 } 4860 } 4861 4862 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type, 4863 sd_card->rsp, rsp_len, false); 4864 if (retval != STATUS_SUCCESS) { 4865 rtsx_trace(chip); 4866 goto SD_Execute_Write_Cmd_Failed; 4867 } 4868 4869 if (data_len <= 512) { 4870 u16 i; 4871 u8 *buf; 4872 4873 buf = kmalloc(data_len, GFP_KERNEL); 4874 if (!buf) { 4875 rtsx_trace(chip); 4876 return TRANSPORT_ERROR; 4877 } 4878 4879 rtsx_stor_get_xfer_buf(buf, data_len, srb); 4880 4881 #ifdef SUPPORT_SD_LOCK 4882 if (cmd_idx == LOCK_UNLOCK) 4883 lock_cmd_type = buf[0] & 0x0F; 4884 #endif 4885 4886 if (data_len > 256) { 4887 rtsx_init_cmd(chip); 4888 for (i = 0; i < 256; i++) { 4889 rtsx_add_cmd(chip, WRITE_REG_CMD, 4890 PPBUF_BASE2 + i, 0xFF, buf[i]); 4891 } 4892 retval = rtsx_send_cmd(chip, 0, 250); 4893 if (retval != STATUS_SUCCESS) { 4894 kfree(buf); 4895 rtsx_trace(chip); 4896 goto SD_Execute_Write_Cmd_Failed; 4897 } 4898 4899 rtsx_init_cmd(chip); 4900 for (i = 256; i < data_len; i++) { 4901 rtsx_add_cmd(chip, WRITE_REG_CMD, 4902 PPBUF_BASE2 + i, 0xFF, buf[i]); 4903 } 4904 retval = rtsx_send_cmd(chip, 0, 250); 4905 if (retval != STATUS_SUCCESS) { 4906 kfree(buf); 4907 rtsx_trace(chip); 4908 goto SD_Execute_Write_Cmd_Failed; 4909 } 4910 } else { 4911 rtsx_init_cmd(chip); 4912 for (i = 0; i < data_len; i++) { 4913 rtsx_add_cmd(chip, WRITE_REG_CMD, 4914 PPBUF_BASE2 + i, 0xFF, buf[i]); 4915 } 4916 retval = rtsx_send_cmd(chip, 0, 250); 4917 if (retval != STATUS_SUCCESS) { 4918 kfree(buf); 4919 rtsx_trace(chip); 4920 goto SD_Execute_Write_Cmd_Failed; 4921 } 4922 } 4923 4924 kfree(buf); 4925 4926 rtsx_init_cmd(chip); 4927 4928 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4929 srb->cmnd[8] & 0x03); 4930 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4931 srb->cmnd[9]); 4932 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 4933 0x00); 4934 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 4935 0x01); 4936 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, 4937 PINGPONG_BUFFER); 4938 4939 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 4940 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 4941 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4942 SD_TRANSFER_END, SD_TRANSFER_END); 4943 4944 retval = rtsx_send_cmd(chip, SD_CARD, 250); 4945 } else if (!(data_len & 0x1FF)) { 4946 rtsx_init_cmd(chip); 4947 4948 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512); 4949 4950 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 4951 0x02); 4952 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 4953 0x00); 4954 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 4955 0xFF, (srb->cmnd[7] & 0xFE) >> 1); 4956 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 4957 0xFF, (u8)((data_len & 0x0001FE00) >> 9)); 4958 4959 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF, 4960 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START); 4961 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, 4962 SD_TRANSFER_END, SD_TRANSFER_END); 4963 4964 rtsx_send_cmd_no_wait(chip); 4965 4966 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb), 4967 scsi_bufflen(srb), scsi_sg_count(srb), 4968 DMA_TO_DEVICE, 10000); 4969 4970 } else { 4971 rtsx_trace(chip); 4972 goto SD_Execute_Write_Cmd_Failed; 4973 } 4974 4975 if (retval < 0) { 4976 write_err = true; 4977 rtsx_clear_sd_error(chip); 4978 rtsx_trace(chip); 4979 goto SD_Execute_Write_Cmd_Failed; 4980 } 4981 4982 #ifdef SUPPORT_SD_LOCK 4983 if (cmd_idx == LOCK_UNLOCK) { 4984 if (lock_cmd_type == SD_ERASE) { 4985 sd_card->sd_erase_status = SD_UNDER_ERASING; 4986 scsi_set_resid(srb, 0); 4987 return TRANSPORT_GOOD; 4988 } 4989 4990 rtsx_init_cmd(chip); 4991 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02); 4992 4993 rtsx_send_cmd(chip, SD_CARD, 250); 4994 4995 retval = sd_update_lock_status(chip); 4996 if (retval != STATUS_SUCCESS) { 4997 dev_dbg(rtsx_dev(chip), "Lock command fail!\n"); 4998 lock_cmd_fail = 1; 4999 } 5000 } 5001 #endif /* SUPPORT_SD_LOCK */ 5002 5003 if (standby) { 5004 retval = sd_select_card(chip, 1); 5005 if (retval != STATUS_SUCCESS) { 5006 rtsx_trace(chip); 5007 goto SD_Execute_Write_Cmd_Failed; 5008 } 5009 } 5010 5011 if (send_cmd12) { 5012 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 5013 0, SD_RSP_TYPE_R1b, NULL, 0, false); 5014 if (retval != STATUS_SUCCESS) { 5015 rtsx_trace(chip); 5016 goto SD_Execute_Write_Cmd_Failed; 5017 } 5018 } 5019 5020 if (data_len < 512) { 5021 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, 5022 SD_RSP_TYPE_R1, NULL, 0, false); 5023 if (retval != STATUS_SUCCESS) { 5024 rtsx_trace(chip); 5025 goto SD_Execute_Write_Cmd_Failed; 5026 } 5027 5028 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02); 5029 if (retval != STATUS_SUCCESS) { 5030 rtsx_trace(chip); 5031 goto SD_Execute_Write_Cmd_Failed; 5032 } 5033 5034 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00); 5035 if (retval != STATUS_SUCCESS) { 5036 rtsx_trace(chip); 5037 goto SD_Execute_Write_Cmd_Failed; 5038 } 5039 } 5040 5041 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04)) 5042 cmd13_checkbit = true; 5043 5044 for (i = 0; i < 3; i++) { 5045 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS, 5046 sd_card->sd_addr, 5047 SD_RSP_TYPE_R1, NULL, 0, 5048 cmd13_checkbit); 5049 if (retval == STATUS_SUCCESS) 5050 break; 5051 } 5052 if (retval != STATUS_SUCCESS) { 5053 rtsx_trace(chip); 5054 goto SD_Execute_Write_Cmd_Failed; 5055 } 5056 5057 #ifdef SUPPORT_SD_LOCK 5058 if (cmd_idx == LOCK_UNLOCK) { 5059 if (!lock_cmd_fail) { 5060 dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n", 5061 lock_cmd_type); 5062 if (lock_cmd_type & SD_CLR_PWD) 5063 sd_card->sd_lock_status &= ~SD_PWD_EXIST; 5064 5065 if (lock_cmd_type & SD_SET_PWD) 5066 sd_card->sd_lock_status |= SD_PWD_EXIST; 5067 } 5068 5069 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n", 5070 sd_lock_state, sd_card->sd_lock_status); 5071 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) { 5072 sd_card->sd_lock_notify = 1; 5073 if (sd_lock_state) { 5074 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) { 5075 sd_card->sd_lock_status |= ( 5076 SD_UNLOCK_POW_ON | SD_SDR_RST); 5077 if (CHK_SD(sd_card)) { 5078 retval = reset_sd(chip); 5079 if (retval != STATUS_SUCCESS) { 5080 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); 5081 rtsx_trace(chip); 5082 goto SD_Execute_Write_Cmd_Failed; 5083 } 5084 } 5085 5086 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST); 5087 } 5088 } 5089 } 5090 } 5091 5092 if (lock_cmd_fail) { 5093 scsi_set_resid(srb, 0); 5094 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 5095 rtsx_trace(chip); 5096 return TRANSPORT_FAILED; 5097 } 5098 #endif /* SUPPORT_SD_LOCK */ 5099 5100 scsi_set_resid(srb, 0); 5101 return TRANSPORT_GOOD; 5102 5103 SD_Execute_Write_Cmd_Failed: 5104 sd_card->pre_cmd_err = 1; 5105 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE); 5106 if (write_err) 5107 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR); 5108 5109 release_sd_card(chip); 5110 do_reset_sd_card(chip); 5111 if (!(chip->card_ready & SD_CARD)) 5112 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 5113 5114 rtsx_trace(chip); 5115 return TRANSPORT_FAILED; 5116 } 5117 5118 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 5119 { 5120 struct sd_info *sd_card = &(chip->sd_card); 5121 unsigned int lun = SCSI_LUN(srb); 5122 int count; 5123 u16 data_len; 5124 5125 if (!sd_card->sd_pass_thru_en) { 5126 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 5127 rtsx_trace(chip); 5128 return TRANSPORT_FAILED; 5129 } 5130 5131 if (sd_card->pre_cmd_err) { 5132 sd_card->pre_cmd_err = 0; 5133 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 5134 rtsx_trace(chip); 5135 return TRANSPORT_FAILED; 5136 } 5137 5138 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8]; 5139 5140 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) { 5141 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 5142 rtsx_trace(chip); 5143 return TRANSPORT_FAILED; 5144 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) { 5145 count = (data_len < 17) ? data_len : 17; 5146 } else { 5147 count = (data_len < 6) ? data_len : 6; 5148 } 5149 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb); 5150 5151 dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len); 5152 dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n", 5153 sd_card->rsp[0], sd_card->rsp[1], 5154 sd_card->rsp[2], sd_card->rsp[3]); 5155 5156 scsi_set_resid(srb, 0); 5157 return TRANSPORT_GOOD; 5158 } 5159 5160 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip) 5161 { 5162 struct sd_info *sd_card = &(chip->sd_card); 5163 unsigned int lun = SCSI_LUN(srb); 5164 int retval; 5165 5166 if (!sd_card->sd_pass_thru_en) { 5167 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 5168 rtsx_trace(chip); 5169 return TRANSPORT_FAILED; 5170 } 5171 5172 if (sd_card->pre_cmd_err) { 5173 sd_card->pre_cmd_err = 0; 5174 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE); 5175 rtsx_trace(chip); 5176 return TRANSPORT_FAILED; 5177 } 5178 5179 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) || 5180 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) || 5181 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) || 5182 (srb->cmnd[8] != 0x64)) { 5183 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 5184 rtsx_trace(chip); 5185 return TRANSPORT_FAILED; 5186 } 5187 5188 switch (srb->cmnd[1] & 0x0F) { 5189 case 0: 5190 #ifdef SUPPORT_SD_LOCK 5191 if (srb->cmnd[9] == 0x64) 5192 sd_card->sd_lock_status |= SD_SDR_RST; 5193 #endif 5194 retval = reset_sd_card(chip); 5195 if (retval != STATUS_SUCCESS) { 5196 #ifdef SUPPORT_SD_LOCK 5197 sd_card->sd_lock_status &= ~SD_SDR_RST; 5198 #endif 5199 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 5200 sd_card->pre_cmd_err = 1; 5201 rtsx_trace(chip); 5202 return TRANSPORT_FAILED; 5203 } 5204 #ifdef SUPPORT_SD_LOCK 5205 sd_card->sd_lock_status &= ~SD_SDR_RST; 5206 #endif 5207 break; 5208 5209 case 1: 5210 retval = soft_reset_sd_card(chip); 5211 if (retval != STATUS_SUCCESS) { 5212 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 5213 sd_card->pre_cmd_err = 1; 5214 rtsx_trace(chip); 5215 return TRANSPORT_FAILED; 5216 } 5217 break; 5218 5219 default: 5220 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 5221 rtsx_trace(chip); 5222 return TRANSPORT_FAILED; 5223 } 5224 5225 scsi_set_resid(srb, 0); 5226 return TRANSPORT_GOOD; 5227 } 5228 #endif 5229 5230 void sd_cleanup_work(struct rtsx_chip *chip) 5231 { 5232 struct sd_info *sd_card = &(chip->sd_card); 5233 5234 if (sd_card->seq_mode) { 5235 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n"); 5236 sd_stop_seq_mode(chip); 5237 sd_card->cleanup_counter = 0; 5238 } 5239 } 5240 5241 int sd_power_off_card3v3(struct rtsx_chip *chip) 5242 { 5243 int retval; 5244 5245 retval = disable_card_clock(chip, SD_CARD); 5246 if (retval != STATUS_SUCCESS) { 5247 rtsx_trace(chip); 5248 return STATUS_FAIL; 5249 } 5250 5251 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 5252 if (retval) { 5253 rtsx_trace(chip); 5254 return retval; 5255 } 5256 5257 if (!chip->ft2_fast_mode) { 5258 retval = card_power_off(chip, SD_CARD); 5259 if (retval != STATUS_SUCCESS) { 5260 rtsx_trace(chip); 5261 return STATUS_FAIL; 5262 } 5263 5264 wait_timeout(50); 5265 } 5266 5267 if (chip->asic_code) { 5268 retval = sd_pull_ctl_disable(chip); 5269 if (retval != STATUS_SUCCESS) { 5270 rtsx_trace(chip); 5271 return STATUS_FAIL; 5272 } 5273 } else { 5274 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 5275 FPGA_SD_PULL_CTL_BIT | 0x20, 5276 FPGA_SD_PULL_CTL_BIT); 5277 if (retval) { 5278 rtsx_trace(chip); 5279 return retval; 5280 } 5281 } 5282 5283 return STATUS_SUCCESS; 5284 } 5285 5286 int release_sd_card(struct rtsx_chip *chip) 5287 { 5288 struct sd_info *sd_card = &(chip->sd_card); 5289 int retval; 5290 5291 chip->card_ready &= ~SD_CARD; 5292 chip->card_fail &= ~SD_CARD; 5293 chip->card_wp &= ~SD_CARD; 5294 5295 chip->sd_io = 0; 5296 chip->sd_int = 0; 5297 5298 #ifdef SUPPORT_SD_LOCK 5299 sd_card->sd_lock_status = 0; 5300 sd_card->sd_erase_status = 0; 5301 #endif 5302 5303 memset(sd_card->raw_csd, 0, 16); 5304 memset(sd_card->raw_scr, 0, 8); 5305 5306 retval = sd_power_off_card3v3(chip); 5307 if (retval != STATUS_SUCCESS) { 5308 rtsx_trace(chip); 5309 return STATUS_FAIL; 5310 } 5311 5312 return STATUS_SUCCESS; 5313 } 5314