1 /* Driver for Realtek PCI-Express card reader 2 * Header file 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2, or (at your option) any 9 * later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 * 19 * Author: 20 * Wei WANG (wei_wang@realsil.com.cn) 21 * Micky Ching (micky_ching@realsil.com.cn) 22 */ 23 24 #ifndef __REALTEK_RTSX_CHIP_H 25 #define __REALTEK_RTSX_CHIP_H 26 27 #include "rtsx.h" 28 29 #define SUPPORT_CPRM 30 #define SUPPORT_OCP 31 #define SUPPORT_SDIO_ASPM 32 #define SUPPORT_MAGIC_GATE 33 #define SUPPORT_MSXC 34 #define SUPPORT_SD_LOCK 35 /* Hardware switch bus_ctl and cd_ctl automatically */ 36 #define HW_AUTO_SWITCH_SD_BUS 37 /* Enable hardware interrupt write clear */ 38 #define HW_INT_WRITE_CLR 39 /* #define LED_AUTO_BLINK */ 40 /* #define DISABLE_CARD_INT */ 41 42 #ifdef SUPPORT_MAGIC_GATE 43 /* Using NORMAL_WRITE instead of AUTO_WRITE to set ICV */ 44 #define MG_SET_ICV_SLOW 45 /* HW may miss ERR/CMDNK signal when sampling INT status. */ 46 #define MS_SAMPLE_INT_ERR 47 /* 48 * HW DO NOT support Wait_INT function 49 * during READ_BYTES transfer mode 50 */ 51 #define READ_BYTES_WAIT_INT 52 #endif 53 54 #ifdef SUPPORT_MSXC 55 #define XC_POWERCLASS 56 #define SUPPORT_PCGL_1P18 57 #endif 58 59 #ifndef LED_AUTO_BLINK 60 #define REGULAR_BLINK 61 #endif 62 63 #define LED_BLINK_SPEED 5 64 #define LED_TOGGLE_INTERVAL 6 65 #define GPIO_TOGGLE_THRESHOLD 1024 66 #define LED_GPIO 0 67 68 #define POLLING_INTERVAL 30 69 70 #define TRACE_ITEM_CNT 64 71 72 #ifndef STATUS_SUCCESS 73 #define STATUS_SUCCESS 0 74 #endif 75 #ifndef STATUS_FAIL 76 #define STATUS_FAIL 1 77 #endif 78 #ifndef STATUS_TIMEDOUT 79 #define STATUS_TIMEDOUT 2 80 #endif 81 #ifndef STATUS_NOMEM 82 #define STATUS_NOMEM 3 83 #endif 84 #ifndef STATUS_READ_FAIL 85 #define STATUS_READ_FAIL 4 86 #endif 87 #ifndef STATUS_WRITE_FAIL 88 #define STATUS_WRITE_FAIL 5 89 #endif 90 #ifndef STATUS_ERROR 91 #define STATUS_ERROR 10 92 #endif 93 94 #define PM_S1 1 95 #define PM_S3 3 96 97 /* 98 * Transport return codes 99 */ 100 101 #define TRANSPORT_GOOD 0 /* Transport good, command good */ 102 #define TRANSPORT_FAILED 1 /* Transport good, command failed */ 103 #define TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */ 104 #define TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */ 105 106 /* 107 * Start-Stop-Unit 108 */ 109 #define STOP_MEDIUM 0x00 /* access disable */ 110 #define MAKE_MEDIUM_READY 0x01 /* access enable */ 111 #define UNLOAD_MEDIUM 0x02 /* unload */ 112 #define LOAD_MEDIUM 0x03 /* load */ 113 114 /* 115 * STANDARD_INQUIRY 116 */ 117 #define QULIFIRE 0x00 118 #define AENC_FNC 0x00 119 #define TRML_IOP 0x00 120 #define REL_ADR 0x00 121 #define WBUS_32 0x00 122 #define WBUS_16 0x00 123 #define SYNC 0x00 124 #define LINKED 0x00 125 #define CMD_QUE 0x00 126 #define SFT_RE 0x00 127 128 #define VEN_ID_LEN 8 /* Vendor ID Length */ 129 #define PRDCT_ID_LEN 16 /* Product ID Length */ 130 #define PRDCT_REV_LEN 4 /* Product LOT Length */ 131 132 /* Dynamic flag definitions: used in set_bit() etc. */ 133 /* 0x00040000 transfer is active */ 134 #define RTSX_FLIDX_TRANS_ACTIVE 18 135 /* 0x00100000 abort is in progress */ 136 #define RTSX_FLIDX_ABORTING 20 137 /* 0x00200000 disconnect in progress */ 138 #define RTSX_FLIDX_DISCONNECTING 21 139 140 #define ABORTING_OR_DISCONNECTING ((1UL << US_FLIDX_ABORTING) | \ 141 (1UL << US_FLIDX_DISCONNECTING)) 142 143 /* 0x00400000 device reset in progress */ 144 #define RTSX_FLIDX_RESETTING 22 145 /* 0x00800000 SCSI midlayer timed out */ 146 #define RTSX_FLIDX_TIMED_OUT 23 147 #define DRCT_ACCESS_DEV 0x00 /* Direct Access Device */ 148 #define RMB_DISC 0x80 /* The Device is Removable */ 149 #define ANSI_SCSI2 0x02 /* Based on ANSI-SCSI2 */ 150 151 #define SCSI 0x00 /* Interface ID */ 152 153 #define WRITE_PROTECTED_MEDIA 0x07 154 155 /*---- sense key ----*/ 156 #define ILI 0x20 /* ILI bit is on */ 157 158 #define NO_SENSE 0x00 /* not exist sense key */ 159 #define RECOVER_ERR 0x01 /* Target/Logical unit is recoverd */ 160 #define NOT_READY 0x02 /* Logical unit is not ready */ 161 #define MEDIA_ERR 0x03 /* medium/data error */ 162 #define HARDWARE_ERR 0x04 /* hardware error */ 163 #define ILGAL_REQ 0x05 /* CDB/parameter/identify msg error */ 164 #define UNIT_ATTENTION 0x06 /* unit attention condition occur */ 165 #define DAT_PRTCT 0x07 /* read/write is desable */ 166 #define BLNC_CHK 0x08 /* find blank/DOF in read */ 167 /* write to unblank area */ 168 #define CPY_ABRT 0x0a /* Copy/Compare/Copy&Verify illgal */ 169 #define ABRT_CMD 0x0b /* Target make the command in error */ 170 #define EQUAL 0x0c /* Search Data end with Equal */ 171 #define VLM_OVRFLW 0x0d /* Some data are left in buffer */ 172 #define MISCMP 0x0e /* find inequality */ 173 174 #define READ_ERR -1 175 #define WRITE_ERR -2 176 177 #define FIRST_RESET 0x01 178 #define USED_EXIST 0x02 179 180 /* 181 * SENSE_DATA 182 */ 183 /*---- valid ----*/ 184 #define SENSE_VALID 0x80 /* Sense data is valid as SCSI2 */ 185 #define SENSE_INVALID 0x00 /* Sense data is invalid as SCSI2 */ 186 187 /*---- error code ----*/ 188 #define CUR_ERR 0x70 /* current error */ 189 #define DEF_ERR 0x71 /* specific command error */ 190 191 /*---- sense key Information ----*/ 192 #define SNSKEYINFO_LEN 3 /* length of sense key information */ 193 194 #define SKSV 0x80 195 #define CDB_ILLEGAL 0x40 196 #define DAT_ILLEGAL 0x00 197 #define BPV 0x08 198 #define BIT_ILLEGAL0 0 /* bit0 is illegal */ 199 #define BIT_ILLEGAL1 1 /* bit1 is illegal */ 200 #define BIT_ILLEGAL2 2 /* bit2 is illegal */ 201 #define BIT_ILLEGAL3 3 /* bit3 is illegal */ 202 #define BIT_ILLEGAL4 4 /* bit4 is illegal */ 203 #define BIT_ILLEGAL5 5 /* bit5 is illegal */ 204 #define BIT_ILLEGAL6 6 /* bit6 is illegal */ 205 #define BIT_ILLEGAL7 7 /* bit7 is illegal */ 206 207 /*---- ASC ----*/ 208 #define ASC_NO_INFO 0x00 209 #define ASC_MISCMP 0x1d 210 #define ASC_INVLD_CDB 0x24 211 #define ASC_INVLD_PARA 0x26 212 #define ASC_LU_NOT_READY 0x04 213 #define ASC_WRITE_ERR 0x0c 214 #define ASC_READ_ERR 0x11 215 #define ASC_LOAD_EJCT_ERR 0x53 216 #define ASC_MEDIA_NOT_PRESENT 0x3A 217 #define ASC_MEDIA_CHANGED 0x28 218 #define ASC_MEDIA_IN_PROCESS 0x04 219 #define ASC_WRITE_PROTECT 0x27 220 #define ASC_LUN_NOT_SUPPORTED 0x25 221 222 /*---- ASQC ----*/ 223 #define ASCQ_NO_INFO 0x00 224 #define ASCQ_MEDIA_IN_PROCESS 0x01 225 #define ASCQ_MISCMP 0x00 226 #define ASCQ_INVLD_CDB 0x00 227 #define ASCQ_INVLD_PARA 0x02 228 #define ASCQ_LU_NOT_READY 0x02 229 #define ASCQ_WRITE_ERR 0x02 230 #define ASCQ_READ_ERR 0x00 231 #define ASCQ_LOAD_EJCT_ERR 0x00 232 #define ASCQ_WRITE_PROTECT 0x00 233 234 struct sense_data_t { 235 unsigned char err_code; /* error code */ 236 /* bit7 : valid */ 237 /* (1 : SCSI2) */ 238 /* (0 : Vendor * specific) */ 239 /* bit6-0 : error * code */ 240 /* (0x70 : current * error) */ 241 /* (0x71 : specific command error) */ 242 unsigned char seg_no; /* segment No. */ 243 unsigned char sense_key; /* byte5 : ILI */ 244 /* bit3-0 : sense key */ 245 unsigned char info[4]; /* information */ 246 unsigned char ad_sense_len; /* additional sense data length */ 247 unsigned char cmd_info[4]; /* command specific information */ 248 unsigned char asc; /* ASC */ 249 unsigned char ascq; /* ASCQ */ 250 unsigned char rfu; /* FRU */ 251 unsigned char sns_key_info[3];/* sense key specific information */ 252 }; 253 254 /* PCI Operation Register Address */ 255 #define RTSX_HCBAR 0x00 256 #define RTSX_HCBCTLR 0x04 257 #define RTSX_HDBAR 0x08 258 #define RTSX_HDBCTLR 0x0C 259 #define RTSX_HAIMR 0x10 260 #define RTSX_BIPR 0x14 261 #define RTSX_BIER 0x18 262 263 /* Host command buffer control register */ 264 #define STOP_CMD (0x01 << 28) 265 266 /* Host data buffer control register */ 267 #define SDMA_MODE 0x00 268 #define ADMA_MODE (0x02 << 26) 269 #define STOP_DMA (0x01 << 28) 270 #define TRIG_DMA (0x01 << 31) 271 272 /* Bus interrupt pending register */ 273 #define CMD_DONE_INT BIT(31) 274 #define DATA_DONE_INT BIT(30) 275 #define TRANS_OK_INT BIT(29) 276 #define TRANS_FAIL_INT BIT(28) 277 #define XD_INT BIT(27) 278 #define MS_INT BIT(26) 279 #define SD_INT BIT(25) 280 #define GPIO0_INT BIT(24) 281 #define OC_INT BIT(23) 282 #define SD_WRITE_PROTECT BIT(19) 283 #define XD_EXIST BIT(18) 284 #define MS_EXIST BIT(17) 285 #define SD_EXIST BIT(16) 286 #define DELINK_INT GPIO0_INT 287 #define MS_OC_INT BIT(23) 288 #define SD_OC_INT BIT(22) 289 290 #define CARD_INT (XD_INT | MS_INT | SD_INT) 291 #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) 292 #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | CARD_INT | \ 293 GPIO0_INT | OC_INT) 294 295 #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) 296 297 /* Bus interrupt enable register */ 298 #define CMD_DONE_INT_EN BIT(31) 299 #define DATA_DONE_INT_EN BIT(30) 300 #define TRANS_OK_INT_EN BIT(29) 301 #define TRANS_FAIL_INT_EN BIT(28) 302 #define XD_INT_EN BIT(27) 303 #define MS_INT_EN BIT(26) 304 #define SD_INT_EN BIT(25) 305 #define GPIO0_INT_EN BIT(24) 306 #define OC_INT_EN BIT(23) 307 #define DELINK_INT_EN GPIO0_INT_EN 308 #define MS_OC_INT_EN BIT(23) 309 #define SD_OC_INT_EN BIT(22) 310 311 #define READ_REG_CMD 0 312 #define WRITE_REG_CMD 1 313 #define CHECK_REG_CMD 2 314 315 #define HOST_TO_DEVICE 0 316 #define DEVICE_TO_HOST 1 317 318 #define RTSX_RESV_BUF_LEN 4096 319 #define HOST_CMDS_BUF_LEN 1024 320 #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) 321 322 #define SD_NR 2 323 #define MS_NR 3 324 #define XD_NR 4 325 #define SPI_NR 7 326 #define SD_CARD BIT(SD_NR) 327 #define MS_CARD BIT(MS_NR) 328 #define XD_CARD BIT(XD_NR) 329 #define SPI_CARD BIT(SPI_NR) 330 331 #define MAX_ALLOWED_LUN_CNT 8 332 333 #define XD_FREE_TABLE_CNT 1200 334 #define MS_FREE_TABLE_CNT 512 335 336 /* Bit Operation */ 337 #define SET_BIT(data, idx) ((data) |= 1 << (idx)) 338 #define CLR_BIT(data, idx) ((data) &= ~(1 << (idx))) 339 #define CHK_BIT(data, idx) ((data) & (1 << (idx))) 340 341 /* SG descriptor */ 342 #define SG_INT 0x04 343 #define SG_END 0x02 344 #define SG_VALID 0x01 345 346 #define SG_NO_OP 0x00 347 #define SG_TRANS_DATA (0x02 << 4) 348 #define SG_LINK_DESC (0x03 << 4) 349 350 struct rtsx_chip; 351 352 typedef int (*card_rw_func)(struct scsi_cmnd *srb, struct rtsx_chip *chip, 353 u32 sec_addr, u16 sec_cnt); 354 355 /* Supported Clock */ 356 enum card_clock {CLK_20 = 1, CLK_30, CLK_40, CLK_50, CLK_60, 357 CLK_80, CLK_100, CLK_120, CLK_150, CLK_200}; 358 359 enum RTSX_STAT {RTSX_STAT_INIT, RTSX_STAT_IDLE, RTSX_STAT_RUN, RTSX_STAT_SS, 360 RTSX_STAT_DELINK, RTSX_STAT_SUSPEND, 361 RTSX_STAT_ABORT, RTSX_STAT_DISCONNECT}; 362 enum IC_VER {IC_VER_AB, IC_VER_C = 2, IC_VER_D = 3}; 363 364 #define MAX_RESET_CNT 3 365 366 /* For MS Card */ 367 #define MAX_DEFECTIVE_BLOCK 10 368 369 struct zone_entry { 370 u16 *l2p_table; 371 u16 *free_table; 372 u16 defect_list[MAX_DEFECTIVE_BLOCK]; /* For MS card only */ 373 int set_index; 374 int get_index; 375 int unused_blk_cnt; 376 int disable_count; 377 /* To indicate whether the L2P table of this zone has been built. */ 378 int build_flag; 379 }; 380 381 #define TYPE_SD 0x0000 382 #define TYPE_MMC 0x0001 383 384 /* TYPE_SD */ 385 #define SD_HS 0x0100 386 #define SD_SDR50 0x0200 387 #define SD_DDR50 0x0400 388 #define SD_SDR104 0x0800 389 #define SD_HCXC 0x1000 390 391 /* TYPE_MMC */ 392 #define MMC_26M 0x0100 393 #define MMC_52M 0x0200 394 #define MMC_4BIT 0x0400 395 #define MMC_8BIT 0x0800 396 #define MMC_SECTOR_MODE 0x1000 397 #define MMC_DDR52 0x2000 398 399 /* SD card */ 400 #define CHK_SD(sd_card) (((sd_card)->sd_type & 0xFF) == TYPE_SD) 401 #define CHK_SD_HS(sd_card) (CHK_SD(sd_card) && \ 402 ((sd_card)->sd_type & SD_HS)) 403 #define CHK_SD_SDR50(sd_card) (CHK_SD(sd_card) && \ 404 ((sd_card)->sd_type & SD_SDR50)) 405 #define CHK_SD_DDR50(sd_card) (CHK_SD(sd_card) && \ 406 ((sd_card)->sd_type & SD_DDR50)) 407 #define CHK_SD_SDR104(sd_card) (CHK_SD(sd_card) && \ 408 ((sd_card)->sd_type & SD_SDR104)) 409 #define CHK_SD_HCXC(sd_card) (CHK_SD(sd_card) && \ 410 ((sd_card)->sd_type & SD_HCXC)) 411 #define CHK_SD_HC(sd_card) (CHK_SD_HCXC(sd_card) && \ 412 ((sd_card)->capacity <= 0x4000000)) 413 #define CHK_SD_XC(sd_card) (CHK_SD_HCXC(sd_card) && \ 414 ((sd_card)->capacity > 0x4000000)) 415 #define CHK_SD30_SPEED(sd_card) (CHK_SD_SDR50(sd_card) || \ 416 CHK_SD_DDR50(sd_card) || \ 417 CHK_SD_SDR104(sd_card)) 418 419 #define SET_SD(sd_card) ((sd_card)->sd_type = TYPE_SD) 420 #define SET_SD_HS(sd_card) ((sd_card)->sd_type |= SD_HS) 421 #define SET_SD_SDR50(sd_card) ((sd_card)->sd_type |= SD_SDR50) 422 #define SET_SD_DDR50(sd_card) ((sd_card)->sd_type |= SD_DDR50) 423 #define SET_SD_SDR104(sd_card) ((sd_card)->sd_type |= SD_SDR104) 424 #define SET_SD_HCXC(sd_card) ((sd_card)->sd_type |= SD_HCXC) 425 426 #define CLR_SD_HS(sd_card) ((sd_card)->sd_type &= ~SD_HS) 427 #define CLR_SD_SDR50(sd_card) ((sd_card)->sd_type &= ~SD_SDR50) 428 #define CLR_SD_DDR50(sd_card) ((sd_card)->sd_type &= ~SD_DDR50) 429 #define CLR_SD_SDR104(sd_card) ((sd_card)->sd_type &= ~SD_SDR104) 430 #define CLR_SD_HCXC(sd_card) ((sd_card)->sd_type &= ~SD_HCXC) 431 432 /* MMC card */ 433 #define CHK_MMC(sd_card) (((sd_card)->sd_type & 0xFF) == \ 434 TYPE_MMC) 435 #define CHK_MMC_26M(sd_card) (CHK_MMC(sd_card) && \ 436 ((sd_card)->sd_type & MMC_26M)) 437 #define CHK_MMC_52M(sd_card) (CHK_MMC(sd_card) && \ 438 ((sd_card)->sd_type & MMC_52M)) 439 #define CHK_MMC_4BIT(sd_card) (CHK_MMC(sd_card) && \ 440 ((sd_card)->sd_type & MMC_4BIT)) 441 #define CHK_MMC_8BIT(sd_card) (CHK_MMC(sd_card) && \ 442 ((sd_card)->sd_type & MMC_8BIT)) 443 #define CHK_MMC_SECTOR_MODE(sd_card) (CHK_MMC(sd_card) && \ 444 ((sd_card)->sd_type & MMC_SECTOR_MODE)) 445 #define CHK_MMC_DDR52(sd_card) (CHK_MMC(sd_card) && \ 446 ((sd_card)->sd_type & MMC_DDR52)) 447 448 #define SET_MMC(sd_card) ((sd_card)->sd_type = TYPE_MMC) 449 #define SET_MMC_26M(sd_card) ((sd_card)->sd_type |= MMC_26M) 450 #define SET_MMC_52M(sd_card) ((sd_card)->sd_type |= MMC_52M) 451 #define SET_MMC_4BIT(sd_card) ((sd_card)->sd_type |= MMC_4BIT) 452 #define SET_MMC_8BIT(sd_card) ((sd_card)->sd_type |= MMC_8BIT) 453 #define SET_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type |= MMC_SECTOR_MODE) 454 #define SET_MMC_DDR52(sd_card) ((sd_card)->sd_type |= MMC_DDR52) 455 456 #define CLR_MMC_26M(sd_card) ((sd_card)->sd_type &= ~MMC_26M) 457 #define CLR_MMC_52M(sd_card) ((sd_card)->sd_type &= ~MMC_52M) 458 #define CLR_MMC_4BIT(sd_card) ((sd_card)->sd_type &= ~MMC_4BIT) 459 #define CLR_MMC_8BIT(sd_card) ((sd_card)->sd_type &= ~MMC_8BIT) 460 #define CLR_MMC_SECTOR_MODE(sd_card) ((sd_card)->sd_type &= ~MMC_SECTOR_MODE) 461 #define CLR_MMC_DDR52(sd_card) ((sd_card)->sd_type &= ~MMC_DDR52) 462 463 #define CHK_MMC_HS(sd_card) (CHK_MMC_52M(sd_card) && \ 464 CHK_MMC_26M(sd_card)) 465 #define CLR_MMC_HS(sd_card) \ 466 do { \ 467 CLR_MMC_DDR52(sd_card); \ 468 CLR_MMC_52M(sd_card); \ 469 CLR_MMC_26M(sd_card); \ 470 } while (0) 471 472 #define SD_SUPPORT_CLASS_TEN 0x01 473 #define SD_SUPPORT_1V8 0x02 474 475 #define SD_SET_CLASS_TEN(sd_card) ((sd_card)->sd_setting |= \ 476 SD_SUPPORT_CLASS_TEN) 477 #define SD_CHK_CLASS_TEN(sd_card) ((sd_card)->sd_setting & \ 478 SD_SUPPORT_CLASS_TEN) 479 #define SD_CLR_CLASS_TEN(sd_card) ((sd_card)->sd_setting &= \ 480 ~SD_SUPPORT_CLASS_TEN) 481 #define SD_SET_1V8(sd_card) ((sd_card)->sd_setting |= \ 482 SD_SUPPORT_1V8) 483 #define SD_CHK_1V8(sd_card) ((sd_card)->sd_setting & \ 484 SD_SUPPORT_1V8) 485 #define SD_CLR_1V8(sd_card) ((sd_card)->sd_setting &= \ 486 ~SD_SUPPORT_1V8) 487 488 struct sd_info { 489 u16 sd_type; 490 u8 err_code; 491 u8 sd_data_buf_ready; 492 u32 sd_addr; 493 u32 capacity; 494 495 u8 raw_csd[16]; 496 u8 raw_scr[8]; 497 498 /* Sequential RW */ 499 int seq_mode; 500 enum dma_data_direction pre_dir; 501 u32 pre_sec_addr; 502 u16 pre_sec_cnt; 503 504 int cleanup_counter; 505 506 int sd_clock; 507 508 int mmc_dont_switch_bus; 509 510 #ifdef SUPPORT_CPRM 511 int sd_pass_thru_en; 512 int pre_cmd_err; 513 u8 last_rsp_type; 514 u8 rsp[17]; 515 #endif 516 517 u8 func_group1_mask; 518 u8 func_group2_mask; 519 u8 func_group3_mask; 520 u8 func_group4_mask; 521 522 u8 sd_switch_fail; 523 u8 sd_read_phase; 524 525 #ifdef SUPPORT_SD_LOCK 526 u8 sd_lock_status; 527 u8 sd_erase_status; 528 u8 sd_lock_notify; 529 #endif 530 int need_retune; 531 }; 532 533 struct xd_delay_write_tag { 534 u32 old_phyblock; 535 u32 new_phyblock; 536 u32 logblock; 537 u8 pageoff; 538 u8 delay_write_flag; 539 }; 540 541 struct xd_info { 542 u8 maker_code; 543 u8 device_code; 544 u8 block_shift; 545 u8 page_off; 546 u8 addr_cycle; 547 u16 cis_block; 548 u8 multi_flag; 549 u8 err_code; 550 u32 capacity; 551 552 struct zone_entry *zone; 553 int zone_cnt; 554 555 struct xd_delay_write_tag delay_write; 556 int cleanup_counter; 557 558 int xd_clock; 559 }; 560 561 #define MODE_512_SEQ 0x01 562 #define MODE_2K_SEQ 0x02 563 564 #define TYPE_MS 0x0000 565 #define TYPE_MSPRO 0x0001 566 567 #define MS_4BIT 0x0100 568 #define MS_8BIT 0x0200 569 #define MS_HG 0x0400 570 #define MS_XC 0x0800 571 572 #define HG8BIT (MS_HG | MS_8BIT) 573 574 #define CHK_MSPRO(ms_card) (((ms_card)->ms_type & 0xFF) == TYPE_MSPRO) 575 #define CHK_HG8BIT(ms_card) (CHK_MSPRO(ms_card) && \ 576 (((ms_card)->ms_type & HG8BIT) == HG8BIT)) 577 #define CHK_MSXC(ms_card) (CHK_MSPRO(ms_card) && \ 578 ((ms_card)->ms_type & MS_XC)) 579 #define CHK_MSHG(ms_card) (CHK_MSPRO(ms_card) && \ 580 ((ms_card)->ms_type & MS_HG)) 581 582 #define CHK_MS8BIT(ms_card) (((ms_card)->ms_type & MS_8BIT)) 583 #define CHK_MS4BIT(ms_card) (((ms_card)->ms_type & MS_4BIT)) 584 585 struct ms_delay_write_tag { 586 u16 old_phyblock; 587 u16 new_phyblock; 588 u16 logblock; 589 u8 pageoff; 590 u8 delay_write_flag; 591 }; 592 593 struct ms_info { 594 u16 ms_type; 595 u8 block_shift; 596 u8 page_off; 597 u16 total_block; 598 u16 boot_block; 599 u32 capacity; 600 601 u8 check_ms_flow; 602 u8 switch_8bit_fail; 603 u8 err_code; 604 605 struct zone_entry *segment; 606 int segment_cnt; 607 608 int pro_under_formatting; 609 int format_status; 610 u16 progress; 611 u8 raw_sys_info[96]; 612 #ifdef SUPPORT_PCGL_1P18 613 u8 raw_model_name[48]; 614 #endif 615 616 u8 multi_flag; 617 618 /* Sequential RW */ 619 u8 seq_mode; 620 enum dma_data_direction pre_dir; 621 u32 pre_sec_addr; 622 u16 pre_sec_cnt; 623 u32 total_sec_cnt; 624 625 struct ms_delay_write_tag delay_write; 626 627 int cleanup_counter; 628 629 int ms_clock; 630 631 #ifdef SUPPORT_MAGIC_GATE 632 u8 magic_gate_id[16]; 633 u8 mg_entry_num; 634 int mg_auth; /* flag to indicate authentication process */ 635 #endif 636 }; 637 638 struct spi_info { 639 u8 use_clk; 640 u8 write_en; 641 u16 clk_div; 642 u8 err_code; 643 644 int spi_clock; 645 }; 646 647 #ifdef _MSG_TRACE 648 struct trace_msg_t { 649 u16 line; 650 #define MSG_FUNC_LEN 64 651 char func[MSG_FUNC_LEN]; 652 #define MSG_FILE_LEN 32 653 char file[MSG_FILE_LEN]; 654 #define TIME_VAL_LEN 16 655 u8 timeval_buf[TIME_VAL_LEN]; 656 u8 valid; 657 }; 658 #endif 659 660 /************/ 661 /* LUN mode */ 662 /************/ 663 /* Single LUN, support xD/SD/MS */ 664 #define DEFAULT_SINGLE 0 665 /* 2 LUN mode, support SD/MS */ 666 #define SD_MS_2LUN 1 667 /* Single LUN, but only support SD/MS, for Barossa LQFP */ 668 #define SD_MS_1LUN 2 669 670 #define LAST_LUN_MODE 2 671 672 /* Barossa package */ 673 #define QFN 0 674 #define LQFP 1 675 676 /******************/ 677 /* sd_ctl bit map */ 678 /******************/ 679 /* SD push point control, bit 0, 1 */ 680 #define SD_PUSH_POINT_CTL_MASK 0x03 681 #define SD_PUSH_POINT_DELAY 0x01 682 #define SD_PUSH_POINT_AUTO 0x02 683 /* SD sample point control, bit 2, 3 */ 684 #define SD_SAMPLE_POINT_CTL_MASK 0x0C 685 #define SD_SAMPLE_POINT_DELAY 0x04 686 #define SD_SAMPLE_POINT_AUTO 0x08 687 /* SD DDR Tx phase set by user, bit 4 */ 688 #define SD_DDR_TX_PHASE_SET_BY_USER 0x10 689 /* MMC DDR Tx phase set by user, bit 5 */ 690 #define MMC_DDR_TX_PHASE_SET_BY_USER 0x20 691 /* Support MMC DDR mode, bit 6 */ 692 #define SUPPORT_MMC_DDR_MODE 0x40 693 /* Reset MMC at first */ 694 #define RESET_MMC_FIRST 0x80 695 696 #define SEQ_START_CRITERIA 0x20 697 698 /* MS Power Class En */ 699 #define POWER_CLASS_2_EN 0x02 700 #define POWER_CLASS_1_EN 0x01 701 702 #define MAX_SHOW_CNT 10 703 #define MAX_RESET_CNT 3 704 705 #define SDIO_EXIST 0x01 706 #define SDIO_IGNORED 0x02 707 708 #define CHK_SDIO_EXIST(chip) ((chip)->sdio_func_exist & SDIO_EXIST) 709 #define SET_SDIO_EXIST(chip) ((chip)->sdio_func_exist |= SDIO_EXIST) 710 #define CLR_SDIO_EXIST(chip) ((chip)->sdio_func_exist &= ~SDIO_EXIST) 711 712 #define CHK_SDIO_IGNORED(chip) ((chip)->sdio_func_exist & SDIO_IGNORED) 713 #define SET_SDIO_IGNORED(chip) ((chip)->sdio_func_exist |= \ 714 SDIO_IGNORED) 715 #define CLR_SDIO_IGNORED(chip) ((chip)->sdio_func_exist &= \ 716 ~SDIO_IGNORED) 717 718 struct rtsx_chip { 719 struct rtsx_dev *rtsx; 720 721 u32 int_reg; /* Bus interrupt pending register */ 722 char max_lun; 723 void *context; 724 725 void *host_cmds_ptr; /* host commands buffer pointer */ 726 dma_addr_t host_cmds_addr; 727 int ci; /* Command Index */ 728 729 void *host_sg_tbl_ptr; /* SG descriptor table */ 730 dma_addr_t host_sg_tbl_addr; 731 int sgi; /* SG entry index */ 732 733 struct scsi_cmnd *srb; /* current srb */ 734 struct sense_data_t sense_buffer[MAX_ALLOWED_LUN_CNT]; 735 736 int cur_clk; /* current card clock */ 737 738 /* Current accessed card */ 739 int cur_card; 740 741 unsigned long need_release; /* need release bit map */ 742 unsigned long need_reset; /* need reset bit map */ 743 /* 744 * Flag to indicate that this card is just resumed from SS state, 745 * and need released before being resetted 746 */ 747 unsigned long need_reinit; 748 749 int rw_need_retry; 750 751 #ifdef SUPPORT_OCP 752 u32 ocp_int; 753 u8 ocp_stat; 754 #endif 755 756 u8 card_exist; /* card exist bit map (physical exist) */ 757 u8 card_ready; /* card ready bit map (reset successfully) */ 758 u8 card_fail; /* card reset fail bit map */ 759 u8 card_ejected; /* card ejected bit map */ 760 u8 card_wp; /* card write protected bit map */ 761 762 u8 lun_mc; /* 763 * flag to indicate whether to answer 764 * MediaChange 765 */ 766 767 #ifndef LED_AUTO_BLINK 768 int led_toggle_counter; 769 #endif 770 771 int sd_reset_counter; 772 int xd_reset_counter; 773 int ms_reset_counter; 774 775 /* card bus width */ 776 u8 card_bus_width[MAX_ALLOWED_LUN_CNT]; 777 /* card capacity */ 778 u32 capacity[MAX_ALLOWED_LUN_CNT]; 779 /* read/write card function pointer */ 780 card_rw_func rw_card[MAX_ALLOWED_LUN_CNT]; 781 /* read/write capacity, used for GPIO Toggle */ 782 u32 rw_cap[MAX_ALLOWED_LUN_CNT]; 783 /* card to lun mapping table */ 784 u8 card2lun[32]; 785 /* lun to card mapping table */ 786 u8 lun2card[MAX_ALLOWED_LUN_CNT]; 787 788 int rw_fail_cnt[MAX_ALLOWED_LUN_CNT]; 789 790 int sd_show_cnt; 791 int xd_show_cnt; 792 int ms_show_cnt; 793 794 /* card information */ 795 struct sd_info sd_card; 796 struct xd_info xd_card; 797 struct ms_info ms_card; 798 799 struct spi_info spi; 800 801 #ifdef _MSG_TRACE 802 struct trace_msg_t trace_msg[TRACE_ITEM_CNT]; 803 int msg_idx; 804 #endif 805 806 int auto_delink_cnt; 807 int auto_delink_allowed; 808 809 int aspm_enabled; 810 811 int sdio_aspm; 812 int sdio_idle; 813 int sdio_counter; 814 u8 sdio_raw_data[12]; 815 816 u8 sd_io; 817 u8 sd_int; 818 819 u8 rtsx_flag; 820 821 int ss_counter; 822 int idle_counter; 823 enum RTSX_STAT rtsx_stat; 824 825 u16 vendor_id; 826 u16 product_id; 827 u8 ic_version; 828 829 int driver_first_load; 830 831 #ifdef HW_AUTO_SWITCH_SD_BUS 832 int sdio_in_charge; 833 #endif 834 835 u8 aspm_level[2]; 836 837 int chip_insert_with_sdio; 838 839 /* Options */ 840 841 int adma_mode; 842 843 int auto_delink_en; 844 int ss_en; 845 u8 lun_mode; 846 u8 aspm_l0s_l1_en; 847 848 int power_down_in_ss; 849 850 int sdr104_en; 851 int ddr50_en; 852 int sdr50_en; 853 854 int baro_pkg; 855 856 int asic_code; 857 int phy_debug_mode; 858 int hw_bypass_sd; 859 int sdio_func_exist; 860 int aux_pwr_exist; 861 u8 ms_power_class_en; 862 863 int mspro_formatter_enable; 864 865 int remote_wakeup_en; 866 867 int ignore_sd; 868 int use_hw_setting; 869 870 int ss_idle_period; 871 872 int dynamic_aspm; 873 874 int fpga_sd_sdr104_clk; 875 int fpga_sd_ddr50_clk; 876 int fpga_sd_sdr50_clk; 877 int fpga_sd_hs_clk; 878 int fpga_mmc_52m_clk; 879 int fpga_ms_hg_clk; 880 int fpga_ms_4bit_clk; 881 int fpga_ms_1bit_clk; 882 883 int asic_sd_sdr104_clk; 884 int asic_sd_ddr50_clk; 885 int asic_sd_sdr50_clk; 886 int asic_sd_hs_clk; 887 int asic_mmc_52m_clk; 888 int asic_ms_hg_clk; 889 int asic_ms_4bit_clk; 890 int asic_ms_1bit_clk; 891 892 u8 ssc_depth_sd_sdr104; 893 u8 ssc_depth_sd_ddr50; 894 u8 ssc_depth_sd_sdr50; 895 u8 ssc_depth_sd_hs; 896 u8 ssc_depth_mmc_52m; 897 u8 ssc_depth_ms_hg; 898 u8 ssc_depth_ms_4bit; 899 u8 ssc_depth_low_speed; 900 901 u8 card_drive_sel; 902 u8 sd30_drive_sel_1v8; 903 u8 sd30_drive_sel_3v3; 904 905 u8 sd_400mA_ocp_thd; 906 u8 sd_800mA_ocp_thd; 907 u8 ms_ocp_thd; 908 909 int ssc_en; 910 int msi_en; 911 912 int xd_timeout; 913 int sd_timeout; 914 int ms_timeout; 915 int mspro_timeout; 916 917 int auto_power_down; 918 919 int sd_ddr_tx_phase; 920 int mmc_ddr_tx_phase; 921 int sd_default_tx_phase; 922 int sd_default_rx_phase; 923 924 int pmos_pwr_on_interval; 925 int sd_voltage_switch_delay; 926 int s3_pwr_off_delay; 927 928 int force_clkreq_0; 929 int ft2_fast_mode; 930 931 int do_delink_before_power_down; 932 int polling_config; 933 int sdio_retry_cnt; 934 935 int delink_stage1_step; 936 int delink_stage2_step; 937 int delink_stage3_step; 938 939 int auto_delink_in_L1; 940 int hp_watch_bios_hotplug; 941 int support_ms_8bit; 942 943 u8 blink_led; 944 u8 phy_voltage; 945 u8 max_payload; 946 947 u32 sd_speed_prior; 948 u32 sd_current_prior; 949 u32 sd_ctl; 950 }; 951 952 static inline struct device *rtsx_dev(const struct rtsx_chip *chip) 953 { 954 return &chip->rtsx->pci->dev; 955 } 956 957 #define rtsx_set_stat(chip, stat) \ 958 do { \ 959 if ((stat) != RTSX_STAT_IDLE) { \ 960 (chip)->idle_counter = 0; \ 961 } \ 962 (chip)->rtsx_stat = (enum RTSX_STAT)(stat); \ 963 } while (0) 964 #define rtsx_get_stat(chip) ((chip)->rtsx_stat) 965 #define rtsx_chk_stat(chip, stat) ((chip)->rtsx_stat == (stat)) 966 967 #define RTSX_SET_DELINK(chip) ((chip)->rtsx_flag |= 0x01) 968 #define RTSX_CLR_DELINK(chip) ((chip)->rtsx_flag &= 0xFE) 969 #define RTSX_TST_DELINK(chip) ((chip)->rtsx_flag & 0x01) 970 971 #define CHECK_PID(chip, pid) ((chip)->product_id == (pid)) 972 #define CHECK_BARO_PKG(chip, pkg) ((chip)->baro_pkg == (pkg)) 973 #define CHECK_LUN_MODE(chip, mode) ((chip)->lun_mode == (mode)) 974 975 /* Power down control */ 976 #define SSC_PDCTL 0x01 977 #define OC_PDCTL 0x02 978 979 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl); 980 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl); 981 982 void rtsx_enable_card_int(struct rtsx_chip *chip); 983 void rtsx_enable_bus_int(struct rtsx_chip *chip); 984 void rtsx_disable_bus_int(struct rtsx_chip *chip); 985 int rtsx_reset_chip(struct rtsx_chip *chip); 986 int rtsx_init_chip(struct rtsx_chip *chip); 987 void rtsx_release_chip(struct rtsx_chip *chip); 988 void rtsx_polling_func(struct rtsx_chip *chip); 989 void rtsx_stop_cmd(struct rtsx_chip *chip, int card); 990 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data); 991 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data); 992 int rtsx_write_cfg_dw(struct rtsx_chip *chip, 993 u8 func_no, u16 addr, u32 mask, u32 val); 994 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val); 995 int rtsx_write_cfg_seq(struct rtsx_chip *chip, 996 u8 func, u16 addr, u8 *buf, int len); 997 int rtsx_read_cfg_seq(struct rtsx_chip *chip, 998 u8 func, u16 addr, u8 *buf, int len); 999 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val); 1000 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val); 1001 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val); 1002 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val); 1003 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); 1004 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit); 1005 void rtsx_enter_ss(struct rtsx_chip *chip); 1006 void rtsx_exit_ss(struct rtsx_chip *chip); 1007 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip); 1008 void rtsx_enter_L1(struct rtsx_chip *chip); 1009 void rtsx_exit_L1(struct rtsx_chip *chip); 1010 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat); 1011 void rtsx_enable_aspm(struct rtsx_chip *chip); 1012 void rtsx_disable_aspm(struct rtsx_chip *chip); 1013 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); 1014 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len); 1015 int rtsx_check_chip_exist(struct rtsx_chip *chip); 1016 1017 #endif /* __REALTEK_RTSX_CHIP_H */ 1018