1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/workqueue.h> 27 #include <linux/kernel.h> 28 29 #include "rtsx.h" 30 #include "sd.h" 31 #include "xd.h" 32 #include "ms.h" 33 34 void do_remaining_work(struct rtsx_chip *chip) 35 { 36 struct sd_info *sd_card = &(chip->sd_card); 37 #ifdef XD_DELAY_WRITE 38 struct xd_info *xd_card = &(chip->xd_card); 39 #endif 40 struct ms_info *ms_card = &(chip->ms_card); 41 42 if (chip->card_ready & SD_CARD) { 43 if (sd_card->seq_mode) { 44 rtsx_set_stat(chip, RTSX_STAT_RUN); 45 sd_card->cleanup_counter++; 46 } else { 47 sd_card->cleanup_counter = 0; 48 } 49 } 50 51 #ifdef XD_DELAY_WRITE 52 if (chip->card_ready & XD_CARD) { 53 if (xd_card->delay_write.delay_write_flag) { 54 rtsx_set_stat(chip, RTSX_STAT_RUN); 55 xd_card->cleanup_counter++; 56 } else { 57 xd_card->cleanup_counter = 0; 58 } 59 } 60 #endif 61 62 if (chip->card_ready & MS_CARD) { 63 if (CHK_MSPRO(ms_card)) { 64 if (ms_card->seq_mode) { 65 rtsx_set_stat(chip, RTSX_STAT_RUN); 66 ms_card->cleanup_counter++; 67 } else { 68 ms_card->cleanup_counter = 0; 69 } 70 } else { 71 #ifdef MS_DELAY_WRITE 72 if (ms_card->delay_write.delay_write_flag) { 73 rtsx_set_stat(chip, RTSX_STAT_RUN); 74 ms_card->cleanup_counter++; 75 } else { 76 ms_card->cleanup_counter = 0; 77 } 78 #endif 79 } 80 } 81 82 if (sd_card->cleanup_counter > POLLING_WAIT_CNT) 83 sd_cleanup_work(chip); 84 85 if (xd_card->cleanup_counter > POLLING_WAIT_CNT) 86 xd_cleanup_work(chip); 87 88 if (ms_card->cleanup_counter > POLLING_WAIT_CNT) 89 ms_cleanup_work(chip); 90 } 91 92 void try_to_switch_sdio_ctrl(struct rtsx_chip *chip) 93 { 94 u8 reg1 = 0, reg2 = 0; 95 96 rtsx_read_register(chip, 0xFF34, ®1); 97 rtsx_read_register(chip, 0xFF38, ®2); 98 dev_dbg(rtsx_dev(chip), "reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", 99 reg1, reg2); 100 if ((reg1 & 0xC0) && (reg2 & 0xC0)) { 101 chip->sd_int = 1; 102 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 103 SDIO_BUS_CTRL | SDIO_CD_CTRL); 104 rtsx_write_register(chip, PWR_GATE_CTRL, 105 LDO3318_PWR_MASK, LDO_ON); 106 } 107 } 108 109 #ifdef SUPPORT_SDIO_ASPM 110 void dynamic_configure_sdio_aspm(struct rtsx_chip *chip) 111 { 112 u8 buf[12], reg; 113 int i; 114 115 for (i = 0; i < 12; i++) 116 rtsx_read_register(chip, 0xFF08 + i, &buf[i]); 117 rtsx_read_register(chip, 0xFF25, ®); 118 if ((memcmp(buf, chip->sdio_raw_data, 12) != 0) || (reg & 0x03)) { 119 chip->sdio_counter = 0; 120 chip->sdio_idle = 0; 121 } else { 122 if (!chip->sdio_idle) { 123 chip->sdio_counter++; 124 if (chip->sdio_counter >= SDIO_IDLE_COUNT) { 125 chip->sdio_counter = 0; 126 chip->sdio_idle = 1; 127 } 128 } 129 } 130 memcpy(chip->sdio_raw_data, buf, 12); 131 132 if (chip->sdio_idle) { 133 if (!chip->sdio_aspm) { 134 dev_dbg(rtsx_dev(chip), "SDIO enter ASPM!\n"); 135 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 136 0x30 | (chip->aspm_level[1] << 2)); 137 chip->sdio_aspm = 1; 138 } 139 } else { 140 if (chip->sdio_aspm) { 141 dev_dbg(rtsx_dev(chip), "SDIO exit ASPM!\n"); 142 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFC, 0x30); 143 chip->sdio_aspm = 0; 144 } 145 } 146 } 147 #endif 148 149 void do_reset_sd_card(struct rtsx_chip *chip) 150 { 151 int retval; 152 153 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 154 chip->sd_reset_counter, chip->card2lun[SD_CARD]); 155 156 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT) { 157 clear_bit(SD_NR, &(chip->need_reset)); 158 chip->sd_reset_counter = 0; 159 chip->sd_show_cnt = 0; 160 return; 161 } 162 163 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0; 164 165 rtsx_set_stat(chip, RTSX_STAT_RUN); 166 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 167 168 retval = reset_sd_card(chip); 169 if (chip->need_release & SD_CARD) 170 return; 171 if (retval == STATUS_SUCCESS) { 172 clear_bit(SD_NR, &(chip->need_reset)); 173 chip->sd_reset_counter = 0; 174 chip->sd_show_cnt = 0; 175 chip->card_ready |= SD_CARD; 176 chip->card_fail &= ~SD_CARD; 177 chip->rw_card[chip->card2lun[SD_CARD]] = sd_rw; 178 } else { 179 if (chip->sd_io || (chip->sd_reset_counter >= MAX_RESET_CNT)) { 180 clear_bit(SD_NR, &(chip->need_reset)); 181 chip->sd_reset_counter = 0; 182 chip->sd_show_cnt = 0; 183 } else { 184 chip->sd_reset_counter++; 185 } 186 chip->card_ready &= ~SD_CARD; 187 chip->card_fail |= SD_CARD; 188 chip->capacity[chip->card2lun[SD_CARD]] = 0; 189 chip->rw_card[chip->card2lun[SD_CARD]] = NULL; 190 191 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0); 192 if (!chip->ft2_fast_mode) 193 card_power_off(chip, SD_CARD); 194 if (chip->sd_io) { 195 chip->sd_int = 0; 196 try_to_switch_sdio_ctrl(chip); 197 } else { 198 disable_card_clock(chip, SD_CARD); 199 } 200 } 201 } 202 203 void do_reset_xd_card(struct rtsx_chip *chip) 204 { 205 int retval; 206 207 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 208 chip->xd_reset_counter, chip->card2lun[XD_CARD]); 209 210 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT) { 211 clear_bit(XD_NR, &(chip->need_reset)); 212 chip->xd_reset_counter = 0; 213 chip->xd_show_cnt = 0; 214 return; 215 } 216 217 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0; 218 219 rtsx_set_stat(chip, RTSX_STAT_RUN); 220 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 221 222 retval = reset_xd_card(chip); 223 if (chip->need_release & XD_CARD) 224 return; 225 if (retval == STATUS_SUCCESS) { 226 clear_bit(XD_NR, &(chip->need_reset)); 227 chip->xd_reset_counter = 0; 228 chip->card_ready |= XD_CARD; 229 chip->card_fail &= ~XD_CARD; 230 chip->rw_card[chip->card2lun[XD_CARD]] = xd_rw; 231 } else { 232 if (chip->xd_reset_counter >= MAX_RESET_CNT) { 233 clear_bit(XD_NR, &(chip->need_reset)); 234 chip->xd_reset_counter = 0; 235 chip->xd_show_cnt = 0; 236 } else { 237 chip->xd_reset_counter++; 238 } 239 chip->card_ready &= ~XD_CARD; 240 chip->card_fail |= XD_CARD; 241 chip->capacity[chip->card2lun[XD_CARD]] = 0; 242 chip->rw_card[chip->card2lun[XD_CARD]] = NULL; 243 244 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0); 245 if (!chip->ft2_fast_mode) 246 card_power_off(chip, XD_CARD); 247 disable_card_clock(chip, XD_CARD); 248 } 249 } 250 251 void do_reset_ms_card(struct rtsx_chip *chip) 252 { 253 int retval; 254 255 dev_dbg(rtsx_dev(chip), "%s: %d, card2lun = 0x%x\n", __func__, 256 chip->ms_reset_counter, chip->card2lun[MS_CARD]); 257 258 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT) { 259 clear_bit(MS_NR, &(chip->need_reset)); 260 chip->ms_reset_counter = 0; 261 chip->ms_show_cnt = 0; 262 return; 263 } 264 265 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0; 266 267 rtsx_set_stat(chip, RTSX_STAT_RUN); 268 rtsx_write_register(chip, SDIO_CTRL, 0xFF, 0); 269 270 retval = reset_ms_card(chip); 271 if (chip->need_release & MS_CARD) 272 return; 273 if (retval == STATUS_SUCCESS) { 274 clear_bit(MS_NR, &(chip->need_reset)); 275 chip->ms_reset_counter = 0; 276 chip->card_ready |= MS_CARD; 277 chip->card_fail &= ~MS_CARD; 278 chip->rw_card[chip->card2lun[MS_CARD]] = ms_rw; 279 } else { 280 if (chip->ms_reset_counter >= MAX_RESET_CNT) { 281 clear_bit(MS_NR, &(chip->need_reset)); 282 chip->ms_reset_counter = 0; 283 chip->ms_show_cnt = 0; 284 } else { 285 chip->ms_reset_counter++; 286 } 287 chip->card_ready &= ~MS_CARD; 288 chip->card_fail |= MS_CARD; 289 chip->capacity[chip->card2lun[MS_CARD]] = 0; 290 chip->rw_card[chip->card2lun[MS_CARD]] = NULL; 291 292 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 293 if (!chip->ft2_fast_mode) 294 card_power_off(chip, MS_CARD); 295 disable_card_clock(chip, MS_CARD); 296 } 297 } 298 299 static void release_sdio(struct rtsx_chip *chip) 300 { 301 if (chip->sd_io) { 302 rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, 303 SD_STOP | SD_CLR_ERR); 304 305 if (chip->chip_insert_with_sdio) { 306 chip->chip_insert_with_sdio = 0; 307 308 if (CHECK_PID(chip, 0x5288)) 309 rtsx_write_register(chip, 0xFE5A, 0x08, 0x00); 310 else 311 rtsx_write_register(chip, 0xFE70, 0x80, 0x00); 312 } 313 314 rtsx_write_register(chip, SDIO_CTRL, SDIO_CD_CTRL, 0); 315 chip->sd_io = 0; 316 } 317 } 318 319 void rtsx_power_off_card(struct rtsx_chip *chip) 320 { 321 if ((chip->card_ready & SD_CARD) || chip->sd_io) { 322 sd_cleanup_work(chip); 323 sd_power_off_card3v3(chip); 324 } 325 326 if (chip->card_ready & XD_CARD) { 327 xd_cleanup_work(chip); 328 xd_power_off_card3v3(chip); 329 } 330 331 if (chip->card_ready & MS_CARD) { 332 ms_cleanup_work(chip); 333 ms_power_off_card3v3(chip); 334 } 335 } 336 337 void rtsx_release_cards(struct rtsx_chip *chip) 338 { 339 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 340 341 if ((chip->card_ready & SD_CARD) || chip->sd_io) { 342 if (chip->int_reg & SD_EXIST) 343 sd_cleanup_work(chip); 344 release_sd_card(chip); 345 } 346 347 if (chip->card_ready & XD_CARD) { 348 if (chip->int_reg & XD_EXIST) 349 xd_cleanup_work(chip); 350 release_xd_card(chip); 351 } 352 353 if (chip->card_ready & MS_CARD) { 354 if (chip->int_reg & MS_EXIST) 355 ms_cleanup_work(chip); 356 release_ms_card(chip); 357 } 358 } 359 360 void rtsx_reset_cards(struct rtsx_chip *chip) 361 { 362 if (!chip->need_reset) 363 return; 364 365 rtsx_set_stat(chip, RTSX_STAT_RUN); 366 367 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 368 369 rtsx_disable_aspm(chip); 370 371 if ((chip->need_reset & SD_CARD) && chip->chip_insert_with_sdio) 372 clear_bit(SD_NR, &(chip->need_reset)); 373 374 if (chip->need_reset & XD_CARD) { 375 chip->card_exist |= XD_CARD; 376 377 if (chip->xd_show_cnt >= MAX_SHOW_CNT) 378 do_reset_xd_card(chip); 379 else 380 chip->xd_show_cnt++; 381 } 382 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) { 383 if (chip->card_exist & XD_CARD) { 384 clear_bit(SD_NR, &(chip->need_reset)); 385 clear_bit(MS_NR, &(chip->need_reset)); 386 } 387 } 388 if (chip->need_reset & SD_CARD) { 389 chip->card_exist |= SD_CARD; 390 391 if (chip->sd_show_cnt >= MAX_SHOW_CNT) { 392 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 393 do_reset_sd_card(chip); 394 } else { 395 chip->sd_show_cnt++; 396 } 397 } 398 if (chip->need_reset & MS_CARD) { 399 chip->card_exist |= MS_CARD; 400 401 if (chip->ms_show_cnt >= MAX_SHOW_CNT) 402 do_reset_ms_card(chip); 403 else 404 chip->ms_show_cnt++; 405 } 406 } 407 408 void rtsx_reinit_cards(struct rtsx_chip *chip, int reset_chip) 409 { 410 rtsx_set_stat(chip, RTSX_STAT_RUN); 411 412 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 413 414 if (reset_chip) 415 rtsx_reset_chip(chip); 416 417 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 418 419 if ((chip->int_reg & SD_EXIST) && (chip->need_reinit & SD_CARD)) { 420 release_sdio(chip); 421 release_sd_card(chip); 422 423 wait_timeout(100); 424 425 chip->card_exist |= SD_CARD; 426 do_reset_sd_card(chip); 427 } 428 429 if ((chip->int_reg & XD_EXIST) && (chip->need_reinit & XD_CARD)) { 430 release_xd_card(chip); 431 432 wait_timeout(100); 433 434 chip->card_exist |= XD_CARD; 435 do_reset_xd_card(chip); 436 } 437 438 if ((chip->int_reg & MS_EXIST) && (chip->need_reinit & MS_CARD)) { 439 release_ms_card(chip); 440 441 wait_timeout(100); 442 443 chip->card_exist |= MS_CARD; 444 do_reset_ms_card(chip); 445 } 446 447 chip->need_reinit = 0; 448 } 449 450 #ifdef DISABLE_CARD_INT 451 void card_cd_debounce(struct rtsx_chip *chip, unsigned long *need_reset, 452 unsigned long *need_release) 453 { 454 u8 release_map = 0, reset_map = 0; 455 456 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 457 458 if (chip->card_exist) { 459 if (chip->card_exist & XD_CARD) { 460 if (!(chip->int_reg & XD_EXIST)) 461 release_map |= XD_CARD; 462 } else if (chip->card_exist & SD_CARD) { 463 if (!(chip->int_reg & SD_EXIST)) 464 release_map |= SD_CARD; 465 } else if (chip->card_exist & MS_CARD) { 466 if (!(chip->int_reg & MS_EXIST)) 467 release_map |= MS_CARD; 468 } 469 } else { 470 if (chip->int_reg & XD_EXIST) 471 reset_map |= XD_CARD; 472 else if (chip->int_reg & SD_EXIST) 473 reset_map |= SD_CARD; 474 else if (chip->int_reg & MS_EXIST) 475 reset_map |= MS_CARD; 476 } 477 478 if (reset_map) { 479 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0; 480 int i; 481 482 for (i = 0; i < (DEBOUNCE_CNT); i++) { 483 chip->int_reg = rtsx_readl(chip, RTSX_BIPR); 484 485 if (chip->int_reg & XD_EXIST) 486 xd_cnt++; 487 else 488 xd_cnt = 0; 489 490 if (chip->int_reg & SD_EXIST) 491 sd_cnt++; 492 else 493 sd_cnt = 0; 494 495 if (chip->int_reg & MS_EXIST) 496 ms_cnt++; 497 else 498 ms_cnt = 0; 499 500 wait_timeout(30); 501 } 502 503 reset_map = 0; 504 if (!(chip->card_exist & XD_CARD) && 505 (xd_cnt > (DEBOUNCE_CNT-1))) 506 reset_map |= XD_CARD; 507 if (!(chip->card_exist & SD_CARD) && 508 (sd_cnt > (DEBOUNCE_CNT-1))) 509 reset_map |= SD_CARD; 510 if (!(chip->card_exist & MS_CARD) && 511 (ms_cnt > (DEBOUNCE_CNT-1))) 512 reset_map |= MS_CARD; 513 } 514 515 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) 516 rtsx_write_register(chip, HOST_SLEEP_STATE, 0xC0, 0x00); 517 518 if (need_reset) 519 *need_reset = reset_map; 520 if (need_release) 521 *need_release = release_map; 522 } 523 #endif 524 525 void rtsx_init_cards(struct rtsx_chip *chip) 526 { 527 if (RTSX_TST_DELINK(chip) && (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 528 dev_dbg(rtsx_dev(chip), "Reset chip in polling thread!\n"); 529 rtsx_reset_chip(chip); 530 RTSX_CLR_DELINK(chip); 531 } 532 533 #ifdef DISABLE_CARD_INT 534 card_cd_debounce(chip, &(chip->need_reset), &(chip->need_release)); 535 #endif 536 537 if (chip->need_release) { 538 if (CHECK_PID(chip, 0x5288) && CHECK_BARO_PKG(chip, QFN)) { 539 if (chip->int_reg & XD_EXIST) { 540 clear_bit(SD_NR, &(chip->need_release)); 541 clear_bit(MS_NR, &(chip->need_release)); 542 } 543 } 544 545 if (!(chip->card_exist & SD_CARD) && !chip->sd_io) 546 clear_bit(SD_NR, &(chip->need_release)); 547 if (!(chip->card_exist & XD_CARD)) 548 clear_bit(XD_NR, &(chip->need_release)); 549 if (!(chip->card_exist & MS_CARD)) 550 clear_bit(MS_NR, &(chip->need_release)); 551 552 dev_dbg(rtsx_dev(chip), "chip->need_release = 0x%x\n", 553 (unsigned int)(chip->need_release)); 554 555 #ifdef SUPPORT_OCP 556 if (chip->need_release) { 557 if (chip->ocp_stat & (CARD_OC_NOW | CARD_OC_EVER)) 558 rtsx_write_register(chip, OCPCLR, 559 CARD_OC_INT_CLR | CARD_OC_CLR, 560 CARD_OC_INT_CLR | CARD_OC_CLR); 561 chip->ocp_stat = 0; 562 } 563 #endif 564 if (chip->need_release) { 565 rtsx_set_stat(chip, RTSX_STAT_RUN); 566 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL); 567 } 568 569 if (chip->need_release & SD_CARD) { 570 clear_bit(SD_NR, &(chip->need_release)); 571 chip->card_exist &= ~SD_CARD; 572 chip->card_ejected &= ~SD_CARD; 573 chip->card_fail &= ~SD_CARD; 574 CLR_BIT(chip->lun_mc, chip->card2lun[SD_CARD]); 575 chip->rw_fail_cnt[chip->card2lun[SD_CARD]] = 0; 576 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 577 578 release_sdio(chip); 579 release_sd_card(chip); 580 } 581 582 if (chip->need_release & XD_CARD) { 583 clear_bit(XD_NR, &(chip->need_release)); 584 chip->card_exist &= ~XD_CARD; 585 chip->card_ejected &= ~XD_CARD; 586 chip->card_fail &= ~XD_CARD; 587 CLR_BIT(chip->lun_mc, chip->card2lun[XD_CARD]); 588 chip->rw_fail_cnt[chip->card2lun[XD_CARD]] = 0; 589 590 release_xd_card(chip); 591 592 if (CHECK_PID(chip, 0x5288) && 593 CHECK_BARO_PKG(chip, QFN)) 594 rtsx_write_register(chip, HOST_SLEEP_STATE, 595 0xC0, 0xC0); 596 } 597 598 if (chip->need_release & MS_CARD) { 599 clear_bit(MS_NR, &(chip->need_release)); 600 chip->card_exist &= ~MS_CARD; 601 chip->card_ejected &= ~MS_CARD; 602 chip->card_fail &= ~MS_CARD; 603 CLR_BIT(chip->lun_mc, chip->card2lun[MS_CARD]); 604 chip->rw_fail_cnt[chip->card2lun[MS_CARD]] = 0; 605 606 release_ms_card(chip); 607 } 608 609 dev_dbg(rtsx_dev(chip), "chip->card_exist = 0x%x\n", 610 chip->card_exist); 611 612 if (!chip->card_exist) 613 turn_off_led(chip, LED_GPIO); 614 } 615 616 if (chip->need_reset) { 617 dev_dbg(rtsx_dev(chip), "chip->need_reset = 0x%x\n", 618 (unsigned int)(chip->need_reset)); 619 620 rtsx_reset_cards(chip); 621 } 622 623 if (chip->need_reinit) { 624 dev_dbg(rtsx_dev(chip), "chip->need_reinit = 0x%x\n", 625 (unsigned int)(chip->need_reinit)); 626 627 rtsx_reinit_cards(chip, 0); 628 } 629 } 630 631 static inline u8 double_depth(u8 depth) 632 { 633 return (depth > 1) ? (depth - 1) : depth; 634 } 635 636 int switch_ssc_clock(struct rtsx_chip *chip, int clk) 637 { 638 int retval; 639 u8 N = (u8)(clk - 2), min_N, max_N; 640 u8 mcu_cnt, div, max_div, ssc_depth, ssc_depth_mask; 641 int sd_vpclk_phase_reset = 0; 642 643 if (chip->cur_clk == clk) 644 return STATUS_SUCCESS; 645 646 min_N = 60; 647 max_N = 120; 648 max_div = CLK_DIV_4; 649 650 dev_dbg(rtsx_dev(chip), "Switch SSC clock to %dMHz (cur_clk = %d)\n", 651 clk, chip->cur_clk); 652 653 if ((clk <= 2) || (N > max_N)) { 654 rtsx_trace(chip); 655 return STATUS_FAIL; 656 } 657 658 mcu_cnt = (u8)(125/clk + 3); 659 if (mcu_cnt > 7) 660 mcu_cnt = 7; 661 662 div = CLK_DIV_1; 663 while ((N < min_N) && (div < max_div)) { 664 N = (N + 2) * 2 - 2; 665 div++; 666 } 667 dev_dbg(rtsx_dev(chip), "N = %d, div = %d\n", N, div); 668 669 if (chip->ssc_en) { 670 ssc_depth = 0x01; 671 N -= 2; 672 } else { 673 ssc_depth = 0; 674 } 675 676 ssc_depth_mask = 0x03; 677 678 dev_dbg(rtsx_dev(chip), "ssc_depth = %d\n", ssc_depth); 679 680 rtsx_init_cmd(chip); 681 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, CLK_LOW_FREQ); 682 rtsx_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0xFF, (div << 4) | mcu_cnt); 683 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0); 684 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, ssc_depth_mask, ssc_depth); 685 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N); 686 rtsx_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, SSC_RSTB); 687 if (sd_vpclk_phase_reset) { 688 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 689 PHASE_NOT_RESET, 0); 690 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, 691 PHASE_NOT_RESET, PHASE_NOT_RESET); 692 } 693 694 retval = rtsx_send_cmd(chip, 0, WAIT_TIME); 695 if (retval < 0) { 696 rtsx_trace(chip); 697 return STATUS_ERROR; 698 } 699 700 udelay(10); 701 retval = rtsx_write_register(chip, CLK_CTL, CLK_LOW_FREQ, 0); 702 if (retval) { 703 rtsx_trace(chip); 704 return retval; 705 } 706 707 chip->cur_clk = clk; 708 709 return STATUS_SUCCESS; 710 } 711 712 int switch_normal_clock(struct rtsx_chip *chip, int clk) 713 { 714 int retval; 715 u8 sel, div, mcu_cnt; 716 int sd_vpclk_phase_reset = 0; 717 718 if (chip->cur_clk == clk) 719 return STATUS_SUCCESS; 720 721 switch (clk) { 722 case CLK_20: 723 dev_dbg(rtsx_dev(chip), "Switch clock to 20MHz\n"); 724 sel = SSC_80; 725 div = CLK_DIV_4; 726 mcu_cnt = 7; 727 break; 728 729 case CLK_30: 730 dev_dbg(rtsx_dev(chip), "Switch clock to 30MHz\n"); 731 sel = SSC_120; 732 div = CLK_DIV_4; 733 mcu_cnt = 7; 734 break; 735 736 case CLK_40: 737 dev_dbg(rtsx_dev(chip), "Switch clock to 40MHz\n"); 738 sel = SSC_80; 739 div = CLK_DIV_2; 740 mcu_cnt = 7; 741 break; 742 743 case CLK_50: 744 dev_dbg(rtsx_dev(chip), "Switch clock to 50MHz\n"); 745 sel = SSC_100; 746 div = CLK_DIV_2; 747 mcu_cnt = 6; 748 break; 749 750 case CLK_60: 751 dev_dbg(rtsx_dev(chip), "Switch clock to 60MHz\n"); 752 sel = SSC_120; 753 div = CLK_DIV_2; 754 mcu_cnt = 6; 755 break; 756 757 case CLK_80: 758 dev_dbg(rtsx_dev(chip), "Switch clock to 80MHz\n"); 759 sel = SSC_80; 760 div = CLK_DIV_1; 761 mcu_cnt = 5; 762 break; 763 764 case CLK_100: 765 dev_dbg(rtsx_dev(chip), "Switch clock to 100MHz\n"); 766 sel = SSC_100; 767 div = CLK_DIV_1; 768 mcu_cnt = 5; 769 break; 770 771 case CLK_120: 772 dev_dbg(rtsx_dev(chip), "Switch clock to 120MHz\n"); 773 sel = SSC_120; 774 div = CLK_DIV_1; 775 mcu_cnt = 5; 776 break; 777 778 case CLK_150: 779 dev_dbg(rtsx_dev(chip), "Switch clock to 150MHz\n"); 780 sel = SSC_150; 781 div = CLK_DIV_1; 782 mcu_cnt = 4; 783 break; 784 785 case CLK_200: 786 dev_dbg(rtsx_dev(chip), "Switch clock to 200MHz\n"); 787 sel = SSC_200; 788 div = CLK_DIV_1; 789 mcu_cnt = 4; 790 break; 791 792 default: 793 dev_dbg(rtsx_dev(chip), "Try to switch to an illegal clock (%d)\n", 794 clk); 795 rtsx_trace(chip); 796 return STATUS_FAIL; 797 } 798 799 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, CLK_LOW_FREQ); 800 if (retval) { 801 rtsx_trace(chip); 802 return retval; 803 } 804 if (sd_vpclk_phase_reset) { 805 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 806 PHASE_NOT_RESET, 0); 807 if (retval) { 808 rtsx_trace(chip); 809 return retval; 810 } 811 retval = rtsx_write_register(chip, SD_VPCLK1_CTL, 812 PHASE_NOT_RESET, 0); 813 if (retval) { 814 rtsx_trace(chip); 815 return retval; 816 } 817 } 818 retval = rtsx_write_register(chip, CLK_DIV, 0xFF, 819 (div << 4) | mcu_cnt); 820 if (retval) { 821 rtsx_trace(chip); 822 return retval; 823 } 824 retval = rtsx_write_register(chip, CLK_SEL, 0xFF, sel); 825 if (retval) { 826 rtsx_trace(chip); 827 return retval; 828 } 829 830 if (sd_vpclk_phase_reset) { 831 udelay(200); 832 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, 833 PHASE_NOT_RESET, PHASE_NOT_RESET); 834 if (retval) { 835 rtsx_trace(chip); 836 return retval; 837 } 838 retval = rtsx_write_register(chip, SD_VPCLK1_CTL, 839 PHASE_NOT_RESET, PHASE_NOT_RESET); 840 if (retval) { 841 rtsx_trace(chip); 842 return retval; 843 } 844 udelay(200); 845 } 846 retval = rtsx_write_register(chip, CLK_CTL, 0xFF, 0); 847 if (retval) { 848 rtsx_trace(chip); 849 return retval; 850 } 851 852 chip->cur_clk = clk; 853 854 return STATUS_SUCCESS; 855 } 856 857 void trans_dma_enable(enum dma_data_direction dir, struct rtsx_chip *chip, 858 u32 byte_cnt, u8 pack_size) 859 { 860 if (pack_size > DMA_1024) 861 pack_size = DMA_512; 862 863 rtsx_add_cmd(chip, WRITE_REG_CMD, IRQSTAT0, DMA_DONE_INT, DMA_DONE_INT); 864 865 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC3, 0xFF, (u8)(byte_cnt >> 24)); 866 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC2, 0xFF, (u8)(byte_cnt >> 16)); 867 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC1, 0xFF, (u8)(byte_cnt >> 8)); 868 rtsx_add_cmd(chip, WRITE_REG_CMD, DMATC0, 0xFF, (u8)byte_cnt); 869 870 if (dir == DMA_FROM_DEVICE) { 871 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 872 0x03 | DMA_PACK_SIZE_MASK, 873 DMA_DIR_FROM_CARD | DMA_EN | pack_size); 874 } else { 875 rtsx_add_cmd(chip, WRITE_REG_CMD, DMACTL, 876 0x03 | DMA_PACK_SIZE_MASK, 877 DMA_DIR_TO_CARD | DMA_EN | pack_size); 878 } 879 880 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER); 881 } 882 883 int enable_card_clock(struct rtsx_chip *chip, u8 card) 884 { 885 int retval; 886 u8 clk_en = 0; 887 888 if (card & XD_CARD) 889 clk_en |= XD_CLK_EN; 890 if (card & SD_CARD) 891 clk_en |= SD_CLK_EN; 892 if (card & MS_CARD) 893 clk_en |= MS_CLK_EN; 894 895 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, clk_en); 896 if (retval) { 897 rtsx_trace(chip); 898 return retval; 899 } 900 901 return STATUS_SUCCESS; 902 } 903 904 int disable_card_clock(struct rtsx_chip *chip, u8 card) 905 { 906 int retval; 907 u8 clk_en = 0; 908 909 if (card & XD_CARD) 910 clk_en |= XD_CLK_EN; 911 if (card & SD_CARD) 912 clk_en |= SD_CLK_EN; 913 if (card & MS_CARD) 914 clk_en |= MS_CLK_EN; 915 916 retval = rtsx_write_register(chip, CARD_CLK_EN, clk_en, 0); 917 if (retval) { 918 rtsx_trace(chip); 919 return retval; 920 } 921 922 return STATUS_SUCCESS; 923 } 924 925 int card_power_on(struct rtsx_chip *chip, u8 card) 926 { 927 int retval; 928 u8 mask, val1, val2; 929 930 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) { 931 mask = MS_POWER_MASK; 932 val1 = MS_PARTIAL_POWER_ON; 933 val2 = MS_POWER_ON; 934 } else { 935 mask = SD_POWER_MASK; 936 val1 = SD_PARTIAL_POWER_ON; 937 val2 = SD_POWER_ON; 938 } 939 940 rtsx_init_cmd(chip); 941 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val1); 942 943 retval = rtsx_send_cmd(chip, 0, 100); 944 if (retval != STATUS_SUCCESS) { 945 rtsx_trace(chip); 946 return STATUS_FAIL; 947 } 948 949 udelay(chip->pmos_pwr_on_interval); 950 951 rtsx_init_cmd(chip); 952 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, mask, val2); 953 954 retval = rtsx_send_cmd(chip, 0, 100); 955 if (retval != STATUS_SUCCESS) { 956 rtsx_trace(chip); 957 return STATUS_FAIL; 958 } 959 960 return STATUS_SUCCESS; 961 } 962 963 int card_power_off(struct rtsx_chip *chip, u8 card) 964 { 965 int retval; 966 u8 mask, val; 967 968 if (CHECK_LUN_MODE(chip, SD_MS_2LUN) && (card == MS_CARD)) { 969 mask = MS_POWER_MASK; 970 val = MS_POWER_OFF; 971 } else { 972 mask = SD_POWER_MASK; 973 val = SD_POWER_OFF; 974 } 975 976 retval = rtsx_write_register(chip, CARD_PWR_CTL, mask, val); 977 if (retval) { 978 rtsx_trace(chip); 979 return retval; 980 } 981 982 return STATUS_SUCCESS; 983 } 984 985 int card_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 986 u32 sec_addr, u16 sec_cnt) 987 { 988 int retval; 989 unsigned int lun = SCSI_LUN(srb); 990 int i; 991 992 if (chip->rw_card[lun] == NULL) { 993 rtsx_trace(chip); 994 return STATUS_FAIL; 995 } 996 997 for (i = 0; i < 3; i++) { 998 chip->rw_need_retry = 0; 999 1000 retval = chip->rw_card[lun](srb, chip, sec_addr, sec_cnt); 1001 if (retval != STATUS_SUCCESS) { 1002 if (rtsx_check_chip_exist(chip) != STATUS_SUCCESS) { 1003 rtsx_release_chip(chip); 1004 rtsx_trace(chip); 1005 return STATUS_FAIL; 1006 } 1007 if (detect_card_cd(chip, chip->cur_card) != 1008 STATUS_SUCCESS) { 1009 rtsx_trace(chip); 1010 return STATUS_FAIL; 1011 } 1012 1013 if (!chip->rw_need_retry) { 1014 dev_dbg(rtsx_dev(chip), "RW fail, but no need to retry\n"); 1015 break; 1016 } 1017 } else { 1018 chip->rw_need_retry = 0; 1019 break; 1020 } 1021 1022 dev_dbg(rtsx_dev(chip), "Retry RW, (i = %d)\n", i); 1023 } 1024 1025 return retval; 1026 } 1027 1028 int card_share_mode(struct rtsx_chip *chip, int card) 1029 { 1030 int retval; 1031 u8 mask, value; 1032 1033 if (CHECK_PID(chip, 0x5208)) { 1034 mask = CARD_SHARE_MASK; 1035 if (card == SD_CARD) 1036 value = CARD_SHARE_48_SD; 1037 else if (card == MS_CARD) 1038 value = CARD_SHARE_48_MS; 1039 else if (card == XD_CARD) 1040 value = CARD_SHARE_48_XD; 1041 else { 1042 rtsx_trace(chip); 1043 return STATUS_FAIL; 1044 } 1045 1046 } else if (CHECK_PID(chip, 0x5288)) { 1047 mask = 0x03; 1048 if (card == SD_CARD) 1049 value = CARD_SHARE_BAROSSA_SD; 1050 else if (card == MS_CARD) 1051 value = CARD_SHARE_BAROSSA_MS; 1052 else if (card == XD_CARD) 1053 value = CARD_SHARE_BAROSSA_XD; 1054 else { 1055 rtsx_trace(chip); 1056 return STATUS_FAIL; 1057 } 1058 1059 } else { 1060 rtsx_trace(chip); 1061 return STATUS_FAIL; 1062 } 1063 1064 retval = rtsx_write_register(chip, CARD_SHARE_MODE, mask, value); 1065 if (retval) { 1066 rtsx_trace(chip); 1067 return retval; 1068 } 1069 1070 return STATUS_SUCCESS; 1071 } 1072 1073 1074 int select_card(struct rtsx_chip *chip, int card) 1075 { 1076 int retval; 1077 1078 if (chip->cur_card != card) { 1079 u8 mod; 1080 1081 if (card == SD_CARD) 1082 mod = SD_MOD_SEL; 1083 else if (card == MS_CARD) 1084 mod = MS_MOD_SEL; 1085 else if (card == XD_CARD) 1086 mod = XD_MOD_SEL; 1087 else if (card == SPI_CARD) 1088 mod = SPI_MOD_SEL; 1089 else { 1090 rtsx_trace(chip); 1091 return STATUS_FAIL; 1092 } 1093 1094 retval = rtsx_write_register(chip, CARD_SELECT, 0x07, mod); 1095 if (retval) { 1096 rtsx_trace(chip); 1097 return retval; 1098 } 1099 chip->cur_card = card; 1100 1101 retval = card_share_mode(chip, card); 1102 if (retval != STATUS_SUCCESS) { 1103 rtsx_trace(chip); 1104 return STATUS_FAIL; 1105 } 1106 } 1107 1108 return STATUS_SUCCESS; 1109 } 1110 1111 void toggle_gpio(struct rtsx_chip *chip, u8 gpio) 1112 { 1113 u8 temp_reg; 1114 1115 rtsx_read_register(chip, CARD_GPIO, &temp_reg); 1116 temp_reg ^= (0x01 << gpio); 1117 rtsx_write_register(chip, CARD_GPIO, 0xFF, temp_reg); 1118 } 1119 1120 void turn_on_led(struct rtsx_chip *chip, u8 gpio) 1121 { 1122 if (CHECK_PID(chip, 0x5288)) 1123 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 1124 (u8)(1 << gpio)); 1125 else 1126 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); 1127 } 1128 1129 void turn_off_led(struct rtsx_chip *chip, u8 gpio) 1130 { 1131 if (CHECK_PID(chip, 0x5288)) 1132 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 0); 1133 else 1134 rtsx_write_register(chip, CARD_GPIO, (u8)(1 << gpio), 1135 (u8)(1 << gpio)); 1136 } 1137 1138 int detect_card_cd(struct rtsx_chip *chip, int card) 1139 { 1140 u32 card_cd, status; 1141 1142 if (card == SD_CARD) { 1143 card_cd = SD_EXIST; 1144 } else if (card == MS_CARD) { 1145 card_cd = MS_EXIST; 1146 } else if (card == XD_CARD) { 1147 card_cd = XD_EXIST; 1148 } else { 1149 dev_dbg(rtsx_dev(chip), "Wrong card type: 0x%x\n", card); 1150 rtsx_trace(chip); 1151 return STATUS_FAIL; 1152 } 1153 1154 status = rtsx_readl(chip, RTSX_BIPR); 1155 if (!(status & card_cd)) { 1156 rtsx_trace(chip); 1157 return STATUS_FAIL; 1158 } 1159 1160 return STATUS_SUCCESS; 1161 } 1162 1163 int check_card_exist(struct rtsx_chip *chip, unsigned int lun) 1164 { 1165 if (chip->card_exist & chip->lun2card[lun]) 1166 return 1; 1167 1168 return 0; 1169 } 1170 1171 int check_card_ready(struct rtsx_chip *chip, unsigned int lun) 1172 { 1173 if (chip->card_ready & chip->lun2card[lun]) 1174 return 1; 1175 1176 return 0; 1177 } 1178 1179 int check_card_wp(struct rtsx_chip *chip, unsigned int lun) 1180 { 1181 if (chip->card_wp & chip->lun2card[lun]) 1182 return 1; 1183 1184 return 0; 1185 } 1186 1187 int check_card_fail(struct rtsx_chip *chip, unsigned int lun) 1188 { 1189 if (chip->card_fail & chip->lun2card[lun]) 1190 return 1; 1191 1192 return 0; 1193 } 1194 1195 int check_card_ejected(struct rtsx_chip *chip, unsigned int lun) 1196 { 1197 if (chip->card_ejected & chip->lun2card[lun]) 1198 return 1; 1199 1200 return 0; 1201 } 1202 1203 u8 get_lun_card(struct rtsx_chip *chip, unsigned int lun) 1204 { 1205 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) 1206 return (u8)XD_CARD; 1207 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) 1208 return (u8)SD_CARD; 1209 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) 1210 return (u8)MS_CARD; 1211 1212 return 0; 1213 } 1214 1215 void eject_card(struct rtsx_chip *chip, unsigned int lun) 1216 { 1217 do_remaining_work(chip); 1218 1219 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) { 1220 release_sd_card(chip); 1221 chip->card_ejected |= SD_CARD; 1222 chip->card_ready &= ~SD_CARD; 1223 chip->capacity[lun] = 0; 1224 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) { 1225 release_xd_card(chip); 1226 chip->card_ejected |= XD_CARD; 1227 chip->card_ready &= ~XD_CARD; 1228 chip->capacity[lun] = 0; 1229 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) { 1230 release_ms_card(chip); 1231 chip->card_ejected |= MS_CARD; 1232 chip->card_ready &= ~MS_CARD; 1233 chip->capacity[lun] = 0; 1234 } 1235 } 1236