1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "ms.h" 30 31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 32 { 33 struct ms_info *ms_card = &chip->ms_card; 34 35 ms_card->err_code = err_code; 36 } 37 38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct ms_info *ms_card = &chip->ms_card; 41 42 return (ms_card->err_code == err_code); 43 } 44 45 static int ms_parse_err_code(struct rtsx_chip *chip) 46 { 47 rtsx_trace(chip); 48 return STATUS_FAIL; 49 } 50 51 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 52 u8 tpc, u8 cnt, u8 cfg) 53 { 54 struct ms_info *ms_card = &chip->ms_card; 55 int retval; 56 u8 *ptr; 57 58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 59 60 rtsx_init_cmd(chip); 61 62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 66 0x01, PINGPONG_BUFFER); 67 68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 69 0xFF, MS_TRANSFER_START | trans_mode); 70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 71 MS_TRANSFER_END, MS_TRANSFER_END); 72 73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 74 75 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 76 if (retval < 0) { 77 rtsx_clear_ms_error(chip); 78 ms_set_err_code(chip, MS_TO_ERROR); 79 rtsx_trace(chip); 80 return ms_parse_err_code(chip); 81 } 82 83 ptr = rtsx_get_cmd_data(chip) + 1; 84 85 if (!(tpc & 0x08)) { /* Read Packet */ 86 if (*ptr & MS_CRC16_ERR) { 87 ms_set_err_code(chip, MS_CRC16_ERROR); 88 rtsx_trace(chip); 89 return ms_parse_err_code(chip); 90 } 91 } else { /* Write Packet */ 92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 94 ms_set_err_code(chip, MS_CMD_NK); 95 rtsx_trace(chip); 96 return ms_parse_err_code(chip); 97 } 98 } 99 } 100 101 if (*ptr & MS_RDY_TIMEOUT) { 102 rtsx_clear_ms_error(chip); 103 ms_set_err_code(chip, MS_TO_ERROR); 104 rtsx_trace(chip); 105 return ms_parse_err_code(chip); 106 } 107 108 return STATUS_SUCCESS; 109 } 110 111 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 113 int use_sg, void *buf, int buf_len) 114 { 115 int retval; 116 u8 val, err_code = 0; 117 enum dma_data_direction dir; 118 119 if (!buf || !buf_len) { 120 rtsx_trace(chip); 121 return STATUS_FAIL; 122 } 123 124 if (trans_mode == MS_TM_AUTO_READ) { 125 dir = DMA_FROM_DEVICE; 126 err_code = MS_FLASH_READ_ERROR; 127 } else if (trans_mode == MS_TM_AUTO_WRITE) { 128 dir = DMA_TO_DEVICE; 129 err_code = MS_FLASH_WRITE_ERROR; 130 } else { 131 rtsx_trace(chip); 132 return STATUS_FAIL; 133 } 134 135 rtsx_init_cmd(chip); 136 137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 138 rtsx_add_cmd(chip, WRITE_REG_CMD, 139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 142 143 if (mode_2k) { 144 rtsx_add_cmd(chip, WRITE_REG_CMD, 145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 146 } else { 147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 148 } 149 150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 151 152 rtsx_add_cmd(chip, WRITE_REG_CMD, 153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 154 rtsx_add_cmd(chip, CHECK_REG_CMD, 155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 156 157 rtsx_send_cmd_no_wait(chip); 158 159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 160 use_sg, dir, chip->mspro_timeout); 161 if (retval < 0) { 162 ms_set_err_code(chip, err_code); 163 if (retval == -ETIMEDOUT) 164 retval = STATUS_TIMEDOUT; 165 else 166 retval = STATUS_FAIL; 167 168 rtsx_trace(chip); 169 return retval; 170 } 171 172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 173 if (retval) { 174 rtsx_trace(chip); 175 return retval; 176 } 177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 178 rtsx_trace(chip); 179 return STATUS_FAIL; 180 } 181 182 return STATUS_SUCCESS; 183 } 184 185 static int ms_write_bytes(struct rtsx_chip *chip, 186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 187 { 188 struct ms_info *ms_card = &chip->ms_card; 189 int retval, i; 190 191 if (!data || (data_len < cnt)) { 192 rtsx_trace(chip); 193 return STATUS_ERROR; 194 } 195 196 rtsx_init_cmd(chip); 197 198 for (i = 0; i < cnt; i++) { 199 rtsx_add_cmd(chip, WRITE_REG_CMD, 200 PPBUF_BASE2 + i, 0xFF, data[i]); 201 } 202 if (cnt % 2) 203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 204 205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 209 0x01, PINGPONG_BUFFER); 210 211 rtsx_add_cmd(chip, WRITE_REG_CMD, 212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 213 rtsx_add_cmd(chip, CHECK_REG_CMD, 214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 215 216 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 217 if (retval < 0) { 218 u8 val = 0; 219 220 rtsx_read_register(chip, MS_TRANS_CFG, &val); 221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 222 223 rtsx_clear_ms_error(chip); 224 225 if (!(tpc & 0x08)) { 226 if (val & MS_CRC16_ERR) { 227 ms_set_err_code(chip, MS_CRC16_ERROR); 228 rtsx_trace(chip); 229 return ms_parse_err_code(chip); 230 } 231 } else { 232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 234 ms_set_err_code(chip, MS_CMD_NK); 235 rtsx_trace(chip); 236 return ms_parse_err_code(chip); 237 } 238 } 239 } 240 241 if (val & MS_RDY_TIMEOUT) { 242 ms_set_err_code(chip, MS_TO_ERROR); 243 rtsx_trace(chip); 244 return ms_parse_err_code(chip); 245 } 246 247 ms_set_err_code(chip, MS_TO_ERROR); 248 rtsx_trace(chip); 249 return ms_parse_err_code(chip); 250 } 251 252 return STATUS_SUCCESS; 253 } 254 255 static int ms_read_bytes(struct rtsx_chip *chip, 256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 257 { 258 struct ms_info *ms_card = &chip->ms_card; 259 int retval, i; 260 u8 *ptr; 261 262 if (!data) { 263 rtsx_trace(chip); 264 return STATUS_ERROR; 265 } 266 267 rtsx_init_cmd(chip); 268 269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 273 0x01, PINGPONG_BUFFER); 274 275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 276 MS_TRANSFER_START | MS_TM_READ_BYTES); 277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 278 MS_TRANSFER_END, MS_TRANSFER_END); 279 280 for (i = 0; i < data_len - 1; i++) 281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 282 283 if (data_len % 2) 284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 285 else 286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 287 0, 0); 288 289 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 290 if (retval < 0) { 291 u8 val = 0; 292 293 rtsx_read_register(chip, MS_TRANS_CFG, &val); 294 rtsx_clear_ms_error(chip); 295 296 if (!(tpc & 0x08)) { 297 if (val & MS_CRC16_ERR) { 298 ms_set_err_code(chip, MS_CRC16_ERROR); 299 rtsx_trace(chip); 300 return ms_parse_err_code(chip); 301 } 302 } else { 303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 305 ms_set_err_code(chip, MS_CMD_NK); 306 rtsx_trace(chip); 307 return ms_parse_err_code(chip); 308 } 309 } 310 } 311 312 if (val & MS_RDY_TIMEOUT) { 313 ms_set_err_code(chip, MS_TO_ERROR); 314 rtsx_trace(chip); 315 return ms_parse_err_code(chip); 316 } 317 318 ms_set_err_code(chip, MS_TO_ERROR); 319 rtsx_trace(chip); 320 return ms_parse_err_code(chip); 321 } 322 323 ptr = rtsx_get_cmd_data(chip) + 1; 324 325 for (i = 0; i < data_len; i++) 326 data[i] = ptr[i]; 327 328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) { 329 dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 331 cnt); 332 } 333 334 return STATUS_SUCCESS; 335 } 336 337 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start, 338 u8 read_cnt, u8 write_start, u8 write_cnt) 339 { 340 int retval, i; 341 u8 data[4]; 342 343 data[0] = read_start; 344 data[1] = read_cnt; 345 data[2] = write_start; 346 data[3] = write_cnt; 347 348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 350 NO_WAIT_INT, data, 4); 351 if (retval == STATUS_SUCCESS) 352 return STATUS_SUCCESS; 353 rtsx_clear_ms_error(chip); 354 } 355 356 rtsx_trace(chip); 357 return STATUS_FAIL; 358 } 359 360 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 361 { 362 u8 data[2]; 363 364 data[0] = cmd; 365 data[1] = 0; 366 367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 368 } 369 370 static int ms_set_init_para(struct rtsx_chip *chip) 371 { 372 struct ms_info *ms_card = &chip->ms_card; 373 int retval; 374 375 if (CHK_HG8BIT(ms_card)) { 376 if (chip->asic_code) 377 ms_card->ms_clock = chip->asic_ms_hg_clk; 378 else 379 ms_card->ms_clock = chip->fpga_ms_hg_clk; 380 381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 382 if (chip->asic_code) 383 ms_card->ms_clock = chip->asic_ms_4bit_clk; 384 else 385 ms_card->ms_clock = chip->fpga_ms_4bit_clk; 386 387 } else { 388 if (chip->asic_code) 389 ms_card->ms_clock = chip->asic_ms_1bit_clk; 390 else 391 ms_card->ms_clock = chip->fpga_ms_1bit_clk; 392 } 393 394 retval = switch_clock(chip, ms_card->ms_clock); 395 if (retval != STATUS_SUCCESS) { 396 rtsx_trace(chip); 397 return STATUS_FAIL; 398 } 399 400 retval = select_card(chip, MS_CARD); 401 if (retval != STATUS_SUCCESS) { 402 rtsx_trace(chip); 403 return STATUS_FAIL; 404 } 405 406 return STATUS_SUCCESS; 407 } 408 409 static int ms_switch_clock(struct rtsx_chip *chip) 410 { 411 struct ms_info *ms_card = &chip->ms_card; 412 int retval; 413 414 retval = select_card(chip, MS_CARD); 415 if (retval != STATUS_SUCCESS) { 416 rtsx_trace(chip); 417 return STATUS_FAIL; 418 } 419 420 retval = switch_clock(chip, ms_card->ms_clock); 421 if (retval != STATUS_SUCCESS) { 422 rtsx_trace(chip); 423 return STATUS_FAIL; 424 } 425 426 return STATUS_SUCCESS; 427 } 428 429 static int ms_pull_ctl_disable(struct rtsx_chip *chip) 430 { 431 int retval; 432 433 if (CHECK_PID(chip, 0x5208)) { 434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 435 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD); 436 if (retval) { 437 rtsx_trace(chip); 438 return retval; 439 } 440 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 441 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD); 442 if (retval) { 443 rtsx_trace(chip); 444 return retval; 445 } 446 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 447 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 448 if (retval) { 449 rtsx_trace(chip); 450 return retval; 451 } 452 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 453 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 454 if (retval) { 455 rtsx_trace(chip); 456 return retval; 457 } 458 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 459 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 460 if (retval) { 461 rtsx_trace(chip); 462 return retval; 463 } 464 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 465 MS_D5_PD | MS_D4_PD); 466 if (retval) { 467 rtsx_trace(chip); 468 return retval; 469 } 470 } else if (CHECK_PID(chip, 0x5288)) { 471 if (CHECK_BARO_PKG(chip, QFN)) { 472 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 473 0xFF, 0x55); 474 if (retval) { 475 rtsx_trace(chip); 476 return retval; 477 } 478 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 479 0xFF, 0x55); 480 if (retval) { 481 rtsx_trace(chip); 482 return retval; 483 } 484 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 485 0xFF, 0x4B); 486 if (retval) { 487 rtsx_trace(chip); 488 return retval; 489 } 490 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 491 0xFF, 0x69); 492 if (retval) { 493 rtsx_trace(chip); 494 return retval; 495 } 496 } 497 } 498 499 return STATUS_SUCCESS; 500 } 501 502 static int ms_pull_ctl_enable(struct rtsx_chip *chip) 503 { 504 int retval; 505 506 rtsx_init_cmd(chip); 507 508 if (CHECK_PID(chip, 0x5208)) { 509 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 510 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 511 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 512 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 513 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 514 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 515 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 516 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 517 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 518 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 519 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 520 MS_D5_PD | MS_D4_PD); 521 } else if (CHECK_PID(chip, 0x5288)) { 522 if (CHECK_BARO_PKG(chip, QFN)) { 523 rtsx_add_cmd(chip, WRITE_REG_CMD, 524 CARD_PULL_CTL1, 0xFF, 0x55); 525 rtsx_add_cmd(chip, WRITE_REG_CMD, 526 CARD_PULL_CTL2, 0xFF, 0x45); 527 rtsx_add_cmd(chip, WRITE_REG_CMD, 528 CARD_PULL_CTL3, 0xFF, 0x4B); 529 rtsx_add_cmd(chip, WRITE_REG_CMD, 530 CARD_PULL_CTL4, 0xFF, 0x29); 531 } 532 } 533 534 retval = rtsx_send_cmd(chip, MS_CARD, 100); 535 if (retval < 0) { 536 rtsx_trace(chip); 537 return STATUS_FAIL; 538 } 539 540 return STATUS_SUCCESS; 541 } 542 543 static int ms_prepare_reset(struct rtsx_chip *chip) 544 { 545 struct ms_info *ms_card = &chip->ms_card; 546 int retval; 547 u8 oc_mask = 0; 548 549 ms_card->ms_type = 0; 550 ms_card->check_ms_flow = 0; 551 ms_card->switch_8bit_fail = 0; 552 ms_card->delay_write.delay_write_flag = 0; 553 554 ms_card->pro_under_formatting = 0; 555 556 retval = ms_power_off_card3v3(chip); 557 if (retval != STATUS_SUCCESS) { 558 rtsx_trace(chip); 559 return STATUS_FAIL; 560 } 561 562 if (!chip->ft2_fast_mode) 563 wait_timeout(250); 564 565 retval = enable_card_clock(chip, MS_CARD); 566 if (retval != STATUS_SUCCESS) { 567 rtsx_trace(chip); 568 return STATUS_FAIL; 569 } 570 571 if (chip->asic_code) { 572 retval = ms_pull_ctl_enable(chip); 573 if (retval != STATUS_SUCCESS) { 574 rtsx_trace(chip); 575 return STATUS_FAIL; 576 } 577 } else { 578 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 579 FPGA_MS_PULL_CTL_BIT | 0x20, 0); 580 if (retval) { 581 rtsx_trace(chip); 582 return retval; 583 } 584 } 585 586 if (!chip->ft2_fast_mode) { 587 retval = card_power_on(chip, MS_CARD); 588 if (retval != STATUS_SUCCESS) { 589 rtsx_trace(chip); 590 return STATUS_FAIL; 591 } 592 593 wait_timeout(150); 594 595 #ifdef SUPPORT_OCP 596 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 597 oc_mask = MS_OC_NOW | MS_OC_EVER; 598 else 599 oc_mask = SD_OC_NOW | SD_OC_EVER; 600 601 if (chip->ocp_stat & oc_mask) { 602 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 603 chip->ocp_stat); 604 rtsx_trace(chip); 605 return STATUS_FAIL; 606 } 607 #endif 608 } 609 610 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 611 MS_OUTPUT_EN); 612 if (retval) { 613 rtsx_trace(chip); 614 return retval; 615 } 616 617 if (chip->asic_code) { 618 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 619 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 620 if (retval) { 621 rtsx_trace(chip); 622 return retval; 623 } 624 } else { 625 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 626 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 627 if (retval) { 628 rtsx_trace(chip); 629 return retval; 630 } 631 } 632 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 633 NO_WAIT_INT | NO_AUTO_READ_INT_REG); 634 if (retval) { 635 rtsx_trace(chip); 636 return retval; 637 } 638 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 639 MS_STOP | MS_CLR_ERR); 640 if (retval) { 641 rtsx_trace(chip); 642 return retval; 643 } 644 645 retval = ms_set_init_para(chip); 646 if (retval != STATUS_SUCCESS) { 647 rtsx_trace(chip); 648 return STATUS_FAIL; 649 } 650 651 return STATUS_SUCCESS; 652 } 653 654 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 655 { 656 struct ms_info *ms_card = &chip->ms_card; 657 int retval, i; 658 u8 val; 659 660 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1); 661 if (retval != STATUS_SUCCESS) { 662 rtsx_trace(chip); 663 return STATUS_FAIL; 664 } 665 666 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 667 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 668 6, NO_WAIT_INT); 669 if (retval == STATUS_SUCCESS) 670 break; 671 } 672 if (i == MS_MAX_RETRY_COUNT) { 673 rtsx_trace(chip); 674 return STATUS_FAIL; 675 } 676 677 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 678 if (retval) { 679 rtsx_trace(chip); 680 return retval; 681 } 682 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 683 if (val != 0x01) { 684 if (val != 0x02) 685 ms_card->check_ms_flow = 1; 686 687 rtsx_trace(chip); 688 return STATUS_FAIL; 689 } 690 691 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 692 if (retval) { 693 rtsx_trace(chip); 694 return retval; 695 } 696 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 697 if (val != 0) { 698 ms_card->check_ms_flow = 1; 699 rtsx_trace(chip); 700 return STATUS_FAIL; 701 } 702 703 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 704 if (retval) { 705 rtsx_trace(chip); 706 return retval; 707 } 708 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 709 if (val == 0) { 710 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 711 if (retval) { 712 rtsx_trace(chip); 713 return retval; 714 } 715 if (val & WRT_PRTCT) 716 chip->card_wp |= MS_CARD; 717 else 718 chip->card_wp &= ~MS_CARD; 719 720 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 721 chip->card_wp |= MS_CARD; 722 } else { 723 ms_card->check_ms_flow = 1; 724 rtsx_trace(chip); 725 return STATUS_FAIL; 726 } 727 728 ms_card->ms_type |= TYPE_MSPRO; 729 730 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 731 if (retval) { 732 rtsx_trace(chip); 733 return retval; 734 } 735 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 736 if (val == 0) { 737 ms_card->ms_type &= 0x0F; 738 } else if (val == 7) { 739 if (switch_8bit_bus) 740 ms_card->ms_type |= MS_HG; 741 else 742 ms_card->ms_type &= 0x0F; 743 744 } else { 745 rtsx_trace(chip); 746 return STATUS_FAIL; 747 } 748 749 return STATUS_SUCCESS; 750 } 751 752 static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 753 { 754 int retval, i, k; 755 u8 val; 756 757 /* Confirm CPU StartUp */ 758 k = 0; 759 do { 760 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 761 ms_set_err_code(chip, MS_NO_CARD); 762 rtsx_trace(chip); 763 return STATUS_FAIL; 764 } 765 766 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 767 retval = ms_read_bytes(chip, GET_INT, 1, 768 NO_WAIT_INT, &val, 1); 769 if (retval == STATUS_SUCCESS) 770 break; 771 } 772 if (i == MS_MAX_RETRY_COUNT) { 773 rtsx_trace(chip); 774 return STATUS_FAIL; 775 } 776 777 if (k > 100) { 778 rtsx_trace(chip); 779 return STATUS_FAIL; 780 } 781 782 k++; 783 wait_timeout(100); 784 } while (!(val & INT_REG_CED)); 785 786 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 787 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 788 if (retval == STATUS_SUCCESS) 789 break; 790 } 791 if (i == MS_MAX_RETRY_COUNT) { 792 rtsx_trace(chip); 793 return STATUS_FAIL; 794 } 795 796 if (val & INT_REG_ERR) { 797 if (val & INT_REG_CMDNK) 798 chip->card_wp |= (MS_CARD); 799 else { 800 rtsx_trace(chip); 801 return STATUS_FAIL; 802 } 803 } 804 /* -- end confirm CPU startup */ 805 806 return STATUS_SUCCESS; 807 } 808 809 static int ms_switch_parallel_bus(struct rtsx_chip *chip) 810 { 811 int retval, i; 812 u8 data[2]; 813 814 data[0] = PARALLEL_4BIT_IF; 815 data[1] = 0; 816 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 817 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 818 data, 2); 819 if (retval == STATUS_SUCCESS) 820 break; 821 } 822 if (retval != STATUS_SUCCESS) { 823 rtsx_trace(chip); 824 return STATUS_FAIL; 825 } 826 827 return STATUS_SUCCESS; 828 } 829 830 static int ms_switch_8bit_bus(struct rtsx_chip *chip) 831 { 832 struct ms_info *ms_card = &chip->ms_card; 833 int retval, i; 834 u8 data[2]; 835 836 data[0] = PARALLEL_8BIT_IF; 837 data[1] = 0; 838 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 839 retval = ms_write_bytes(chip, WRITE_REG, 1, 840 NO_WAIT_INT, data, 2); 841 if (retval == STATUS_SUCCESS) 842 break; 843 } 844 if (retval != STATUS_SUCCESS) { 845 rtsx_trace(chip); 846 return STATUS_FAIL; 847 } 848 849 retval = rtsx_write_register(chip, MS_CFG, 0x98, 850 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 851 if (retval) { 852 rtsx_trace(chip); 853 return retval; 854 } 855 ms_card->ms_type |= MS_8BIT; 856 retval = ms_set_init_para(chip); 857 if (retval != STATUS_SUCCESS) { 858 rtsx_trace(chip); 859 return STATUS_FAIL; 860 } 861 862 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 863 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 864 1, NO_WAIT_INT); 865 if (retval != STATUS_SUCCESS) { 866 rtsx_trace(chip); 867 return STATUS_FAIL; 868 } 869 } 870 871 return STATUS_SUCCESS; 872 } 873 874 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 875 { 876 struct ms_info *ms_card = &chip->ms_card; 877 int retval, i; 878 879 for (i = 0; i < 3; i++) { 880 retval = ms_prepare_reset(chip); 881 if (retval != STATUS_SUCCESS) { 882 rtsx_trace(chip); 883 return STATUS_FAIL; 884 } 885 886 retval = ms_identify_media_type(chip, switch_8bit_bus); 887 if (retval != STATUS_SUCCESS) { 888 rtsx_trace(chip); 889 return STATUS_FAIL; 890 } 891 892 retval = ms_confirm_cpu_startup(chip); 893 if (retval != STATUS_SUCCESS) { 894 rtsx_trace(chip); 895 return STATUS_FAIL; 896 } 897 898 retval = ms_switch_parallel_bus(chip); 899 if (retval != STATUS_SUCCESS) { 900 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 901 ms_set_err_code(chip, MS_NO_CARD); 902 rtsx_trace(chip); 903 return STATUS_FAIL; 904 } 905 continue; 906 } else { 907 break; 908 } 909 } 910 911 if (retval != STATUS_SUCCESS) { 912 rtsx_trace(chip); 913 return STATUS_FAIL; 914 } 915 916 /* Switch MS-PRO into Parallel mode */ 917 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 918 if (retval) { 919 rtsx_trace(chip); 920 return retval; 921 } 922 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 923 PUSH_TIME_ODD); 924 if (retval) { 925 rtsx_trace(chip); 926 return retval; 927 } 928 929 retval = ms_set_init_para(chip); 930 if (retval != STATUS_SUCCESS) { 931 rtsx_trace(chip); 932 return STATUS_FAIL; 933 } 934 935 /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 936 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 937 retval = ms_switch_8bit_bus(chip); 938 if (retval != STATUS_SUCCESS) { 939 ms_card->switch_8bit_fail = 1; 940 rtsx_trace(chip); 941 return STATUS_FAIL; 942 } 943 } 944 945 return STATUS_SUCCESS; 946 } 947 948 #ifdef XC_POWERCLASS 949 static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 950 { 951 int retval; 952 u8 buf[6]; 953 954 ms_cleanup_work(chip); 955 956 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 957 if (retval != STATUS_SUCCESS) { 958 rtsx_trace(chip); 959 return STATUS_FAIL; 960 } 961 962 buf[0] = 0; 963 buf[1] = mode; 964 buf[2] = 0; 965 buf[3] = 0; 966 buf[4] = 0; 967 buf[5] = 0; 968 969 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 970 if (retval != STATUS_SUCCESS) { 971 rtsx_trace(chip); 972 return STATUS_FAIL; 973 } 974 975 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 976 if (retval != STATUS_SUCCESS) { 977 rtsx_trace(chip); 978 return STATUS_FAIL; 979 } 980 981 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 982 if (retval) { 983 rtsx_trace(chip); 984 return retval; 985 } 986 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) { 987 rtsx_trace(chip); 988 return STATUS_FAIL; 989 } 990 991 return STATUS_SUCCESS; 992 } 993 #endif 994 995 static int ms_read_attribute_info(struct rtsx_chip *chip) 996 { 997 struct ms_info *ms_card = &chip->ms_card; 998 int retval, i; 999 u8 val, *buf, class_code, device_type, sub_class, data[16]; 1000 u16 total_blk = 0, blk_size = 0; 1001 #ifdef SUPPORT_MSXC 1002 u32 xc_total_blk = 0, xc_blk_size = 0; 1003 #endif 1004 u32 sys_info_addr = 0, sys_info_size; 1005 #ifdef SUPPORT_PCGL_1P18 1006 u32 model_name_addr = 0, model_name_size; 1007 int found_sys_info = 0, found_model_name = 0; 1008 #endif 1009 1010 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7); 1011 if (retval != STATUS_SUCCESS) { 1012 rtsx_trace(chip); 1013 return STATUS_FAIL; 1014 } 1015 1016 if (CHK_MS8BIT(ms_card)) 1017 data[0] = PARALLEL_8BIT_IF; 1018 else 1019 data[0] = PARALLEL_4BIT_IF; 1020 1021 data[1] = 0; 1022 1023 data[2] = 0x40; 1024 data[3] = 0; 1025 data[4] = 0; 1026 data[5] = 0; 1027 data[6] = 0; 1028 data[7] = 0; 1029 1030 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1031 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 1032 data, 8); 1033 if (retval == STATUS_SUCCESS) 1034 break; 1035 } 1036 if (retval != STATUS_SUCCESS) { 1037 rtsx_trace(chip); 1038 return STATUS_FAIL; 1039 } 1040 1041 buf = kmalloc(64 * 512, GFP_KERNEL); 1042 if (!buf) { 1043 rtsx_trace(chip); 1044 return STATUS_ERROR; 1045 } 1046 1047 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1048 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 1049 if (retval != STATUS_SUCCESS) 1050 continue; 1051 1052 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1053 if (retval != STATUS_SUCCESS) { 1054 kfree(buf); 1055 rtsx_trace(chip); 1056 return STATUS_FAIL; 1057 } 1058 if (!(val & MS_INT_BREQ)) { 1059 kfree(buf); 1060 rtsx_trace(chip); 1061 return STATUS_FAIL; 1062 } 1063 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 1064 PRO_READ_LONG_DATA, 0x40, WAIT_INT, 1065 0, 0, buf, 64 * 512); 1066 if (retval == STATUS_SUCCESS) 1067 break; 1068 1069 rtsx_clear_ms_error(chip); 1070 } 1071 if (retval != STATUS_SUCCESS) { 1072 kfree(buf); 1073 rtsx_trace(chip); 1074 return STATUS_FAIL; 1075 } 1076 1077 i = 0; 1078 do { 1079 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1080 if (retval != STATUS_SUCCESS) { 1081 kfree(buf); 1082 rtsx_trace(chip); 1083 return STATUS_FAIL; 1084 } 1085 1086 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 1087 break; 1088 1089 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 1090 PRO_READ_LONG_DATA, 0, WAIT_INT); 1091 if (retval != STATUS_SUCCESS) { 1092 kfree(buf); 1093 rtsx_trace(chip); 1094 return STATUS_FAIL; 1095 } 1096 1097 i++; 1098 } while (i < 1024); 1099 1100 if (retval != STATUS_SUCCESS) { 1101 kfree(buf); 1102 rtsx_trace(chip); 1103 return STATUS_FAIL; 1104 } 1105 1106 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) { 1107 /* Signature code is wrong */ 1108 kfree(buf); 1109 rtsx_trace(chip); 1110 return STATUS_FAIL; 1111 } 1112 1113 if ((buf[4] < 1) || (buf[4] > 12)) { 1114 kfree(buf); 1115 rtsx_trace(chip); 1116 return STATUS_FAIL; 1117 } 1118 1119 for (i = 0; i < buf[4]; i++) { 1120 int cur_addr_off = 16 + i * 12; 1121 1122 #ifdef SUPPORT_MSXC 1123 if ((buf[cur_addr_off + 8] == 0x10) || 1124 (buf[cur_addr_off + 8] == 0x13)) { 1125 #else 1126 if (buf[cur_addr_off + 8] == 0x10) { 1127 #endif 1128 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1129 ((u32)buf[cur_addr_off + 1] << 16) | 1130 ((u32)buf[cur_addr_off + 2] << 8) | 1131 buf[cur_addr_off + 3]; 1132 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 1133 ((u32)buf[cur_addr_off + 5] << 16) | 1134 ((u32)buf[cur_addr_off + 6] << 8) | 1135 buf[cur_addr_off + 7]; 1136 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 1137 sys_info_addr, sys_info_size); 1138 if (sys_info_size != 96) { 1139 kfree(buf); 1140 rtsx_trace(chip); 1141 return STATUS_FAIL; 1142 } 1143 if (sys_info_addr < 0x1A0) { 1144 kfree(buf); 1145 rtsx_trace(chip); 1146 return STATUS_FAIL; 1147 } 1148 if ((sys_info_size + sys_info_addr) > 0x8000) { 1149 kfree(buf); 1150 rtsx_trace(chip); 1151 return STATUS_FAIL; 1152 } 1153 1154 #ifdef SUPPORT_MSXC 1155 if (buf[cur_addr_off + 8] == 0x13) 1156 ms_card->ms_type |= MS_XC; 1157 #endif 1158 #ifdef SUPPORT_PCGL_1P18 1159 found_sys_info = 1; 1160 #else 1161 break; 1162 #endif 1163 } 1164 #ifdef SUPPORT_PCGL_1P18 1165 if (buf[cur_addr_off + 8] == 0x15) { 1166 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1167 ((u32)buf[cur_addr_off + 1] << 16) | 1168 ((u32)buf[cur_addr_off + 2] << 8) | 1169 buf[cur_addr_off + 3]; 1170 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1171 ((u32)buf[cur_addr_off + 5] << 16) | 1172 ((u32)buf[cur_addr_off + 6] << 8) | 1173 buf[cur_addr_off + 7]; 1174 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1175 model_name_addr, model_name_size); 1176 if (model_name_size != 48) { 1177 kfree(buf); 1178 rtsx_trace(chip); 1179 return STATUS_FAIL; 1180 } 1181 if (model_name_addr < 0x1A0) { 1182 kfree(buf); 1183 rtsx_trace(chip); 1184 return STATUS_FAIL; 1185 } 1186 if ((model_name_size + model_name_addr) > 0x8000) { 1187 kfree(buf); 1188 rtsx_trace(chip); 1189 return STATUS_FAIL; 1190 } 1191 1192 found_model_name = 1; 1193 } 1194 1195 if (found_sys_info && found_model_name) 1196 break; 1197 #endif 1198 } 1199 1200 if (i == buf[4]) { 1201 kfree(buf); 1202 rtsx_trace(chip); 1203 return STATUS_FAIL; 1204 } 1205 1206 class_code = buf[sys_info_addr + 0]; 1207 device_type = buf[sys_info_addr + 56]; 1208 sub_class = buf[sys_info_addr + 46]; 1209 #ifdef SUPPORT_MSXC 1210 if (CHK_MSXC(ms_card)) { 1211 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1212 ((u32)buf[sys_info_addr + 7] << 16) | 1213 ((u32)buf[sys_info_addr + 8] << 8) | 1214 buf[sys_info_addr + 9]; 1215 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1216 ((u32)buf[sys_info_addr + 33] << 16) | 1217 ((u32)buf[sys_info_addr + 34] << 8) | 1218 buf[sys_info_addr + 35]; 1219 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1220 xc_total_blk, xc_blk_size); 1221 } else { 1222 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1223 buf[sys_info_addr + 7]; 1224 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1225 buf[sys_info_addr + 3]; 1226 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1227 total_blk, blk_size); 1228 } 1229 #else 1230 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1231 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1232 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1233 total_blk, blk_size); 1234 #endif 1235 1236 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1237 class_code, device_type, sub_class); 1238 1239 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1240 #ifdef SUPPORT_PCGL_1P18 1241 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1242 #endif 1243 1244 kfree(buf); 1245 1246 #ifdef SUPPORT_MSXC 1247 if (CHK_MSXC(ms_card)) { 1248 if (class_code != 0x03) { 1249 rtsx_trace(chip); 1250 return STATUS_FAIL; 1251 } 1252 } else { 1253 if (class_code != 0x02) { 1254 rtsx_trace(chip); 1255 return STATUS_FAIL; 1256 } 1257 } 1258 #else 1259 if (class_code != 0x02) { 1260 rtsx_trace(chip); 1261 return STATUS_FAIL; 1262 } 1263 #endif 1264 1265 if (device_type != 0x00) { 1266 if ((device_type == 0x01) || (device_type == 0x02) || 1267 (device_type == 0x03)) { 1268 chip->card_wp |= MS_CARD; 1269 } else { 1270 rtsx_trace(chip); 1271 return STATUS_FAIL; 1272 } 1273 } 1274 1275 if (sub_class & 0xC0) { 1276 rtsx_trace(chip); 1277 return STATUS_FAIL; 1278 } 1279 1280 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1281 class_code, device_type, sub_class); 1282 1283 #ifdef SUPPORT_MSXC 1284 if (CHK_MSXC(ms_card)) { 1285 chip->capacity[chip->card2lun[MS_CARD]] = 1286 ms_card->capacity = xc_total_blk * xc_blk_size; 1287 } else { 1288 chip->capacity[chip->card2lun[MS_CARD]] = 1289 ms_card->capacity = total_blk * blk_size; 1290 } 1291 #else 1292 ms_card->capacity = total_blk * blk_size; 1293 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1294 #endif 1295 1296 return STATUS_SUCCESS; 1297 } 1298 1299 #ifdef SUPPORT_MAGIC_GATE 1300 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1301 int type, u8 mg_entry_num); 1302 #endif 1303 1304 static int reset_ms_pro(struct rtsx_chip *chip) 1305 { 1306 struct ms_info *ms_card = &chip->ms_card; 1307 int retval; 1308 #ifdef XC_POWERCLASS 1309 u8 change_power_class; 1310 1311 if (chip->ms_power_class_en & 0x02) 1312 change_power_class = 2; 1313 else if (chip->ms_power_class_en & 0x01) 1314 change_power_class = 1; 1315 else 1316 change_power_class = 0; 1317 #endif 1318 1319 #ifdef XC_POWERCLASS 1320 Retry: 1321 #endif 1322 retval = ms_pro_reset_flow(chip, 1); 1323 if (retval != STATUS_SUCCESS) { 1324 if (ms_card->switch_8bit_fail) { 1325 retval = ms_pro_reset_flow(chip, 0); 1326 if (retval != STATUS_SUCCESS) { 1327 rtsx_trace(chip); 1328 return STATUS_FAIL; 1329 } 1330 } else { 1331 rtsx_trace(chip); 1332 return STATUS_FAIL; 1333 } 1334 } 1335 1336 retval = ms_read_attribute_info(chip); 1337 if (retval != STATUS_SUCCESS) { 1338 rtsx_trace(chip); 1339 return STATUS_FAIL; 1340 } 1341 1342 #ifdef XC_POWERCLASS 1343 if (CHK_HG8BIT(ms_card)) 1344 change_power_class = 0; 1345 1346 if (change_power_class && CHK_MSXC(ms_card)) { 1347 u8 power_class_en = chip->ms_power_class_en; 1348 1349 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1350 power_class_en); 1351 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1352 change_power_class); 1353 1354 if (change_power_class) 1355 power_class_en &= (1 << (change_power_class - 1)); 1356 else 1357 power_class_en = 0; 1358 1359 if (power_class_en) { 1360 u8 power_class_mode = 1361 (ms_card->raw_sys_info[46] & 0x18) >> 3; 1362 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1363 power_class_mode); 1364 if (change_power_class > power_class_mode) 1365 change_power_class = power_class_mode; 1366 if (change_power_class) { 1367 retval = msxc_change_power(chip, 1368 change_power_class); 1369 if (retval != STATUS_SUCCESS) { 1370 change_power_class--; 1371 goto Retry; 1372 } 1373 } 1374 } 1375 } 1376 #endif 1377 1378 #ifdef SUPPORT_MAGIC_GATE 1379 retval = mg_set_tpc_para_sub(chip, 0, 0); 1380 if (retval != STATUS_SUCCESS) { 1381 rtsx_trace(chip); 1382 return STATUS_FAIL; 1383 } 1384 #endif 1385 1386 if (CHK_HG8BIT(ms_card)) 1387 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1388 else 1389 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1390 1391 return STATUS_SUCCESS; 1392 } 1393 1394 static int ms_read_status_reg(struct rtsx_chip *chip) 1395 { 1396 int retval; 1397 u8 val[2]; 1398 1399 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0); 1400 if (retval != STATUS_SUCCESS) { 1401 rtsx_trace(chip); 1402 return STATUS_FAIL; 1403 } 1404 1405 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1406 if (retval != STATUS_SUCCESS) { 1407 rtsx_trace(chip); 1408 return STATUS_FAIL; 1409 } 1410 1411 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1412 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1413 rtsx_trace(chip); 1414 return STATUS_FAIL; 1415 } 1416 1417 return STATUS_SUCCESS; 1418 } 1419 1420 static int ms_read_extra_data(struct rtsx_chip *chip, 1421 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1422 { 1423 struct ms_info *ms_card = &chip->ms_card; 1424 int retval, i; 1425 u8 val, data[10]; 1426 1427 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1428 SystemParm, 6); 1429 if (retval != STATUS_SUCCESS) { 1430 rtsx_trace(chip); 1431 return STATUS_FAIL; 1432 } 1433 1434 if (CHK_MS4BIT(ms_card)) { 1435 /* Parallel interface */ 1436 data[0] = 0x88; 1437 } else { 1438 /* Serial interface */ 1439 data[0] = 0x80; 1440 } 1441 data[1] = 0; 1442 data[2] = (u8)(block_addr >> 8); 1443 data[3] = (u8)block_addr; 1444 data[4] = 0x40; 1445 data[5] = page_num; 1446 1447 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1448 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1449 data, 6); 1450 if (retval == STATUS_SUCCESS) 1451 break; 1452 } 1453 if (i == MS_MAX_RETRY_COUNT) { 1454 rtsx_trace(chip); 1455 return STATUS_FAIL; 1456 } 1457 1458 ms_set_err_code(chip, MS_NO_ERROR); 1459 1460 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1461 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1462 if (retval == STATUS_SUCCESS) 1463 break; 1464 } 1465 if (i == MS_MAX_RETRY_COUNT) { 1466 rtsx_trace(chip); 1467 return STATUS_FAIL; 1468 } 1469 1470 ms_set_err_code(chip, MS_NO_ERROR); 1471 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1472 if (retval != STATUS_SUCCESS) { 1473 rtsx_trace(chip); 1474 return STATUS_FAIL; 1475 } 1476 1477 if (val & INT_REG_CMDNK) { 1478 ms_set_err_code(chip, MS_CMD_NK); 1479 rtsx_trace(chip); 1480 return STATUS_FAIL; 1481 } 1482 if (val & INT_REG_CED) { 1483 if (val & INT_REG_ERR) { 1484 retval = ms_read_status_reg(chip); 1485 if (retval != STATUS_SUCCESS) { 1486 rtsx_trace(chip); 1487 return STATUS_FAIL; 1488 } 1489 1490 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1491 MS_EXTRA_SIZE, SystemParm, 6); 1492 if (retval != STATUS_SUCCESS) { 1493 rtsx_trace(chip); 1494 return STATUS_FAIL; 1495 } 1496 } 1497 } 1498 1499 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1500 data, MS_EXTRA_SIZE); 1501 if (retval != STATUS_SUCCESS) { 1502 rtsx_trace(chip); 1503 return STATUS_FAIL; 1504 } 1505 1506 if (buf && buf_len) { 1507 if (buf_len > MS_EXTRA_SIZE) 1508 buf_len = MS_EXTRA_SIZE; 1509 memcpy(buf, data, buf_len); 1510 } 1511 1512 return STATUS_SUCCESS; 1513 } 1514 1515 static int ms_write_extra_data(struct rtsx_chip *chip, 1516 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1517 { 1518 struct ms_info *ms_card = &chip->ms_card; 1519 int retval, i; 1520 u8 val, data[16]; 1521 1522 if (!buf || (buf_len < MS_EXTRA_SIZE)) { 1523 rtsx_trace(chip); 1524 return STATUS_FAIL; 1525 } 1526 1527 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1528 SystemParm, 6 + MS_EXTRA_SIZE); 1529 if (retval != STATUS_SUCCESS) { 1530 rtsx_trace(chip); 1531 return STATUS_FAIL; 1532 } 1533 1534 if (CHK_MS4BIT(ms_card)) 1535 data[0] = 0x88; 1536 else 1537 data[0] = 0x80; 1538 1539 data[1] = 0; 1540 data[2] = (u8)(block_addr >> 8); 1541 data[3] = (u8)block_addr; 1542 data[4] = 0x40; 1543 data[5] = page_num; 1544 1545 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1546 data[i] = buf[i - 6]; 1547 1548 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1549 NO_WAIT_INT, data, 16); 1550 if (retval != STATUS_SUCCESS) { 1551 rtsx_trace(chip); 1552 return STATUS_FAIL; 1553 } 1554 1555 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1556 if (retval != STATUS_SUCCESS) { 1557 rtsx_trace(chip); 1558 return STATUS_FAIL; 1559 } 1560 1561 ms_set_err_code(chip, MS_NO_ERROR); 1562 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1563 if (retval != STATUS_SUCCESS) { 1564 rtsx_trace(chip); 1565 return STATUS_FAIL; 1566 } 1567 1568 if (val & INT_REG_CMDNK) { 1569 ms_set_err_code(chip, MS_CMD_NK); 1570 rtsx_trace(chip); 1571 return STATUS_FAIL; 1572 } 1573 if (val & INT_REG_CED) { 1574 if (val & INT_REG_ERR) { 1575 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1576 rtsx_trace(chip); 1577 return STATUS_FAIL; 1578 } 1579 } 1580 1581 return STATUS_SUCCESS; 1582 } 1583 1584 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1585 { 1586 struct ms_info *ms_card = &chip->ms_card; 1587 int retval; 1588 u8 val, data[6]; 1589 1590 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1591 SystemParm, 6); 1592 if (retval != STATUS_SUCCESS) { 1593 rtsx_trace(chip); 1594 return STATUS_FAIL; 1595 } 1596 1597 if (CHK_MS4BIT(ms_card)) 1598 data[0] = 0x88; 1599 else 1600 data[0] = 0x80; 1601 1602 data[1] = 0; 1603 data[2] = (u8)(block_addr >> 8); 1604 data[3] = (u8)block_addr; 1605 data[4] = 0x20; 1606 data[5] = page_num; 1607 1608 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1609 if (retval != STATUS_SUCCESS) { 1610 rtsx_trace(chip); 1611 return STATUS_FAIL; 1612 } 1613 1614 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1615 if (retval != STATUS_SUCCESS) { 1616 rtsx_trace(chip); 1617 return STATUS_FAIL; 1618 } 1619 1620 ms_set_err_code(chip, MS_NO_ERROR); 1621 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1622 if (retval != STATUS_SUCCESS) { 1623 rtsx_trace(chip); 1624 return STATUS_FAIL; 1625 } 1626 1627 if (val & INT_REG_CMDNK) { 1628 ms_set_err_code(chip, MS_CMD_NK); 1629 rtsx_trace(chip); 1630 return STATUS_FAIL; 1631 } 1632 1633 if (val & INT_REG_CED) { 1634 if (val & INT_REG_ERR) { 1635 if (!(val & INT_REG_BREQ)) { 1636 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1637 rtsx_trace(chip); 1638 return STATUS_FAIL; 1639 } 1640 retval = ms_read_status_reg(chip); 1641 if (retval != STATUS_SUCCESS) 1642 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1643 1644 } else { 1645 if (!(val & INT_REG_BREQ)) { 1646 ms_set_err_code(chip, MS_BREQ_ERROR); 1647 rtsx_trace(chip); 1648 return STATUS_FAIL; 1649 } 1650 } 1651 } 1652 1653 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1654 0, NO_WAIT_INT); 1655 if (retval != STATUS_SUCCESS) { 1656 rtsx_trace(chip); 1657 return STATUS_FAIL; 1658 } 1659 1660 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1661 rtsx_trace(chip); 1662 return STATUS_FAIL; 1663 } 1664 1665 return STATUS_SUCCESS; 1666 } 1667 1668 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1669 { 1670 struct ms_info *ms_card = &chip->ms_card; 1671 int retval; 1672 u8 val, data[8], extra[MS_EXTRA_SIZE]; 1673 1674 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1675 if (retval != STATUS_SUCCESS) { 1676 rtsx_trace(chip); 1677 return STATUS_FAIL; 1678 } 1679 1680 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1681 SystemParm, 7); 1682 if (retval != STATUS_SUCCESS) { 1683 rtsx_trace(chip); 1684 return STATUS_FAIL; 1685 } 1686 1687 ms_set_err_code(chip, MS_NO_ERROR); 1688 1689 if (CHK_MS4BIT(ms_card)) 1690 data[0] = 0x88; 1691 else 1692 data[0] = 0x80; 1693 1694 data[1] = 0; 1695 data[2] = (u8)(phy_blk >> 8); 1696 data[3] = (u8)phy_blk; 1697 data[4] = 0x80; 1698 data[5] = 0; 1699 data[6] = extra[0] & 0x7F; 1700 data[7] = 0xFF; 1701 1702 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1703 if (retval != STATUS_SUCCESS) { 1704 rtsx_trace(chip); 1705 return STATUS_FAIL; 1706 } 1707 1708 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1709 if (retval != STATUS_SUCCESS) { 1710 rtsx_trace(chip); 1711 return STATUS_FAIL; 1712 } 1713 1714 ms_set_err_code(chip, MS_NO_ERROR); 1715 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1716 if (retval != STATUS_SUCCESS) { 1717 rtsx_trace(chip); 1718 return STATUS_FAIL; 1719 } 1720 1721 if (val & INT_REG_CMDNK) { 1722 ms_set_err_code(chip, MS_CMD_NK); 1723 rtsx_trace(chip); 1724 return STATUS_FAIL; 1725 } 1726 1727 if (val & INT_REG_CED) { 1728 if (val & INT_REG_ERR) { 1729 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1730 rtsx_trace(chip); 1731 return STATUS_FAIL; 1732 } 1733 } 1734 1735 return STATUS_SUCCESS; 1736 } 1737 1738 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1739 { 1740 struct ms_info *ms_card = &chip->ms_card; 1741 int retval, i = 0; 1742 u8 val, data[6]; 1743 1744 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1745 SystemParm, 6); 1746 if (retval != STATUS_SUCCESS) { 1747 rtsx_trace(chip); 1748 return STATUS_FAIL; 1749 } 1750 1751 ms_set_err_code(chip, MS_NO_ERROR); 1752 1753 if (CHK_MS4BIT(ms_card)) 1754 data[0] = 0x88; 1755 else 1756 data[0] = 0x80; 1757 1758 data[1] = 0; 1759 data[2] = (u8)(phy_blk >> 8); 1760 data[3] = (u8)phy_blk; 1761 data[4] = 0; 1762 data[5] = 0; 1763 1764 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1765 if (retval != STATUS_SUCCESS) { 1766 rtsx_trace(chip); 1767 return STATUS_FAIL; 1768 } 1769 1770 ERASE_RTY: 1771 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1772 if (retval != STATUS_SUCCESS) { 1773 rtsx_trace(chip); 1774 return STATUS_FAIL; 1775 } 1776 1777 ms_set_err_code(chip, MS_NO_ERROR); 1778 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1779 if (retval != STATUS_SUCCESS) { 1780 rtsx_trace(chip); 1781 return STATUS_FAIL; 1782 } 1783 1784 if (val & INT_REG_CMDNK) { 1785 if (i < 3) { 1786 i++; 1787 goto ERASE_RTY; 1788 } 1789 1790 ms_set_err_code(chip, MS_CMD_NK); 1791 ms_set_bad_block(chip, phy_blk); 1792 rtsx_trace(chip); 1793 return STATUS_FAIL; 1794 } 1795 1796 if (val & INT_REG_CED) { 1797 if (val & INT_REG_ERR) { 1798 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1799 rtsx_trace(chip); 1800 return STATUS_FAIL; 1801 } 1802 } 1803 1804 return STATUS_SUCCESS; 1805 } 1806 1807 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1808 { 1809 if (!extra || (extra_len < MS_EXTRA_SIZE)) 1810 return; 1811 1812 memset(extra, 0xFF, MS_EXTRA_SIZE); 1813 1814 if (type == setPS_NG) { 1815 /* set page status as 1:NG,and block status keep 1:OK */ 1816 extra[0] = 0xB8; 1817 } else { 1818 /* set page status as 0:Data Error,and block status keep 1:OK */ 1819 extra[0] = 0x98; 1820 } 1821 1822 extra[2] = (u8)(log_blk >> 8); 1823 extra[3] = (u8)log_blk; 1824 } 1825 1826 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1827 u8 start_page, u8 end_page) 1828 { 1829 int retval; 1830 u8 extra[MS_EXTRA_SIZE], i; 1831 1832 memset(extra, 0xff, MS_EXTRA_SIZE); 1833 1834 extra[0] = 0xf8; /* Block, page OK, data erased */ 1835 extra[1] = 0xff; 1836 extra[2] = (u8)(log_blk >> 8); 1837 extra[3] = (u8)log_blk; 1838 1839 for (i = start_page; i < end_page; i++) { 1840 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1841 ms_set_err_code(chip, MS_NO_CARD); 1842 rtsx_trace(chip); 1843 return STATUS_FAIL; 1844 } 1845 1846 retval = ms_write_extra_data(chip, phy_blk, i, 1847 extra, MS_EXTRA_SIZE); 1848 if (retval != STATUS_SUCCESS) { 1849 rtsx_trace(chip); 1850 return STATUS_FAIL; 1851 } 1852 } 1853 1854 return STATUS_SUCCESS; 1855 } 1856 1857 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1858 u16 log_blk, u8 start_page, u8 end_page) 1859 { 1860 struct ms_info *ms_card = &chip->ms_card; 1861 bool uncorrect_flag = false; 1862 int retval, rty_cnt; 1863 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1864 1865 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1866 old_blk, new_blk, log_blk); 1867 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1868 start_page, end_page); 1869 1870 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1871 if (retval != STATUS_SUCCESS) { 1872 rtsx_trace(chip); 1873 return STATUS_FAIL; 1874 } 1875 1876 retval = ms_read_status_reg(chip); 1877 if (retval != STATUS_SUCCESS) { 1878 rtsx_trace(chip); 1879 return STATUS_FAIL; 1880 } 1881 1882 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1883 if (retval) { 1884 rtsx_trace(chip); 1885 return retval; 1886 } 1887 1888 if (val & BUF_FULL) { 1889 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1890 if (retval != STATUS_SUCCESS) { 1891 rtsx_trace(chip); 1892 return STATUS_FAIL; 1893 } 1894 1895 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1896 if (retval != STATUS_SUCCESS) { 1897 rtsx_trace(chip); 1898 return STATUS_FAIL; 1899 } 1900 1901 if (!(val & INT_REG_CED)) { 1902 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1903 rtsx_trace(chip); 1904 return STATUS_FAIL; 1905 } 1906 } 1907 1908 for (i = start_page; i < end_page; i++) { 1909 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1910 ms_set_err_code(chip, MS_NO_CARD); 1911 rtsx_trace(chip); 1912 return STATUS_FAIL; 1913 } 1914 1915 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE); 1916 1917 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1918 MS_EXTRA_SIZE, SystemParm, 6); 1919 if (retval != STATUS_SUCCESS) { 1920 rtsx_trace(chip); 1921 return STATUS_FAIL; 1922 } 1923 1924 ms_set_err_code(chip, MS_NO_ERROR); 1925 1926 if (CHK_MS4BIT(ms_card)) 1927 data[0] = 0x88; 1928 else 1929 data[0] = 0x80; 1930 1931 data[1] = 0; 1932 data[2] = (u8)(old_blk >> 8); 1933 data[3] = (u8)old_blk; 1934 data[4] = 0x20; 1935 data[5] = i; 1936 1937 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1938 data, 6); 1939 if (retval != STATUS_SUCCESS) { 1940 rtsx_trace(chip); 1941 return STATUS_FAIL; 1942 } 1943 1944 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1945 if (retval != STATUS_SUCCESS) { 1946 rtsx_trace(chip); 1947 return STATUS_FAIL; 1948 } 1949 1950 ms_set_err_code(chip, MS_NO_ERROR); 1951 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1952 if (retval != STATUS_SUCCESS) { 1953 rtsx_trace(chip); 1954 return STATUS_FAIL; 1955 } 1956 1957 if (val & INT_REG_CMDNK) { 1958 ms_set_err_code(chip, MS_CMD_NK); 1959 rtsx_trace(chip); 1960 return STATUS_FAIL; 1961 } 1962 1963 if (val & INT_REG_CED) { 1964 if (val & INT_REG_ERR) { 1965 retval = ms_read_status_reg(chip); 1966 if (retval != STATUS_SUCCESS) { 1967 uncorrect_flag = true; 1968 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1969 } else { 1970 uncorrect_flag = false; 1971 } 1972 1973 retval = ms_transfer_tpc(chip, 1974 MS_TM_NORMAL_READ, 1975 READ_PAGE_DATA, 1976 0, NO_WAIT_INT); 1977 if (retval != STATUS_SUCCESS) { 1978 rtsx_trace(chip); 1979 return STATUS_FAIL; 1980 } 1981 1982 if (uncorrect_flag) { 1983 ms_set_page_status(log_blk, setPS_NG, 1984 extra, MS_EXTRA_SIZE); 1985 if (i == 0) 1986 extra[0] &= 0xEF; 1987 1988 ms_write_extra_data(chip, old_blk, i, 1989 extra, MS_EXTRA_SIZE); 1990 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1991 i, extra[0]); 1992 MS_SET_BAD_BLOCK_FLG(ms_card); 1993 1994 ms_set_page_status(log_blk, setPS_Error, 1995 extra, MS_EXTRA_SIZE); 1996 ms_write_extra_data(chip, new_blk, i, 1997 extra, MS_EXTRA_SIZE); 1998 continue; 1999 } 2000 2001 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 2002 rty_cnt++) { 2003 retval = ms_transfer_tpc( 2004 chip, 2005 MS_TM_NORMAL_WRITE, 2006 WRITE_PAGE_DATA, 2007 0, NO_WAIT_INT); 2008 if (retval == STATUS_SUCCESS) 2009 break; 2010 } 2011 if (rty_cnt == MS_MAX_RETRY_COUNT) { 2012 rtsx_trace(chip); 2013 return STATUS_FAIL; 2014 } 2015 } 2016 2017 if (!(val & INT_REG_BREQ)) { 2018 ms_set_err_code(chip, MS_BREQ_ERROR); 2019 rtsx_trace(chip); 2020 return STATUS_FAIL; 2021 } 2022 } 2023 2024 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2025 MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE)); 2026 2027 ms_set_err_code(chip, MS_NO_ERROR); 2028 2029 if (CHK_MS4BIT(ms_card)) 2030 data[0] = 0x88; 2031 else 2032 data[0] = 0x80; 2033 2034 data[1] = 0; 2035 data[2] = (u8)(new_blk >> 8); 2036 data[3] = (u8)new_blk; 2037 data[4] = 0x20; 2038 data[5] = i; 2039 2040 if ((extra[0] & 0x60) != 0x60) 2041 data[6] = extra[0]; 2042 else 2043 data[6] = 0xF8; 2044 2045 data[6 + 1] = 0xFF; 2046 data[6 + 2] = (u8)(log_blk >> 8); 2047 data[6 + 3] = (u8)log_blk; 2048 2049 for (j = 4; j <= MS_EXTRA_SIZE; j++) 2050 data[6 + j] = 0xFF; 2051 2052 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 2053 NO_WAIT_INT, data, 16); 2054 if (retval != STATUS_SUCCESS) { 2055 rtsx_trace(chip); 2056 return STATUS_FAIL; 2057 } 2058 2059 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2060 if (retval != STATUS_SUCCESS) { 2061 rtsx_trace(chip); 2062 return STATUS_FAIL; 2063 } 2064 2065 ms_set_err_code(chip, MS_NO_ERROR); 2066 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 2067 if (retval != STATUS_SUCCESS) { 2068 rtsx_trace(chip); 2069 return STATUS_FAIL; 2070 } 2071 2072 if (val & INT_REG_CMDNK) { 2073 ms_set_err_code(chip, MS_CMD_NK); 2074 rtsx_trace(chip); 2075 return STATUS_FAIL; 2076 } 2077 2078 if (val & INT_REG_CED) { 2079 if (val & INT_REG_ERR) { 2080 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 2081 rtsx_trace(chip); 2082 return STATUS_FAIL; 2083 } 2084 } 2085 2086 if (i == 0) { 2087 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2088 MS_EXTRA_SIZE, SystemParm, 7); 2089 if (retval != STATUS_SUCCESS) { 2090 rtsx_trace(chip); 2091 return STATUS_FAIL; 2092 } 2093 2094 ms_set_err_code(chip, MS_NO_ERROR); 2095 2096 if (CHK_MS4BIT(ms_card)) 2097 data[0] = 0x88; 2098 else 2099 data[0] = 0x80; 2100 2101 data[1] = 0; 2102 data[2] = (u8)(old_blk >> 8); 2103 data[3] = (u8)old_blk; 2104 data[4] = 0x80; 2105 data[5] = 0; 2106 data[6] = 0xEF; 2107 data[7] = 0xFF; 2108 2109 retval = ms_write_bytes(chip, WRITE_REG, 7, 2110 NO_WAIT_INT, data, 8); 2111 if (retval != STATUS_SUCCESS) { 2112 rtsx_trace(chip); 2113 return STATUS_FAIL; 2114 } 2115 2116 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2117 if (retval != STATUS_SUCCESS) { 2118 rtsx_trace(chip); 2119 return STATUS_FAIL; 2120 } 2121 2122 ms_set_err_code(chip, MS_NO_ERROR); 2123 retval = ms_read_bytes(chip, GET_INT, 1, 2124 NO_WAIT_INT, &val, 1); 2125 if (retval != STATUS_SUCCESS) { 2126 rtsx_trace(chip); 2127 return STATUS_FAIL; 2128 } 2129 2130 if (val & INT_REG_CMDNK) { 2131 ms_set_err_code(chip, MS_CMD_NK); 2132 rtsx_trace(chip); 2133 return STATUS_FAIL; 2134 } 2135 2136 if (val & INT_REG_CED) { 2137 if (val & INT_REG_ERR) { 2138 ms_set_err_code(chip, 2139 MS_FLASH_WRITE_ERROR); 2140 rtsx_trace(chip); 2141 return STATUS_FAIL; 2142 } 2143 } 2144 } 2145 } 2146 2147 return STATUS_SUCCESS; 2148 } 2149 2150 static int reset_ms(struct rtsx_chip *chip) 2151 { 2152 struct ms_info *ms_card = &chip->ms_card; 2153 int retval; 2154 u16 i, reg_addr, block_size; 2155 u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 2156 #ifndef SUPPORT_MAGIC_GATE 2157 u16 eblock_cnt; 2158 #endif 2159 2160 retval = ms_prepare_reset(chip); 2161 if (retval != STATUS_SUCCESS) { 2162 rtsx_trace(chip); 2163 return STATUS_FAIL; 2164 } 2165 2166 ms_card->ms_type |= TYPE_MS; 2167 2168 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 2169 if (retval != STATUS_SUCCESS) { 2170 rtsx_trace(chip); 2171 return STATUS_FAIL; 2172 } 2173 2174 retval = ms_read_status_reg(chip); 2175 if (retval != STATUS_SUCCESS) { 2176 rtsx_trace(chip); 2177 return STATUS_FAIL; 2178 } 2179 2180 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 2181 if (retval) { 2182 rtsx_trace(chip); 2183 return retval; 2184 } 2185 if (val & WRT_PRTCT) 2186 chip->card_wp |= MS_CARD; 2187 else 2188 chip->card_wp &= ~MS_CARD; 2189 2190 i = 0; 2191 2192 RE_SEARCH: 2193 /* Search Boot Block */ 2194 while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 2195 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2196 ms_set_err_code(chip, MS_NO_CARD); 2197 rtsx_trace(chip); 2198 return STATUS_FAIL; 2199 } 2200 2201 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 2202 if (retval != STATUS_SUCCESS) { 2203 i++; 2204 continue; 2205 } 2206 2207 if (extra[0] & BLOCK_OK) { 2208 if (!(extra[1] & NOT_BOOT_BLOCK)) { 2209 ms_card->boot_block = i; 2210 break; 2211 } 2212 } 2213 i++; 2214 } 2215 2216 if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 2217 dev_dbg(rtsx_dev(chip), "No boot block found!"); 2218 rtsx_trace(chip); 2219 return STATUS_FAIL; 2220 } 2221 2222 for (j = 0; j < 3; j++) { 2223 retval = ms_read_page(chip, ms_card->boot_block, j); 2224 if (retval != STATUS_SUCCESS) { 2225 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 2226 i = ms_card->boot_block + 1; 2227 ms_set_err_code(chip, MS_NO_ERROR); 2228 goto RE_SEARCH; 2229 } 2230 } 2231 } 2232 2233 retval = ms_read_page(chip, ms_card->boot_block, 0); 2234 if (retval != STATUS_SUCCESS) { 2235 rtsx_trace(chip); 2236 return STATUS_FAIL; 2237 } 2238 2239 /* Read MS system information as sys_info */ 2240 rtsx_init_cmd(chip); 2241 2242 for (i = 0; i < 96; i++) 2243 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 2244 2245 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2246 if (retval < 0) { 2247 rtsx_trace(chip); 2248 return STATUS_FAIL; 2249 } 2250 2251 ptr = rtsx_get_cmd_data(chip); 2252 memcpy(ms_card->raw_sys_info, ptr, 96); 2253 2254 /* Read useful block contents */ 2255 rtsx_init_cmd(chip); 2256 2257 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 2258 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 2259 2260 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 2261 reg_addr++) 2262 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2263 2264 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 2265 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2266 2267 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0); 2268 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0); 2269 2270 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2271 if (retval < 0) { 2272 rtsx_trace(chip); 2273 return STATUS_FAIL; 2274 } 2275 2276 ptr = rtsx_get_cmd_data(chip); 2277 2278 dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 2279 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 2280 2281 /* Block ID error 2282 * HEADER_ID0, HEADER_ID1 2283 */ 2284 if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2285 i = ms_card->boot_block + 1; 2286 goto RE_SEARCH; 2287 } 2288 2289 /* Page size error 2290 * PAGE_SIZE_0, PAGE_SIZE_1 2291 */ 2292 if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2293 i = ms_card->boot_block + 1; 2294 goto RE_SEARCH; 2295 } 2296 2297 if ((ptr[14] == 1) || (ptr[14] == 3)) 2298 chip->card_wp |= MS_CARD; 2299 2300 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2301 block_size = ((u16)ptr[6] << 8) | ptr[7]; 2302 if (block_size == 0x0010) { 2303 /* Block size 16KB */ 2304 ms_card->block_shift = 5; 2305 ms_card->page_off = 0x1F; 2306 } else if (block_size == 0x0008) { 2307 /* Block size 8KB */ 2308 ms_card->block_shift = 4; 2309 ms_card->page_off = 0x0F; 2310 } 2311 2312 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2313 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2314 2315 #ifdef SUPPORT_MAGIC_GATE 2316 j = ptr[10]; 2317 2318 if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2319 if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2320 ms_card->capacity = 0x1EE0; 2321 } else { /* Effective block for 8MB: 0x3E0 */ 2322 ms_card->capacity = 0x3DE0; 2323 } 2324 } else { /* 16MB, 32MB, 64MB or 128MB */ 2325 if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2326 ms_card->capacity = 0x7BC0; 2327 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2328 ms_card->capacity = 0xF7C0; 2329 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2330 ms_card->capacity = 0x1EF80; 2331 } else { /* Effective block for 128MB: 0x1F00 */ 2332 ms_card->capacity = 0x3DF00; 2333 } 2334 } 2335 #else 2336 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2337 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2338 2339 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2340 #endif 2341 2342 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2343 2344 /* Switch I/F Mode */ 2345 if (ptr[15]) { 2346 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1); 2347 if (retval != STATUS_SUCCESS) { 2348 rtsx_trace(chip); 2349 return STATUS_FAIL; 2350 } 2351 2352 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2353 if (retval) { 2354 rtsx_trace(chip); 2355 return retval; 2356 } 2357 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2358 if (retval) { 2359 rtsx_trace(chip); 2360 return retval; 2361 } 2362 2363 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2364 NO_WAIT_INT); 2365 if (retval != STATUS_SUCCESS) { 2366 rtsx_trace(chip); 2367 return STATUS_FAIL; 2368 } 2369 2370 retval = rtsx_write_register(chip, MS_CFG, 2371 0x58 | MS_NO_CHECK_INT, 2372 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT); 2373 if (retval) { 2374 rtsx_trace(chip); 2375 return retval; 2376 } 2377 2378 ms_card->ms_type |= MS_4BIT; 2379 } 2380 2381 if (CHK_MS4BIT(ms_card)) 2382 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2383 else 2384 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2385 2386 return STATUS_SUCCESS; 2387 } 2388 2389 static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2390 { 2391 struct ms_info *ms_card = &chip->ms_card; 2392 int size, i, seg_no, retval; 2393 u16 defect_block, reg_addr; 2394 u8 val1, val2; 2395 2396 ms_card->segment_cnt = ms_card->total_block >> 9; 2397 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2398 ms_card->segment_cnt); 2399 2400 size = ms_card->segment_cnt * sizeof(struct zone_entry); 2401 ms_card->segment = vzalloc(size); 2402 if (!ms_card->segment) { 2403 rtsx_trace(chip); 2404 return STATUS_FAIL; 2405 } 2406 2407 retval = ms_read_page(chip, ms_card->boot_block, 1); 2408 if (retval != STATUS_SUCCESS) { 2409 rtsx_trace(chip); 2410 goto INIT_FAIL; 2411 } 2412 2413 reg_addr = PPBUF_BASE2; 2414 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2415 int block_no; 2416 2417 retval = rtsx_read_register(chip, reg_addr++, &val1); 2418 if (retval != STATUS_SUCCESS) { 2419 rtsx_trace(chip); 2420 goto INIT_FAIL; 2421 } 2422 2423 retval = rtsx_read_register(chip, reg_addr++, &val2); 2424 if (retval != STATUS_SUCCESS) { 2425 rtsx_trace(chip); 2426 goto INIT_FAIL; 2427 } 2428 2429 defect_block = ((u16)val1 << 8) | val2; 2430 if (defect_block == 0xFFFF) 2431 break; 2432 2433 seg_no = defect_block / 512; 2434 2435 block_no = ms_card->segment[seg_no].disable_count++; 2436 ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2437 } 2438 2439 for (i = 0; i < ms_card->segment_cnt; i++) { 2440 ms_card->segment[i].build_flag = 0; 2441 ms_card->segment[i].l2p_table = NULL; 2442 ms_card->segment[i].free_table = NULL; 2443 ms_card->segment[i].get_index = 0; 2444 ms_card->segment[i].set_index = 0; 2445 ms_card->segment[i].unused_blk_cnt = 0; 2446 2447 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2448 i, ms_card->segment[i].disable_count); 2449 } 2450 2451 return STATUS_SUCCESS; 2452 2453 INIT_FAIL: 2454 vfree(ms_card->segment); 2455 ms_card->segment = NULL; 2456 2457 return STATUS_FAIL; 2458 } 2459 2460 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2461 { 2462 struct ms_info *ms_card = &chip->ms_card; 2463 struct zone_entry *segment; 2464 2465 if (!ms_card->segment) 2466 return 0xFFFF; 2467 2468 segment = &ms_card->segment[seg_no]; 2469 2470 if (segment->l2p_table) 2471 return segment->l2p_table[log_off]; 2472 2473 return 0xFFFF; 2474 } 2475 2476 static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2477 int seg_no, u16 log_off, u16 phy_blk) 2478 { 2479 struct ms_info *ms_card = &chip->ms_card; 2480 struct zone_entry *segment; 2481 2482 if (!ms_card->segment) 2483 return; 2484 2485 segment = &ms_card->segment[seg_no]; 2486 if (segment->l2p_table) 2487 segment->l2p_table[log_off] = phy_blk; 2488 } 2489 2490 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2491 { 2492 struct ms_info *ms_card = &chip->ms_card; 2493 struct zone_entry *segment; 2494 int seg_no; 2495 2496 seg_no = (int)phy_blk >> 9; 2497 segment = &ms_card->segment[seg_no]; 2498 2499 segment->free_table[segment->set_index++] = phy_blk; 2500 if (segment->set_index >= MS_FREE_TABLE_CNT) 2501 segment->set_index = 0; 2502 2503 segment->unused_blk_cnt++; 2504 } 2505 2506 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2507 { 2508 struct ms_info *ms_card = &chip->ms_card; 2509 struct zone_entry *segment; 2510 u16 phy_blk; 2511 2512 segment = &ms_card->segment[seg_no]; 2513 2514 if (segment->unused_blk_cnt <= 0) 2515 return 0xFFFF; 2516 2517 phy_blk = segment->free_table[segment->get_index]; 2518 segment->free_table[segment->get_index++] = 0xFFFF; 2519 if (segment->get_index >= MS_FREE_TABLE_CNT) 2520 segment->get_index = 0; 2521 2522 segment->unused_blk_cnt--; 2523 2524 return phy_blk; 2525 } 2526 2527 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2528 2974, 3470, 3966, 4462, 4958, 2529 5454, 5950, 6446, 6942, 7438, 2530 7934}; 2531 2532 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2533 u16 log_off, u8 us1, u8 us2) 2534 { 2535 struct ms_info *ms_card = &chip->ms_card; 2536 struct zone_entry *segment; 2537 int seg_no; 2538 u16 tmp_blk; 2539 2540 seg_no = (int)phy_blk >> 9; 2541 segment = &ms_card->segment[seg_no]; 2542 tmp_blk = segment->l2p_table[log_off]; 2543 2544 if (us1 != us2) { 2545 if (us1 == 0) { 2546 if (!(chip->card_wp & MS_CARD)) 2547 ms_erase_block(chip, tmp_blk); 2548 2549 ms_set_unused_block(chip, tmp_blk); 2550 segment->l2p_table[log_off] = phy_blk; 2551 } else { 2552 if (!(chip->card_wp & MS_CARD)) 2553 ms_erase_block(chip, phy_blk); 2554 2555 ms_set_unused_block(chip, phy_blk); 2556 } 2557 } else { 2558 if (phy_blk < tmp_blk) { 2559 if (!(chip->card_wp & MS_CARD)) 2560 ms_erase_block(chip, phy_blk); 2561 2562 ms_set_unused_block(chip, phy_blk); 2563 } else { 2564 if (!(chip->card_wp & MS_CARD)) 2565 ms_erase_block(chip, tmp_blk); 2566 2567 ms_set_unused_block(chip, tmp_blk); 2568 segment->l2p_table[log_off] = phy_blk; 2569 } 2570 } 2571 2572 return STATUS_SUCCESS; 2573 } 2574 2575 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2576 { 2577 struct ms_info *ms_card = &chip->ms_card; 2578 struct zone_entry *segment; 2579 bool defect_flag; 2580 int retval, table_size, disable_cnt, i; 2581 u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2582 u8 extra[MS_EXTRA_SIZE], us1, us2; 2583 2584 dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no); 2585 2586 if (!ms_card->segment) { 2587 retval = ms_init_l2p_tbl(chip); 2588 if (retval != STATUS_SUCCESS) { 2589 rtsx_trace(chip); 2590 return retval; 2591 } 2592 } 2593 2594 if (ms_card->segment[seg_no].build_flag) { 2595 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2596 seg_no); 2597 return STATUS_SUCCESS; 2598 } 2599 2600 if (seg_no == 0) 2601 table_size = 494; 2602 else 2603 table_size = 496; 2604 2605 segment = &ms_card->segment[seg_no]; 2606 2607 if (!segment->l2p_table) { 2608 segment->l2p_table = vmalloc(table_size * 2); 2609 if (!segment->l2p_table) { 2610 rtsx_trace(chip); 2611 goto BUILD_FAIL; 2612 } 2613 } 2614 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2); 2615 2616 if (!segment->free_table) { 2617 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2); 2618 if (!segment->free_table) { 2619 rtsx_trace(chip); 2620 goto BUILD_FAIL; 2621 } 2622 } 2623 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2); 2624 2625 start = (u16)seg_no << 9; 2626 end = (u16)(seg_no + 1) << 9; 2627 2628 disable_cnt = segment->disable_count; 2629 2630 segment->get_index = segment->set_index = 0; 2631 segment->unused_blk_cnt = 0; 2632 2633 for (phy_blk = start; phy_blk < end; phy_blk++) { 2634 if (disable_cnt) { 2635 defect_flag = false; 2636 for (i = 0; i < segment->disable_count; i++) { 2637 if (phy_blk == segment->defect_list[i]) { 2638 defect_flag = true; 2639 break; 2640 } 2641 } 2642 if (defect_flag) { 2643 disable_cnt--; 2644 continue; 2645 } 2646 } 2647 2648 retval = ms_read_extra_data(chip, phy_blk, 0, 2649 extra, MS_EXTRA_SIZE); 2650 if (retval != STATUS_SUCCESS) { 2651 dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2652 ms_set_bad_block(chip, phy_blk); 2653 continue; 2654 } 2655 2656 if (seg_no == ms_card->segment_cnt - 1) { 2657 if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2658 if (!(chip->card_wp & MS_CARD)) { 2659 retval = ms_erase_block(chip, phy_blk); 2660 if (retval != STATUS_SUCCESS) 2661 continue; 2662 extra[2] = 0xff; 2663 extra[3] = 0xff; 2664 } 2665 } 2666 } 2667 2668 if (!(extra[0] & BLOCK_OK)) 2669 continue; 2670 if (!(extra[1] & NOT_BOOT_BLOCK)) 2671 continue; 2672 if ((extra[0] & PAGE_OK) != PAGE_OK) 2673 continue; 2674 2675 log_blk = ((u16)extra[2] << 8) | extra[3]; 2676 2677 if (log_blk == 0xFFFF) { 2678 if (!(chip->card_wp & MS_CARD)) { 2679 retval = ms_erase_block(chip, phy_blk); 2680 if (retval != STATUS_SUCCESS) 2681 continue; 2682 } 2683 ms_set_unused_block(chip, phy_blk); 2684 continue; 2685 } 2686 2687 if ((log_blk < ms_start_idx[seg_no]) || 2688 (log_blk >= ms_start_idx[seg_no + 1])) { 2689 if (!(chip->card_wp & MS_CARD)) { 2690 retval = ms_erase_block(chip, phy_blk); 2691 if (retval != STATUS_SUCCESS) 2692 continue; 2693 } 2694 ms_set_unused_block(chip, phy_blk); 2695 continue; 2696 } 2697 2698 idx = log_blk - ms_start_idx[seg_no]; 2699 2700 if (segment->l2p_table[idx] == 0xFFFF) { 2701 segment->l2p_table[idx] = phy_blk; 2702 continue; 2703 } 2704 2705 us1 = extra[0] & 0x10; 2706 tmp_blk = segment->l2p_table[idx]; 2707 retval = ms_read_extra_data(chip, tmp_blk, 0, 2708 extra, MS_EXTRA_SIZE); 2709 if (retval != STATUS_SUCCESS) 2710 continue; 2711 us2 = extra[0] & 0x10; 2712 2713 (void)ms_arbitrate_l2p(chip, phy_blk, 2714 log_blk - ms_start_idx[seg_no], us1, us2); 2715 continue; 2716 } 2717 2718 segment->build_flag = 1; 2719 2720 dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2721 segment->unused_blk_cnt); 2722 2723 /* Logical Address Confirmation Process */ 2724 if (seg_no == ms_card->segment_cnt - 1) { 2725 if (segment->unused_blk_cnt < 2) 2726 chip->card_wp |= MS_CARD; 2727 } else { 2728 if (segment->unused_blk_cnt < 1) 2729 chip->card_wp |= MS_CARD; 2730 } 2731 2732 if (chip->card_wp & MS_CARD) 2733 return STATUS_SUCCESS; 2734 2735 for (log_blk = ms_start_idx[seg_no]; 2736 log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2737 idx = log_blk - ms_start_idx[seg_no]; 2738 if (segment->l2p_table[idx] == 0xFFFF) { 2739 phy_blk = ms_get_unused_block(chip, seg_no); 2740 if (phy_blk == 0xFFFF) { 2741 chip->card_wp |= MS_CARD; 2742 return STATUS_SUCCESS; 2743 } 2744 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2745 if (retval != STATUS_SUCCESS) { 2746 rtsx_trace(chip); 2747 goto BUILD_FAIL; 2748 } 2749 2750 segment->l2p_table[idx] = phy_blk; 2751 if (seg_no == ms_card->segment_cnt - 1) { 2752 if (segment->unused_blk_cnt < 2) { 2753 chip->card_wp |= MS_CARD; 2754 return STATUS_SUCCESS; 2755 } 2756 } else { 2757 if (segment->unused_blk_cnt < 1) { 2758 chip->card_wp |= MS_CARD; 2759 return STATUS_SUCCESS; 2760 } 2761 } 2762 } 2763 } 2764 2765 /* Make boot block be the first normal block */ 2766 if (seg_no == 0) { 2767 for (log_blk = 0; log_blk < 494; log_blk++) { 2768 tmp_blk = segment->l2p_table[log_blk]; 2769 if (tmp_blk < ms_card->boot_block) { 2770 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2771 2772 if (chip->card_wp & MS_CARD) 2773 break; 2774 2775 phy_blk = ms_get_unused_block(chip, 0); 2776 retval = ms_copy_page(chip, tmp_blk, phy_blk, 2777 log_blk, 0, ms_card->page_off + 1); 2778 if (retval != STATUS_SUCCESS) { 2779 rtsx_trace(chip); 2780 return STATUS_FAIL; 2781 } 2782 2783 segment->l2p_table[log_blk] = phy_blk; 2784 2785 retval = ms_set_bad_block(chip, tmp_blk); 2786 if (retval != STATUS_SUCCESS) { 2787 rtsx_trace(chip); 2788 return STATUS_FAIL; 2789 } 2790 } 2791 } 2792 } 2793 2794 return STATUS_SUCCESS; 2795 2796 BUILD_FAIL: 2797 segment->build_flag = 0; 2798 vfree(segment->l2p_table); 2799 segment->l2p_table = NULL; 2800 vfree(segment->free_table); 2801 segment->free_table = NULL; 2802 2803 return STATUS_FAIL; 2804 } 2805 2806 int reset_ms_card(struct rtsx_chip *chip) 2807 { 2808 struct ms_info *ms_card = &chip->ms_card; 2809 int retval; 2810 2811 memset(ms_card, 0, sizeof(struct ms_info)); 2812 2813 retval = enable_card_clock(chip, MS_CARD); 2814 if (retval != STATUS_SUCCESS) { 2815 rtsx_trace(chip); 2816 return STATUS_FAIL; 2817 } 2818 2819 retval = select_card(chip, MS_CARD); 2820 if (retval != STATUS_SUCCESS) { 2821 rtsx_trace(chip); 2822 return STATUS_FAIL; 2823 } 2824 2825 ms_card->ms_type = 0; 2826 2827 retval = reset_ms_pro(chip); 2828 if (retval != STATUS_SUCCESS) { 2829 if (ms_card->check_ms_flow) { 2830 retval = reset_ms(chip); 2831 if (retval != STATUS_SUCCESS) { 2832 rtsx_trace(chip); 2833 return STATUS_FAIL; 2834 } 2835 } else { 2836 rtsx_trace(chip); 2837 return STATUS_FAIL; 2838 } 2839 } 2840 2841 retval = ms_set_init_para(chip); 2842 if (retval != STATUS_SUCCESS) { 2843 rtsx_trace(chip); 2844 return STATUS_FAIL; 2845 } 2846 2847 if (!CHK_MSPRO(ms_card)) { 2848 /* Build table for the last segment, 2849 * to check if L2P table block exists, erasing it 2850 */ 2851 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1); 2852 if (retval != STATUS_SUCCESS) { 2853 rtsx_trace(chip); 2854 return STATUS_FAIL; 2855 } 2856 } 2857 2858 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2859 2860 return STATUS_SUCCESS; 2861 } 2862 2863 static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2864 u32 start_sec, u16 sec_cnt, u8 cmd) 2865 { 2866 int retval, i; 2867 u8 data[8]; 2868 2869 data[0] = cmd; 2870 data[1] = (u8)(sec_cnt >> 8); 2871 data[2] = (u8)sec_cnt; 2872 data[3] = (u8)(start_sec >> 24); 2873 data[4] = (u8)(start_sec >> 16); 2874 data[5] = (u8)(start_sec >> 8); 2875 data[6] = (u8)start_sec; 2876 data[7] = 0; 2877 2878 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2879 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2880 WAIT_INT, data, 8); 2881 if (retval == STATUS_SUCCESS) 2882 break; 2883 } 2884 if (i == MS_MAX_RETRY_COUNT) { 2885 rtsx_trace(chip); 2886 return STATUS_FAIL; 2887 } 2888 2889 return STATUS_SUCCESS; 2890 } 2891 2892 void mspro_stop_seq_mode(struct rtsx_chip *chip) 2893 { 2894 struct ms_info *ms_card = &chip->ms_card; 2895 int retval; 2896 2897 if (ms_card->seq_mode) { 2898 retval = ms_switch_clock(chip); 2899 if (retval != STATUS_SUCCESS) 2900 return; 2901 2902 ms_card->seq_mode = 0; 2903 ms_card->total_sec_cnt = 0; 2904 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2905 2906 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2907 } 2908 } 2909 2910 static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2911 { 2912 struct ms_info *ms_card = &chip->ms_card; 2913 int retval; 2914 2915 if (chip->asic_code) { 2916 if (ms_card->ms_clock > 30) 2917 ms_card->ms_clock -= 20; 2918 } else { 2919 if (ms_card->ms_clock == CLK_80) 2920 ms_card->ms_clock = CLK_60; 2921 else if (ms_card->ms_clock == CLK_60) 2922 ms_card->ms_clock = CLK_40; 2923 } 2924 2925 retval = ms_switch_clock(chip); 2926 if (retval != STATUS_SUCCESS) { 2927 rtsx_trace(chip); 2928 return STATUS_FAIL; 2929 } 2930 2931 return STATUS_SUCCESS; 2932 } 2933 2934 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2935 struct rtsx_chip *chip, u32 start_sector, 2936 u16 sector_cnt) 2937 { 2938 struct ms_info *ms_card = &chip->ms_card; 2939 bool mode_2k = false; 2940 int retval; 2941 u16 count; 2942 u8 val, trans_mode, rw_tpc, rw_cmd; 2943 2944 ms_set_err_code(chip, MS_NO_ERROR); 2945 2946 ms_card->cleanup_counter = 0; 2947 2948 if (CHK_MSHG(ms_card)) { 2949 if ((start_sector % 4) || (sector_cnt % 4)) { 2950 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2951 rw_tpc = PRO_READ_LONG_DATA; 2952 rw_cmd = PRO_READ_DATA; 2953 } else { 2954 rw_tpc = PRO_WRITE_LONG_DATA; 2955 rw_cmd = PRO_WRITE_DATA; 2956 } 2957 } else { 2958 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2959 rw_tpc = PRO_READ_QUAD_DATA; 2960 rw_cmd = PRO_READ_2K_DATA; 2961 } else { 2962 rw_tpc = PRO_WRITE_QUAD_DATA; 2963 rw_cmd = PRO_WRITE_2K_DATA; 2964 } 2965 mode_2k = true; 2966 } 2967 } else { 2968 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2969 rw_tpc = PRO_READ_LONG_DATA; 2970 rw_cmd = PRO_READ_DATA; 2971 } else { 2972 rw_tpc = PRO_WRITE_LONG_DATA; 2973 rw_cmd = PRO_WRITE_DATA; 2974 } 2975 } 2976 2977 retval = ms_switch_clock(chip); 2978 if (retval != STATUS_SUCCESS) { 2979 rtsx_trace(chip); 2980 return STATUS_FAIL; 2981 } 2982 2983 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2984 trans_mode = MS_TM_AUTO_READ; 2985 else 2986 trans_mode = MS_TM_AUTO_WRITE; 2987 2988 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 2989 if (retval) { 2990 rtsx_trace(chip); 2991 return retval; 2992 } 2993 2994 if (ms_card->seq_mode) { 2995 if ((ms_card->pre_dir != srb->sc_data_direction) 2996 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector) 2997 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) 2998 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) 2999 || !(val & MS_INT_BREQ) 3000 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 3001 ms_card->seq_mode = 0; 3002 ms_card->total_sec_cnt = 0; 3003 if (val & MS_INT_BREQ) { 3004 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3005 if (retval != STATUS_SUCCESS) { 3006 rtsx_trace(chip); 3007 return STATUS_FAIL; 3008 } 3009 3010 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3011 } 3012 } 3013 } 3014 3015 if (!ms_card->seq_mode) { 3016 ms_card->total_sec_cnt = 0; 3017 if (sector_cnt >= SEQ_START_CRITERIA) { 3018 if ((ms_card->capacity - start_sector) > 0xFE00) 3019 count = 0xFE00; 3020 else 3021 count = (u16)(ms_card->capacity - start_sector); 3022 3023 if (count > sector_cnt) { 3024 if (mode_2k) 3025 ms_card->seq_mode = MODE_2K_SEQ; 3026 else 3027 ms_card->seq_mode = MODE_512_SEQ; 3028 } 3029 } else { 3030 count = sector_cnt; 3031 } 3032 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 3033 if (retval != STATUS_SUCCESS) { 3034 ms_card->seq_mode = 0; 3035 rtsx_trace(chip); 3036 return STATUS_FAIL; 3037 } 3038 } 3039 3040 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 3041 WAIT_INT, mode_2k, scsi_sg_count(srb), 3042 scsi_sglist(srb), scsi_bufflen(srb)); 3043 if (retval != STATUS_SUCCESS) { 3044 ms_card->seq_mode = 0; 3045 rtsx_read_register(chip, MS_TRANS_CFG, &val); 3046 rtsx_clear_ms_error(chip); 3047 3048 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3049 chip->rw_need_retry = 0; 3050 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n"); 3051 rtsx_trace(chip); 3052 return STATUS_FAIL; 3053 } 3054 3055 if (val & MS_INT_BREQ) 3056 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3057 3058 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3059 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 3060 chip->rw_need_retry = 1; 3061 ms_auto_tune_clock(chip); 3062 } 3063 3064 rtsx_trace(chip); 3065 return retval; 3066 } 3067 3068 if (ms_card->seq_mode) { 3069 ms_card->pre_sec_addr = start_sector; 3070 ms_card->pre_sec_cnt = sector_cnt; 3071 ms_card->pre_dir = srb->sc_data_direction; 3072 ms_card->total_sec_cnt += sector_cnt; 3073 } 3074 3075 return STATUS_SUCCESS; 3076 } 3077 3078 static int mspro_read_format_progress(struct rtsx_chip *chip, 3079 const int short_data_len) 3080 { 3081 struct ms_info *ms_card = &chip->ms_card; 3082 int retval, i; 3083 u32 total_progress, cur_progress; 3084 u8 cnt, tmp; 3085 u8 data[8]; 3086 3087 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n", 3088 short_data_len); 3089 3090 retval = ms_switch_clock(chip); 3091 if (retval != STATUS_SUCCESS) { 3092 ms_card->format_status = FORMAT_FAIL; 3093 rtsx_trace(chip); 3094 return STATUS_FAIL; 3095 } 3096 3097 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3098 if (retval != STATUS_SUCCESS) { 3099 ms_card->format_status = FORMAT_FAIL; 3100 rtsx_trace(chip); 3101 return STATUS_FAIL; 3102 } 3103 3104 if (!(tmp & MS_INT_BREQ)) { 3105 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) { 3106 ms_card->format_status = FORMAT_SUCCESS; 3107 return STATUS_SUCCESS; 3108 } 3109 ms_card->format_status = FORMAT_FAIL; 3110 rtsx_trace(chip); 3111 return STATUS_FAIL; 3112 } 3113 3114 if (short_data_len >= 256) 3115 cnt = 0; 3116 else 3117 cnt = (u8)short_data_len; 3118 3119 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 3120 MS_NO_CHECK_INT); 3121 if (retval != STATUS_SUCCESS) { 3122 ms_card->format_status = FORMAT_FAIL; 3123 rtsx_trace(chip); 3124 return STATUS_FAIL; 3125 } 3126 3127 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 3128 data, 8); 3129 if (retval != STATUS_SUCCESS) { 3130 ms_card->format_status = FORMAT_FAIL; 3131 rtsx_trace(chip); 3132 return STATUS_FAIL; 3133 } 3134 3135 total_progress = (data[0] << 24) | (data[1] << 16) | 3136 (data[2] << 8) | data[3]; 3137 cur_progress = (data[4] << 24) | (data[5] << 16) | 3138 (data[6] << 8) | data[7]; 3139 3140 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 3141 total_progress, cur_progress); 3142 3143 if (total_progress == 0) { 3144 ms_card->progress = 0; 3145 } else { 3146 u64 ulltmp = (u64)cur_progress * (u64)65535; 3147 3148 do_div(ulltmp, total_progress); 3149 ms_card->progress = (u16)ulltmp; 3150 } 3151 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 3152 3153 for (i = 0; i < 5000; i++) { 3154 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3155 if (retval != STATUS_SUCCESS) { 3156 ms_card->format_status = FORMAT_FAIL; 3157 rtsx_trace(chip); 3158 return STATUS_FAIL; 3159 } 3160 if (tmp & (MS_INT_CED | MS_INT_CMDNK | 3161 MS_INT_BREQ | MS_INT_ERR)) 3162 break; 3163 3164 wait_timeout(1); 3165 } 3166 3167 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 3168 if (retval != STATUS_SUCCESS) { 3169 ms_card->format_status = FORMAT_FAIL; 3170 rtsx_trace(chip); 3171 return STATUS_FAIL; 3172 } 3173 3174 if (i == 5000) { 3175 ms_card->format_status = FORMAT_FAIL; 3176 rtsx_trace(chip); 3177 return STATUS_FAIL; 3178 } 3179 3180 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3181 ms_card->format_status = FORMAT_FAIL; 3182 rtsx_trace(chip); 3183 return STATUS_FAIL; 3184 } 3185 3186 if (tmp & MS_INT_CED) { 3187 ms_card->format_status = FORMAT_SUCCESS; 3188 ms_card->pro_under_formatting = 0; 3189 } else if (tmp & MS_INT_BREQ) { 3190 ms_card->format_status = FORMAT_IN_PROGRESS; 3191 } else { 3192 ms_card->format_status = FORMAT_FAIL; 3193 ms_card->pro_under_formatting = 0; 3194 rtsx_trace(chip); 3195 return STATUS_FAIL; 3196 } 3197 3198 return STATUS_SUCCESS; 3199 } 3200 3201 void mspro_polling_format_status(struct rtsx_chip *chip) 3202 { 3203 struct ms_info *ms_card = &chip->ms_card; 3204 int i; 3205 3206 if (ms_card->pro_under_formatting && 3207 (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 3208 rtsx_set_stat(chip, RTSX_STAT_RUN); 3209 3210 for (i = 0; i < 65535; i++) { 3211 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 3212 if (ms_card->format_status != FORMAT_IN_PROGRESS) 3213 break; 3214 } 3215 } 3216 } 3217 3218 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3219 int short_data_len, bool quick_format) 3220 { 3221 struct ms_info *ms_card = &chip->ms_card; 3222 int retval, i; 3223 u8 buf[8], tmp; 3224 u16 para; 3225 3226 retval = ms_switch_clock(chip); 3227 if (retval != STATUS_SUCCESS) { 3228 rtsx_trace(chip); 3229 return STATUS_FAIL; 3230 } 3231 3232 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01); 3233 if (retval != STATUS_SUCCESS) { 3234 rtsx_trace(chip); 3235 return STATUS_FAIL; 3236 } 3237 3238 memset(buf, 0, 2); 3239 switch (short_data_len) { 3240 case 32: 3241 buf[0] = 0; 3242 break; 3243 case 64: 3244 buf[0] = 1; 3245 break; 3246 case 128: 3247 buf[0] = 2; 3248 break; 3249 case 256: 3250 default: 3251 buf[0] = 3; 3252 break; 3253 } 3254 3255 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3256 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 3257 NO_WAIT_INT, buf, 2); 3258 if (retval == STATUS_SUCCESS) 3259 break; 3260 } 3261 if (i == MS_MAX_RETRY_COUNT) { 3262 rtsx_trace(chip); 3263 return STATUS_FAIL; 3264 } 3265 3266 if (quick_format) 3267 para = 0x0000; 3268 else 3269 para = 0x0001; 3270 3271 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 3272 if (retval != STATUS_SUCCESS) { 3273 rtsx_trace(chip); 3274 return STATUS_FAIL; 3275 } 3276 3277 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3278 if (retval) { 3279 rtsx_trace(chip); 3280 return retval; 3281 } 3282 3283 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3284 rtsx_trace(chip); 3285 return STATUS_FAIL; 3286 } 3287 3288 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 3289 ms_card->pro_under_formatting = 1; 3290 ms_card->progress = 0; 3291 ms_card->format_status = FORMAT_IN_PROGRESS; 3292 return STATUS_SUCCESS; 3293 } 3294 3295 if (tmp & MS_INT_CED) { 3296 ms_card->pro_under_formatting = 0; 3297 ms_card->progress = 0; 3298 ms_card->format_status = FORMAT_SUCCESS; 3299 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 3300 return STATUS_SUCCESS; 3301 } 3302 3303 rtsx_trace(chip); 3304 return STATUS_FAIL; 3305 } 3306 3307 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 3308 u16 log_blk, u8 start_page, u8 end_page, 3309 u8 *buf, unsigned int *index, 3310 unsigned int *offset) 3311 { 3312 struct ms_info *ms_card = &chip->ms_card; 3313 int retval, i; 3314 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 3315 u8 *ptr; 3316 3317 retval = ms_read_extra_data(chip, phy_blk, start_page, 3318 extra, MS_EXTRA_SIZE); 3319 if (retval == STATUS_SUCCESS) { 3320 if ((extra[1] & 0x30) != 0x30) { 3321 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3322 rtsx_trace(chip); 3323 return STATUS_FAIL; 3324 } 3325 } 3326 3327 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3328 SystemParm, 6); 3329 if (retval != STATUS_SUCCESS) { 3330 rtsx_trace(chip); 3331 return STATUS_FAIL; 3332 } 3333 3334 if (CHK_MS4BIT(ms_card)) 3335 data[0] = 0x88; 3336 else 3337 data[0] = 0x80; 3338 3339 data[1] = 0; 3340 data[2] = (u8)(phy_blk >> 8); 3341 data[3] = (u8)phy_blk; 3342 data[4] = 0; 3343 data[5] = start_page; 3344 3345 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3346 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 3347 data, 6); 3348 if (retval == STATUS_SUCCESS) 3349 break; 3350 } 3351 if (i == MS_MAX_RETRY_COUNT) { 3352 rtsx_trace(chip); 3353 return STATUS_FAIL; 3354 } 3355 3356 ms_set_err_code(chip, MS_NO_ERROR); 3357 3358 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3359 if (retval != STATUS_SUCCESS) { 3360 rtsx_trace(chip); 3361 return STATUS_FAIL; 3362 } 3363 3364 ptr = buf; 3365 3366 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3367 ms_set_err_code(chip, MS_NO_ERROR); 3368 3369 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3370 ms_set_err_code(chip, MS_NO_CARD); 3371 rtsx_trace(chip); 3372 return STATUS_FAIL; 3373 } 3374 3375 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3376 if (retval != STATUS_SUCCESS) { 3377 rtsx_trace(chip); 3378 return STATUS_FAIL; 3379 } 3380 3381 if (val & INT_REG_CMDNK) { 3382 ms_set_err_code(chip, MS_CMD_NK); 3383 rtsx_trace(chip); 3384 return STATUS_FAIL; 3385 } 3386 if (val & INT_REG_ERR) { 3387 if (val & INT_REG_BREQ) { 3388 retval = ms_read_status_reg(chip); 3389 if (retval != STATUS_SUCCESS) { 3390 if (!(chip->card_wp & MS_CARD)) { 3391 reset_ms(chip); 3392 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE); 3393 ms_write_extra_data(chip, phy_blk, 3394 page_addr, extra, MS_EXTRA_SIZE); 3395 } 3396 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3397 rtsx_trace(chip); 3398 return STATUS_FAIL; 3399 } 3400 } else { 3401 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3402 rtsx_trace(chip); 3403 return STATUS_FAIL; 3404 } 3405 } else { 3406 if (!(val & INT_REG_BREQ)) { 3407 ms_set_err_code(chip, MS_BREQ_ERROR); 3408 rtsx_trace(chip); 3409 return STATUS_FAIL; 3410 } 3411 } 3412 3413 if (page_addr == (end_page - 1)) { 3414 if (!(val & INT_REG_CED)) { 3415 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3416 if (retval != STATUS_SUCCESS) { 3417 rtsx_trace(chip); 3418 return STATUS_FAIL; 3419 } 3420 } 3421 3422 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3423 &val, 1); 3424 if (retval != STATUS_SUCCESS) { 3425 rtsx_trace(chip); 3426 return STATUS_FAIL; 3427 } 3428 3429 if (!(val & INT_REG_CED)) { 3430 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3431 rtsx_trace(chip); 3432 return STATUS_FAIL; 3433 } 3434 3435 trans_cfg = NO_WAIT_INT; 3436 } else { 3437 trans_cfg = WAIT_INT; 3438 } 3439 3440 rtsx_init_cmd(chip); 3441 3442 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3443 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3444 0xFF, trans_cfg); 3445 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3446 0x01, RING_BUFFER); 3447 3448 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3449 3450 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3451 MS_TRANSFER_START | MS_TM_NORMAL_READ); 3452 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3453 MS_TRANSFER_END, MS_TRANSFER_END); 3454 3455 rtsx_send_cmd_no_wait(chip); 3456 3457 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3458 512, scsi_sg_count(chip->srb), 3459 index, offset, DMA_FROM_DEVICE, 3460 chip->ms_timeout); 3461 if (retval < 0) { 3462 if (retval == -ETIMEDOUT) { 3463 ms_set_err_code(chip, MS_TO_ERROR); 3464 rtsx_clear_ms_error(chip); 3465 rtsx_trace(chip); 3466 return STATUS_TIMEDOUT; 3467 } 3468 3469 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3470 if (retval != STATUS_SUCCESS) { 3471 ms_set_err_code(chip, MS_TO_ERROR); 3472 rtsx_clear_ms_error(chip); 3473 rtsx_trace(chip); 3474 return STATUS_TIMEDOUT; 3475 } 3476 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3477 ms_set_err_code(chip, MS_CRC16_ERROR); 3478 rtsx_clear_ms_error(chip); 3479 rtsx_trace(chip); 3480 return STATUS_FAIL; 3481 } 3482 } 3483 3484 if (scsi_sg_count(chip->srb) == 0) 3485 ptr += 512; 3486 } 3487 3488 return STATUS_SUCCESS; 3489 } 3490 3491 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3492 u16 new_blk, u16 log_blk, u8 start_page, 3493 u8 end_page, u8 *buf, unsigned int *index, 3494 unsigned int *offset) 3495 { 3496 struct ms_info *ms_card = &chip->ms_card; 3497 int retval, i; 3498 u8 page_addr, val, data[16]; 3499 u8 *ptr; 3500 3501 if (!start_page) { 3502 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3503 SystemParm, 7); 3504 if (retval != STATUS_SUCCESS) { 3505 rtsx_trace(chip); 3506 return STATUS_FAIL; 3507 } 3508 3509 if (CHK_MS4BIT(ms_card)) 3510 data[0] = 0x88; 3511 else 3512 data[0] = 0x80; 3513 3514 data[1] = 0; 3515 data[2] = (u8)(old_blk >> 8); 3516 data[3] = (u8)old_blk; 3517 data[4] = 0x80; 3518 data[5] = 0; 3519 data[6] = 0xEF; 3520 data[7] = 0xFF; 3521 3522 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3523 data, 8); 3524 if (retval != STATUS_SUCCESS) { 3525 rtsx_trace(chip); 3526 return STATUS_FAIL; 3527 } 3528 3529 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3530 if (retval != STATUS_SUCCESS) { 3531 rtsx_trace(chip); 3532 return STATUS_FAIL; 3533 } 3534 3535 ms_set_err_code(chip, MS_NO_ERROR); 3536 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3537 NO_WAIT_INT); 3538 if (retval != STATUS_SUCCESS) { 3539 rtsx_trace(chip); 3540 return STATUS_FAIL; 3541 } 3542 } 3543 3544 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3545 SystemParm, (6 + MS_EXTRA_SIZE)); 3546 if (retval != STATUS_SUCCESS) { 3547 rtsx_trace(chip); 3548 return STATUS_FAIL; 3549 } 3550 3551 ms_set_err_code(chip, MS_NO_ERROR); 3552 3553 if (CHK_MS4BIT(ms_card)) 3554 data[0] = 0x88; 3555 else 3556 data[0] = 0x80; 3557 3558 data[1] = 0; 3559 data[2] = (u8)(new_blk >> 8); 3560 data[3] = (u8)new_blk; 3561 if ((end_page - start_page) == 1) 3562 data[4] = 0x20; 3563 else 3564 data[4] = 0; 3565 3566 data[5] = start_page; 3567 data[6] = 0xF8; 3568 data[7] = 0xFF; 3569 data[8] = (u8)(log_blk >> 8); 3570 data[9] = (u8)log_blk; 3571 3572 for (i = 0x0A; i < 0x10; i++) 3573 data[i] = 0xFF; 3574 3575 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3576 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3577 NO_WAIT_INT, data, 16); 3578 if (retval == STATUS_SUCCESS) 3579 break; 3580 } 3581 if (i == MS_MAX_RETRY_COUNT) { 3582 rtsx_trace(chip); 3583 return STATUS_FAIL; 3584 } 3585 3586 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3587 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3588 if (retval == STATUS_SUCCESS) 3589 break; 3590 } 3591 if (i == MS_MAX_RETRY_COUNT) { 3592 rtsx_trace(chip); 3593 return STATUS_FAIL; 3594 } 3595 3596 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3597 if (retval != STATUS_SUCCESS) { 3598 rtsx_trace(chip); 3599 return STATUS_FAIL; 3600 } 3601 3602 ptr = buf; 3603 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3604 ms_set_err_code(chip, MS_NO_ERROR); 3605 3606 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3607 ms_set_err_code(chip, MS_NO_CARD); 3608 rtsx_trace(chip); 3609 return STATUS_FAIL; 3610 } 3611 3612 if (val & INT_REG_CMDNK) { 3613 ms_set_err_code(chip, MS_CMD_NK); 3614 rtsx_trace(chip); 3615 return STATUS_FAIL; 3616 } 3617 if (val & INT_REG_ERR) { 3618 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3619 rtsx_trace(chip); 3620 return STATUS_FAIL; 3621 } 3622 if (!(val & INT_REG_BREQ)) { 3623 ms_set_err_code(chip, MS_BREQ_ERROR); 3624 rtsx_trace(chip); 3625 return STATUS_FAIL; 3626 } 3627 3628 udelay(30); 3629 3630 rtsx_init_cmd(chip); 3631 3632 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3633 0xFF, WRITE_PAGE_DATA); 3634 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3635 0xFF, WAIT_INT); 3636 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3637 0x01, RING_BUFFER); 3638 3639 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3640 3641 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3642 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3643 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3644 MS_TRANSFER_END, MS_TRANSFER_END); 3645 3646 rtsx_send_cmd_no_wait(chip); 3647 3648 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3649 512, scsi_sg_count(chip->srb), 3650 index, offset, DMA_TO_DEVICE, 3651 chip->ms_timeout); 3652 if (retval < 0) { 3653 ms_set_err_code(chip, MS_TO_ERROR); 3654 rtsx_clear_ms_error(chip); 3655 3656 if (retval == -ETIMEDOUT) { 3657 rtsx_trace(chip); 3658 return STATUS_TIMEDOUT; 3659 } 3660 rtsx_trace(chip); 3661 return STATUS_FAIL; 3662 } 3663 3664 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3665 if (retval != STATUS_SUCCESS) { 3666 rtsx_trace(chip); 3667 return STATUS_FAIL; 3668 } 3669 3670 if ((end_page - start_page) == 1) { 3671 if (!(val & INT_REG_CED)) { 3672 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3673 rtsx_trace(chip); 3674 return STATUS_FAIL; 3675 } 3676 } else { 3677 if (page_addr == (end_page - 1)) { 3678 if (!(val & INT_REG_CED)) { 3679 retval = ms_send_cmd(chip, BLOCK_END, 3680 WAIT_INT); 3681 if (retval != STATUS_SUCCESS) { 3682 rtsx_trace(chip); 3683 return STATUS_FAIL; 3684 } 3685 } 3686 3687 retval = ms_read_bytes(chip, GET_INT, 1, 3688 NO_WAIT_INT, &val, 1); 3689 if (retval != STATUS_SUCCESS) { 3690 rtsx_trace(chip); 3691 return STATUS_FAIL; 3692 } 3693 } 3694 3695 if ((page_addr == (end_page - 1)) || 3696 (page_addr == ms_card->page_off)) { 3697 if (!(val & INT_REG_CED)) { 3698 ms_set_err_code(chip, 3699 MS_FLASH_WRITE_ERROR); 3700 rtsx_trace(chip); 3701 return STATUS_FAIL; 3702 } 3703 } 3704 } 3705 3706 if (scsi_sg_count(chip->srb) == 0) 3707 ptr += 512; 3708 } 3709 3710 return STATUS_SUCCESS; 3711 } 3712 3713 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3714 u16 log_blk, u8 page_off) 3715 { 3716 struct ms_info *ms_card = &chip->ms_card; 3717 int retval, seg_no; 3718 3719 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3720 page_off, ms_card->page_off + 1); 3721 if (retval != STATUS_SUCCESS) { 3722 rtsx_trace(chip); 3723 return STATUS_FAIL; 3724 } 3725 3726 seg_no = old_blk >> 9; 3727 3728 if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3729 MS_CLR_BAD_BLOCK_FLG(ms_card); 3730 ms_set_bad_block(chip, old_blk); 3731 } else { 3732 retval = ms_erase_block(chip, old_blk); 3733 if (retval == STATUS_SUCCESS) 3734 ms_set_unused_block(chip, old_blk); 3735 } 3736 3737 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3738 3739 return STATUS_SUCCESS; 3740 } 3741 3742 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3743 u16 log_blk, u8 start_page) 3744 { 3745 int retval; 3746 3747 if (start_page) { 3748 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3749 0, start_page); 3750 if (retval != STATUS_SUCCESS) { 3751 rtsx_trace(chip); 3752 return STATUS_FAIL; 3753 } 3754 } 3755 3756 return STATUS_SUCCESS; 3757 } 3758 3759 #ifdef MS_DELAY_WRITE 3760 int ms_delay_write(struct rtsx_chip *chip) 3761 { 3762 struct ms_info *ms_card = &chip->ms_card; 3763 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3764 int retval; 3765 3766 if (delay_write->delay_write_flag) { 3767 retval = ms_set_init_para(chip); 3768 if (retval != STATUS_SUCCESS) { 3769 rtsx_trace(chip); 3770 return STATUS_FAIL; 3771 } 3772 3773 delay_write->delay_write_flag = 0; 3774 retval = ms_finish_write(chip, 3775 delay_write->old_phyblock, 3776 delay_write->new_phyblock, 3777 delay_write->logblock, 3778 delay_write->pageoff); 3779 if (retval != STATUS_SUCCESS) { 3780 rtsx_trace(chip); 3781 return STATUS_FAIL; 3782 } 3783 } 3784 3785 return STATUS_SUCCESS; 3786 } 3787 #endif 3788 3789 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3790 { 3791 if (srb->sc_data_direction == DMA_FROM_DEVICE) 3792 set_sense_type(chip, SCSI_LUN(srb), 3793 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3794 else 3795 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3796 } 3797 3798 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3799 u32 start_sector, u16 sector_cnt) 3800 { 3801 struct ms_info *ms_card = &chip->ms_card; 3802 unsigned int lun = SCSI_LUN(srb); 3803 int retval, seg_no; 3804 unsigned int index = 0, offset = 0; 3805 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3806 u8 start_page, end_page = 0, page_cnt; 3807 u8 *ptr; 3808 #ifdef MS_DELAY_WRITE 3809 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3810 #endif 3811 3812 ms_set_err_code(chip, MS_NO_ERROR); 3813 3814 ms_card->cleanup_counter = 0; 3815 3816 ptr = (u8 *)scsi_sglist(srb); 3817 3818 retval = ms_switch_clock(chip); 3819 if (retval != STATUS_SUCCESS) { 3820 ms_rw_fail(srb, chip); 3821 rtsx_trace(chip); 3822 return STATUS_FAIL; 3823 } 3824 3825 log_blk = (u16)(start_sector >> ms_card->block_shift); 3826 start_page = (u8)(start_sector & ms_card->page_off); 3827 3828 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3829 if (log_blk < ms_start_idx[seg_no + 1]) 3830 break; 3831 } 3832 3833 if (ms_card->segment[seg_no].build_flag == 0) { 3834 retval = ms_build_l2p_tbl(chip, seg_no); 3835 if (retval != STATUS_SUCCESS) { 3836 chip->card_fail |= MS_CARD; 3837 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3838 rtsx_trace(chip); 3839 return STATUS_FAIL; 3840 } 3841 } 3842 3843 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3844 #ifdef MS_DELAY_WRITE 3845 if (delay_write->delay_write_flag && 3846 (delay_write->logblock == log_blk) && 3847 (start_page > delay_write->pageoff)) { 3848 delay_write->delay_write_flag = 0; 3849 retval = ms_copy_page(chip, 3850 delay_write->old_phyblock, 3851 delay_write->new_phyblock, log_blk, 3852 delay_write->pageoff, start_page); 3853 if (retval != STATUS_SUCCESS) { 3854 set_sense_type(chip, lun, 3855 SENSE_TYPE_MEDIA_WRITE_ERR); 3856 rtsx_trace(chip); 3857 return STATUS_FAIL; 3858 } 3859 old_blk = delay_write->old_phyblock; 3860 new_blk = delay_write->new_phyblock; 3861 } else if (delay_write->delay_write_flag && 3862 (delay_write->logblock == log_blk) && 3863 (start_page == delay_write->pageoff)) { 3864 delay_write->delay_write_flag = 0; 3865 old_blk = delay_write->old_phyblock; 3866 new_blk = delay_write->new_phyblock; 3867 } else { 3868 retval = ms_delay_write(chip); 3869 if (retval != STATUS_SUCCESS) { 3870 set_sense_type(chip, lun, 3871 SENSE_TYPE_MEDIA_WRITE_ERR); 3872 rtsx_trace(chip); 3873 return STATUS_FAIL; 3874 } 3875 #endif 3876 old_blk = ms_get_l2p_tbl(chip, seg_no, 3877 log_blk - ms_start_idx[seg_no]); 3878 new_blk = ms_get_unused_block(chip, seg_no); 3879 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) { 3880 set_sense_type(chip, lun, 3881 SENSE_TYPE_MEDIA_WRITE_ERR); 3882 rtsx_trace(chip); 3883 return STATUS_FAIL; 3884 } 3885 3886 retval = ms_prepare_write(chip, old_blk, new_blk, 3887 log_blk, start_page); 3888 if (retval != STATUS_SUCCESS) { 3889 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3890 set_sense_type(chip, lun, 3891 SENSE_TYPE_MEDIA_NOT_PRESENT); 3892 rtsx_trace(chip); 3893 return STATUS_FAIL; 3894 } 3895 set_sense_type(chip, lun, 3896 SENSE_TYPE_MEDIA_WRITE_ERR); 3897 rtsx_trace(chip); 3898 return STATUS_FAIL; 3899 } 3900 #ifdef MS_DELAY_WRITE 3901 } 3902 #endif 3903 } else { 3904 #ifdef MS_DELAY_WRITE 3905 retval = ms_delay_write(chip); 3906 if (retval != STATUS_SUCCESS) { 3907 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3908 set_sense_type(chip, lun, 3909 SENSE_TYPE_MEDIA_NOT_PRESENT); 3910 rtsx_trace(chip); 3911 return STATUS_FAIL; 3912 } 3913 set_sense_type(chip, lun, 3914 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3915 rtsx_trace(chip); 3916 return STATUS_FAIL; 3917 } 3918 #endif 3919 old_blk = ms_get_l2p_tbl(chip, seg_no, 3920 log_blk - ms_start_idx[seg_no]); 3921 if (old_blk == 0xFFFF) { 3922 set_sense_type(chip, lun, 3923 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3924 rtsx_trace(chip); 3925 return STATUS_FAIL; 3926 } 3927 } 3928 3929 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3930 seg_no, old_blk, new_blk); 3931 3932 while (total_sec_cnt) { 3933 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3934 end_page = ms_card->page_off + 1; 3935 else 3936 end_page = start_page + (u8)total_sec_cnt; 3937 3938 page_cnt = end_page - start_page; 3939 3940 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3941 start_page, end_page, page_cnt); 3942 3943 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3944 retval = ms_read_multiple_pages(chip, 3945 old_blk, log_blk, start_page, end_page, 3946 ptr, &index, &offset); 3947 } else { 3948 retval = ms_write_multiple_pages(chip, old_blk, 3949 new_blk, log_blk, start_page, end_page, 3950 ptr, &index, &offset); 3951 } 3952 3953 if (retval != STATUS_SUCCESS) { 3954 toggle_gpio(chip, 1); 3955 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3956 set_sense_type(chip, lun, 3957 SENSE_TYPE_MEDIA_NOT_PRESENT); 3958 rtsx_trace(chip); 3959 return STATUS_FAIL; 3960 } 3961 ms_rw_fail(srb, chip); 3962 rtsx_trace(chip); 3963 return STATUS_FAIL; 3964 } 3965 3966 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3967 if (end_page == (ms_card->page_off + 1)) { 3968 retval = ms_erase_block(chip, old_blk); 3969 if (retval == STATUS_SUCCESS) 3970 ms_set_unused_block(chip, old_blk); 3971 3972 ms_set_l2p_tbl(chip, seg_no, 3973 log_blk - ms_start_idx[seg_no], 3974 new_blk); 3975 } 3976 } 3977 3978 total_sec_cnt -= page_cnt; 3979 if (scsi_sg_count(srb) == 0) 3980 ptr += page_cnt * 512; 3981 3982 if (total_sec_cnt == 0) 3983 break; 3984 3985 log_blk++; 3986 3987 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 3988 seg_no++) { 3989 if (log_blk < ms_start_idx[seg_no + 1]) 3990 break; 3991 } 3992 3993 if (ms_card->segment[seg_no].build_flag == 0) { 3994 retval = ms_build_l2p_tbl(chip, seg_no); 3995 if (retval != STATUS_SUCCESS) { 3996 chip->card_fail |= MS_CARD; 3997 set_sense_type(chip, lun, 3998 SENSE_TYPE_MEDIA_NOT_PRESENT); 3999 rtsx_trace(chip); 4000 return STATUS_FAIL; 4001 } 4002 } 4003 4004 old_blk = ms_get_l2p_tbl(chip, seg_no, 4005 log_blk - ms_start_idx[seg_no]); 4006 if (old_blk == 0xFFFF) { 4007 ms_rw_fail(srb, chip); 4008 rtsx_trace(chip); 4009 return STATUS_FAIL; 4010 } 4011 4012 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4013 new_blk = ms_get_unused_block(chip, seg_no); 4014 if (new_blk == 0xFFFF) { 4015 ms_rw_fail(srb, chip); 4016 rtsx_trace(chip); 4017 return STATUS_FAIL; 4018 } 4019 } 4020 4021 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 4022 seg_no, old_blk, new_blk); 4023 4024 start_page = 0; 4025 } 4026 4027 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4028 if (end_page < (ms_card->page_off + 1)) { 4029 #ifdef MS_DELAY_WRITE 4030 delay_write->delay_write_flag = 1; 4031 delay_write->old_phyblock = old_blk; 4032 delay_write->new_phyblock = new_blk; 4033 delay_write->logblock = log_blk; 4034 delay_write->pageoff = end_page; 4035 #else 4036 retval = ms_finish_write(chip, old_blk, new_blk, 4037 log_blk, end_page); 4038 if (retval != STATUS_SUCCESS) { 4039 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 4040 set_sense_type(chip, lun, 4041 SENSE_TYPE_MEDIA_NOT_PRESENT); 4042 rtsx_trace(chip); 4043 return STATUS_FAIL; 4044 } 4045 4046 ms_rw_fail(srb, chip); 4047 rtsx_trace(chip); 4048 return STATUS_FAIL; 4049 } 4050 #endif 4051 } 4052 } 4053 4054 scsi_set_resid(srb, 0); 4055 4056 return STATUS_SUCCESS; 4057 } 4058 4059 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 4060 u32 start_sector, u16 sector_cnt) 4061 { 4062 struct ms_info *ms_card = &chip->ms_card; 4063 int retval; 4064 4065 if (CHK_MSPRO(ms_card)) 4066 retval = mspro_rw_multi_sector(srb, chip, start_sector, 4067 sector_cnt); 4068 else 4069 retval = ms_rw_multi_sector(srb, chip, start_sector, 4070 sector_cnt); 4071 4072 return retval; 4073 } 4074 4075 void ms_free_l2p_tbl(struct rtsx_chip *chip) 4076 { 4077 struct ms_info *ms_card = &chip->ms_card; 4078 int i = 0; 4079 4080 if (ms_card->segment) { 4081 for (i = 0; i < ms_card->segment_cnt; i++) { 4082 vfree(ms_card->segment[i].l2p_table); 4083 ms_card->segment[i].l2p_table = NULL; 4084 vfree(ms_card->segment[i].free_table); 4085 ms_card->segment[i].free_table = NULL; 4086 } 4087 vfree(ms_card->segment); 4088 ms_card->segment = NULL; 4089 } 4090 } 4091 4092 #ifdef SUPPORT_MAGIC_GATE 4093 4094 #ifdef READ_BYTES_WAIT_INT 4095 static int ms_poll_int(struct rtsx_chip *chip) 4096 { 4097 int retval; 4098 u8 val; 4099 4100 rtsx_init_cmd(chip); 4101 4102 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 4103 4104 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 4105 if (retval != STATUS_SUCCESS) { 4106 rtsx_trace(chip); 4107 return STATUS_FAIL; 4108 } 4109 4110 val = *rtsx_get_cmd_data(chip); 4111 if (val & MS_INT_ERR) { 4112 rtsx_trace(chip); 4113 return STATUS_FAIL; 4114 } 4115 4116 return STATUS_SUCCESS; 4117 } 4118 #endif 4119 4120 #ifdef MS_SAMPLE_INT_ERR 4121 static int check_ms_err(struct rtsx_chip *chip) 4122 { 4123 int retval; 4124 u8 val; 4125 4126 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4127 if (retval != STATUS_SUCCESS) 4128 return 1; 4129 if (val & MS_TRANSFER_ERR) 4130 return 1; 4131 4132 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 4133 if (retval != STATUS_SUCCESS) 4134 return 1; 4135 4136 if (val & (MS_INT_ERR | MS_INT_CMDNK)) 4137 return 1; 4138 4139 return 0; 4140 } 4141 #else 4142 static int check_ms_err(struct rtsx_chip *chip) 4143 { 4144 int retval; 4145 u8 val; 4146 4147 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4148 if (retval != STATUS_SUCCESS) 4149 return 1; 4150 if (val & MS_TRANSFER_ERR) 4151 return 1; 4152 4153 return 0; 4154 } 4155 #endif 4156 4157 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 4158 { 4159 int retval, i; 4160 u8 data[8]; 4161 4162 data[0] = cmd; 4163 data[1] = 0; 4164 data[2] = 0; 4165 data[3] = 0; 4166 data[4] = 0; 4167 data[5] = 0; 4168 data[6] = entry_num; 4169 data[7] = 0; 4170 4171 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 4172 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 4173 data, 8); 4174 if (retval == STATUS_SUCCESS) 4175 break; 4176 } 4177 if (i == MS_MAX_RETRY_COUNT) { 4178 rtsx_trace(chip); 4179 return STATUS_FAIL; 4180 } 4181 4182 if (check_ms_err(chip)) { 4183 rtsx_clear_ms_error(chip); 4184 rtsx_trace(chip); 4185 return STATUS_FAIL; 4186 } 4187 4188 return STATUS_SUCCESS; 4189 } 4190 4191 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 4192 u8 mg_entry_num) 4193 { 4194 int retval; 4195 u8 buf[6]; 4196 4197 if (type == 0) 4198 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1); 4199 else 4200 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 4201 4202 if (retval != STATUS_SUCCESS) { 4203 rtsx_trace(chip); 4204 return STATUS_FAIL; 4205 } 4206 4207 buf[0] = 0; 4208 buf[1] = 0; 4209 if (type == 1) { 4210 buf[2] = 0; 4211 buf[3] = 0; 4212 buf[4] = 0; 4213 buf[5] = mg_entry_num; 4214 } 4215 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 4216 NO_WAIT_INT, buf, 6); 4217 if (retval != STATUS_SUCCESS) { 4218 rtsx_trace(chip); 4219 return STATUS_FAIL; 4220 } 4221 4222 return STATUS_SUCCESS; 4223 } 4224 4225 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4226 { 4227 int retval; 4228 int i; 4229 unsigned int lun = SCSI_LUN(srb); 4230 u8 buf1[32], buf2[12]; 4231 4232 if (scsi_bufflen(srb) < 12) { 4233 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4234 rtsx_trace(chip); 4235 return STATUS_FAIL; 4236 } 4237 4238 ms_cleanup_work(chip); 4239 4240 retval = ms_switch_clock(chip); 4241 if (retval != STATUS_SUCCESS) { 4242 rtsx_trace(chip); 4243 return STATUS_FAIL; 4244 } 4245 4246 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 4247 if (retval != STATUS_SUCCESS) { 4248 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4249 rtsx_trace(chip); 4250 return STATUS_FAIL; 4251 } 4252 4253 memset(buf1, 0, 32); 4254 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 4255 for (i = 0; i < 8; i++) 4256 buf1[8 + i] = buf2[4 + i]; 4257 4258 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4259 buf1, 32); 4260 if (retval != STATUS_SUCCESS) { 4261 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4262 rtsx_trace(chip); 4263 return STATUS_FAIL; 4264 } 4265 if (check_ms_err(chip)) { 4266 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4267 rtsx_clear_ms_error(chip); 4268 rtsx_trace(chip); 4269 return STATUS_FAIL; 4270 } 4271 4272 return STATUS_SUCCESS; 4273 } 4274 4275 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4276 { 4277 int retval = STATUS_FAIL; 4278 int bufflen; 4279 unsigned int lun = SCSI_LUN(srb); 4280 u8 *buf = NULL; 4281 4282 ms_cleanup_work(chip); 4283 4284 retval = ms_switch_clock(chip); 4285 if (retval != STATUS_SUCCESS) { 4286 rtsx_trace(chip); 4287 return STATUS_FAIL; 4288 } 4289 4290 buf = kmalloc(1540, GFP_KERNEL); 4291 if (!buf) { 4292 rtsx_trace(chip); 4293 return STATUS_ERROR; 4294 } 4295 4296 buf[0] = 0x04; 4297 buf[1] = 0x1A; 4298 buf[2] = 0x00; 4299 buf[3] = 0x00; 4300 4301 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 4302 if (retval != STATUS_SUCCESS) { 4303 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4304 rtsx_trace(chip); 4305 goto free_buffer; 4306 } 4307 4308 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4309 3, WAIT_INT, 0, 0, buf + 4, 1536); 4310 if (retval != STATUS_SUCCESS) { 4311 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4312 rtsx_clear_ms_error(chip); 4313 rtsx_trace(chip); 4314 goto free_buffer; 4315 } 4316 if (check_ms_err(chip)) { 4317 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4318 rtsx_clear_ms_error(chip); 4319 rtsx_trace(chip); 4320 retval = STATUS_FAIL; 4321 goto free_buffer; 4322 } 4323 4324 bufflen = min_t(int, 1052, scsi_bufflen(srb)); 4325 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4326 4327 free_buffer: 4328 kfree(buf); 4329 return retval; 4330 } 4331 4332 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4333 { 4334 struct ms_info *ms_card = &chip->ms_card; 4335 int retval; 4336 int bufflen; 4337 int i; 4338 unsigned int lun = SCSI_LUN(srb); 4339 u8 buf[32]; 4340 4341 ms_cleanup_work(chip); 4342 4343 retval = ms_switch_clock(chip); 4344 if (retval != STATUS_SUCCESS) { 4345 rtsx_trace(chip); 4346 return STATUS_FAIL; 4347 } 4348 4349 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 4350 if (retval != STATUS_SUCCESS) { 4351 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4352 rtsx_trace(chip); 4353 return STATUS_FAIL; 4354 } 4355 4356 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4357 buf, 32); 4358 if (retval != STATUS_SUCCESS) { 4359 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4360 rtsx_trace(chip); 4361 return STATUS_FAIL; 4362 } 4363 if (check_ms_err(chip)) { 4364 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4365 rtsx_clear_ms_error(chip); 4366 rtsx_trace(chip); 4367 return STATUS_FAIL; 4368 } 4369 4370 memcpy(ms_card->magic_gate_id, buf, 16); 4371 4372 #ifdef READ_BYTES_WAIT_INT 4373 retval = ms_poll_int(chip); 4374 if (retval != STATUS_SUCCESS) { 4375 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4376 rtsx_trace(chip); 4377 return STATUS_FAIL; 4378 } 4379 #endif 4380 4381 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 4382 if (retval != STATUS_SUCCESS) { 4383 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4384 rtsx_trace(chip); 4385 return STATUS_FAIL; 4386 } 4387 4388 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4389 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4390 4391 for (i = 0; i < 8; i++) 4392 buf[i] = buf[4 + i]; 4393 4394 for (i = 0; i < 24; i++) 4395 buf[8 + i] = 0; 4396 4397 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 4398 32, WAIT_INT, buf, 32); 4399 if (retval != STATUS_SUCCESS) { 4400 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4401 rtsx_trace(chip); 4402 return STATUS_FAIL; 4403 } 4404 if (check_ms_err(chip)) { 4405 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4406 rtsx_clear_ms_error(chip); 4407 rtsx_trace(chip); 4408 return STATUS_FAIL; 4409 } 4410 4411 ms_card->mg_auth = 0; 4412 4413 return STATUS_SUCCESS; 4414 } 4415 4416 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4417 { 4418 struct ms_info *ms_card = &chip->ms_card; 4419 int retval; 4420 int bufflen; 4421 unsigned int lun = SCSI_LUN(srb); 4422 u8 buf1[32], buf2[36]; 4423 4424 ms_cleanup_work(chip); 4425 4426 retval = ms_switch_clock(chip); 4427 if (retval != STATUS_SUCCESS) { 4428 rtsx_trace(chip); 4429 return STATUS_FAIL; 4430 } 4431 4432 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 4433 if (retval != STATUS_SUCCESS) { 4434 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4435 rtsx_trace(chip); 4436 return STATUS_FAIL; 4437 } 4438 4439 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4440 buf1, 32); 4441 if (retval != STATUS_SUCCESS) { 4442 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4443 rtsx_trace(chip); 4444 return STATUS_FAIL; 4445 } 4446 if (check_ms_err(chip)) { 4447 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4448 rtsx_clear_ms_error(chip); 4449 rtsx_trace(chip); 4450 return STATUS_FAIL; 4451 } 4452 4453 buf2[0] = 0x00; 4454 buf2[1] = 0x22; 4455 buf2[2] = 0x00; 4456 buf2[3] = 0x00; 4457 4458 memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4459 memcpy(buf2 + 20, buf1, 16); 4460 4461 bufflen = min_t(int, 36, scsi_bufflen(srb)); 4462 rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4463 4464 #ifdef READ_BYTES_WAIT_INT 4465 retval = ms_poll_int(chip); 4466 if (retval != STATUS_SUCCESS) { 4467 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4468 rtsx_trace(chip); 4469 return STATUS_FAIL; 4470 } 4471 #endif 4472 4473 return STATUS_SUCCESS; 4474 } 4475 4476 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4477 { 4478 struct ms_info *ms_card = &chip->ms_card; 4479 int retval; 4480 int i; 4481 int bufflen; 4482 unsigned int lun = SCSI_LUN(srb); 4483 u8 buf[32]; 4484 4485 ms_cleanup_work(chip); 4486 4487 retval = ms_switch_clock(chip); 4488 if (retval != STATUS_SUCCESS) { 4489 rtsx_trace(chip); 4490 return STATUS_FAIL; 4491 } 4492 4493 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4494 if (retval != STATUS_SUCCESS) { 4495 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4496 rtsx_trace(chip); 4497 return STATUS_FAIL; 4498 } 4499 4500 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4501 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4502 4503 for (i = 0; i < 8; i++) 4504 buf[i] = buf[4 + i]; 4505 4506 for (i = 0; i < 24; i++) 4507 buf[8 + i] = 0; 4508 4509 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4510 buf, 32); 4511 if (retval != STATUS_SUCCESS) { 4512 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4513 rtsx_trace(chip); 4514 return STATUS_FAIL; 4515 } 4516 if (check_ms_err(chip)) { 4517 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4518 rtsx_clear_ms_error(chip); 4519 rtsx_trace(chip); 4520 return STATUS_FAIL; 4521 } 4522 4523 ms_card->mg_auth = 1; 4524 4525 return STATUS_SUCCESS; 4526 } 4527 4528 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4529 { 4530 struct ms_info *ms_card = &chip->ms_card; 4531 int retval; 4532 int bufflen; 4533 unsigned int lun = SCSI_LUN(srb); 4534 u8 *buf = NULL; 4535 4536 ms_cleanup_work(chip); 4537 4538 retval = ms_switch_clock(chip); 4539 if (retval != STATUS_SUCCESS) { 4540 rtsx_trace(chip); 4541 return STATUS_FAIL; 4542 } 4543 4544 buf = kmalloc(1028, GFP_KERNEL); 4545 if (!buf) { 4546 rtsx_trace(chip); 4547 return STATUS_ERROR; 4548 } 4549 4550 buf[0] = 0x04; 4551 buf[1] = 0x02; 4552 buf[2] = 0x00; 4553 buf[3] = 0x00; 4554 4555 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4556 if (retval != STATUS_SUCCESS) { 4557 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4558 rtsx_trace(chip); 4559 goto free_buffer; 4560 } 4561 4562 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4563 2, WAIT_INT, 0, 0, buf + 4, 1024); 4564 if (retval != STATUS_SUCCESS) { 4565 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4566 rtsx_clear_ms_error(chip); 4567 rtsx_trace(chip); 4568 goto free_buffer; 4569 } 4570 if (check_ms_err(chip)) { 4571 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4572 rtsx_clear_ms_error(chip); 4573 rtsx_trace(chip); 4574 retval = STATUS_FAIL; 4575 goto free_buffer; 4576 } 4577 4578 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4579 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4580 4581 free_buffer: 4582 kfree(buf); 4583 return retval; 4584 } 4585 4586 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4587 { 4588 struct ms_info *ms_card = &chip->ms_card; 4589 int retval; 4590 int bufflen; 4591 #ifdef MG_SET_ICV_SLOW 4592 int i; 4593 #endif 4594 unsigned int lun = SCSI_LUN(srb); 4595 u8 *buf = NULL; 4596 4597 ms_cleanup_work(chip); 4598 4599 retval = ms_switch_clock(chip); 4600 if (retval != STATUS_SUCCESS) { 4601 rtsx_trace(chip); 4602 return STATUS_FAIL; 4603 } 4604 4605 buf = kmalloc(1028, GFP_KERNEL); 4606 if (!buf) { 4607 rtsx_trace(chip); 4608 return STATUS_ERROR; 4609 } 4610 4611 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4612 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4613 4614 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4615 if (retval != STATUS_SUCCESS) { 4616 if (ms_card->mg_auth == 0) { 4617 if ((buf[5] & 0xC0) != 0) 4618 set_sense_type(chip, lun, 4619 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4620 else 4621 set_sense_type(chip, lun, 4622 SENSE_TYPE_MG_WRITE_ERR); 4623 } else { 4624 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4625 } 4626 rtsx_trace(chip); 4627 goto SetICVFinish; 4628 } 4629 4630 #ifdef MG_SET_ICV_SLOW 4631 for (i = 0; i < 2; i++) { 4632 udelay(50); 4633 4634 rtsx_init_cmd(chip); 4635 4636 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4637 0xFF, PRO_WRITE_LONG_DATA); 4638 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4639 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4640 0x01, RING_BUFFER); 4641 4642 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4643 4644 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4645 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4646 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4647 MS_TRANSFER_END, MS_TRANSFER_END); 4648 4649 rtsx_send_cmd_no_wait(chip); 4650 4651 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512, 4652 512, 0, DMA_TO_DEVICE, 3000); 4653 if ((retval < 0) || check_ms_err(chip)) { 4654 rtsx_clear_ms_error(chip); 4655 if (ms_card->mg_auth == 0) { 4656 if ((buf[5] & 0xC0) != 0) 4657 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4658 else 4659 set_sense_type(chip, lun, 4660 SENSE_TYPE_MG_WRITE_ERR); 4661 } else { 4662 set_sense_type(chip, lun, 4663 SENSE_TYPE_MG_WRITE_ERR); 4664 } 4665 retval = STATUS_FAIL; 4666 rtsx_trace(chip); 4667 goto SetICVFinish; 4668 } 4669 } 4670 #else 4671 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4672 2, WAIT_INT, 0, 0, buf + 4, 1024); 4673 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) { 4674 rtsx_clear_ms_error(chip); 4675 if (ms_card->mg_auth == 0) { 4676 if ((buf[5] & 0xC0) != 0) 4677 set_sense_type(chip, lun, 4678 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4679 else 4680 set_sense_type(chip, lun, 4681 SENSE_TYPE_MG_WRITE_ERR); 4682 } else { 4683 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4684 } 4685 rtsx_trace(chip); 4686 goto SetICVFinish; 4687 } 4688 #endif 4689 4690 SetICVFinish: 4691 kfree(buf); 4692 return retval; 4693 } 4694 4695 #endif /* SUPPORT_MAGIC_GATE */ 4696 4697 void ms_cleanup_work(struct rtsx_chip *chip) 4698 { 4699 struct ms_info *ms_card = &chip->ms_card; 4700 4701 if (CHK_MSPRO(ms_card)) { 4702 if (ms_card->seq_mode) { 4703 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4704 mspro_stop_seq_mode(chip); 4705 ms_card->cleanup_counter = 0; 4706 } 4707 if (CHK_MSHG(ms_card)) { 4708 rtsx_write_register(chip, MS_CFG, 4709 MS_2K_SECTOR_MODE, 0x00); 4710 } 4711 } 4712 #ifdef MS_DELAY_WRITE 4713 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) { 4714 dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4715 ms_delay_write(chip); 4716 ms_card->cleanup_counter = 0; 4717 } 4718 #endif 4719 } 4720 4721 int ms_power_off_card3v3(struct rtsx_chip *chip) 4722 { 4723 int retval; 4724 4725 retval = disable_card_clock(chip, MS_CARD); 4726 if (retval != STATUS_SUCCESS) { 4727 rtsx_trace(chip); 4728 return STATUS_FAIL; 4729 } 4730 4731 if (chip->asic_code) { 4732 retval = ms_pull_ctl_disable(chip); 4733 if (retval != STATUS_SUCCESS) { 4734 rtsx_trace(chip); 4735 return STATUS_FAIL; 4736 } 4737 } else { 4738 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4739 FPGA_MS_PULL_CTL_BIT | 0x20, 4740 FPGA_MS_PULL_CTL_BIT); 4741 if (retval) { 4742 rtsx_trace(chip); 4743 return retval; 4744 } 4745 } 4746 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4747 if (retval) { 4748 rtsx_trace(chip); 4749 return retval; 4750 } 4751 if (!chip->ft2_fast_mode) { 4752 retval = card_power_off(chip, MS_CARD); 4753 if (retval != STATUS_SUCCESS) { 4754 rtsx_trace(chip); 4755 return STATUS_FAIL; 4756 } 4757 } 4758 4759 return STATUS_SUCCESS; 4760 } 4761 4762 int release_ms_card(struct rtsx_chip *chip) 4763 { 4764 struct ms_info *ms_card = &chip->ms_card; 4765 int retval; 4766 4767 #ifdef MS_DELAY_WRITE 4768 ms_card->delay_write.delay_write_flag = 0; 4769 #endif 4770 ms_card->pro_under_formatting = 0; 4771 4772 chip->card_ready &= ~MS_CARD; 4773 chip->card_fail &= ~MS_CARD; 4774 chip->card_wp &= ~MS_CARD; 4775 4776 ms_free_l2p_tbl(chip); 4777 4778 memset(ms_card->raw_sys_info, 0, 96); 4779 #ifdef SUPPORT_PCGL_1P18 4780 memset(ms_card->raw_model_name, 0, 48); 4781 #endif 4782 4783 retval = ms_power_off_card3v3(chip); 4784 if (retval != STATUS_SUCCESS) { 4785 rtsx_trace(chip); 4786 return STATUS_FAIL; 4787 } 4788 4789 return STATUS_SUCCESS; 4790 } 4791