1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "ms.h" 30 31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 32 { 33 struct ms_info *ms_card = &chip->ms_card; 34 35 ms_card->err_code = err_code; 36 } 37 38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct ms_info *ms_card = &chip->ms_card; 41 42 return (ms_card->err_code == err_code); 43 } 44 45 static int ms_parse_err_code(struct rtsx_chip *chip) 46 { 47 rtsx_trace(chip); 48 return STATUS_FAIL; 49 } 50 51 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 52 u8 tpc, u8 cnt, u8 cfg) 53 { 54 struct ms_info *ms_card = &chip->ms_card; 55 int retval; 56 u8 *ptr; 57 58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 59 60 rtsx_init_cmd(chip); 61 62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 66 0x01, PINGPONG_BUFFER); 67 68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 69 0xFF, MS_TRANSFER_START | trans_mode); 70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 71 MS_TRANSFER_END, MS_TRANSFER_END); 72 73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 74 75 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 76 if (retval < 0) { 77 rtsx_clear_ms_error(chip); 78 ms_set_err_code(chip, MS_TO_ERROR); 79 rtsx_trace(chip); 80 return ms_parse_err_code(chip); 81 } 82 83 ptr = rtsx_get_cmd_data(chip) + 1; 84 85 if (!(tpc & 0x08)) { /* Read Packet */ 86 if (*ptr & MS_CRC16_ERR) { 87 ms_set_err_code(chip, MS_CRC16_ERROR); 88 rtsx_trace(chip); 89 return ms_parse_err_code(chip); 90 } 91 } else { /* Write Packet */ 92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 94 ms_set_err_code(chip, MS_CMD_NK); 95 rtsx_trace(chip); 96 return ms_parse_err_code(chip); 97 } 98 } 99 } 100 101 if (*ptr & MS_RDY_TIMEOUT) { 102 rtsx_clear_ms_error(chip); 103 ms_set_err_code(chip, MS_TO_ERROR); 104 rtsx_trace(chip); 105 return ms_parse_err_code(chip); 106 } 107 108 return STATUS_SUCCESS; 109 } 110 111 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 113 int use_sg, void *buf, int buf_len) 114 { 115 int retval; 116 u8 val, err_code = 0; 117 enum dma_data_direction dir; 118 119 if (!buf || !buf_len) { 120 rtsx_trace(chip); 121 return STATUS_FAIL; 122 } 123 124 if (trans_mode == MS_TM_AUTO_READ) { 125 dir = DMA_FROM_DEVICE; 126 err_code = MS_FLASH_READ_ERROR; 127 } else if (trans_mode == MS_TM_AUTO_WRITE) { 128 dir = DMA_TO_DEVICE; 129 err_code = MS_FLASH_WRITE_ERROR; 130 } else { 131 rtsx_trace(chip); 132 return STATUS_FAIL; 133 } 134 135 rtsx_init_cmd(chip); 136 137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 138 rtsx_add_cmd(chip, WRITE_REG_CMD, 139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 142 143 if (mode_2k) { 144 rtsx_add_cmd(chip, WRITE_REG_CMD, 145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 146 } else { 147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 148 } 149 150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 151 152 rtsx_add_cmd(chip, WRITE_REG_CMD, 153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 154 rtsx_add_cmd(chip, CHECK_REG_CMD, 155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 156 157 rtsx_send_cmd_no_wait(chip); 158 159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 160 use_sg, dir, chip->mspro_timeout); 161 if (retval < 0) { 162 ms_set_err_code(chip, err_code); 163 if (retval == -ETIMEDOUT) 164 retval = STATUS_TIMEDOUT; 165 else 166 retval = STATUS_FAIL; 167 168 rtsx_trace(chip); 169 return retval; 170 } 171 172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 173 if (retval) { 174 rtsx_trace(chip); 175 return retval; 176 } 177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 178 rtsx_trace(chip); 179 return STATUS_FAIL; 180 } 181 182 return STATUS_SUCCESS; 183 } 184 185 static int ms_write_bytes(struct rtsx_chip *chip, 186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 187 { 188 struct ms_info *ms_card = &chip->ms_card; 189 int retval, i; 190 191 if (!data || (data_len < cnt)) { 192 rtsx_trace(chip); 193 return STATUS_ERROR; 194 } 195 196 rtsx_init_cmd(chip); 197 198 for (i = 0; i < cnt; i++) { 199 rtsx_add_cmd(chip, WRITE_REG_CMD, 200 PPBUF_BASE2 + i, 0xFF, data[i]); 201 } 202 if (cnt % 2) 203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 204 205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 209 0x01, PINGPONG_BUFFER); 210 211 rtsx_add_cmd(chip, WRITE_REG_CMD, 212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 213 rtsx_add_cmd(chip, CHECK_REG_CMD, 214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 215 216 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 217 if (retval < 0) { 218 u8 val = 0; 219 220 rtsx_read_register(chip, MS_TRANS_CFG, &val); 221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 222 223 rtsx_clear_ms_error(chip); 224 225 if (!(tpc & 0x08)) { 226 if (val & MS_CRC16_ERR) { 227 ms_set_err_code(chip, MS_CRC16_ERROR); 228 rtsx_trace(chip); 229 return ms_parse_err_code(chip); 230 } 231 } else { 232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 234 ms_set_err_code(chip, MS_CMD_NK); 235 rtsx_trace(chip); 236 return ms_parse_err_code(chip); 237 } 238 } 239 } 240 241 if (val & MS_RDY_TIMEOUT) { 242 ms_set_err_code(chip, MS_TO_ERROR); 243 rtsx_trace(chip); 244 return ms_parse_err_code(chip); 245 } 246 247 ms_set_err_code(chip, MS_TO_ERROR); 248 rtsx_trace(chip); 249 return ms_parse_err_code(chip); 250 } 251 252 return STATUS_SUCCESS; 253 } 254 255 static int ms_read_bytes(struct rtsx_chip *chip, 256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 257 { 258 struct ms_info *ms_card = &chip->ms_card; 259 int retval, i; 260 u8 *ptr; 261 262 if (!data) { 263 rtsx_trace(chip); 264 return STATUS_ERROR; 265 } 266 267 rtsx_init_cmd(chip); 268 269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 273 0x01, PINGPONG_BUFFER); 274 275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 276 MS_TRANSFER_START | MS_TM_READ_BYTES); 277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 278 MS_TRANSFER_END, MS_TRANSFER_END); 279 280 for (i = 0; i < data_len - 1; i++) 281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 282 283 if (data_len % 2) 284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 285 else 286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 287 0, 0); 288 289 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 290 if (retval < 0) { 291 u8 val = 0; 292 293 rtsx_read_register(chip, MS_TRANS_CFG, &val); 294 rtsx_clear_ms_error(chip); 295 296 if (!(tpc & 0x08)) { 297 if (val & MS_CRC16_ERR) { 298 ms_set_err_code(chip, MS_CRC16_ERROR); 299 rtsx_trace(chip); 300 return ms_parse_err_code(chip); 301 } 302 } else { 303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 305 ms_set_err_code(chip, MS_CMD_NK); 306 rtsx_trace(chip); 307 return ms_parse_err_code(chip); 308 } 309 } 310 } 311 312 if (val & MS_RDY_TIMEOUT) { 313 ms_set_err_code(chip, MS_TO_ERROR); 314 rtsx_trace(chip); 315 return ms_parse_err_code(chip); 316 } 317 318 ms_set_err_code(chip, MS_TO_ERROR); 319 rtsx_trace(chip); 320 return ms_parse_err_code(chip); 321 } 322 323 ptr = rtsx_get_cmd_data(chip) + 1; 324 325 for (i = 0; i < data_len; i++) 326 data[i] = ptr[i]; 327 328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) { 329 dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 331 cnt); 332 } 333 334 return STATUS_SUCCESS; 335 } 336 337 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start, 338 u8 read_cnt, u8 write_start, u8 write_cnt) 339 { 340 int retval, i; 341 u8 data[4]; 342 343 data[0] = read_start; 344 data[1] = read_cnt; 345 data[2] = write_start; 346 data[3] = write_cnt; 347 348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 350 NO_WAIT_INT, data, 4); 351 if (retval == STATUS_SUCCESS) 352 return STATUS_SUCCESS; 353 rtsx_clear_ms_error(chip); 354 } 355 356 rtsx_trace(chip); 357 return STATUS_FAIL; 358 } 359 360 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 361 { 362 u8 data[2]; 363 364 data[0] = cmd; 365 data[1] = 0; 366 367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 368 } 369 370 static int ms_set_init_para(struct rtsx_chip *chip) 371 { 372 struct ms_info *ms_card = &chip->ms_card; 373 int retval; 374 375 if (CHK_HG8BIT(ms_card)) { 376 if (chip->asic_code) 377 ms_card->ms_clock = chip->asic_ms_hg_clk; 378 else 379 ms_card->ms_clock = chip->fpga_ms_hg_clk; 380 381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 382 if (chip->asic_code) 383 ms_card->ms_clock = chip->asic_ms_4bit_clk; 384 else 385 ms_card->ms_clock = chip->fpga_ms_4bit_clk; 386 387 } else { 388 if (chip->asic_code) 389 ms_card->ms_clock = chip->asic_ms_1bit_clk; 390 else 391 ms_card->ms_clock = chip->fpga_ms_1bit_clk; 392 } 393 394 retval = switch_clock(chip, ms_card->ms_clock); 395 if (retval != STATUS_SUCCESS) { 396 rtsx_trace(chip); 397 return STATUS_FAIL; 398 } 399 400 retval = select_card(chip, MS_CARD); 401 if (retval != STATUS_SUCCESS) { 402 rtsx_trace(chip); 403 return STATUS_FAIL; 404 } 405 406 return STATUS_SUCCESS; 407 } 408 409 static int ms_switch_clock(struct rtsx_chip *chip) 410 { 411 struct ms_info *ms_card = &chip->ms_card; 412 int retval; 413 414 retval = select_card(chip, MS_CARD); 415 if (retval != STATUS_SUCCESS) { 416 rtsx_trace(chip); 417 return STATUS_FAIL; 418 } 419 420 retval = switch_clock(chip, ms_card->ms_clock); 421 if (retval != STATUS_SUCCESS) { 422 rtsx_trace(chip); 423 return STATUS_FAIL; 424 } 425 426 return STATUS_SUCCESS; 427 } 428 429 static int ms_pull_ctl_disable(struct rtsx_chip *chip) 430 { 431 int retval; 432 433 if (CHECK_PID(chip, 0x5208)) { 434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 435 MS_D1_PD | MS_D2_PD | MS_CLK_PD | 436 MS_D6_PD); 437 if (retval) { 438 rtsx_trace(chip); 439 return retval; 440 } 441 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 442 MS_D3_PD | MS_D0_PD | MS_BS_PD | 443 XD_D4_PD); 444 if (retval) { 445 rtsx_trace(chip); 446 return retval; 447 } 448 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 449 MS_D7_PD | XD_CE_PD | XD_CLE_PD | 450 XD_CD_PU); 451 if (retval) { 452 rtsx_trace(chip); 453 return retval; 454 } 455 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 456 XD_RDY_PD | SD_D3_PD | SD_D2_PD | 457 XD_ALE_PD); 458 if (retval) { 459 rtsx_trace(chip); 460 return retval; 461 } 462 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 463 MS_INS_PU | SD_WP_PD | SD_CD_PU | 464 SD_CMD_PD); 465 if (retval) { 466 rtsx_trace(chip); 467 return retval; 468 } 469 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 470 MS_D5_PD | MS_D4_PD); 471 if (retval) { 472 rtsx_trace(chip); 473 return retval; 474 } 475 } else if (CHECK_PID(chip, 0x5288)) { 476 if (CHECK_BARO_PKG(chip, QFN)) { 477 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 478 0xFF, 0x55); 479 if (retval) { 480 rtsx_trace(chip); 481 return retval; 482 } 483 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 484 0xFF, 0x55); 485 if (retval) { 486 rtsx_trace(chip); 487 return retval; 488 } 489 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 490 0xFF, 0x4B); 491 if (retval) { 492 rtsx_trace(chip); 493 return retval; 494 } 495 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 496 0xFF, 0x69); 497 if (retval) { 498 rtsx_trace(chip); 499 return retval; 500 } 501 } 502 } 503 504 return STATUS_SUCCESS; 505 } 506 507 static int ms_pull_ctl_enable(struct rtsx_chip *chip) 508 { 509 int retval; 510 511 rtsx_init_cmd(chip); 512 513 if (CHECK_PID(chip, 0x5208)) { 514 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 515 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 516 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 517 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 518 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 519 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 520 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 521 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 522 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 523 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 524 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 525 MS_D5_PD | MS_D4_PD); 526 } else if (CHECK_PID(chip, 0x5288)) { 527 if (CHECK_BARO_PKG(chip, QFN)) { 528 rtsx_add_cmd(chip, WRITE_REG_CMD, 529 CARD_PULL_CTL1, 0xFF, 0x55); 530 rtsx_add_cmd(chip, WRITE_REG_CMD, 531 CARD_PULL_CTL2, 0xFF, 0x45); 532 rtsx_add_cmd(chip, WRITE_REG_CMD, 533 CARD_PULL_CTL3, 0xFF, 0x4B); 534 rtsx_add_cmd(chip, WRITE_REG_CMD, 535 CARD_PULL_CTL4, 0xFF, 0x29); 536 } 537 } 538 539 retval = rtsx_send_cmd(chip, MS_CARD, 100); 540 if (retval < 0) { 541 rtsx_trace(chip); 542 return STATUS_FAIL; 543 } 544 545 return STATUS_SUCCESS; 546 } 547 548 static int ms_prepare_reset(struct rtsx_chip *chip) 549 { 550 struct ms_info *ms_card = &chip->ms_card; 551 int retval; 552 u8 oc_mask = 0; 553 554 ms_card->ms_type = 0; 555 ms_card->check_ms_flow = 0; 556 ms_card->switch_8bit_fail = 0; 557 ms_card->delay_write.delay_write_flag = 0; 558 559 ms_card->pro_under_formatting = 0; 560 561 retval = ms_power_off_card3v3(chip); 562 if (retval != STATUS_SUCCESS) { 563 rtsx_trace(chip); 564 return STATUS_FAIL; 565 } 566 567 if (!chip->ft2_fast_mode) 568 wait_timeout(250); 569 570 retval = enable_card_clock(chip, MS_CARD); 571 if (retval != STATUS_SUCCESS) { 572 rtsx_trace(chip); 573 return STATUS_FAIL; 574 } 575 576 if (chip->asic_code) { 577 retval = ms_pull_ctl_enable(chip); 578 if (retval != STATUS_SUCCESS) { 579 rtsx_trace(chip); 580 return STATUS_FAIL; 581 } 582 } else { 583 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 584 FPGA_MS_PULL_CTL_BIT | 0x20, 0); 585 if (retval) { 586 rtsx_trace(chip); 587 return retval; 588 } 589 } 590 591 if (!chip->ft2_fast_mode) { 592 retval = card_power_on(chip, MS_CARD); 593 if (retval != STATUS_SUCCESS) { 594 rtsx_trace(chip); 595 return STATUS_FAIL; 596 } 597 598 wait_timeout(150); 599 600 #ifdef SUPPORT_OCP 601 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 602 oc_mask = MS_OC_NOW | MS_OC_EVER; 603 else 604 oc_mask = SD_OC_NOW | SD_OC_EVER; 605 606 if (chip->ocp_stat & oc_mask) { 607 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 608 chip->ocp_stat); 609 rtsx_trace(chip); 610 return STATUS_FAIL; 611 } 612 #endif 613 } 614 615 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 616 MS_OUTPUT_EN); 617 if (retval) { 618 rtsx_trace(chip); 619 return retval; 620 } 621 622 if (chip->asic_code) { 623 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 624 SAMPLE_TIME_RISING | 625 PUSH_TIME_DEFAULT | 626 NO_EXTEND_TOGGLE | 627 MS_BUS_WIDTH_1); 628 if (retval) { 629 rtsx_trace(chip); 630 return retval; 631 } 632 } else { 633 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 634 SAMPLE_TIME_FALLING | 635 PUSH_TIME_DEFAULT | 636 NO_EXTEND_TOGGLE | 637 MS_BUS_WIDTH_1); 638 if (retval) { 639 rtsx_trace(chip); 640 return retval; 641 } 642 } 643 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 644 NO_WAIT_INT | NO_AUTO_READ_INT_REG); 645 if (retval) { 646 rtsx_trace(chip); 647 return retval; 648 } 649 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 650 MS_STOP | MS_CLR_ERR); 651 if (retval) { 652 rtsx_trace(chip); 653 return retval; 654 } 655 656 retval = ms_set_init_para(chip); 657 if (retval != STATUS_SUCCESS) { 658 rtsx_trace(chip); 659 return STATUS_FAIL; 660 } 661 662 return STATUS_SUCCESS; 663 } 664 665 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 666 { 667 struct ms_info *ms_card = &chip->ms_card; 668 int retval, i; 669 u8 val; 670 671 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1); 672 if (retval != STATUS_SUCCESS) { 673 rtsx_trace(chip); 674 return STATUS_FAIL; 675 } 676 677 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 678 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 679 6, NO_WAIT_INT); 680 if (retval == STATUS_SUCCESS) 681 break; 682 } 683 if (i == MS_MAX_RETRY_COUNT) { 684 rtsx_trace(chip); 685 return STATUS_FAIL; 686 } 687 688 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 689 if (retval) { 690 rtsx_trace(chip); 691 return retval; 692 } 693 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 694 if (val != 0x01) { 695 if (val != 0x02) 696 ms_card->check_ms_flow = 1; 697 698 rtsx_trace(chip); 699 return STATUS_FAIL; 700 } 701 702 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 703 if (retval) { 704 rtsx_trace(chip); 705 return retval; 706 } 707 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 708 if (val != 0) { 709 ms_card->check_ms_flow = 1; 710 rtsx_trace(chip); 711 return STATUS_FAIL; 712 } 713 714 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 715 if (retval) { 716 rtsx_trace(chip); 717 return retval; 718 } 719 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 720 if (val == 0) { 721 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 722 if (retval) { 723 rtsx_trace(chip); 724 return retval; 725 } 726 if (val & WRT_PRTCT) 727 chip->card_wp |= MS_CARD; 728 else 729 chip->card_wp &= ~MS_CARD; 730 731 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 732 chip->card_wp |= MS_CARD; 733 } else { 734 ms_card->check_ms_flow = 1; 735 rtsx_trace(chip); 736 return STATUS_FAIL; 737 } 738 739 ms_card->ms_type |= TYPE_MSPRO; 740 741 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 742 if (retval) { 743 rtsx_trace(chip); 744 return retval; 745 } 746 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 747 if (val == 0) { 748 ms_card->ms_type &= 0x0F; 749 } else if (val == 7) { 750 if (switch_8bit_bus) 751 ms_card->ms_type |= MS_HG; 752 else 753 ms_card->ms_type &= 0x0F; 754 755 } else { 756 rtsx_trace(chip); 757 return STATUS_FAIL; 758 } 759 760 return STATUS_SUCCESS; 761 } 762 763 static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 764 { 765 int retval, i, k; 766 u8 val; 767 768 /* Confirm CPU StartUp */ 769 k = 0; 770 do { 771 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 772 ms_set_err_code(chip, MS_NO_CARD); 773 rtsx_trace(chip); 774 return STATUS_FAIL; 775 } 776 777 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 778 retval = ms_read_bytes(chip, GET_INT, 1, 779 NO_WAIT_INT, &val, 1); 780 if (retval == STATUS_SUCCESS) 781 break; 782 } 783 if (i == MS_MAX_RETRY_COUNT) { 784 rtsx_trace(chip); 785 return STATUS_FAIL; 786 } 787 788 if (k > 100) { 789 rtsx_trace(chip); 790 return STATUS_FAIL; 791 } 792 793 k++; 794 wait_timeout(100); 795 } while (!(val & INT_REG_CED)); 796 797 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 798 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 799 if (retval == STATUS_SUCCESS) 800 break; 801 } 802 if (i == MS_MAX_RETRY_COUNT) { 803 rtsx_trace(chip); 804 return STATUS_FAIL; 805 } 806 807 if (val & INT_REG_ERR) { 808 if (val & INT_REG_CMDNK) { 809 chip->card_wp |= (MS_CARD); 810 } else { 811 rtsx_trace(chip); 812 return STATUS_FAIL; 813 } 814 } 815 /* -- end confirm CPU startup */ 816 817 return STATUS_SUCCESS; 818 } 819 820 static int ms_switch_parallel_bus(struct rtsx_chip *chip) 821 { 822 int retval, i; 823 u8 data[2]; 824 825 data[0] = PARALLEL_4BIT_IF; 826 data[1] = 0; 827 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 828 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 829 data, 2); 830 if (retval == STATUS_SUCCESS) 831 break; 832 } 833 if (retval != STATUS_SUCCESS) { 834 rtsx_trace(chip); 835 return STATUS_FAIL; 836 } 837 838 return STATUS_SUCCESS; 839 } 840 841 static int ms_switch_8bit_bus(struct rtsx_chip *chip) 842 { 843 struct ms_info *ms_card = &chip->ms_card; 844 int retval, i; 845 u8 data[2]; 846 847 data[0] = PARALLEL_8BIT_IF; 848 data[1] = 0; 849 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 850 retval = ms_write_bytes(chip, WRITE_REG, 1, 851 NO_WAIT_INT, data, 2); 852 if (retval == STATUS_SUCCESS) 853 break; 854 } 855 if (retval != STATUS_SUCCESS) { 856 rtsx_trace(chip); 857 return STATUS_FAIL; 858 } 859 860 retval = rtsx_write_register(chip, MS_CFG, 0x98, 861 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 862 if (retval) { 863 rtsx_trace(chip); 864 return retval; 865 } 866 ms_card->ms_type |= MS_8BIT; 867 retval = ms_set_init_para(chip); 868 if (retval != STATUS_SUCCESS) { 869 rtsx_trace(chip); 870 return STATUS_FAIL; 871 } 872 873 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 874 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 875 1, NO_WAIT_INT); 876 if (retval != STATUS_SUCCESS) { 877 rtsx_trace(chip); 878 return STATUS_FAIL; 879 } 880 } 881 882 return STATUS_SUCCESS; 883 } 884 885 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 886 { 887 struct ms_info *ms_card = &chip->ms_card; 888 int retval, i; 889 890 for (i = 0; i < 3; i++) { 891 retval = ms_prepare_reset(chip); 892 if (retval != STATUS_SUCCESS) { 893 rtsx_trace(chip); 894 return STATUS_FAIL; 895 } 896 897 retval = ms_identify_media_type(chip, switch_8bit_bus); 898 if (retval != STATUS_SUCCESS) { 899 rtsx_trace(chip); 900 return STATUS_FAIL; 901 } 902 903 retval = ms_confirm_cpu_startup(chip); 904 if (retval != STATUS_SUCCESS) { 905 rtsx_trace(chip); 906 return STATUS_FAIL; 907 } 908 909 retval = ms_switch_parallel_bus(chip); 910 if (retval != STATUS_SUCCESS) { 911 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 912 ms_set_err_code(chip, MS_NO_CARD); 913 rtsx_trace(chip); 914 return STATUS_FAIL; 915 } 916 continue; 917 } else { 918 break; 919 } 920 } 921 922 if (retval != STATUS_SUCCESS) { 923 rtsx_trace(chip); 924 return STATUS_FAIL; 925 } 926 927 /* Switch MS-PRO into Parallel mode */ 928 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 929 if (retval) { 930 rtsx_trace(chip); 931 return retval; 932 } 933 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 934 PUSH_TIME_ODD); 935 if (retval) { 936 rtsx_trace(chip); 937 return retval; 938 } 939 940 retval = ms_set_init_para(chip); 941 if (retval != STATUS_SUCCESS) { 942 rtsx_trace(chip); 943 return STATUS_FAIL; 944 } 945 946 /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 947 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 948 retval = ms_switch_8bit_bus(chip); 949 if (retval != STATUS_SUCCESS) { 950 ms_card->switch_8bit_fail = 1; 951 rtsx_trace(chip); 952 return STATUS_FAIL; 953 } 954 } 955 956 return STATUS_SUCCESS; 957 } 958 959 #ifdef XC_POWERCLASS 960 static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 961 { 962 int retval; 963 u8 buf[6]; 964 965 ms_cleanup_work(chip); 966 967 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 968 if (retval != STATUS_SUCCESS) { 969 rtsx_trace(chip); 970 return STATUS_FAIL; 971 } 972 973 buf[0] = 0; 974 buf[1] = mode; 975 buf[2] = 0; 976 buf[3] = 0; 977 buf[4] = 0; 978 buf[5] = 0; 979 980 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 981 if (retval != STATUS_SUCCESS) { 982 rtsx_trace(chip); 983 return STATUS_FAIL; 984 } 985 986 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 987 if (retval != STATUS_SUCCESS) { 988 rtsx_trace(chip); 989 return STATUS_FAIL; 990 } 991 992 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 993 if (retval) { 994 rtsx_trace(chip); 995 return retval; 996 } 997 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) { 998 rtsx_trace(chip); 999 return STATUS_FAIL; 1000 } 1001 1002 return STATUS_SUCCESS; 1003 } 1004 #endif 1005 1006 static int ms_read_attribute_info(struct rtsx_chip *chip) 1007 { 1008 struct ms_info *ms_card = &chip->ms_card; 1009 int retval, i; 1010 u8 val, *buf, class_code, device_type, sub_class, data[16]; 1011 u16 total_blk = 0, blk_size = 0; 1012 #ifdef SUPPORT_MSXC 1013 u32 xc_total_blk = 0, xc_blk_size = 0; 1014 #endif 1015 u32 sys_info_addr = 0, sys_info_size; 1016 #ifdef SUPPORT_PCGL_1P18 1017 u32 model_name_addr = 0, model_name_size; 1018 int found_sys_info = 0, found_model_name = 0; 1019 #endif 1020 1021 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7); 1022 if (retval != STATUS_SUCCESS) { 1023 rtsx_trace(chip); 1024 return STATUS_FAIL; 1025 } 1026 1027 if (CHK_MS8BIT(ms_card)) 1028 data[0] = PARALLEL_8BIT_IF; 1029 else 1030 data[0] = PARALLEL_4BIT_IF; 1031 1032 data[1] = 0; 1033 1034 data[2] = 0x40; 1035 data[3] = 0; 1036 data[4] = 0; 1037 data[5] = 0; 1038 data[6] = 0; 1039 data[7] = 0; 1040 1041 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1042 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 1043 data, 8); 1044 if (retval == STATUS_SUCCESS) 1045 break; 1046 } 1047 if (retval != STATUS_SUCCESS) { 1048 rtsx_trace(chip); 1049 return STATUS_FAIL; 1050 } 1051 1052 buf = kmalloc(64 * 512, GFP_KERNEL); 1053 if (!buf) { 1054 rtsx_trace(chip); 1055 return STATUS_ERROR; 1056 } 1057 1058 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1059 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 1060 if (retval != STATUS_SUCCESS) 1061 continue; 1062 1063 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1064 if (retval != STATUS_SUCCESS) { 1065 kfree(buf); 1066 rtsx_trace(chip); 1067 return STATUS_FAIL; 1068 } 1069 if (!(val & MS_INT_BREQ)) { 1070 kfree(buf); 1071 rtsx_trace(chip); 1072 return STATUS_FAIL; 1073 } 1074 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 1075 PRO_READ_LONG_DATA, 0x40, WAIT_INT, 1076 0, 0, buf, 64 * 512); 1077 if (retval == STATUS_SUCCESS) 1078 break; 1079 1080 rtsx_clear_ms_error(chip); 1081 } 1082 if (retval != STATUS_SUCCESS) { 1083 kfree(buf); 1084 rtsx_trace(chip); 1085 return STATUS_FAIL; 1086 } 1087 1088 i = 0; 1089 do { 1090 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1091 if (retval != STATUS_SUCCESS) { 1092 kfree(buf); 1093 rtsx_trace(chip); 1094 return STATUS_FAIL; 1095 } 1096 1097 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 1098 break; 1099 1100 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 1101 PRO_READ_LONG_DATA, 0, WAIT_INT); 1102 if (retval != STATUS_SUCCESS) { 1103 kfree(buf); 1104 rtsx_trace(chip); 1105 return STATUS_FAIL; 1106 } 1107 1108 i++; 1109 } while (i < 1024); 1110 1111 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) { 1112 /* Signature code is wrong */ 1113 kfree(buf); 1114 rtsx_trace(chip); 1115 return STATUS_FAIL; 1116 } 1117 1118 if ((buf[4] < 1) || (buf[4] > 12)) { 1119 kfree(buf); 1120 rtsx_trace(chip); 1121 return STATUS_FAIL; 1122 } 1123 1124 for (i = 0; i < buf[4]; i++) { 1125 int cur_addr_off = 16 + i * 12; 1126 1127 #ifdef SUPPORT_MSXC 1128 if ((buf[cur_addr_off + 8] == 0x10) || 1129 (buf[cur_addr_off + 8] == 0x13)) { 1130 #else 1131 if (buf[cur_addr_off + 8] == 0x10) { 1132 #endif 1133 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1134 ((u32)buf[cur_addr_off + 1] << 16) | 1135 ((u32)buf[cur_addr_off + 2] << 8) | 1136 buf[cur_addr_off + 3]; 1137 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 1138 ((u32)buf[cur_addr_off + 5] << 16) | 1139 ((u32)buf[cur_addr_off + 6] << 8) | 1140 buf[cur_addr_off + 7]; 1141 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 1142 sys_info_addr, sys_info_size); 1143 if (sys_info_size != 96) { 1144 kfree(buf); 1145 rtsx_trace(chip); 1146 return STATUS_FAIL; 1147 } 1148 if (sys_info_addr < 0x1A0) { 1149 kfree(buf); 1150 rtsx_trace(chip); 1151 return STATUS_FAIL; 1152 } 1153 if ((sys_info_size + sys_info_addr) > 0x8000) { 1154 kfree(buf); 1155 rtsx_trace(chip); 1156 return STATUS_FAIL; 1157 } 1158 1159 #ifdef SUPPORT_MSXC 1160 if (buf[cur_addr_off + 8] == 0x13) 1161 ms_card->ms_type |= MS_XC; 1162 #endif 1163 #ifdef SUPPORT_PCGL_1P18 1164 found_sys_info = 1; 1165 #else 1166 break; 1167 #endif 1168 } 1169 #ifdef SUPPORT_PCGL_1P18 1170 if (buf[cur_addr_off + 8] == 0x15) { 1171 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1172 ((u32)buf[cur_addr_off + 1] << 16) | 1173 ((u32)buf[cur_addr_off + 2] << 8) | 1174 buf[cur_addr_off + 3]; 1175 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1176 ((u32)buf[cur_addr_off + 5] << 16) | 1177 ((u32)buf[cur_addr_off + 6] << 8) | 1178 buf[cur_addr_off + 7]; 1179 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1180 model_name_addr, model_name_size); 1181 if (model_name_size != 48) { 1182 kfree(buf); 1183 rtsx_trace(chip); 1184 return STATUS_FAIL; 1185 } 1186 if (model_name_addr < 0x1A0) { 1187 kfree(buf); 1188 rtsx_trace(chip); 1189 return STATUS_FAIL; 1190 } 1191 if ((model_name_size + model_name_addr) > 0x8000) { 1192 kfree(buf); 1193 rtsx_trace(chip); 1194 return STATUS_FAIL; 1195 } 1196 1197 found_model_name = 1; 1198 } 1199 1200 if (found_sys_info && found_model_name) 1201 break; 1202 #endif 1203 } 1204 1205 if (i == buf[4]) { 1206 kfree(buf); 1207 rtsx_trace(chip); 1208 return STATUS_FAIL; 1209 } 1210 1211 class_code = buf[sys_info_addr + 0]; 1212 device_type = buf[sys_info_addr + 56]; 1213 sub_class = buf[sys_info_addr + 46]; 1214 #ifdef SUPPORT_MSXC 1215 if (CHK_MSXC(ms_card)) { 1216 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1217 ((u32)buf[sys_info_addr + 7] << 16) | 1218 ((u32)buf[sys_info_addr + 8] << 8) | 1219 buf[sys_info_addr + 9]; 1220 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1221 ((u32)buf[sys_info_addr + 33] << 16) | 1222 ((u32)buf[sys_info_addr + 34] << 8) | 1223 buf[sys_info_addr + 35]; 1224 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1225 xc_total_blk, xc_blk_size); 1226 } else { 1227 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1228 buf[sys_info_addr + 7]; 1229 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1230 buf[sys_info_addr + 3]; 1231 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1232 total_blk, blk_size); 1233 } 1234 #else 1235 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1236 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1237 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1238 total_blk, blk_size); 1239 #endif 1240 1241 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1242 class_code, device_type, sub_class); 1243 1244 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1245 #ifdef SUPPORT_PCGL_1P18 1246 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1247 #endif 1248 1249 kfree(buf); 1250 1251 #ifdef SUPPORT_MSXC 1252 if (CHK_MSXC(ms_card)) { 1253 if (class_code != 0x03) { 1254 rtsx_trace(chip); 1255 return STATUS_FAIL; 1256 } 1257 } else { 1258 if (class_code != 0x02) { 1259 rtsx_trace(chip); 1260 return STATUS_FAIL; 1261 } 1262 } 1263 #else 1264 if (class_code != 0x02) { 1265 rtsx_trace(chip); 1266 return STATUS_FAIL; 1267 } 1268 #endif 1269 1270 if (device_type != 0x00) { 1271 if ((device_type == 0x01) || (device_type == 0x02) || 1272 (device_type == 0x03)) { 1273 chip->card_wp |= MS_CARD; 1274 } else { 1275 rtsx_trace(chip); 1276 return STATUS_FAIL; 1277 } 1278 } 1279 1280 if (sub_class & 0xC0) { 1281 rtsx_trace(chip); 1282 return STATUS_FAIL; 1283 } 1284 1285 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1286 class_code, device_type, sub_class); 1287 1288 #ifdef SUPPORT_MSXC 1289 if (CHK_MSXC(ms_card)) { 1290 chip->capacity[chip->card2lun[MS_CARD]] = 1291 ms_card->capacity = xc_total_blk * xc_blk_size; 1292 } else { 1293 chip->capacity[chip->card2lun[MS_CARD]] = 1294 ms_card->capacity = total_blk * blk_size; 1295 } 1296 #else 1297 ms_card->capacity = total_blk * blk_size; 1298 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1299 #endif 1300 1301 return STATUS_SUCCESS; 1302 } 1303 1304 #ifdef SUPPORT_MAGIC_GATE 1305 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1306 int type, u8 mg_entry_num); 1307 #endif 1308 1309 static int reset_ms_pro(struct rtsx_chip *chip) 1310 { 1311 struct ms_info *ms_card = &chip->ms_card; 1312 int retval; 1313 #ifdef XC_POWERCLASS 1314 u8 change_power_class; 1315 1316 if (chip->ms_power_class_en & 0x02) 1317 change_power_class = 2; 1318 else if (chip->ms_power_class_en & 0x01) 1319 change_power_class = 1; 1320 else 1321 change_power_class = 0; 1322 #endif 1323 1324 #ifdef XC_POWERCLASS 1325 retry: 1326 #endif 1327 retval = ms_pro_reset_flow(chip, 1); 1328 if (retval != STATUS_SUCCESS) { 1329 if (ms_card->switch_8bit_fail) { 1330 retval = ms_pro_reset_flow(chip, 0); 1331 if (retval != STATUS_SUCCESS) { 1332 rtsx_trace(chip); 1333 return STATUS_FAIL; 1334 } 1335 } else { 1336 rtsx_trace(chip); 1337 return STATUS_FAIL; 1338 } 1339 } 1340 1341 retval = ms_read_attribute_info(chip); 1342 if (retval != STATUS_SUCCESS) { 1343 rtsx_trace(chip); 1344 return STATUS_FAIL; 1345 } 1346 1347 #ifdef XC_POWERCLASS 1348 if (CHK_HG8BIT(ms_card)) 1349 change_power_class = 0; 1350 1351 if (change_power_class && CHK_MSXC(ms_card)) { 1352 u8 power_class_en = chip->ms_power_class_en; 1353 1354 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1355 power_class_en); 1356 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1357 change_power_class); 1358 1359 if (change_power_class) 1360 power_class_en &= (1 << (change_power_class - 1)); 1361 else 1362 power_class_en = 0; 1363 1364 if (power_class_en) { 1365 u8 power_class_mode = 1366 (ms_card->raw_sys_info[46] & 0x18) >> 3; 1367 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1368 power_class_mode); 1369 if (change_power_class > power_class_mode) 1370 change_power_class = power_class_mode; 1371 if (change_power_class) { 1372 retval = msxc_change_power(chip, 1373 change_power_class); 1374 if (retval != STATUS_SUCCESS) { 1375 change_power_class--; 1376 goto retry; 1377 } 1378 } 1379 } 1380 } 1381 #endif 1382 1383 #ifdef SUPPORT_MAGIC_GATE 1384 retval = mg_set_tpc_para_sub(chip, 0, 0); 1385 if (retval != STATUS_SUCCESS) { 1386 rtsx_trace(chip); 1387 return STATUS_FAIL; 1388 } 1389 #endif 1390 1391 if (CHK_HG8BIT(ms_card)) 1392 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1393 else 1394 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1395 1396 return STATUS_SUCCESS; 1397 } 1398 1399 static int ms_read_status_reg(struct rtsx_chip *chip) 1400 { 1401 int retval; 1402 u8 val[2]; 1403 1404 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0); 1405 if (retval != STATUS_SUCCESS) { 1406 rtsx_trace(chip); 1407 return STATUS_FAIL; 1408 } 1409 1410 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1411 if (retval != STATUS_SUCCESS) { 1412 rtsx_trace(chip); 1413 return STATUS_FAIL; 1414 } 1415 1416 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1417 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1418 rtsx_trace(chip); 1419 return STATUS_FAIL; 1420 } 1421 1422 return STATUS_SUCCESS; 1423 } 1424 1425 static int ms_read_extra_data(struct rtsx_chip *chip, 1426 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1427 { 1428 struct ms_info *ms_card = &chip->ms_card; 1429 int retval, i; 1430 u8 val, data[10]; 1431 1432 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1433 SystemParm, 6); 1434 if (retval != STATUS_SUCCESS) { 1435 rtsx_trace(chip); 1436 return STATUS_FAIL; 1437 } 1438 1439 if (CHK_MS4BIT(ms_card)) { 1440 /* Parallel interface */ 1441 data[0] = 0x88; 1442 } else { 1443 /* Serial interface */ 1444 data[0] = 0x80; 1445 } 1446 data[1] = 0; 1447 data[2] = (u8)(block_addr >> 8); 1448 data[3] = (u8)block_addr; 1449 data[4] = 0x40; 1450 data[5] = page_num; 1451 1452 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1453 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1454 data, 6); 1455 if (retval == STATUS_SUCCESS) 1456 break; 1457 } 1458 if (i == MS_MAX_RETRY_COUNT) { 1459 rtsx_trace(chip); 1460 return STATUS_FAIL; 1461 } 1462 1463 ms_set_err_code(chip, MS_NO_ERROR); 1464 1465 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1466 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1467 if (retval == STATUS_SUCCESS) 1468 break; 1469 } 1470 if (i == MS_MAX_RETRY_COUNT) { 1471 rtsx_trace(chip); 1472 return STATUS_FAIL; 1473 } 1474 1475 ms_set_err_code(chip, MS_NO_ERROR); 1476 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1477 if (retval != STATUS_SUCCESS) { 1478 rtsx_trace(chip); 1479 return STATUS_FAIL; 1480 } 1481 1482 if (val & INT_REG_CMDNK) { 1483 ms_set_err_code(chip, MS_CMD_NK); 1484 rtsx_trace(chip); 1485 return STATUS_FAIL; 1486 } 1487 if (val & INT_REG_CED) { 1488 if (val & INT_REG_ERR) { 1489 retval = ms_read_status_reg(chip); 1490 if (retval != STATUS_SUCCESS) { 1491 rtsx_trace(chip); 1492 return STATUS_FAIL; 1493 } 1494 1495 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1496 MS_EXTRA_SIZE, SystemParm, 1497 6); 1498 if (retval != STATUS_SUCCESS) { 1499 rtsx_trace(chip); 1500 return STATUS_FAIL; 1501 } 1502 } 1503 } 1504 1505 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1506 data, MS_EXTRA_SIZE); 1507 if (retval != STATUS_SUCCESS) { 1508 rtsx_trace(chip); 1509 return STATUS_FAIL; 1510 } 1511 1512 if (buf && buf_len) { 1513 if (buf_len > MS_EXTRA_SIZE) 1514 buf_len = MS_EXTRA_SIZE; 1515 memcpy(buf, data, buf_len); 1516 } 1517 1518 return STATUS_SUCCESS; 1519 } 1520 1521 static int ms_write_extra_data(struct rtsx_chip *chip, u16 block_addr, 1522 u8 page_num, u8 *buf, int buf_len) 1523 { 1524 struct ms_info *ms_card = &chip->ms_card; 1525 int retval, i; 1526 u8 val, data[16]; 1527 1528 if (!buf || (buf_len < MS_EXTRA_SIZE)) { 1529 rtsx_trace(chip); 1530 return STATUS_FAIL; 1531 } 1532 1533 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1534 SystemParm, 6 + MS_EXTRA_SIZE); 1535 if (retval != STATUS_SUCCESS) { 1536 rtsx_trace(chip); 1537 return STATUS_FAIL; 1538 } 1539 1540 if (CHK_MS4BIT(ms_card)) 1541 data[0] = 0x88; 1542 else 1543 data[0] = 0x80; 1544 1545 data[1] = 0; 1546 data[2] = (u8)(block_addr >> 8); 1547 data[3] = (u8)block_addr; 1548 data[4] = 0x40; 1549 data[5] = page_num; 1550 1551 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1552 data[i] = buf[i - 6]; 1553 1554 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1555 NO_WAIT_INT, data, 16); 1556 if (retval != STATUS_SUCCESS) { 1557 rtsx_trace(chip); 1558 return STATUS_FAIL; 1559 } 1560 1561 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1562 if (retval != STATUS_SUCCESS) { 1563 rtsx_trace(chip); 1564 return STATUS_FAIL; 1565 } 1566 1567 ms_set_err_code(chip, MS_NO_ERROR); 1568 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1569 if (retval != STATUS_SUCCESS) { 1570 rtsx_trace(chip); 1571 return STATUS_FAIL; 1572 } 1573 1574 if (val & INT_REG_CMDNK) { 1575 ms_set_err_code(chip, MS_CMD_NK); 1576 rtsx_trace(chip); 1577 return STATUS_FAIL; 1578 } 1579 if (val & INT_REG_CED) { 1580 if (val & INT_REG_ERR) { 1581 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1582 rtsx_trace(chip); 1583 return STATUS_FAIL; 1584 } 1585 } 1586 1587 return STATUS_SUCCESS; 1588 } 1589 1590 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1591 { 1592 struct ms_info *ms_card = &chip->ms_card; 1593 int retval; 1594 u8 val, data[6]; 1595 1596 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1597 SystemParm, 6); 1598 if (retval != STATUS_SUCCESS) { 1599 rtsx_trace(chip); 1600 return STATUS_FAIL; 1601 } 1602 1603 if (CHK_MS4BIT(ms_card)) 1604 data[0] = 0x88; 1605 else 1606 data[0] = 0x80; 1607 1608 data[1] = 0; 1609 data[2] = (u8)(block_addr >> 8); 1610 data[3] = (u8)block_addr; 1611 data[4] = 0x20; 1612 data[5] = page_num; 1613 1614 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1615 if (retval != STATUS_SUCCESS) { 1616 rtsx_trace(chip); 1617 return STATUS_FAIL; 1618 } 1619 1620 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1621 if (retval != STATUS_SUCCESS) { 1622 rtsx_trace(chip); 1623 return STATUS_FAIL; 1624 } 1625 1626 ms_set_err_code(chip, MS_NO_ERROR); 1627 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1628 if (retval != STATUS_SUCCESS) { 1629 rtsx_trace(chip); 1630 return STATUS_FAIL; 1631 } 1632 1633 if (val & INT_REG_CMDNK) { 1634 ms_set_err_code(chip, MS_CMD_NK); 1635 rtsx_trace(chip); 1636 return STATUS_FAIL; 1637 } 1638 1639 if (val & INT_REG_CED) { 1640 if (val & INT_REG_ERR) { 1641 if (!(val & INT_REG_BREQ)) { 1642 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1643 rtsx_trace(chip); 1644 return STATUS_FAIL; 1645 } 1646 retval = ms_read_status_reg(chip); 1647 if (retval != STATUS_SUCCESS) 1648 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1649 1650 } else { 1651 if (!(val & INT_REG_BREQ)) { 1652 ms_set_err_code(chip, MS_BREQ_ERROR); 1653 rtsx_trace(chip); 1654 return STATUS_FAIL; 1655 } 1656 } 1657 } 1658 1659 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1660 0, NO_WAIT_INT); 1661 if (retval != STATUS_SUCCESS) { 1662 rtsx_trace(chip); 1663 return STATUS_FAIL; 1664 } 1665 1666 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1667 rtsx_trace(chip); 1668 return STATUS_FAIL; 1669 } 1670 1671 return STATUS_SUCCESS; 1672 } 1673 1674 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1675 { 1676 struct ms_info *ms_card = &chip->ms_card; 1677 int retval; 1678 u8 val, data[8], extra[MS_EXTRA_SIZE]; 1679 1680 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1681 if (retval != STATUS_SUCCESS) { 1682 rtsx_trace(chip); 1683 return STATUS_FAIL; 1684 } 1685 1686 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1687 SystemParm, 7); 1688 if (retval != STATUS_SUCCESS) { 1689 rtsx_trace(chip); 1690 return STATUS_FAIL; 1691 } 1692 1693 ms_set_err_code(chip, MS_NO_ERROR); 1694 1695 if (CHK_MS4BIT(ms_card)) 1696 data[0] = 0x88; 1697 else 1698 data[0] = 0x80; 1699 1700 data[1] = 0; 1701 data[2] = (u8)(phy_blk >> 8); 1702 data[3] = (u8)phy_blk; 1703 data[4] = 0x80; 1704 data[5] = 0; 1705 data[6] = extra[0] & 0x7F; 1706 data[7] = 0xFF; 1707 1708 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1709 if (retval != STATUS_SUCCESS) { 1710 rtsx_trace(chip); 1711 return STATUS_FAIL; 1712 } 1713 1714 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1715 if (retval != STATUS_SUCCESS) { 1716 rtsx_trace(chip); 1717 return STATUS_FAIL; 1718 } 1719 1720 ms_set_err_code(chip, MS_NO_ERROR); 1721 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1722 if (retval != STATUS_SUCCESS) { 1723 rtsx_trace(chip); 1724 return STATUS_FAIL; 1725 } 1726 1727 if (val & INT_REG_CMDNK) { 1728 ms_set_err_code(chip, MS_CMD_NK); 1729 rtsx_trace(chip); 1730 return STATUS_FAIL; 1731 } 1732 1733 if (val & INT_REG_CED) { 1734 if (val & INT_REG_ERR) { 1735 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1736 rtsx_trace(chip); 1737 return STATUS_FAIL; 1738 } 1739 } 1740 1741 return STATUS_SUCCESS; 1742 } 1743 1744 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1745 { 1746 struct ms_info *ms_card = &chip->ms_card; 1747 int retval, i = 0; 1748 u8 val, data[6]; 1749 1750 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1751 SystemParm, 6); 1752 if (retval != STATUS_SUCCESS) { 1753 rtsx_trace(chip); 1754 return STATUS_FAIL; 1755 } 1756 1757 ms_set_err_code(chip, MS_NO_ERROR); 1758 1759 if (CHK_MS4BIT(ms_card)) 1760 data[0] = 0x88; 1761 else 1762 data[0] = 0x80; 1763 1764 data[1] = 0; 1765 data[2] = (u8)(phy_blk >> 8); 1766 data[3] = (u8)phy_blk; 1767 data[4] = 0; 1768 data[5] = 0; 1769 1770 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1771 if (retval != STATUS_SUCCESS) { 1772 rtsx_trace(chip); 1773 return STATUS_FAIL; 1774 } 1775 1776 ERASE_RTY: 1777 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1778 if (retval != STATUS_SUCCESS) { 1779 rtsx_trace(chip); 1780 return STATUS_FAIL; 1781 } 1782 1783 ms_set_err_code(chip, MS_NO_ERROR); 1784 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1785 if (retval != STATUS_SUCCESS) { 1786 rtsx_trace(chip); 1787 return STATUS_FAIL; 1788 } 1789 1790 if (val & INT_REG_CMDNK) { 1791 if (i < 3) { 1792 i++; 1793 goto ERASE_RTY; 1794 } 1795 1796 ms_set_err_code(chip, MS_CMD_NK); 1797 ms_set_bad_block(chip, phy_blk); 1798 rtsx_trace(chip); 1799 return STATUS_FAIL; 1800 } 1801 1802 if (val & INT_REG_CED) { 1803 if (val & INT_REG_ERR) { 1804 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1805 rtsx_trace(chip); 1806 return STATUS_FAIL; 1807 } 1808 } 1809 1810 return STATUS_SUCCESS; 1811 } 1812 1813 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1814 { 1815 if (!extra || (extra_len < MS_EXTRA_SIZE)) 1816 return; 1817 1818 memset(extra, 0xFF, MS_EXTRA_SIZE); 1819 1820 if (type == setPS_NG) { 1821 /* set page status as 1:NG,and block status keep 1:OK */ 1822 extra[0] = 0xB8; 1823 } else { 1824 /* set page status as 0:Data Error,and block status keep 1:OK */ 1825 extra[0] = 0x98; 1826 } 1827 1828 extra[2] = (u8)(log_blk >> 8); 1829 extra[3] = (u8)log_blk; 1830 } 1831 1832 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1833 u8 start_page, u8 end_page) 1834 { 1835 int retval; 1836 u8 extra[MS_EXTRA_SIZE], i; 1837 1838 memset(extra, 0xff, MS_EXTRA_SIZE); 1839 1840 extra[0] = 0xf8; /* Block, page OK, data erased */ 1841 extra[1] = 0xff; 1842 extra[2] = (u8)(log_blk >> 8); 1843 extra[3] = (u8)log_blk; 1844 1845 for (i = start_page; i < end_page; i++) { 1846 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1847 ms_set_err_code(chip, MS_NO_CARD); 1848 rtsx_trace(chip); 1849 return STATUS_FAIL; 1850 } 1851 1852 retval = ms_write_extra_data(chip, phy_blk, i, 1853 extra, MS_EXTRA_SIZE); 1854 if (retval != STATUS_SUCCESS) { 1855 rtsx_trace(chip); 1856 return STATUS_FAIL; 1857 } 1858 } 1859 1860 return STATUS_SUCCESS; 1861 } 1862 1863 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1864 u16 log_blk, u8 start_page, u8 end_page) 1865 { 1866 struct ms_info *ms_card = &chip->ms_card; 1867 bool uncorrect_flag = false; 1868 int retval, rty_cnt; 1869 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1870 1871 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1872 old_blk, new_blk, log_blk); 1873 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1874 start_page, end_page); 1875 1876 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1877 if (retval != STATUS_SUCCESS) { 1878 rtsx_trace(chip); 1879 return STATUS_FAIL; 1880 } 1881 1882 retval = ms_read_status_reg(chip); 1883 if (retval != STATUS_SUCCESS) { 1884 rtsx_trace(chip); 1885 return STATUS_FAIL; 1886 } 1887 1888 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1889 if (retval) { 1890 rtsx_trace(chip); 1891 return retval; 1892 } 1893 1894 if (val & BUF_FULL) { 1895 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1896 if (retval != STATUS_SUCCESS) { 1897 rtsx_trace(chip); 1898 return STATUS_FAIL; 1899 } 1900 1901 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1902 if (retval != STATUS_SUCCESS) { 1903 rtsx_trace(chip); 1904 return STATUS_FAIL; 1905 } 1906 1907 if (!(val & INT_REG_CED)) { 1908 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1909 rtsx_trace(chip); 1910 return STATUS_FAIL; 1911 } 1912 } 1913 1914 for (i = start_page; i < end_page; i++) { 1915 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1916 ms_set_err_code(chip, MS_NO_CARD); 1917 rtsx_trace(chip); 1918 return STATUS_FAIL; 1919 } 1920 1921 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE); 1922 1923 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1924 MS_EXTRA_SIZE, SystemParm, 6); 1925 if (retval != STATUS_SUCCESS) { 1926 rtsx_trace(chip); 1927 return STATUS_FAIL; 1928 } 1929 1930 ms_set_err_code(chip, MS_NO_ERROR); 1931 1932 if (CHK_MS4BIT(ms_card)) 1933 data[0] = 0x88; 1934 else 1935 data[0] = 0x80; 1936 1937 data[1] = 0; 1938 data[2] = (u8)(old_blk >> 8); 1939 data[3] = (u8)old_blk; 1940 data[4] = 0x20; 1941 data[5] = i; 1942 1943 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1944 data, 6); 1945 if (retval != STATUS_SUCCESS) { 1946 rtsx_trace(chip); 1947 return STATUS_FAIL; 1948 } 1949 1950 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1951 if (retval != STATUS_SUCCESS) { 1952 rtsx_trace(chip); 1953 return STATUS_FAIL; 1954 } 1955 1956 ms_set_err_code(chip, MS_NO_ERROR); 1957 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1958 if (retval != STATUS_SUCCESS) { 1959 rtsx_trace(chip); 1960 return STATUS_FAIL; 1961 } 1962 1963 if (val & INT_REG_CMDNK) { 1964 ms_set_err_code(chip, MS_CMD_NK); 1965 rtsx_trace(chip); 1966 return STATUS_FAIL; 1967 } 1968 1969 if (val & INT_REG_CED) { 1970 if (val & INT_REG_ERR) { 1971 retval = ms_read_status_reg(chip); 1972 if (retval != STATUS_SUCCESS) { 1973 uncorrect_flag = true; 1974 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1975 } else { 1976 uncorrect_flag = false; 1977 } 1978 1979 retval = ms_transfer_tpc(chip, 1980 MS_TM_NORMAL_READ, 1981 READ_PAGE_DATA, 1982 0, NO_WAIT_INT); 1983 if (retval != STATUS_SUCCESS) { 1984 rtsx_trace(chip); 1985 return STATUS_FAIL; 1986 } 1987 1988 if (uncorrect_flag) { 1989 ms_set_page_status(log_blk, setPS_NG, 1990 extra, 1991 MS_EXTRA_SIZE); 1992 if (i == 0) 1993 extra[0] &= 0xEF; 1994 1995 ms_write_extra_data(chip, old_blk, i, 1996 extra, 1997 MS_EXTRA_SIZE); 1998 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1999 i, extra[0]); 2000 MS_SET_BAD_BLOCK_FLG(ms_card); 2001 2002 ms_set_page_status(log_blk, setPS_Error, 2003 extra, 2004 MS_EXTRA_SIZE); 2005 ms_write_extra_data(chip, new_blk, i, 2006 extra, 2007 MS_EXTRA_SIZE); 2008 continue; 2009 } 2010 2011 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 2012 rty_cnt++) { 2013 retval = ms_transfer_tpc( 2014 chip, 2015 MS_TM_NORMAL_WRITE, 2016 WRITE_PAGE_DATA, 2017 0, NO_WAIT_INT); 2018 if (retval == STATUS_SUCCESS) 2019 break; 2020 } 2021 if (rty_cnt == MS_MAX_RETRY_COUNT) { 2022 rtsx_trace(chip); 2023 return STATUS_FAIL; 2024 } 2025 } 2026 2027 if (!(val & INT_REG_BREQ)) { 2028 ms_set_err_code(chip, MS_BREQ_ERROR); 2029 rtsx_trace(chip); 2030 return STATUS_FAIL; 2031 } 2032 } 2033 2034 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 2035 SystemParm, (6 + MS_EXTRA_SIZE)); 2036 2037 ms_set_err_code(chip, MS_NO_ERROR); 2038 2039 if (CHK_MS4BIT(ms_card)) 2040 data[0] = 0x88; 2041 else 2042 data[0] = 0x80; 2043 2044 data[1] = 0; 2045 data[2] = (u8)(new_blk >> 8); 2046 data[3] = (u8)new_blk; 2047 data[4] = 0x20; 2048 data[5] = i; 2049 2050 if ((extra[0] & 0x60) != 0x60) 2051 data[6] = extra[0]; 2052 else 2053 data[6] = 0xF8; 2054 2055 data[6 + 1] = 0xFF; 2056 data[6 + 2] = (u8)(log_blk >> 8); 2057 data[6 + 3] = (u8)log_blk; 2058 2059 for (j = 4; j <= MS_EXTRA_SIZE; j++) 2060 data[6 + j] = 0xFF; 2061 2062 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 2063 NO_WAIT_INT, data, 16); 2064 if (retval != STATUS_SUCCESS) { 2065 rtsx_trace(chip); 2066 return STATUS_FAIL; 2067 } 2068 2069 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2070 if (retval != STATUS_SUCCESS) { 2071 rtsx_trace(chip); 2072 return STATUS_FAIL; 2073 } 2074 2075 ms_set_err_code(chip, MS_NO_ERROR); 2076 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 2077 if (retval != STATUS_SUCCESS) { 2078 rtsx_trace(chip); 2079 return STATUS_FAIL; 2080 } 2081 2082 if (val & INT_REG_CMDNK) { 2083 ms_set_err_code(chip, MS_CMD_NK); 2084 rtsx_trace(chip); 2085 return STATUS_FAIL; 2086 } 2087 2088 if (val & INT_REG_CED) { 2089 if (val & INT_REG_ERR) { 2090 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 2091 rtsx_trace(chip); 2092 return STATUS_FAIL; 2093 } 2094 } 2095 2096 if (i == 0) { 2097 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2098 MS_EXTRA_SIZE, SystemParm, 2099 7); 2100 if (retval != STATUS_SUCCESS) { 2101 rtsx_trace(chip); 2102 return STATUS_FAIL; 2103 } 2104 2105 ms_set_err_code(chip, MS_NO_ERROR); 2106 2107 if (CHK_MS4BIT(ms_card)) 2108 data[0] = 0x88; 2109 else 2110 data[0] = 0x80; 2111 2112 data[1] = 0; 2113 data[2] = (u8)(old_blk >> 8); 2114 data[3] = (u8)old_blk; 2115 data[4] = 0x80; 2116 data[5] = 0; 2117 data[6] = 0xEF; 2118 data[7] = 0xFF; 2119 2120 retval = ms_write_bytes(chip, WRITE_REG, 7, 2121 NO_WAIT_INT, data, 8); 2122 if (retval != STATUS_SUCCESS) { 2123 rtsx_trace(chip); 2124 return STATUS_FAIL; 2125 } 2126 2127 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2128 if (retval != STATUS_SUCCESS) { 2129 rtsx_trace(chip); 2130 return STATUS_FAIL; 2131 } 2132 2133 ms_set_err_code(chip, MS_NO_ERROR); 2134 retval = ms_read_bytes(chip, GET_INT, 1, 2135 NO_WAIT_INT, &val, 1); 2136 if (retval != STATUS_SUCCESS) { 2137 rtsx_trace(chip); 2138 return STATUS_FAIL; 2139 } 2140 2141 if (val & INT_REG_CMDNK) { 2142 ms_set_err_code(chip, MS_CMD_NK); 2143 rtsx_trace(chip); 2144 return STATUS_FAIL; 2145 } 2146 2147 if (val & INT_REG_CED) { 2148 if (val & INT_REG_ERR) { 2149 ms_set_err_code(chip, 2150 MS_FLASH_WRITE_ERROR); 2151 rtsx_trace(chip); 2152 return STATUS_FAIL; 2153 } 2154 } 2155 } 2156 } 2157 2158 return STATUS_SUCCESS; 2159 } 2160 2161 static int reset_ms(struct rtsx_chip *chip) 2162 { 2163 struct ms_info *ms_card = &chip->ms_card; 2164 int retval; 2165 u16 i, reg_addr, block_size; 2166 u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 2167 #ifndef SUPPORT_MAGIC_GATE 2168 u16 eblock_cnt; 2169 #endif 2170 2171 retval = ms_prepare_reset(chip); 2172 if (retval != STATUS_SUCCESS) { 2173 rtsx_trace(chip); 2174 return STATUS_FAIL; 2175 } 2176 2177 ms_card->ms_type |= TYPE_MS; 2178 2179 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 2180 if (retval != STATUS_SUCCESS) { 2181 rtsx_trace(chip); 2182 return STATUS_FAIL; 2183 } 2184 2185 retval = ms_read_status_reg(chip); 2186 if (retval != STATUS_SUCCESS) { 2187 rtsx_trace(chip); 2188 return STATUS_FAIL; 2189 } 2190 2191 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 2192 if (retval) { 2193 rtsx_trace(chip); 2194 return retval; 2195 } 2196 if (val & WRT_PRTCT) 2197 chip->card_wp |= MS_CARD; 2198 else 2199 chip->card_wp &= ~MS_CARD; 2200 2201 i = 0; 2202 2203 RE_SEARCH: 2204 /* Search Boot Block */ 2205 while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 2206 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2207 ms_set_err_code(chip, MS_NO_CARD); 2208 rtsx_trace(chip); 2209 return STATUS_FAIL; 2210 } 2211 2212 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 2213 if (retval != STATUS_SUCCESS) { 2214 i++; 2215 continue; 2216 } 2217 2218 if (extra[0] & BLOCK_OK) { 2219 if (!(extra[1] & NOT_BOOT_BLOCK)) { 2220 ms_card->boot_block = i; 2221 break; 2222 } 2223 } 2224 i++; 2225 } 2226 2227 if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 2228 dev_dbg(rtsx_dev(chip), "No boot block found!"); 2229 rtsx_trace(chip); 2230 return STATUS_FAIL; 2231 } 2232 2233 for (j = 0; j < 3; j++) { 2234 retval = ms_read_page(chip, ms_card->boot_block, j); 2235 if (retval != STATUS_SUCCESS) { 2236 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 2237 i = ms_card->boot_block + 1; 2238 ms_set_err_code(chip, MS_NO_ERROR); 2239 goto RE_SEARCH; 2240 } 2241 } 2242 } 2243 2244 retval = ms_read_page(chip, ms_card->boot_block, 0); 2245 if (retval != STATUS_SUCCESS) { 2246 rtsx_trace(chip); 2247 return STATUS_FAIL; 2248 } 2249 2250 /* Read MS system information as sys_info */ 2251 rtsx_init_cmd(chip); 2252 2253 for (i = 0; i < 96; i++) 2254 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 2255 2256 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2257 if (retval < 0) { 2258 rtsx_trace(chip); 2259 return STATUS_FAIL; 2260 } 2261 2262 ptr = rtsx_get_cmd_data(chip); 2263 memcpy(ms_card->raw_sys_info, ptr, 96); 2264 2265 /* Read useful block contents */ 2266 rtsx_init_cmd(chip); 2267 2268 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 2269 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 2270 2271 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 2272 reg_addr++) 2273 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2274 2275 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 2276 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2277 2278 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0); 2279 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0); 2280 2281 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2282 if (retval < 0) { 2283 rtsx_trace(chip); 2284 return STATUS_FAIL; 2285 } 2286 2287 ptr = rtsx_get_cmd_data(chip); 2288 2289 dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 2290 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 2291 2292 /* Block ID error 2293 * HEADER_ID0, HEADER_ID1 2294 */ 2295 if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2296 i = ms_card->boot_block + 1; 2297 goto RE_SEARCH; 2298 } 2299 2300 /* Page size error 2301 * PAGE_SIZE_0, PAGE_SIZE_1 2302 */ 2303 if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2304 i = ms_card->boot_block + 1; 2305 goto RE_SEARCH; 2306 } 2307 2308 if ((ptr[14] == 1) || (ptr[14] == 3)) 2309 chip->card_wp |= MS_CARD; 2310 2311 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2312 block_size = ((u16)ptr[6] << 8) | ptr[7]; 2313 if (block_size == 0x0010) { 2314 /* Block size 16KB */ 2315 ms_card->block_shift = 5; 2316 ms_card->page_off = 0x1F; 2317 } else if (block_size == 0x0008) { 2318 /* Block size 8KB */ 2319 ms_card->block_shift = 4; 2320 ms_card->page_off = 0x0F; 2321 } 2322 2323 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2324 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2325 2326 #ifdef SUPPORT_MAGIC_GATE 2327 j = ptr[10]; 2328 2329 if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2330 if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2331 ms_card->capacity = 0x1EE0; 2332 } else { /* Effective block for 8MB: 0x3E0 */ 2333 ms_card->capacity = 0x3DE0; 2334 } 2335 } else { /* 16MB, 32MB, 64MB or 128MB */ 2336 if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2337 ms_card->capacity = 0x7BC0; 2338 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2339 ms_card->capacity = 0xF7C0; 2340 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2341 ms_card->capacity = 0x1EF80; 2342 } else { /* Effective block for 128MB: 0x1F00 */ 2343 ms_card->capacity = 0x3DF00; 2344 } 2345 } 2346 #else 2347 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2348 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2349 2350 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2351 #endif 2352 2353 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2354 2355 /* Switch I/F Mode */ 2356 if (ptr[15]) { 2357 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1); 2358 if (retval != STATUS_SUCCESS) { 2359 rtsx_trace(chip); 2360 return STATUS_FAIL; 2361 } 2362 2363 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2364 if (retval) { 2365 rtsx_trace(chip); 2366 return retval; 2367 } 2368 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2369 if (retval) { 2370 rtsx_trace(chip); 2371 return retval; 2372 } 2373 2374 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2375 NO_WAIT_INT); 2376 if (retval != STATUS_SUCCESS) { 2377 rtsx_trace(chip); 2378 return STATUS_FAIL; 2379 } 2380 2381 retval = rtsx_write_register(chip, MS_CFG, 2382 0x58 | MS_NO_CHECK_INT, 2383 MS_BUS_WIDTH_4 | 2384 PUSH_TIME_ODD | 2385 MS_NO_CHECK_INT); 2386 if (retval) { 2387 rtsx_trace(chip); 2388 return retval; 2389 } 2390 2391 ms_card->ms_type |= MS_4BIT; 2392 } 2393 2394 if (CHK_MS4BIT(ms_card)) 2395 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2396 else 2397 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2398 2399 return STATUS_SUCCESS; 2400 } 2401 2402 static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2403 { 2404 struct ms_info *ms_card = &chip->ms_card; 2405 int size, i, seg_no, retval; 2406 u16 defect_block, reg_addr; 2407 u8 val1, val2; 2408 2409 ms_card->segment_cnt = ms_card->total_block >> 9; 2410 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2411 ms_card->segment_cnt); 2412 2413 size = ms_card->segment_cnt * sizeof(struct zone_entry); 2414 ms_card->segment = vzalloc(size); 2415 if (!ms_card->segment) { 2416 rtsx_trace(chip); 2417 return STATUS_FAIL; 2418 } 2419 2420 retval = ms_read_page(chip, ms_card->boot_block, 1); 2421 if (retval != STATUS_SUCCESS) { 2422 rtsx_trace(chip); 2423 goto INIT_FAIL; 2424 } 2425 2426 reg_addr = PPBUF_BASE2; 2427 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2428 int block_no; 2429 2430 retval = rtsx_read_register(chip, reg_addr++, &val1); 2431 if (retval != STATUS_SUCCESS) { 2432 rtsx_trace(chip); 2433 goto INIT_FAIL; 2434 } 2435 2436 retval = rtsx_read_register(chip, reg_addr++, &val2); 2437 if (retval != STATUS_SUCCESS) { 2438 rtsx_trace(chip); 2439 goto INIT_FAIL; 2440 } 2441 2442 defect_block = ((u16)val1 << 8) | val2; 2443 if (defect_block == 0xFFFF) 2444 break; 2445 2446 seg_no = defect_block / 512; 2447 2448 block_no = ms_card->segment[seg_no].disable_count++; 2449 ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2450 } 2451 2452 for (i = 0; i < ms_card->segment_cnt; i++) { 2453 ms_card->segment[i].build_flag = 0; 2454 ms_card->segment[i].l2p_table = NULL; 2455 ms_card->segment[i].free_table = NULL; 2456 ms_card->segment[i].get_index = 0; 2457 ms_card->segment[i].set_index = 0; 2458 ms_card->segment[i].unused_blk_cnt = 0; 2459 2460 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2461 i, ms_card->segment[i].disable_count); 2462 } 2463 2464 return STATUS_SUCCESS; 2465 2466 INIT_FAIL: 2467 vfree(ms_card->segment); 2468 ms_card->segment = NULL; 2469 2470 return STATUS_FAIL; 2471 } 2472 2473 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2474 { 2475 struct ms_info *ms_card = &chip->ms_card; 2476 struct zone_entry *segment; 2477 2478 if (!ms_card->segment) 2479 return 0xFFFF; 2480 2481 segment = &ms_card->segment[seg_no]; 2482 2483 if (segment->l2p_table) 2484 return segment->l2p_table[log_off]; 2485 2486 return 0xFFFF; 2487 } 2488 2489 static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2490 int seg_no, u16 log_off, u16 phy_blk) 2491 { 2492 struct ms_info *ms_card = &chip->ms_card; 2493 struct zone_entry *segment; 2494 2495 if (!ms_card->segment) 2496 return; 2497 2498 segment = &ms_card->segment[seg_no]; 2499 if (segment->l2p_table) 2500 segment->l2p_table[log_off] = phy_blk; 2501 } 2502 2503 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2504 { 2505 struct ms_info *ms_card = &chip->ms_card; 2506 struct zone_entry *segment; 2507 int seg_no; 2508 2509 seg_no = (int)phy_blk >> 9; 2510 segment = &ms_card->segment[seg_no]; 2511 2512 segment->free_table[segment->set_index++] = phy_blk; 2513 if (segment->set_index >= MS_FREE_TABLE_CNT) 2514 segment->set_index = 0; 2515 2516 segment->unused_blk_cnt++; 2517 } 2518 2519 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2520 { 2521 struct ms_info *ms_card = &chip->ms_card; 2522 struct zone_entry *segment; 2523 u16 phy_blk; 2524 2525 segment = &ms_card->segment[seg_no]; 2526 2527 if (segment->unused_blk_cnt <= 0) 2528 return 0xFFFF; 2529 2530 phy_blk = segment->free_table[segment->get_index]; 2531 segment->free_table[segment->get_index++] = 0xFFFF; 2532 if (segment->get_index >= MS_FREE_TABLE_CNT) 2533 segment->get_index = 0; 2534 2535 segment->unused_blk_cnt--; 2536 2537 return phy_blk; 2538 } 2539 2540 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2541 2974, 3470, 3966, 4462, 4958, 2542 5454, 5950, 6446, 6942, 7438, 2543 7934}; 2544 2545 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2546 u16 log_off, u8 us1, u8 us2) 2547 { 2548 struct ms_info *ms_card = &chip->ms_card; 2549 struct zone_entry *segment; 2550 int seg_no; 2551 u16 tmp_blk; 2552 2553 seg_no = (int)phy_blk >> 9; 2554 segment = &ms_card->segment[seg_no]; 2555 tmp_blk = segment->l2p_table[log_off]; 2556 2557 if (us1 != us2) { 2558 if (us1 == 0) { 2559 if (!(chip->card_wp & MS_CARD)) 2560 ms_erase_block(chip, tmp_blk); 2561 2562 ms_set_unused_block(chip, tmp_blk); 2563 segment->l2p_table[log_off] = phy_blk; 2564 } else { 2565 if (!(chip->card_wp & MS_CARD)) 2566 ms_erase_block(chip, phy_blk); 2567 2568 ms_set_unused_block(chip, phy_blk); 2569 } 2570 } else { 2571 if (phy_blk < tmp_blk) { 2572 if (!(chip->card_wp & MS_CARD)) 2573 ms_erase_block(chip, phy_blk); 2574 2575 ms_set_unused_block(chip, phy_blk); 2576 } else { 2577 if (!(chip->card_wp & MS_CARD)) 2578 ms_erase_block(chip, tmp_blk); 2579 2580 ms_set_unused_block(chip, tmp_blk); 2581 segment->l2p_table[log_off] = phy_blk; 2582 } 2583 } 2584 2585 return STATUS_SUCCESS; 2586 } 2587 2588 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2589 { 2590 struct ms_info *ms_card = &chip->ms_card; 2591 struct zone_entry *segment; 2592 bool defect_flag; 2593 int retval, table_size, disable_cnt, i; 2594 u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2595 u8 extra[MS_EXTRA_SIZE], us1, us2; 2596 2597 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, seg_no); 2598 2599 if (!ms_card->segment) { 2600 retval = ms_init_l2p_tbl(chip); 2601 if (retval != STATUS_SUCCESS) { 2602 rtsx_trace(chip); 2603 return retval; 2604 } 2605 } 2606 2607 if (ms_card->segment[seg_no].build_flag) { 2608 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2609 seg_no); 2610 return STATUS_SUCCESS; 2611 } 2612 2613 if (seg_no == 0) 2614 table_size = 494; 2615 else 2616 table_size = 496; 2617 2618 segment = &ms_card->segment[seg_no]; 2619 2620 if (!segment->l2p_table) { 2621 segment->l2p_table = vmalloc(table_size * 2); 2622 if (!segment->l2p_table) { 2623 rtsx_trace(chip); 2624 goto BUILD_FAIL; 2625 } 2626 } 2627 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2); 2628 2629 if (!segment->free_table) { 2630 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2); 2631 if (!segment->free_table) { 2632 rtsx_trace(chip); 2633 goto BUILD_FAIL; 2634 } 2635 } 2636 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2); 2637 2638 start = (u16)seg_no << 9; 2639 end = (u16)(seg_no + 1) << 9; 2640 2641 disable_cnt = segment->disable_count; 2642 2643 segment->get_index = 0; 2644 segment->set_index = 0; 2645 segment->unused_blk_cnt = 0; 2646 2647 for (phy_blk = start; phy_blk < end; phy_blk++) { 2648 if (disable_cnt) { 2649 defect_flag = false; 2650 for (i = 0; i < segment->disable_count; i++) { 2651 if (phy_blk == segment->defect_list[i]) { 2652 defect_flag = true; 2653 break; 2654 } 2655 } 2656 if (defect_flag) { 2657 disable_cnt--; 2658 continue; 2659 } 2660 } 2661 2662 retval = ms_read_extra_data(chip, phy_blk, 0, 2663 extra, MS_EXTRA_SIZE); 2664 if (retval != STATUS_SUCCESS) { 2665 dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2666 ms_set_bad_block(chip, phy_blk); 2667 continue; 2668 } 2669 2670 if (seg_no == ms_card->segment_cnt - 1) { 2671 if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2672 if (!(chip->card_wp & MS_CARD)) { 2673 retval = ms_erase_block(chip, phy_blk); 2674 if (retval != STATUS_SUCCESS) 2675 continue; 2676 extra[2] = 0xff; 2677 extra[3] = 0xff; 2678 } 2679 } 2680 } 2681 2682 if (!(extra[0] & BLOCK_OK)) 2683 continue; 2684 if (!(extra[1] & NOT_BOOT_BLOCK)) 2685 continue; 2686 if ((extra[0] & PAGE_OK) != PAGE_OK) 2687 continue; 2688 2689 log_blk = ((u16)extra[2] << 8) | extra[3]; 2690 2691 if (log_blk == 0xFFFF) { 2692 if (!(chip->card_wp & MS_CARD)) { 2693 retval = ms_erase_block(chip, phy_blk); 2694 if (retval != STATUS_SUCCESS) 2695 continue; 2696 } 2697 ms_set_unused_block(chip, phy_blk); 2698 continue; 2699 } 2700 2701 if ((log_blk < ms_start_idx[seg_no]) || 2702 (log_blk >= ms_start_idx[seg_no + 1])) { 2703 if (!(chip->card_wp & MS_CARD)) { 2704 retval = ms_erase_block(chip, phy_blk); 2705 if (retval != STATUS_SUCCESS) 2706 continue; 2707 } 2708 ms_set_unused_block(chip, phy_blk); 2709 continue; 2710 } 2711 2712 idx = log_blk - ms_start_idx[seg_no]; 2713 2714 if (segment->l2p_table[idx] == 0xFFFF) { 2715 segment->l2p_table[idx] = phy_blk; 2716 continue; 2717 } 2718 2719 us1 = extra[0] & 0x10; 2720 tmp_blk = segment->l2p_table[idx]; 2721 retval = ms_read_extra_data(chip, tmp_blk, 0, 2722 extra, MS_EXTRA_SIZE); 2723 if (retval != STATUS_SUCCESS) 2724 continue; 2725 us2 = extra[0] & 0x10; 2726 2727 (void)ms_arbitrate_l2p(chip, phy_blk, 2728 log_blk - ms_start_idx[seg_no], us1, us2); 2729 continue; 2730 } 2731 2732 segment->build_flag = 1; 2733 2734 dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2735 segment->unused_blk_cnt); 2736 2737 /* Logical Address Confirmation Process */ 2738 if (seg_no == ms_card->segment_cnt - 1) { 2739 if (segment->unused_blk_cnt < 2) 2740 chip->card_wp |= MS_CARD; 2741 } else { 2742 if (segment->unused_blk_cnt < 1) 2743 chip->card_wp |= MS_CARD; 2744 } 2745 2746 if (chip->card_wp & MS_CARD) 2747 return STATUS_SUCCESS; 2748 2749 for (log_blk = ms_start_idx[seg_no]; 2750 log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2751 idx = log_blk - ms_start_idx[seg_no]; 2752 if (segment->l2p_table[idx] == 0xFFFF) { 2753 phy_blk = ms_get_unused_block(chip, seg_no); 2754 if (phy_blk == 0xFFFF) { 2755 chip->card_wp |= MS_CARD; 2756 return STATUS_SUCCESS; 2757 } 2758 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2759 if (retval != STATUS_SUCCESS) { 2760 rtsx_trace(chip); 2761 goto BUILD_FAIL; 2762 } 2763 2764 segment->l2p_table[idx] = phy_blk; 2765 if (seg_no == ms_card->segment_cnt - 1) { 2766 if (segment->unused_blk_cnt < 2) { 2767 chip->card_wp |= MS_CARD; 2768 return STATUS_SUCCESS; 2769 } 2770 } else { 2771 if (segment->unused_blk_cnt < 1) { 2772 chip->card_wp |= MS_CARD; 2773 return STATUS_SUCCESS; 2774 } 2775 } 2776 } 2777 } 2778 2779 /* Make boot block be the first normal block */ 2780 if (seg_no == 0) { 2781 for (log_blk = 0; log_blk < 494; log_blk++) { 2782 tmp_blk = segment->l2p_table[log_blk]; 2783 if (tmp_blk < ms_card->boot_block) { 2784 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2785 2786 if (chip->card_wp & MS_CARD) 2787 break; 2788 2789 phy_blk = ms_get_unused_block(chip, 0); 2790 retval = ms_copy_page(chip, tmp_blk, phy_blk, 2791 log_blk, 0, 2792 ms_card->page_off + 1); 2793 if (retval != STATUS_SUCCESS) { 2794 rtsx_trace(chip); 2795 return STATUS_FAIL; 2796 } 2797 2798 segment->l2p_table[log_blk] = phy_blk; 2799 2800 retval = ms_set_bad_block(chip, tmp_blk); 2801 if (retval != STATUS_SUCCESS) { 2802 rtsx_trace(chip); 2803 return STATUS_FAIL; 2804 } 2805 } 2806 } 2807 } 2808 2809 return STATUS_SUCCESS; 2810 2811 BUILD_FAIL: 2812 segment->build_flag = 0; 2813 vfree(segment->l2p_table); 2814 segment->l2p_table = NULL; 2815 vfree(segment->free_table); 2816 segment->free_table = NULL; 2817 2818 return STATUS_FAIL; 2819 } 2820 2821 int reset_ms_card(struct rtsx_chip *chip) 2822 { 2823 struct ms_info *ms_card = &chip->ms_card; 2824 int retval; 2825 2826 memset(ms_card, 0, sizeof(struct ms_info)); 2827 2828 retval = enable_card_clock(chip, MS_CARD); 2829 if (retval != STATUS_SUCCESS) { 2830 rtsx_trace(chip); 2831 return STATUS_FAIL; 2832 } 2833 2834 retval = select_card(chip, MS_CARD); 2835 if (retval != STATUS_SUCCESS) { 2836 rtsx_trace(chip); 2837 return STATUS_FAIL; 2838 } 2839 2840 ms_card->ms_type = 0; 2841 2842 retval = reset_ms_pro(chip); 2843 if (retval != STATUS_SUCCESS) { 2844 if (ms_card->check_ms_flow) { 2845 retval = reset_ms(chip); 2846 if (retval != STATUS_SUCCESS) { 2847 rtsx_trace(chip); 2848 return STATUS_FAIL; 2849 } 2850 } else { 2851 rtsx_trace(chip); 2852 return STATUS_FAIL; 2853 } 2854 } 2855 2856 retval = ms_set_init_para(chip); 2857 if (retval != STATUS_SUCCESS) { 2858 rtsx_trace(chip); 2859 return STATUS_FAIL; 2860 } 2861 2862 if (!CHK_MSPRO(ms_card)) { 2863 /* Build table for the last segment, 2864 * to check if L2P table block exists, erasing it 2865 */ 2866 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1); 2867 if (retval != STATUS_SUCCESS) { 2868 rtsx_trace(chip); 2869 return STATUS_FAIL; 2870 } 2871 } 2872 2873 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2874 2875 return STATUS_SUCCESS; 2876 } 2877 2878 static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2879 u32 start_sec, u16 sec_cnt, u8 cmd) 2880 { 2881 int retval, i; 2882 u8 data[8]; 2883 2884 data[0] = cmd; 2885 data[1] = (u8)(sec_cnt >> 8); 2886 data[2] = (u8)sec_cnt; 2887 data[3] = (u8)(start_sec >> 24); 2888 data[4] = (u8)(start_sec >> 16); 2889 data[5] = (u8)(start_sec >> 8); 2890 data[6] = (u8)start_sec; 2891 data[7] = 0; 2892 2893 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2894 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2895 WAIT_INT, data, 8); 2896 if (retval == STATUS_SUCCESS) 2897 break; 2898 } 2899 if (i == MS_MAX_RETRY_COUNT) { 2900 rtsx_trace(chip); 2901 return STATUS_FAIL; 2902 } 2903 2904 return STATUS_SUCCESS; 2905 } 2906 2907 void mspro_stop_seq_mode(struct rtsx_chip *chip) 2908 { 2909 struct ms_info *ms_card = &chip->ms_card; 2910 int retval; 2911 2912 if (ms_card->seq_mode) { 2913 retval = ms_switch_clock(chip); 2914 if (retval != STATUS_SUCCESS) 2915 return; 2916 2917 ms_card->seq_mode = 0; 2918 ms_card->total_sec_cnt = 0; 2919 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2920 2921 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2922 } 2923 } 2924 2925 static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2926 { 2927 struct ms_info *ms_card = &chip->ms_card; 2928 int retval; 2929 2930 if (chip->asic_code) { 2931 if (ms_card->ms_clock > 30) 2932 ms_card->ms_clock -= 20; 2933 } else { 2934 if (ms_card->ms_clock == CLK_80) 2935 ms_card->ms_clock = CLK_60; 2936 else if (ms_card->ms_clock == CLK_60) 2937 ms_card->ms_clock = CLK_40; 2938 } 2939 2940 retval = ms_switch_clock(chip); 2941 if (retval != STATUS_SUCCESS) { 2942 rtsx_trace(chip); 2943 return STATUS_FAIL; 2944 } 2945 2946 return STATUS_SUCCESS; 2947 } 2948 2949 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2950 struct rtsx_chip *chip, u32 start_sector, 2951 u16 sector_cnt) 2952 { 2953 struct ms_info *ms_card = &chip->ms_card; 2954 bool mode_2k = false; 2955 int retval; 2956 u16 count; 2957 u8 val, trans_mode, rw_tpc, rw_cmd; 2958 2959 ms_set_err_code(chip, MS_NO_ERROR); 2960 2961 ms_card->cleanup_counter = 0; 2962 2963 if (CHK_MSHG(ms_card)) { 2964 if ((start_sector % 4) || (sector_cnt % 4)) { 2965 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2966 rw_tpc = PRO_READ_LONG_DATA; 2967 rw_cmd = PRO_READ_DATA; 2968 } else { 2969 rw_tpc = PRO_WRITE_LONG_DATA; 2970 rw_cmd = PRO_WRITE_DATA; 2971 } 2972 } else { 2973 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2974 rw_tpc = PRO_READ_QUAD_DATA; 2975 rw_cmd = PRO_READ_2K_DATA; 2976 } else { 2977 rw_tpc = PRO_WRITE_QUAD_DATA; 2978 rw_cmd = PRO_WRITE_2K_DATA; 2979 } 2980 mode_2k = true; 2981 } 2982 } else { 2983 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2984 rw_tpc = PRO_READ_LONG_DATA; 2985 rw_cmd = PRO_READ_DATA; 2986 } else { 2987 rw_tpc = PRO_WRITE_LONG_DATA; 2988 rw_cmd = PRO_WRITE_DATA; 2989 } 2990 } 2991 2992 retval = ms_switch_clock(chip); 2993 if (retval != STATUS_SUCCESS) { 2994 rtsx_trace(chip); 2995 return STATUS_FAIL; 2996 } 2997 2998 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2999 trans_mode = MS_TM_AUTO_READ; 3000 else 3001 trans_mode = MS_TM_AUTO_WRITE; 3002 3003 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3004 if (retval) { 3005 rtsx_trace(chip); 3006 return retval; 3007 } 3008 3009 if (ms_card->seq_mode) { 3010 if ((ms_card->pre_dir != srb->sc_data_direction) || 3011 ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != 3012 start_sector) || 3013 (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) || 3014 (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) || 3015 !(val & MS_INT_BREQ) || 3016 ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 3017 ms_card->seq_mode = 0; 3018 ms_card->total_sec_cnt = 0; 3019 if (val & MS_INT_BREQ) { 3020 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3021 if (retval != STATUS_SUCCESS) { 3022 rtsx_trace(chip); 3023 return STATUS_FAIL; 3024 } 3025 3026 rtsx_write_register(chip, RBCTL, RB_FLUSH, 3027 RB_FLUSH); 3028 } 3029 } 3030 } 3031 3032 if (!ms_card->seq_mode) { 3033 ms_card->total_sec_cnt = 0; 3034 if (sector_cnt >= SEQ_START_CRITERIA) { 3035 if ((ms_card->capacity - start_sector) > 0xFE00) 3036 count = 0xFE00; 3037 else 3038 count = (u16)(ms_card->capacity - start_sector); 3039 3040 if (count > sector_cnt) { 3041 if (mode_2k) 3042 ms_card->seq_mode = MODE_2K_SEQ; 3043 else 3044 ms_card->seq_mode = MODE_512_SEQ; 3045 } 3046 } else { 3047 count = sector_cnt; 3048 } 3049 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 3050 if (retval != STATUS_SUCCESS) { 3051 ms_card->seq_mode = 0; 3052 rtsx_trace(chip); 3053 return STATUS_FAIL; 3054 } 3055 } 3056 3057 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 3058 WAIT_INT, mode_2k, scsi_sg_count(srb), 3059 scsi_sglist(srb), scsi_bufflen(srb)); 3060 if (retval != STATUS_SUCCESS) { 3061 ms_card->seq_mode = 0; 3062 rtsx_read_register(chip, MS_TRANS_CFG, &val); 3063 rtsx_clear_ms_error(chip); 3064 3065 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3066 chip->rw_need_retry = 0; 3067 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", 3068 __func__); 3069 rtsx_trace(chip); 3070 return STATUS_FAIL; 3071 } 3072 3073 if (val & MS_INT_BREQ) 3074 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3075 3076 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3077 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 3078 chip->rw_need_retry = 1; 3079 ms_auto_tune_clock(chip); 3080 } 3081 3082 rtsx_trace(chip); 3083 return retval; 3084 } 3085 3086 if (ms_card->seq_mode) { 3087 ms_card->pre_sec_addr = start_sector; 3088 ms_card->pre_sec_cnt = sector_cnt; 3089 ms_card->pre_dir = srb->sc_data_direction; 3090 ms_card->total_sec_cnt += sector_cnt; 3091 } 3092 3093 return STATUS_SUCCESS; 3094 } 3095 3096 static int mspro_read_format_progress(struct rtsx_chip *chip, 3097 const int short_data_len) 3098 { 3099 struct ms_info *ms_card = &chip->ms_card; 3100 int retval, i; 3101 u32 total_progress, cur_progress; 3102 u8 cnt, tmp; 3103 u8 data[8]; 3104 3105 dev_dbg(rtsx_dev(chip), "%s, short_data_len = %d\n", __func__, 3106 short_data_len); 3107 3108 retval = ms_switch_clock(chip); 3109 if (retval != STATUS_SUCCESS) { 3110 ms_card->format_status = FORMAT_FAIL; 3111 rtsx_trace(chip); 3112 return STATUS_FAIL; 3113 } 3114 3115 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3116 if (retval != STATUS_SUCCESS) { 3117 ms_card->format_status = FORMAT_FAIL; 3118 rtsx_trace(chip); 3119 return STATUS_FAIL; 3120 } 3121 3122 if (!(tmp & MS_INT_BREQ)) { 3123 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | 3124 MS_INT_ERR)) == MS_INT_CED) { 3125 ms_card->format_status = FORMAT_SUCCESS; 3126 return STATUS_SUCCESS; 3127 } 3128 ms_card->format_status = FORMAT_FAIL; 3129 rtsx_trace(chip); 3130 return STATUS_FAIL; 3131 } 3132 3133 if (short_data_len >= 256) 3134 cnt = 0; 3135 else 3136 cnt = (u8)short_data_len; 3137 3138 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 3139 MS_NO_CHECK_INT); 3140 if (retval != STATUS_SUCCESS) { 3141 ms_card->format_status = FORMAT_FAIL; 3142 rtsx_trace(chip); 3143 return STATUS_FAIL; 3144 } 3145 3146 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 3147 data, 8); 3148 if (retval != STATUS_SUCCESS) { 3149 ms_card->format_status = FORMAT_FAIL; 3150 rtsx_trace(chip); 3151 return STATUS_FAIL; 3152 } 3153 3154 total_progress = (data[0] << 24) | (data[1] << 16) | 3155 (data[2] << 8) | data[3]; 3156 cur_progress = (data[4] << 24) | (data[5] << 16) | 3157 (data[6] << 8) | data[7]; 3158 3159 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 3160 total_progress, cur_progress); 3161 3162 if (total_progress == 0) { 3163 ms_card->progress = 0; 3164 } else { 3165 u64 ulltmp = (u64)cur_progress * (u64)65535; 3166 3167 do_div(ulltmp, total_progress); 3168 ms_card->progress = (u16)ulltmp; 3169 } 3170 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 3171 3172 for (i = 0; i < 5000; i++) { 3173 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3174 if (retval != STATUS_SUCCESS) { 3175 ms_card->format_status = FORMAT_FAIL; 3176 rtsx_trace(chip); 3177 return STATUS_FAIL; 3178 } 3179 if (tmp & (MS_INT_CED | MS_INT_CMDNK | 3180 MS_INT_BREQ | MS_INT_ERR)) 3181 break; 3182 3183 wait_timeout(1); 3184 } 3185 3186 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 3187 if (retval != STATUS_SUCCESS) { 3188 ms_card->format_status = FORMAT_FAIL; 3189 rtsx_trace(chip); 3190 return STATUS_FAIL; 3191 } 3192 3193 if (i == 5000) { 3194 ms_card->format_status = FORMAT_FAIL; 3195 rtsx_trace(chip); 3196 return STATUS_FAIL; 3197 } 3198 3199 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3200 ms_card->format_status = FORMAT_FAIL; 3201 rtsx_trace(chip); 3202 return STATUS_FAIL; 3203 } 3204 3205 if (tmp & MS_INT_CED) { 3206 ms_card->format_status = FORMAT_SUCCESS; 3207 ms_card->pro_under_formatting = 0; 3208 } else if (tmp & MS_INT_BREQ) { 3209 ms_card->format_status = FORMAT_IN_PROGRESS; 3210 } else { 3211 ms_card->format_status = FORMAT_FAIL; 3212 ms_card->pro_under_formatting = 0; 3213 rtsx_trace(chip); 3214 return STATUS_FAIL; 3215 } 3216 3217 return STATUS_SUCCESS; 3218 } 3219 3220 void mspro_polling_format_status(struct rtsx_chip *chip) 3221 { 3222 struct ms_info *ms_card = &chip->ms_card; 3223 int i; 3224 3225 if (ms_card->pro_under_formatting && 3226 (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 3227 rtsx_set_stat(chip, RTSX_STAT_RUN); 3228 3229 for (i = 0; i < 65535; i++) { 3230 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 3231 if (ms_card->format_status != FORMAT_IN_PROGRESS) 3232 break; 3233 } 3234 } 3235 } 3236 3237 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3238 int short_data_len, bool quick_format) 3239 { 3240 struct ms_info *ms_card = &chip->ms_card; 3241 int retval, i; 3242 u8 buf[8], tmp; 3243 u16 para; 3244 3245 retval = ms_switch_clock(chip); 3246 if (retval != STATUS_SUCCESS) { 3247 rtsx_trace(chip); 3248 return STATUS_FAIL; 3249 } 3250 3251 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01); 3252 if (retval != STATUS_SUCCESS) { 3253 rtsx_trace(chip); 3254 return STATUS_FAIL; 3255 } 3256 3257 memset(buf, 0, 2); 3258 switch (short_data_len) { 3259 case 32: 3260 buf[0] = 0; 3261 break; 3262 case 64: 3263 buf[0] = 1; 3264 break; 3265 case 128: 3266 buf[0] = 2; 3267 break; 3268 case 256: 3269 default: 3270 buf[0] = 3; 3271 break; 3272 } 3273 3274 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3275 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 3276 NO_WAIT_INT, buf, 2); 3277 if (retval == STATUS_SUCCESS) 3278 break; 3279 } 3280 if (i == MS_MAX_RETRY_COUNT) { 3281 rtsx_trace(chip); 3282 return STATUS_FAIL; 3283 } 3284 3285 if (quick_format) 3286 para = 0x0000; 3287 else 3288 para = 0x0001; 3289 3290 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 3291 if (retval != STATUS_SUCCESS) { 3292 rtsx_trace(chip); 3293 return STATUS_FAIL; 3294 } 3295 3296 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3297 if (retval) { 3298 rtsx_trace(chip); 3299 return retval; 3300 } 3301 3302 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3303 rtsx_trace(chip); 3304 return STATUS_FAIL; 3305 } 3306 3307 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 3308 ms_card->pro_under_formatting = 1; 3309 ms_card->progress = 0; 3310 ms_card->format_status = FORMAT_IN_PROGRESS; 3311 return STATUS_SUCCESS; 3312 } 3313 3314 if (tmp & MS_INT_CED) { 3315 ms_card->pro_under_formatting = 0; 3316 ms_card->progress = 0; 3317 ms_card->format_status = FORMAT_SUCCESS; 3318 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 3319 return STATUS_SUCCESS; 3320 } 3321 3322 rtsx_trace(chip); 3323 return STATUS_FAIL; 3324 } 3325 3326 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 3327 u16 log_blk, u8 start_page, u8 end_page, 3328 u8 *buf, unsigned int *index, 3329 unsigned int *offset) 3330 { 3331 struct ms_info *ms_card = &chip->ms_card; 3332 int retval, i; 3333 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 3334 u8 *ptr; 3335 3336 retval = ms_read_extra_data(chip, phy_blk, start_page, 3337 extra, MS_EXTRA_SIZE); 3338 if (retval == STATUS_SUCCESS) { 3339 if ((extra[1] & 0x30) != 0x30) { 3340 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3341 rtsx_trace(chip); 3342 return STATUS_FAIL; 3343 } 3344 } 3345 3346 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3347 SystemParm, 6); 3348 if (retval != STATUS_SUCCESS) { 3349 rtsx_trace(chip); 3350 return STATUS_FAIL; 3351 } 3352 3353 if (CHK_MS4BIT(ms_card)) 3354 data[0] = 0x88; 3355 else 3356 data[0] = 0x80; 3357 3358 data[1] = 0; 3359 data[2] = (u8)(phy_blk >> 8); 3360 data[3] = (u8)phy_blk; 3361 data[4] = 0; 3362 data[5] = start_page; 3363 3364 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3365 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 3366 data, 6); 3367 if (retval == STATUS_SUCCESS) 3368 break; 3369 } 3370 if (i == MS_MAX_RETRY_COUNT) { 3371 rtsx_trace(chip); 3372 return STATUS_FAIL; 3373 } 3374 3375 ms_set_err_code(chip, MS_NO_ERROR); 3376 3377 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3378 if (retval != STATUS_SUCCESS) { 3379 rtsx_trace(chip); 3380 return STATUS_FAIL; 3381 } 3382 3383 ptr = buf; 3384 3385 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3386 ms_set_err_code(chip, MS_NO_ERROR); 3387 3388 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3389 ms_set_err_code(chip, MS_NO_CARD); 3390 rtsx_trace(chip); 3391 return STATUS_FAIL; 3392 } 3393 3394 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3395 if (retval != STATUS_SUCCESS) { 3396 rtsx_trace(chip); 3397 return STATUS_FAIL; 3398 } 3399 3400 if (val & INT_REG_CMDNK) { 3401 ms_set_err_code(chip, MS_CMD_NK); 3402 rtsx_trace(chip); 3403 return STATUS_FAIL; 3404 } 3405 if (val & INT_REG_ERR) { 3406 if (val & INT_REG_BREQ) { 3407 retval = ms_read_status_reg(chip); 3408 if (retval != STATUS_SUCCESS) { 3409 if (!(chip->card_wp & MS_CARD)) { 3410 reset_ms(chip); 3411 ms_set_page_status 3412 (log_blk, setPS_NG, 3413 extra, 3414 MS_EXTRA_SIZE); 3415 ms_write_extra_data 3416 (chip, phy_blk, 3417 page_addr, extra, 3418 MS_EXTRA_SIZE); 3419 } 3420 ms_set_err_code(chip, 3421 MS_FLASH_READ_ERROR); 3422 rtsx_trace(chip); 3423 return STATUS_FAIL; 3424 } 3425 } else { 3426 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3427 rtsx_trace(chip); 3428 return STATUS_FAIL; 3429 } 3430 } else { 3431 if (!(val & INT_REG_BREQ)) { 3432 ms_set_err_code(chip, MS_BREQ_ERROR); 3433 rtsx_trace(chip); 3434 return STATUS_FAIL; 3435 } 3436 } 3437 3438 if (page_addr == (end_page - 1)) { 3439 if (!(val & INT_REG_CED)) { 3440 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3441 if (retval != STATUS_SUCCESS) { 3442 rtsx_trace(chip); 3443 return STATUS_FAIL; 3444 } 3445 } 3446 3447 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3448 &val, 1); 3449 if (retval != STATUS_SUCCESS) { 3450 rtsx_trace(chip); 3451 return STATUS_FAIL; 3452 } 3453 3454 if (!(val & INT_REG_CED)) { 3455 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3456 rtsx_trace(chip); 3457 return STATUS_FAIL; 3458 } 3459 3460 trans_cfg = NO_WAIT_INT; 3461 } else { 3462 trans_cfg = WAIT_INT; 3463 } 3464 3465 rtsx_init_cmd(chip); 3466 3467 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3468 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3469 0xFF, trans_cfg); 3470 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3471 0x01, RING_BUFFER); 3472 3473 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3474 3475 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3476 MS_TRANSFER_START | MS_TM_NORMAL_READ); 3477 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3478 MS_TRANSFER_END, MS_TRANSFER_END); 3479 3480 rtsx_send_cmd_no_wait(chip); 3481 3482 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3483 scsi_sg_count(chip->srb), 3484 index, offset, 3485 DMA_FROM_DEVICE, 3486 chip->ms_timeout); 3487 if (retval < 0) { 3488 if (retval == -ETIMEDOUT) { 3489 ms_set_err_code(chip, MS_TO_ERROR); 3490 rtsx_clear_ms_error(chip); 3491 rtsx_trace(chip); 3492 return STATUS_TIMEDOUT; 3493 } 3494 3495 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3496 if (retval != STATUS_SUCCESS) { 3497 ms_set_err_code(chip, MS_TO_ERROR); 3498 rtsx_clear_ms_error(chip); 3499 rtsx_trace(chip); 3500 return STATUS_TIMEDOUT; 3501 } 3502 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3503 ms_set_err_code(chip, MS_CRC16_ERROR); 3504 rtsx_clear_ms_error(chip); 3505 rtsx_trace(chip); 3506 return STATUS_FAIL; 3507 } 3508 } 3509 3510 if (scsi_sg_count(chip->srb) == 0) 3511 ptr += 512; 3512 } 3513 3514 return STATUS_SUCCESS; 3515 } 3516 3517 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3518 u16 new_blk, u16 log_blk, u8 start_page, 3519 u8 end_page, u8 *buf, unsigned int *index, 3520 unsigned int *offset) 3521 { 3522 struct ms_info *ms_card = &chip->ms_card; 3523 int retval, i; 3524 u8 page_addr, val, data[16]; 3525 u8 *ptr; 3526 3527 if (!start_page) { 3528 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3529 SystemParm, 7); 3530 if (retval != STATUS_SUCCESS) { 3531 rtsx_trace(chip); 3532 return STATUS_FAIL; 3533 } 3534 3535 if (CHK_MS4BIT(ms_card)) 3536 data[0] = 0x88; 3537 else 3538 data[0] = 0x80; 3539 3540 data[1] = 0; 3541 data[2] = (u8)(old_blk >> 8); 3542 data[3] = (u8)old_blk; 3543 data[4] = 0x80; 3544 data[5] = 0; 3545 data[6] = 0xEF; 3546 data[7] = 0xFF; 3547 3548 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3549 data, 8); 3550 if (retval != STATUS_SUCCESS) { 3551 rtsx_trace(chip); 3552 return STATUS_FAIL; 3553 } 3554 3555 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3556 if (retval != STATUS_SUCCESS) { 3557 rtsx_trace(chip); 3558 return STATUS_FAIL; 3559 } 3560 3561 ms_set_err_code(chip, MS_NO_ERROR); 3562 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3563 NO_WAIT_INT); 3564 if (retval != STATUS_SUCCESS) { 3565 rtsx_trace(chip); 3566 return STATUS_FAIL; 3567 } 3568 } 3569 3570 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3571 SystemParm, (6 + MS_EXTRA_SIZE)); 3572 if (retval != STATUS_SUCCESS) { 3573 rtsx_trace(chip); 3574 return STATUS_FAIL; 3575 } 3576 3577 ms_set_err_code(chip, MS_NO_ERROR); 3578 3579 if (CHK_MS4BIT(ms_card)) 3580 data[0] = 0x88; 3581 else 3582 data[0] = 0x80; 3583 3584 data[1] = 0; 3585 data[2] = (u8)(new_blk >> 8); 3586 data[3] = (u8)new_blk; 3587 if ((end_page - start_page) == 1) 3588 data[4] = 0x20; 3589 else 3590 data[4] = 0; 3591 3592 data[5] = start_page; 3593 data[6] = 0xF8; 3594 data[7] = 0xFF; 3595 data[8] = (u8)(log_blk >> 8); 3596 data[9] = (u8)log_blk; 3597 3598 for (i = 0x0A; i < 0x10; i++) 3599 data[i] = 0xFF; 3600 3601 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3602 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3603 NO_WAIT_INT, data, 16); 3604 if (retval == STATUS_SUCCESS) 3605 break; 3606 } 3607 if (i == MS_MAX_RETRY_COUNT) { 3608 rtsx_trace(chip); 3609 return STATUS_FAIL; 3610 } 3611 3612 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3613 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3614 if (retval == STATUS_SUCCESS) 3615 break; 3616 } 3617 if (i == MS_MAX_RETRY_COUNT) { 3618 rtsx_trace(chip); 3619 return STATUS_FAIL; 3620 } 3621 3622 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3623 if (retval != STATUS_SUCCESS) { 3624 rtsx_trace(chip); 3625 return STATUS_FAIL; 3626 } 3627 3628 ptr = buf; 3629 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3630 ms_set_err_code(chip, MS_NO_ERROR); 3631 3632 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3633 ms_set_err_code(chip, MS_NO_CARD); 3634 rtsx_trace(chip); 3635 return STATUS_FAIL; 3636 } 3637 3638 if (val & INT_REG_CMDNK) { 3639 ms_set_err_code(chip, MS_CMD_NK); 3640 rtsx_trace(chip); 3641 return STATUS_FAIL; 3642 } 3643 if (val & INT_REG_ERR) { 3644 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3645 rtsx_trace(chip); 3646 return STATUS_FAIL; 3647 } 3648 if (!(val & INT_REG_BREQ)) { 3649 ms_set_err_code(chip, MS_BREQ_ERROR); 3650 rtsx_trace(chip); 3651 return STATUS_FAIL; 3652 } 3653 3654 udelay(30); 3655 3656 rtsx_init_cmd(chip); 3657 3658 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3659 0xFF, WRITE_PAGE_DATA); 3660 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3661 0xFF, WAIT_INT); 3662 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3663 0x01, RING_BUFFER); 3664 3665 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3666 3667 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3668 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3669 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3670 MS_TRANSFER_END, MS_TRANSFER_END); 3671 3672 rtsx_send_cmd_no_wait(chip); 3673 3674 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3675 scsi_sg_count(chip->srb), 3676 index, offset, 3677 DMA_TO_DEVICE, 3678 chip->ms_timeout); 3679 if (retval < 0) { 3680 ms_set_err_code(chip, MS_TO_ERROR); 3681 rtsx_clear_ms_error(chip); 3682 3683 if (retval == -ETIMEDOUT) { 3684 rtsx_trace(chip); 3685 return STATUS_TIMEDOUT; 3686 } 3687 rtsx_trace(chip); 3688 return STATUS_FAIL; 3689 } 3690 3691 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3692 if (retval != STATUS_SUCCESS) { 3693 rtsx_trace(chip); 3694 return STATUS_FAIL; 3695 } 3696 3697 if ((end_page - start_page) == 1) { 3698 if (!(val & INT_REG_CED)) { 3699 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3700 rtsx_trace(chip); 3701 return STATUS_FAIL; 3702 } 3703 } else { 3704 if (page_addr == (end_page - 1)) { 3705 if (!(val & INT_REG_CED)) { 3706 retval = ms_send_cmd(chip, BLOCK_END, 3707 WAIT_INT); 3708 if (retval != STATUS_SUCCESS) { 3709 rtsx_trace(chip); 3710 return STATUS_FAIL; 3711 } 3712 } 3713 3714 retval = ms_read_bytes(chip, GET_INT, 1, 3715 NO_WAIT_INT, &val, 1); 3716 if (retval != STATUS_SUCCESS) { 3717 rtsx_trace(chip); 3718 return STATUS_FAIL; 3719 } 3720 } 3721 3722 if ((page_addr == (end_page - 1)) || 3723 (page_addr == ms_card->page_off)) { 3724 if (!(val & INT_REG_CED)) { 3725 ms_set_err_code(chip, 3726 MS_FLASH_WRITE_ERROR); 3727 rtsx_trace(chip); 3728 return STATUS_FAIL; 3729 } 3730 } 3731 } 3732 3733 if (scsi_sg_count(chip->srb) == 0) 3734 ptr += 512; 3735 } 3736 3737 return STATUS_SUCCESS; 3738 } 3739 3740 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3741 u16 log_blk, u8 page_off) 3742 { 3743 struct ms_info *ms_card = &chip->ms_card; 3744 int retval, seg_no; 3745 3746 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3747 page_off, ms_card->page_off + 1); 3748 if (retval != STATUS_SUCCESS) { 3749 rtsx_trace(chip); 3750 return STATUS_FAIL; 3751 } 3752 3753 seg_no = old_blk >> 9; 3754 3755 if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3756 MS_CLR_BAD_BLOCK_FLG(ms_card); 3757 ms_set_bad_block(chip, old_blk); 3758 } else { 3759 retval = ms_erase_block(chip, old_blk); 3760 if (retval == STATUS_SUCCESS) 3761 ms_set_unused_block(chip, old_blk); 3762 } 3763 3764 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3765 3766 return STATUS_SUCCESS; 3767 } 3768 3769 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3770 u16 log_blk, u8 start_page) 3771 { 3772 int retval; 3773 3774 if (start_page) { 3775 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3776 0, start_page); 3777 if (retval != STATUS_SUCCESS) { 3778 rtsx_trace(chip); 3779 return STATUS_FAIL; 3780 } 3781 } 3782 3783 return STATUS_SUCCESS; 3784 } 3785 3786 #ifdef MS_DELAY_WRITE 3787 int ms_delay_write(struct rtsx_chip *chip) 3788 { 3789 struct ms_info *ms_card = &chip->ms_card; 3790 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3791 int retval; 3792 3793 if (delay_write->delay_write_flag) { 3794 retval = ms_set_init_para(chip); 3795 if (retval != STATUS_SUCCESS) { 3796 rtsx_trace(chip); 3797 return STATUS_FAIL; 3798 } 3799 3800 delay_write->delay_write_flag = 0; 3801 retval = ms_finish_write(chip, 3802 delay_write->old_phyblock, 3803 delay_write->new_phyblock, 3804 delay_write->logblock, 3805 delay_write->pageoff); 3806 if (retval != STATUS_SUCCESS) { 3807 rtsx_trace(chip); 3808 return STATUS_FAIL; 3809 } 3810 } 3811 3812 return STATUS_SUCCESS; 3813 } 3814 #endif 3815 3816 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3817 { 3818 if (srb->sc_data_direction == DMA_FROM_DEVICE) 3819 set_sense_type(chip, SCSI_LUN(srb), 3820 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3821 else 3822 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3823 } 3824 3825 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3826 u32 start_sector, u16 sector_cnt) 3827 { 3828 struct ms_info *ms_card = &chip->ms_card; 3829 unsigned int lun = SCSI_LUN(srb); 3830 int retval, seg_no; 3831 unsigned int index = 0, offset = 0; 3832 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3833 u8 start_page, end_page = 0, page_cnt; 3834 u8 *ptr; 3835 #ifdef MS_DELAY_WRITE 3836 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3837 #endif 3838 3839 ms_set_err_code(chip, MS_NO_ERROR); 3840 3841 ms_card->cleanup_counter = 0; 3842 3843 ptr = (u8 *)scsi_sglist(srb); 3844 3845 retval = ms_switch_clock(chip); 3846 if (retval != STATUS_SUCCESS) { 3847 ms_rw_fail(srb, chip); 3848 rtsx_trace(chip); 3849 return STATUS_FAIL; 3850 } 3851 3852 log_blk = (u16)(start_sector >> ms_card->block_shift); 3853 start_page = (u8)(start_sector & ms_card->page_off); 3854 3855 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3856 if (log_blk < ms_start_idx[seg_no + 1]) 3857 break; 3858 } 3859 3860 if (ms_card->segment[seg_no].build_flag == 0) { 3861 retval = ms_build_l2p_tbl(chip, seg_no); 3862 if (retval != STATUS_SUCCESS) { 3863 chip->card_fail |= MS_CARD; 3864 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3865 rtsx_trace(chip); 3866 return STATUS_FAIL; 3867 } 3868 } 3869 3870 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3871 #ifdef MS_DELAY_WRITE 3872 if (delay_write->delay_write_flag && 3873 (delay_write->logblock == log_blk) && 3874 (start_page > delay_write->pageoff)) { 3875 delay_write->delay_write_flag = 0; 3876 retval = ms_copy_page(chip, 3877 delay_write->old_phyblock, 3878 delay_write->new_phyblock, 3879 log_blk, 3880 delay_write->pageoff, start_page); 3881 if (retval != STATUS_SUCCESS) { 3882 set_sense_type(chip, lun, 3883 SENSE_TYPE_MEDIA_WRITE_ERR); 3884 rtsx_trace(chip); 3885 return STATUS_FAIL; 3886 } 3887 old_blk = delay_write->old_phyblock; 3888 new_blk = delay_write->new_phyblock; 3889 } else if (delay_write->delay_write_flag && 3890 (delay_write->logblock == log_blk) && 3891 (start_page == delay_write->pageoff)) { 3892 delay_write->delay_write_flag = 0; 3893 old_blk = delay_write->old_phyblock; 3894 new_blk = delay_write->new_phyblock; 3895 } else { 3896 retval = ms_delay_write(chip); 3897 if (retval != STATUS_SUCCESS) { 3898 set_sense_type(chip, lun, 3899 SENSE_TYPE_MEDIA_WRITE_ERR); 3900 rtsx_trace(chip); 3901 return STATUS_FAIL; 3902 } 3903 #endif 3904 old_blk = ms_get_l2p_tbl 3905 (chip, seg_no, 3906 log_blk - ms_start_idx[seg_no]); 3907 new_blk = ms_get_unused_block(chip, seg_no); 3908 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) { 3909 set_sense_type(chip, lun, 3910 SENSE_TYPE_MEDIA_WRITE_ERR); 3911 rtsx_trace(chip); 3912 return STATUS_FAIL; 3913 } 3914 3915 retval = ms_prepare_write(chip, old_blk, new_blk, 3916 log_blk, start_page); 3917 if (retval != STATUS_SUCCESS) { 3918 if (detect_card_cd(chip, MS_CARD) != 3919 STATUS_SUCCESS) { 3920 set_sense_type 3921 (chip, lun, 3922 SENSE_TYPE_MEDIA_NOT_PRESENT); 3923 rtsx_trace(chip); 3924 return STATUS_FAIL; 3925 } 3926 set_sense_type(chip, lun, 3927 SENSE_TYPE_MEDIA_WRITE_ERR); 3928 rtsx_trace(chip); 3929 return STATUS_FAIL; 3930 } 3931 #ifdef MS_DELAY_WRITE 3932 } 3933 #endif 3934 } else { 3935 #ifdef MS_DELAY_WRITE 3936 retval = ms_delay_write(chip); 3937 if (retval != STATUS_SUCCESS) { 3938 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3939 set_sense_type(chip, lun, 3940 SENSE_TYPE_MEDIA_NOT_PRESENT); 3941 rtsx_trace(chip); 3942 return STATUS_FAIL; 3943 } 3944 set_sense_type(chip, lun, 3945 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3946 rtsx_trace(chip); 3947 return STATUS_FAIL; 3948 } 3949 #endif 3950 old_blk = ms_get_l2p_tbl(chip, seg_no, 3951 log_blk - ms_start_idx[seg_no]); 3952 if (old_blk == 0xFFFF) { 3953 set_sense_type(chip, lun, 3954 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3955 rtsx_trace(chip); 3956 return STATUS_FAIL; 3957 } 3958 } 3959 3960 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3961 seg_no, old_blk, new_blk); 3962 3963 while (total_sec_cnt) { 3964 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3965 end_page = ms_card->page_off + 1; 3966 else 3967 end_page = start_page + (u8)total_sec_cnt; 3968 3969 page_cnt = end_page - start_page; 3970 3971 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3972 start_page, end_page, page_cnt); 3973 3974 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3975 retval = ms_read_multiple_pages(chip, 3976 old_blk, log_blk, 3977 start_page, end_page, 3978 ptr, &index, &offset); 3979 } else { 3980 retval = ms_write_multiple_pages(chip, old_blk, new_blk, 3981 log_blk, start_page, 3982 end_page, ptr, &index, 3983 &offset); 3984 } 3985 3986 if (retval != STATUS_SUCCESS) { 3987 toggle_gpio(chip, 1); 3988 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3989 set_sense_type(chip, lun, 3990 SENSE_TYPE_MEDIA_NOT_PRESENT); 3991 rtsx_trace(chip); 3992 return STATUS_FAIL; 3993 } 3994 ms_rw_fail(srb, chip); 3995 rtsx_trace(chip); 3996 return STATUS_FAIL; 3997 } 3998 3999 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4000 if (end_page == (ms_card->page_off + 1)) { 4001 retval = ms_erase_block(chip, old_blk); 4002 if (retval == STATUS_SUCCESS) 4003 ms_set_unused_block(chip, old_blk); 4004 4005 ms_set_l2p_tbl(chip, seg_no, 4006 log_blk - ms_start_idx[seg_no], 4007 new_blk); 4008 } 4009 } 4010 4011 total_sec_cnt -= page_cnt; 4012 if (scsi_sg_count(srb) == 0) 4013 ptr += page_cnt * 512; 4014 4015 if (total_sec_cnt == 0) 4016 break; 4017 4018 log_blk++; 4019 4020 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 4021 seg_no++) { 4022 if (log_blk < ms_start_idx[seg_no + 1]) 4023 break; 4024 } 4025 4026 if (ms_card->segment[seg_no].build_flag == 0) { 4027 retval = ms_build_l2p_tbl(chip, seg_no); 4028 if (retval != STATUS_SUCCESS) { 4029 chip->card_fail |= MS_CARD; 4030 set_sense_type(chip, lun, 4031 SENSE_TYPE_MEDIA_NOT_PRESENT); 4032 rtsx_trace(chip); 4033 return STATUS_FAIL; 4034 } 4035 } 4036 4037 old_blk = ms_get_l2p_tbl(chip, seg_no, 4038 log_blk - ms_start_idx[seg_no]); 4039 if (old_blk == 0xFFFF) { 4040 ms_rw_fail(srb, chip); 4041 rtsx_trace(chip); 4042 return STATUS_FAIL; 4043 } 4044 4045 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4046 new_blk = ms_get_unused_block(chip, seg_no); 4047 if (new_blk == 0xFFFF) { 4048 ms_rw_fail(srb, chip); 4049 rtsx_trace(chip); 4050 return STATUS_FAIL; 4051 } 4052 } 4053 4054 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 4055 seg_no, old_blk, new_blk); 4056 4057 start_page = 0; 4058 } 4059 4060 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4061 if (end_page < (ms_card->page_off + 1)) { 4062 #ifdef MS_DELAY_WRITE 4063 delay_write->delay_write_flag = 1; 4064 delay_write->old_phyblock = old_blk; 4065 delay_write->new_phyblock = new_blk; 4066 delay_write->logblock = log_blk; 4067 delay_write->pageoff = end_page; 4068 #else 4069 retval = ms_finish_write(chip, old_blk, new_blk, 4070 log_blk, end_page); 4071 if (retval != STATUS_SUCCESS) { 4072 if (detect_card_cd(chip, MS_CARD) != 4073 STATUS_SUCCESS) { 4074 set_sense_type 4075 (chip, lun, 4076 SENSE_TYPE_MEDIA_NOT_PRESENT); 4077 rtsx_trace(chip); 4078 return STATUS_FAIL; 4079 } 4080 4081 ms_rw_fail(srb, chip); 4082 rtsx_trace(chip); 4083 return STATUS_FAIL; 4084 } 4085 #endif 4086 } 4087 } 4088 4089 scsi_set_resid(srb, 0); 4090 4091 return STATUS_SUCCESS; 4092 } 4093 4094 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 4095 u32 start_sector, u16 sector_cnt) 4096 { 4097 struct ms_info *ms_card = &chip->ms_card; 4098 int retval; 4099 4100 if (CHK_MSPRO(ms_card)) 4101 retval = mspro_rw_multi_sector(srb, chip, start_sector, 4102 sector_cnt); 4103 else 4104 retval = ms_rw_multi_sector(srb, chip, start_sector, 4105 sector_cnt); 4106 4107 return retval; 4108 } 4109 4110 void ms_free_l2p_tbl(struct rtsx_chip *chip) 4111 { 4112 struct ms_info *ms_card = &chip->ms_card; 4113 int i = 0; 4114 4115 if (ms_card->segment) { 4116 for (i = 0; i < ms_card->segment_cnt; i++) { 4117 vfree(ms_card->segment[i].l2p_table); 4118 ms_card->segment[i].l2p_table = NULL; 4119 vfree(ms_card->segment[i].free_table); 4120 ms_card->segment[i].free_table = NULL; 4121 } 4122 vfree(ms_card->segment); 4123 ms_card->segment = NULL; 4124 } 4125 } 4126 4127 #ifdef SUPPORT_MAGIC_GATE 4128 4129 #ifdef READ_BYTES_WAIT_INT 4130 static int ms_poll_int(struct rtsx_chip *chip) 4131 { 4132 int retval; 4133 u8 val; 4134 4135 rtsx_init_cmd(chip); 4136 4137 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 4138 4139 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 4140 if (retval != STATUS_SUCCESS) { 4141 rtsx_trace(chip); 4142 return STATUS_FAIL; 4143 } 4144 4145 val = *rtsx_get_cmd_data(chip); 4146 if (val & MS_INT_ERR) { 4147 rtsx_trace(chip); 4148 return STATUS_FAIL; 4149 } 4150 4151 return STATUS_SUCCESS; 4152 } 4153 #endif 4154 4155 #ifdef MS_SAMPLE_INT_ERR 4156 static int check_ms_err(struct rtsx_chip *chip) 4157 { 4158 int retval; 4159 u8 val; 4160 4161 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4162 if (retval != STATUS_SUCCESS) 4163 return 1; 4164 if (val & MS_TRANSFER_ERR) 4165 return 1; 4166 4167 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 4168 if (retval != STATUS_SUCCESS) 4169 return 1; 4170 4171 if (val & (MS_INT_ERR | MS_INT_CMDNK)) 4172 return 1; 4173 4174 return 0; 4175 } 4176 #else 4177 static int check_ms_err(struct rtsx_chip *chip) 4178 { 4179 int retval; 4180 u8 val; 4181 4182 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4183 if (retval != STATUS_SUCCESS) 4184 return 1; 4185 if (val & MS_TRANSFER_ERR) 4186 return 1; 4187 4188 return 0; 4189 } 4190 #endif 4191 4192 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 4193 { 4194 int retval, i; 4195 u8 data[8]; 4196 4197 data[0] = cmd; 4198 data[1] = 0; 4199 data[2] = 0; 4200 data[3] = 0; 4201 data[4] = 0; 4202 data[5] = 0; 4203 data[6] = entry_num; 4204 data[7] = 0; 4205 4206 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 4207 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 4208 data, 8); 4209 if (retval == STATUS_SUCCESS) 4210 break; 4211 } 4212 if (i == MS_MAX_RETRY_COUNT) { 4213 rtsx_trace(chip); 4214 return STATUS_FAIL; 4215 } 4216 4217 if (check_ms_err(chip)) { 4218 rtsx_clear_ms_error(chip); 4219 rtsx_trace(chip); 4220 return STATUS_FAIL; 4221 } 4222 4223 return STATUS_SUCCESS; 4224 } 4225 4226 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 4227 u8 mg_entry_num) 4228 { 4229 int retval; 4230 u8 buf[6]; 4231 4232 if (type == 0) 4233 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1); 4234 else 4235 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 4236 4237 if (retval != STATUS_SUCCESS) { 4238 rtsx_trace(chip); 4239 return STATUS_FAIL; 4240 } 4241 4242 buf[0] = 0; 4243 buf[1] = 0; 4244 if (type == 1) { 4245 buf[2] = 0; 4246 buf[3] = 0; 4247 buf[4] = 0; 4248 buf[5] = mg_entry_num; 4249 } 4250 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 4251 NO_WAIT_INT, buf, 6); 4252 if (retval != STATUS_SUCCESS) { 4253 rtsx_trace(chip); 4254 return STATUS_FAIL; 4255 } 4256 4257 return STATUS_SUCCESS; 4258 } 4259 4260 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4261 { 4262 int retval; 4263 int i; 4264 unsigned int lun = SCSI_LUN(srb); 4265 u8 buf1[32], buf2[12]; 4266 4267 if (scsi_bufflen(srb) < 12) { 4268 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4269 rtsx_trace(chip); 4270 return STATUS_FAIL; 4271 } 4272 4273 ms_cleanup_work(chip); 4274 4275 retval = ms_switch_clock(chip); 4276 if (retval != STATUS_SUCCESS) { 4277 rtsx_trace(chip); 4278 return STATUS_FAIL; 4279 } 4280 4281 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 4282 if (retval != STATUS_SUCCESS) { 4283 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4284 rtsx_trace(chip); 4285 return STATUS_FAIL; 4286 } 4287 4288 memset(buf1, 0, 32); 4289 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 4290 for (i = 0; i < 8; i++) 4291 buf1[8 + i] = buf2[4 + i]; 4292 4293 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4294 buf1, 32); 4295 if (retval != STATUS_SUCCESS) { 4296 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4297 rtsx_trace(chip); 4298 return STATUS_FAIL; 4299 } 4300 if (check_ms_err(chip)) { 4301 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4302 rtsx_clear_ms_error(chip); 4303 rtsx_trace(chip); 4304 return STATUS_FAIL; 4305 } 4306 4307 return STATUS_SUCCESS; 4308 } 4309 4310 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4311 { 4312 int retval = STATUS_FAIL; 4313 int bufflen; 4314 unsigned int lun = SCSI_LUN(srb); 4315 u8 *buf = NULL; 4316 4317 ms_cleanup_work(chip); 4318 4319 retval = ms_switch_clock(chip); 4320 if (retval != STATUS_SUCCESS) { 4321 rtsx_trace(chip); 4322 return STATUS_FAIL; 4323 } 4324 4325 buf = kmalloc(1540, GFP_KERNEL); 4326 if (!buf) { 4327 rtsx_trace(chip); 4328 return STATUS_ERROR; 4329 } 4330 4331 buf[0] = 0x04; 4332 buf[1] = 0x1A; 4333 buf[2] = 0x00; 4334 buf[3] = 0x00; 4335 4336 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 4337 if (retval != STATUS_SUCCESS) { 4338 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4339 rtsx_trace(chip); 4340 goto free_buffer; 4341 } 4342 4343 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4344 3, WAIT_INT, 0, 0, buf + 4, 1536); 4345 if (retval != STATUS_SUCCESS) { 4346 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4347 rtsx_clear_ms_error(chip); 4348 rtsx_trace(chip); 4349 goto free_buffer; 4350 } 4351 if (check_ms_err(chip)) { 4352 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4353 rtsx_clear_ms_error(chip); 4354 rtsx_trace(chip); 4355 retval = STATUS_FAIL; 4356 goto free_buffer; 4357 } 4358 4359 bufflen = min_t(int, 1052, scsi_bufflen(srb)); 4360 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4361 4362 free_buffer: 4363 kfree(buf); 4364 return retval; 4365 } 4366 4367 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4368 { 4369 struct ms_info *ms_card = &chip->ms_card; 4370 int retval; 4371 int bufflen; 4372 int i; 4373 unsigned int lun = SCSI_LUN(srb); 4374 u8 buf[32]; 4375 4376 ms_cleanup_work(chip); 4377 4378 retval = ms_switch_clock(chip); 4379 if (retval != STATUS_SUCCESS) { 4380 rtsx_trace(chip); 4381 return STATUS_FAIL; 4382 } 4383 4384 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 4385 if (retval != STATUS_SUCCESS) { 4386 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4387 rtsx_trace(chip); 4388 return STATUS_FAIL; 4389 } 4390 4391 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4392 buf, 32); 4393 if (retval != STATUS_SUCCESS) { 4394 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4395 rtsx_trace(chip); 4396 return STATUS_FAIL; 4397 } 4398 if (check_ms_err(chip)) { 4399 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4400 rtsx_clear_ms_error(chip); 4401 rtsx_trace(chip); 4402 return STATUS_FAIL; 4403 } 4404 4405 memcpy(ms_card->magic_gate_id, buf, 16); 4406 4407 #ifdef READ_BYTES_WAIT_INT 4408 retval = ms_poll_int(chip); 4409 if (retval != STATUS_SUCCESS) { 4410 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4411 rtsx_trace(chip); 4412 return STATUS_FAIL; 4413 } 4414 #endif 4415 4416 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 4417 if (retval != STATUS_SUCCESS) { 4418 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4419 rtsx_trace(chip); 4420 return STATUS_FAIL; 4421 } 4422 4423 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4424 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4425 4426 for (i = 0; i < 8; i++) 4427 buf[i] = buf[4 + i]; 4428 4429 for (i = 0; i < 24; i++) 4430 buf[8 + i] = 0; 4431 4432 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 4433 32, WAIT_INT, buf, 32); 4434 if (retval != STATUS_SUCCESS) { 4435 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4436 rtsx_trace(chip); 4437 return STATUS_FAIL; 4438 } 4439 if (check_ms_err(chip)) { 4440 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4441 rtsx_clear_ms_error(chip); 4442 rtsx_trace(chip); 4443 return STATUS_FAIL; 4444 } 4445 4446 ms_card->mg_auth = 0; 4447 4448 return STATUS_SUCCESS; 4449 } 4450 4451 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4452 { 4453 struct ms_info *ms_card = &chip->ms_card; 4454 int retval; 4455 int bufflen; 4456 unsigned int lun = SCSI_LUN(srb); 4457 u8 buf1[32], buf2[36]; 4458 4459 ms_cleanup_work(chip); 4460 4461 retval = ms_switch_clock(chip); 4462 if (retval != STATUS_SUCCESS) { 4463 rtsx_trace(chip); 4464 return STATUS_FAIL; 4465 } 4466 4467 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 4468 if (retval != STATUS_SUCCESS) { 4469 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4470 rtsx_trace(chip); 4471 return STATUS_FAIL; 4472 } 4473 4474 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4475 buf1, 32); 4476 if (retval != STATUS_SUCCESS) { 4477 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4478 rtsx_trace(chip); 4479 return STATUS_FAIL; 4480 } 4481 if (check_ms_err(chip)) { 4482 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4483 rtsx_clear_ms_error(chip); 4484 rtsx_trace(chip); 4485 return STATUS_FAIL; 4486 } 4487 4488 buf2[0] = 0x00; 4489 buf2[1] = 0x22; 4490 buf2[2] = 0x00; 4491 buf2[3] = 0x00; 4492 4493 memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4494 memcpy(buf2 + 20, buf1, 16); 4495 4496 bufflen = min_t(int, 36, scsi_bufflen(srb)); 4497 rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4498 4499 #ifdef READ_BYTES_WAIT_INT 4500 retval = ms_poll_int(chip); 4501 if (retval != STATUS_SUCCESS) { 4502 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4503 rtsx_trace(chip); 4504 return STATUS_FAIL; 4505 } 4506 #endif 4507 4508 return STATUS_SUCCESS; 4509 } 4510 4511 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4512 { 4513 struct ms_info *ms_card = &chip->ms_card; 4514 int retval; 4515 int i; 4516 int bufflen; 4517 unsigned int lun = SCSI_LUN(srb); 4518 u8 buf[32]; 4519 4520 ms_cleanup_work(chip); 4521 4522 retval = ms_switch_clock(chip); 4523 if (retval != STATUS_SUCCESS) { 4524 rtsx_trace(chip); 4525 return STATUS_FAIL; 4526 } 4527 4528 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4529 if (retval != STATUS_SUCCESS) { 4530 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4531 rtsx_trace(chip); 4532 return STATUS_FAIL; 4533 } 4534 4535 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4536 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4537 4538 for (i = 0; i < 8; i++) 4539 buf[i] = buf[4 + i]; 4540 4541 for (i = 0; i < 24; i++) 4542 buf[8 + i] = 0; 4543 4544 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4545 buf, 32); 4546 if (retval != STATUS_SUCCESS) { 4547 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4548 rtsx_trace(chip); 4549 return STATUS_FAIL; 4550 } 4551 if (check_ms_err(chip)) { 4552 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4553 rtsx_clear_ms_error(chip); 4554 rtsx_trace(chip); 4555 return STATUS_FAIL; 4556 } 4557 4558 ms_card->mg_auth = 1; 4559 4560 return STATUS_SUCCESS; 4561 } 4562 4563 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4564 { 4565 struct ms_info *ms_card = &chip->ms_card; 4566 int retval; 4567 int bufflen; 4568 unsigned int lun = SCSI_LUN(srb); 4569 u8 *buf = NULL; 4570 4571 ms_cleanup_work(chip); 4572 4573 retval = ms_switch_clock(chip); 4574 if (retval != STATUS_SUCCESS) { 4575 rtsx_trace(chip); 4576 return STATUS_FAIL; 4577 } 4578 4579 buf = kmalloc(1028, GFP_KERNEL); 4580 if (!buf) { 4581 rtsx_trace(chip); 4582 return STATUS_ERROR; 4583 } 4584 4585 buf[0] = 0x04; 4586 buf[1] = 0x02; 4587 buf[2] = 0x00; 4588 buf[3] = 0x00; 4589 4590 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4591 if (retval != STATUS_SUCCESS) { 4592 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4593 rtsx_trace(chip); 4594 goto free_buffer; 4595 } 4596 4597 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4598 2, WAIT_INT, 0, 0, buf + 4, 1024); 4599 if (retval != STATUS_SUCCESS) { 4600 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4601 rtsx_clear_ms_error(chip); 4602 rtsx_trace(chip); 4603 goto free_buffer; 4604 } 4605 if (check_ms_err(chip)) { 4606 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4607 rtsx_clear_ms_error(chip); 4608 rtsx_trace(chip); 4609 retval = STATUS_FAIL; 4610 goto free_buffer; 4611 } 4612 4613 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4614 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4615 4616 free_buffer: 4617 kfree(buf); 4618 return retval; 4619 } 4620 4621 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4622 { 4623 struct ms_info *ms_card = &chip->ms_card; 4624 int retval; 4625 int bufflen; 4626 #ifdef MG_SET_ICV_SLOW 4627 int i; 4628 #endif 4629 unsigned int lun = SCSI_LUN(srb); 4630 u8 *buf = NULL; 4631 4632 ms_cleanup_work(chip); 4633 4634 retval = ms_switch_clock(chip); 4635 if (retval != STATUS_SUCCESS) { 4636 rtsx_trace(chip); 4637 return STATUS_FAIL; 4638 } 4639 4640 buf = kmalloc(1028, GFP_KERNEL); 4641 if (!buf) { 4642 rtsx_trace(chip); 4643 return STATUS_ERROR; 4644 } 4645 4646 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4647 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4648 4649 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4650 if (retval != STATUS_SUCCESS) { 4651 if (ms_card->mg_auth == 0) { 4652 if ((buf[5] & 0xC0) != 0) 4653 set_sense_type 4654 (chip, lun, 4655 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4656 else 4657 set_sense_type(chip, lun, 4658 SENSE_TYPE_MG_WRITE_ERR); 4659 } else { 4660 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4661 } 4662 rtsx_trace(chip); 4663 goto SetICVFinish; 4664 } 4665 4666 #ifdef MG_SET_ICV_SLOW 4667 for (i = 0; i < 2; i++) { 4668 udelay(50); 4669 4670 rtsx_init_cmd(chip); 4671 4672 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4673 0xFF, PRO_WRITE_LONG_DATA); 4674 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4675 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4676 0x01, RING_BUFFER); 4677 4678 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4679 4680 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4681 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4682 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4683 MS_TRANSFER_END, MS_TRANSFER_END); 4684 4685 rtsx_send_cmd_no_wait(chip); 4686 4687 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512, 4688 512, 0, DMA_TO_DEVICE, 3000); 4689 if ((retval < 0) || check_ms_err(chip)) { 4690 rtsx_clear_ms_error(chip); 4691 if (ms_card->mg_auth == 0) { 4692 if ((buf[5] & 0xC0) != 0) 4693 set_sense_type 4694 (chip, lun, 4695 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4696 else 4697 set_sense_type(chip, lun, 4698 SENSE_TYPE_MG_WRITE_ERR); 4699 } else { 4700 set_sense_type(chip, lun, 4701 SENSE_TYPE_MG_WRITE_ERR); 4702 } 4703 retval = STATUS_FAIL; 4704 rtsx_trace(chip); 4705 goto SetICVFinish; 4706 } 4707 } 4708 #else 4709 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4710 2, WAIT_INT, 0, 0, buf + 4, 1024); 4711 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) { 4712 rtsx_clear_ms_error(chip); 4713 if (ms_card->mg_auth == 0) { 4714 if ((buf[5] & 0xC0) != 0) 4715 set_sense_type 4716 (chip, lun, 4717 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4718 else 4719 set_sense_type(chip, lun, 4720 SENSE_TYPE_MG_WRITE_ERR); 4721 } else { 4722 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4723 } 4724 rtsx_trace(chip); 4725 goto SetICVFinish; 4726 } 4727 #endif 4728 4729 SetICVFinish: 4730 kfree(buf); 4731 return retval; 4732 } 4733 4734 #endif /* SUPPORT_MAGIC_GATE */ 4735 4736 void ms_cleanup_work(struct rtsx_chip *chip) 4737 { 4738 struct ms_info *ms_card = &chip->ms_card; 4739 4740 if (CHK_MSPRO(ms_card)) { 4741 if (ms_card->seq_mode) { 4742 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4743 mspro_stop_seq_mode(chip); 4744 ms_card->cleanup_counter = 0; 4745 } 4746 if (CHK_MSHG(ms_card)) { 4747 rtsx_write_register(chip, MS_CFG, 4748 MS_2K_SECTOR_MODE, 0x00); 4749 } 4750 } 4751 #ifdef MS_DELAY_WRITE 4752 else if ((!CHK_MSPRO(ms_card)) && 4753 ms_card->delay_write.delay_write_flag) { 4754 dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4755 ms_delay_write(chip); 4756 ms_card->cleanup_counter = 0; 4757 } 4758 #endif 4759 } 4760 4761 int ms_power_off_card3v3(struct rtsx_chip *chip) 4762 { 4763 int retval; 4764 4765 retval = disable_card_clock(chip, MS_CARD); 4766 if (retval != STATUS_SUCCESS) { 4767 rtsx_trace(chip); 4768 return STATUS_FAIL; 4769 } 4770 4771 if (chip->asic_code) { 4772 retval = ms_pull_ctl_disable(chip); 4773 if (retval != STATUS_SUCCESS) { 4774 rtsx_trace(chip); 4775 return STATUS_FAIL; 4776 } 4777 } else { 4778 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4779 FPGA_MS_PULL_CTL_BIT | 0x20, 4780 FPGA_MS_PULL_CTL_BIT); 4781 if (retval) { 4782 rtsx_trace(chip); 4783 return retval; 4784 } 4785 } 4786 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4787 if (retval) { 4788 rtsx_trace(chip); 4789 return retval; 4790 } 4791 if (!chip->ft2_fast_mode) { 4792 retval = card_power_off(chip, MS_CARD); 4793 if (retval != STATUS_SUCCESS) { 4794 rtsx_trace(chip); 4795 return STATUS_FAIL; 4796 } 4797 } 4798 4799 return STATUS_SUCCESS; 4800 } 4801 4802 int release_ms_card(struct rtsx_chip *chip) 4803 { 4804 struct ms_info *ms_card = &chip->ms_card; 4805 int retval; 4806 4807 #ifdef MS_DELAY_WRITE 4808 ms_card->delay_write.delay_write_flag = 0; 4809 #endif 4810 ms_card->pro_under_formatting = 0; 4811 4812 chip->card_ready &= ~MS_CARD; 4813 chip->card_fail &= ~MS_CARD; 4814 chip->card_wp &= ~MS_CARD; 4815 4816 ms_free_l2p_tbl(chip); 4817 4818 memset(ms_card->raw_sys_info, 0, 96); 4819 #ifdef SUPPORT_PCGL_1P18 4820 memset(ms_card->raw_model_name, 0, 48); 4821 #endif 4822 4823 retval = ms_power_off_card3v3(chip); 4824 if (retval != STATUS_SUCCESS) { 4825 rtsx_trace(chip); 4826 return STATUS_FAIL; 4827 } 4828 4829 return STATUS_SUCCESS; 4830 } 4831