1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "ms.h" 30 31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 32 { 33 struct ms_info *ms_card = &(chip->ms_card); 34 35 ms_card->err_code = err_code; 36 } 37 38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct ms_info *ms_card = &(chip->ms_card); 41 42 return (ms_card->err_code == err_code); 43 } 44 45 static int ms_parse_err_code(struct rtsx_chip *chip) 46 { 47 rtsx_trace(chip); 48 return STATUS_FAIL; 49 } 50 51 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 52 u8 tpc, u8 cnt, u8 cfg) 53 { 54 struct ms_info *ms_card = &(chip->ms_card); 55 int retval; 56 u8 *ptr; 57 58 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 59 60 rtsx_init_cmd(chip); 61 62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 65 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 66 0x01, PINGPONG_BUFFER); 67 68 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 69 0xFF, MS_TRANSFER_START | trans_mode); 70 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 71 MS_TRANSFER_END, MS_TRANSFER_END); 72 73 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 74 75 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 76 if (retval < 0) { 77 rtsx_clear_ms_error(chip); 78 ms_set_err_code(chip, MS_TO_ERROR); 79 rtsx_trace(chip); 80 return ms_parse_err_code(chip); 81 } 82 83 ptr = rtsx_get_cmd_data(chip) + 1; 84 85 if (!(tpc & 0x08)) { /* Read Packet */ 86 if (*ptr & MS_CRC16_ERR) { 87 ms_set_err_code(chip, MS_CRC16_ERROR); 88 rtsx_trace(chip); 89 return ms_parse_err_code(chip); 90 } 91 } else { /* Write Packet */ 92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 94 ms_set_err_code(chip, MS_CMD_NK); 95 rtsx_trace(chip); 96 return ms_parse_err_code(chip); 97 } 98 } 99 } 100 101 if (*ptr & MS_RDY_TIMEOUT) { 102 rtsx_clear_ms_error(chip); 103 ms_set_err_code(chip, MS_TO_ERROR); 104 rtsx_trace(chip); 105 return ms_parse_err_code(chip); 106 } 107 108 return STATUS_SUCCESS; 109 } 110 111 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 112 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 113 int use_sg, void *buf, int buf_len) 114 { 115 int retval; 116 u8 val, err_code = 0; 117 enum dma_data_direction dir; 118 119 if (!buf || !buf_len) { 120 rtsx_trace(chip); 121 return STATUS_FAIL; 122 } 123 124 if (trans_mode == MS_TM_AUTO_READ) { 125 dir = DMA_FROM_DEVICE; 126 err_code = MS_FLASH_READ_ERROR; 127 } else if (trans_mode == MS_TM_AUTO_WRITE) { 128 dir = DMA_TO_DEVICE; 129 err_code = MS_FLASH_WRITE_ERROR; 130 } else { 131 rtsx_trace(chip); 132 return STATUS_FAIL; 133 } 134 135 rtsx_init_cmd(chip); 136 137 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 138 rtsx_add_cmd(chip, WRITE_REG_CMD, 139 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 141 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 142 143 if (mode_2k) { 144 rtsx_add_cmd(chip, WRITE_REG_CMD, 145 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 146 } else { 147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 148 } 149 150 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 151 152 rtsx_add_cmd(chip, WRITE_REG_CMD, 153 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 154 rtsx_add_cmd(chip, CHECK_REG_CMD, 155 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 156 157 rtsx_send_cmd_no_wait(chip); 158 159 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 160 use_sg, dir, chip->mspro_timeout); 161 if (retval < 0) { 162 ms_set_err_code(chip, err_code); 163 if (retval == -ETIMEDOUT) 164 retval = STATUS_TIMEDOUT; 165 else 166 retval = STATUS_FAIL; 167 168 rtsx_trace(chip); 169 return retval; 170 } 171 172 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 173 if (retval) { 174 rtsx_trace(chip); 175 return retval; 176 } 177 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 178 rtsx_trace(chip); 179 return STATUS_FAIL; 180 } 181 182 return STATUS_SUCCESS; 183 } 184 185 static int ms_write_bytes(struct rtsx_chip *chip, 186 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 187 { 188 struct ms_info *ms_card = &(chip->ms_card); 189 int retval, i; 190 191 if (!data || (data_len < cnt)) { 192 rtsx_trace(chip); 193 return STATUS_ERROR; 194 } 195 196 rtsx_init_cmd(chip); 197 198 for (i = 0; i < cnt; i++) { 199 rtsx_add_cmd(chip, WRITE_REG_CMD, 200 PPBUF_BASE2 + i, 0xFF, data[i]); 201 } 202 if (cnt % 2) 203 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 204 205 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 206 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 207 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 208 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 209 0x01, PINGPONG_BUFFER); 210 211 rtsx_add_cmd(chip, WRITE_REG_CMD, 212 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 213 rtsx_add_cmd(chip, CHECK_REG_CMD, 214 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 215 216 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 217 if (retval < 0) { 218 u8 val = 0; 219 220 rtsx_read_register(chip, MS_TRANS_CFG, &val); 221 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 222 223 rtsx_clear_ms_error(chip); 224 225 if (!(tpc & 0x08)) { 226 if (val & MS_CRC16_ERR) { 227 ms_set_err_code(chip, MS_CRC16_ERROR); 228 rtsx_trace(chip); 229 return ms_parse_err_code(chip); 230 } 231 } else { 232 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 233 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 234 ms_set_err_code(chip, MS_CMD_NK); 235 rtsx_trace(chip); 236 return ms_parse_err_code(chip); 237 } 238 } 239 } 240 241 if (val & MS_RDY_TIMEOUT) { 242 ms_set_err_code(chip, MS_TO_ERROR); 243 rtsx_trace(chip); 244 return ms_parse_err_code(chip); 245 } 246 247 ms_set_err_code(chip, MS_TO_ERROR); 248 rtsx_trace(chip); 249 return ms_parse_err_code(chip); 250 } 251 252 return STATUS_SUCCESS; 253 } 254 255 static int ms_read_bytes(struct rtsx_chip *chip, 256 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 257 { 258 struct ms_info *ms_card = &(chip->ms_card); 259 int retval, i; 260 u8 *ptr; 261 262 if (!data) { 263 rtsx_trace(chip); 264 return STATUS_ERROR; 265 } 266 267 rtsx_init_cmd(chip); 268 269 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 270 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 271 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 272 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 273 0x01, PINGPONG_BUFFER); 274 275 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 276 MS_TRANSFER_START | MS_TM_READ_BYTES); 277 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 278 MS_TRANSFER_END, MS_TRANSFER_END); 279 280 for (i = 0; i < data_len - 1; i++) 281 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 282 283 if (data_len % 2) 284 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 285 else 286 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 287 0, 0); 288 289 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 290 if (retval < 0) { 291 u8 val = 0; 292 293 rtsx_read_register(chip, MS_TRANS_CFG, &val); 294 rtsx_clear_ms_error(chip); 295 296 if (!(tpc & 0x08)) { 297 if (val & MS_CRC16_ERR) { 298 ms_set_err_code(chip, MS_CRC16_ERROR); 299 rtsx_trace(chip); 300 return ms_parse_err_code(chip); 301 } 302 } else { 303 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 304 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 305 ms_set_err_code(chip, MS_CMD_NK); 306 rtsx_trace(chip); 307 return ms_parse_err_code(chip); 308 } 309 } 310 } 311 312 if (val & MS_RDY_TIMEOUT) { 313 ms_set_err_code(chip, MS_TO_ERROR); 314 rtsx_trace(chip); 315 return ms_parse_err_code(chip); 316 } 317 318 ms_set_err_code(chip, MS_TO_ERROR); 319 rtsx_trace(chip); 320 return ms_parse_err_code(chip); 321 } 322 323 ptr = rtsx_get_cmd_data(chip) + 1; 324 325 for (i = 0; i < data_len; i++) 326 data[i] = ptr[i]; 327 328 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) { 329 dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 330 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 331 cnt); 332 } 333 334 return STATUS_SUCCESS; 335 } 336 337 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, 338 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt) 339 { 340 int retval, i; 341 u8 data[4]; 342 343 data[0] = read_start; 344 data[1] = read_cnt; 345 data[2] = write_start; 346 data[3] = write_cnt; 347 348 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 349 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 350 NO_WAIT_INT, data, 4); 351 if (retval == STATUS_SUCCESS) 352 return STATUS_SUCCESS; 353 rtsx_clear_ms_error(chip); 354 } 355 356 rtsx_trace(chip); 357 return STATUS_FAIL; 358 } 359 360 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 361 { 362 u8 data[2]; 363 364 data[0] = cmd; 365 data[1] = 0; 366 367 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 368 } 369 370 static int ms_set_init_para(struct rtsx_chip *chip) 371 { 372 struct ms_info *ms_card = &(chip->ms_card); 373 int retval; 374 375 if (CHK_HG8BIT(ms_card)) { 376 if (chip->asic_code) 377 ms_card->ms_clock = chip->asic_ms_hg_clk; 378 else 379 ms_card->ms_clock = chip->fpga_ms_hg_clk; 380 381 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 382 if (chip->asic_code) 383 ms_card->ms_clock = chip->asic_ms_4bit_clk; 384 else 385 ms_card->ms_clock = chip->fpga_ms_4bit_clk; 386 387 } else { 388 if (chip->asic_code) 389 ms_card->ms_clock = chip->asic_ms_1bit_clk; 390 else 391 ms_card->ms_clock = chip->fpga_ms_1bit_clk; 392 } 393 394 retval = switch_clock(chip, ms_card->ms_clock); 395 if (retval != STATUS_SUCCESS) { 396 rtsx_trace(chip); 397 return STATUS_FAIL; 398 } 399 400 retval = select_card(chip, MS_CARD); 401 if (retval != STATUS_SUCCESS) { 402 rtsx_trace(chip); 403 return STATUS_FAIL; 404 } 405 406 return STATUS_SUCCESS; 407 } 408 409 static int ms_switch_clock(struct rtsx_chip *chip) 410 { 411 struct ms_info *ms_card = &(chip->ms_card); 412 int retval; 413 414 retval = select_card(chip, MS_CARD); 415 if (retval != STATUS_SUCCESS) { 416 rtsx_trace(chip); 417 return STATUS_FAIL; 418 } 419 420 retval = switch_clock(chip, ms_card->ms_clock); 421 if (retval != STATUS_SUCCESS) { 422 rtsx_trace(chip); 423 return STATUS_FAIL; 424 } 425 426 return STATUS_SUCCESS; 427 } 428 429 static int ms_pull_ctl_disable(struct rtsx_chip *chip) 430 { 431 int retval; 432 433 if (CHECK_PID(chip, 0x5208)) { 434 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 435 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD); 436 if (retval) { 437 rtsx_trace(chip); 438 return retval; 439 } 440 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 441 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD); 442 if (retval) { 443 rtsx_trace(chip); 444 return retval; 445 } 446 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 447 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 448 if (retval) { 449 rtsx_trace(chip); 450 return retval; 451 } 452 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 453 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 454 if (retval) { 455 rtsx_trace(chip); 456 return retval; 457 } 458 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 459 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 460 if (retval) { 461 rtsx_trace(chip); 462 return retval; 463 } 464 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 465 MS_D5_PD | MS_D4_PD); 466 if (retval) { 467 rtsx_trace(chip); 468 return retval; 469 } 470 } else if (CHECK_PID(chip, 0x5288)) { 471 if (CHECK_BARO_PKG(chip, QFN)) { 472 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 473 0xFF, 0x55); 474 if (retval) { 475 rtsx_trace(chip); 476 return retval; 477 } 478 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 479 0xFF, 0x55); 480 if (retval) { 481 rtsx_trace(chip); 482 return retval; 483 } 484 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 485 0xFF, 0x4B); 486 if (retval) { 487 rtsx_trace(chip); 488 return retval; 489 } 490 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 491 0xFF, 0x69); 492 if (retval) { 493 rtsx_trace(chip); 494 return retval; 495 } 496 } 497 } 498 499 return STATUS_SUCCESS; 500 } 501 502 static int ms_pull_ctl_enable(struct rtsx_chip *chip) 503 { 504 int retval; 505 506 rtsx_init_cmd(chip); 507 508 if (CHECK_PID(chip, 0x5208)) { 509 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 510 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 511 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 512 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 513 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 514 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 515 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 516 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 517 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 518 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 519 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 520 MS_D5_PD | MS_D4_PD); 521 } else if (CHECK_PID(chip, 0x5288)) { 522 if (CHECK_BARO_PKG(chip, QFN)) { 523 rtsx_add_cmd(chip, WRITE_REG_CMD, 524 CARD_PULL_CTL1, 0xFF, 0x55); 525 rtsx_add_cmd(chip, WRITE_REG_CMD, 526 CARD_PULL_CTL2, 0xFF, 0x45); 527 rtsx_add_cmd(chip, WRITE_REG_CMD, 528 CARD_PULL_CTL3, 0xFF, 0x4B); 529 rtsx_add_cmd(chip, WRITE_REG_CMD, 530 CARD_PULL_CTL4, 0xFF, 0x29); 531 } 532 } 533 534 retval = rtsx_send_cmd(chip, MS_CARD, 100); 535 if (retval < 0) { 536 rtsx_trace(chip); 537 return STATUS_FAIL; 538 } 539 540 return STATUS_SUCCESS; 541 } 542 543 static int ms_prepare_reset(struct rtsx_chip *chip) 544 { 545 struct ms_info *ms_card = &(chip->ms_card); 546 int retval; 547 u8 oc_mask = 0; 548 549 ms_card->ms_type = 0; 550 ms_card->check_ms_flow = 0; 551 ms_card->switch_8bit_fail = 0; 552 ms_card->delay_write.delay_write_flag = 0; 553 554 ms_card->pro_under_formatting = 0; 555 556 retval = ms_power_off_card3v3(chip); 557 if (retval != STATUS_SUCCESS) { 558 rtsx_trace(chip); 559 return STATUS_FAIL; 560 } 561 562 if (!chip->ft2_fast_mode) 563 wait_timeout(250); 564 565 retval = enable_card_clock(chip, MS_CARD); 566 if (retval != STATUS_SUCCESS) { 567 rtsx_trace(chip); 568 return STATUS_FAIL; 569 } 570 571 if (chip->asic_code) { 572 retval = ms_pull_ctl_enable(chip); 573 if (retval != STATUS_SUCCESS) { 574 rtsx_trace(chip); 575 return STATUS_FAIL; 576 } 577 } else { 578 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 579 FPGA_MS_PULL_CTL_BIT | 0x20, 0); 580 if (retval) { 581 rtsx_trace(chip); 582 return retval; 583 } 584 } 585 586 if (!chip->ft2_fast_mode) { 587 retval = card_power_on(chip, MS_CARD); 588 if (retval != STATUS_SUCCESS) { 589 rtsx_trace(chip); 590 return STATUS_FAIL; 591 } 592 593 wait_timeout(150); 594 595 #ifdef SUPPORT_OCP 596 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 597 oc_mask = MS_OC_NOW | MS_OC_EVER; 598 else 599 oc_mask = SD_OC_NOW | SD_OC_EVER; 600 601 if (chip->ocp_stat & oc_mask) { 602 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 603 chip->ocp_stat); 604 rtsx_trace(chip); 605 return STATUS_FAIL; 606 } 607 #endif 608 } 609 610 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 611 MS_OUTPUT_EN); 612 if (retval) { 613 rtsx_trace(chip); 614 return retval; 615 } 616 617 if (chip->asic_code) { 618 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 619 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 620 if (retval) { 621 rtsx_trace(chip); 622 return retval; 623 } 624 } else { 625 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 626 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT | NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1); 627 if (retval) { 628 rtsx_trace(chip); 629 return retval; 630 } 631 } 632 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 633 NO_WAIT_INT | NO_AUTO_READ_INT_REG); 634 if (retval) { 635 rtsx_trace(chip); 636 return retval; 637 } 638 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 639 MS_STOP | MS_CLR_ERR); 640 if (retval) { 641 rtsx_trace(chip); 642 return retval; 643 } 644 645 retval = ms_set_init_para(chip); 646 if (retval != STATUS_SUCCESS) { 647 rtsx_trace(chip); 648 return STATUS_FAIL; 649 } 650 651 return STATUS_SUCCESS; 652 } 653 654 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 655 { 656 struct ms_info *ms_card = &(chip->ms_card); 657 int retval, i; 658 u8 val; 659 660 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1); 661 if (retval != STATUS_SUCCESS) { 662 rtsx_trace(chip); 663 return STATUS_FAIL; 664 } 665 666 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 667 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 668 6, NO_WAIT_INT); 669 if (retval == STATUS_SUCCESS) 670 break; 671 } 672 if (i == MS_MAX_RETRY_COUNT) { 673 rtsx_trace(chip); 674 return STATUS_FAIL; 675 } 676 677 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 678 if (retval) { 679 rtsx_trace(chip); 680 return retval; 681 } 682 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 683 if (val != 0x01) { 684 if (val != 0x02) 685 ms_card->check_ms_flow = 1; 686 687 rtsx_trace(chip); 688 return STATUS_FAIL; 689 } 690 691 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 692 if (retval) { 693 rtsx_trace(chip); 694 return retval; 695 } 696 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 697 if (val != 0) { 698 ms_card->check_ms_flow = 1; 699 rtsx_trace(chip); 700 return STATUS_FAIL; 701 } 702 703 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 704 if (retval) { 705 rtsx_trace(chip); 706 return retval; 707 } 708 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 709 if (val == 0) { 710 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 711 if (retval) { 712 rtsx_trace(chip); 713 return retval; 714 } 715 if (val & WRT_PRTCT) 716 chip->card_wp |= MS_CARD; 717 else 718 chip->card_wp &= ~MS_CARD; 719 720 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 721 chip->card_wp |= MS_CARD; 722 } else { 723 ms_card->check_ms_flow = 1; 724 rtsx_trace(chip); 725 return STATUS_FAIL; 726 } 727 728 ms_card->ms_type |= TYPE_MSPRO; 729 730 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 731 if (retval) { 732 rtsx_trace(chip); 733 return retval; 734 } 735 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 736 if (val == 0) { 737 ms_card->ms_type &= 0x0F; 738 } else if (val == 7) { 739 if (switch_8bit_bus) 740 ms_card->ms_type |= MS_HG; 741 else 742 ms_card->ms_type &= 0x0F; 743 744 } else { 745 rtsx_trace(chip); 746 return STATUS_FAIL; 747 } 748 749 return STATUS_SUCCESS; 750 } 751 752 static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 753 { 754 int retval, i, k; 755 u8 val; 756 757 /* Confirm CPU StartUp */ 758 k = 0; 759 do { 760 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 761 ms_set_err_code(chip, MS_NO_CARD); 762 rtsx_trace(chip); 763 return STATUS_FAIL; 764 } 765 766 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 767 retval = ms_read_bytes(chip, GET_INT, 1, 768 NO_WAIT_INT, &val, 1); 769 if (retval == STATUS_SUCCESS) 770 break; 771 } 772 if (i == MS_MAX_RETRY_COUNT) { 773 rtsx_trace(chip); 774 return STATUS_FAIL; 775 } 776 777 if (k > 100) { 778 rtsx_trace(chip); 779 return STATUS_FAIL; 780 } 781 782 k++; 783 wait_timeout(100); 784 } while (!(val & INT_REG_CED)); 785 786 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 787 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 788 if (retval == STATUS_SUCCESS) 789 break; 790 } 791 if (i == MS_MAX_RETRY_COUNT) { 792 rtsx_trace(chip); 793 return STATUS_FAIL; 794 } 795 796 if (val & INT_REG_ERR) { 797 if (val & INT_REG_CMDNK) 798 chip->card_wp |= (MS_CARD); 799 else { 800 rtsx_trace(chip); 801 return STATUS_FAIL; 802 } 803 } 804 /* -- end confirm CPU startup */ 805 806 return STATUS_SUCCESS; 807 } 808 809 static int ms_switch_parallel_bus(struct rtsx_chip *chip) 810 { 811 int retval, i; 812 u8 data[2]; 813 814 data[0] = PARALLEL_4BIT_IF; 815 data[1] = 0; 816 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 817 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 818 data, 2); 819 if (retval == STATUS_SUCCESS) 820 break; 821 } 822 if (retval != STATUS_SUCCESS) { 823 rtsx_trace(chip); 824 return STATUS_FAIL; 825 } 826 827 return STATUS_SUCCESS; 828 } 829 830 static int ms_switch_8bit_bus(struct rtsx_chip *chip) 831 { 832 struct ms_info *ms_card = &(chip->ms_card); 833 int retval, i; 834 u8 data[2]; 835 836 data[0] = PARALLEL_8BIT_IF; 837 data[1] = 0; 838 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 839 retval = ms_write_bytes(chip, WRITE_REG, 1, 840 NO_WAIT_INT, data, 2); 841 if (retval == STATUS_SUCCESS) 842 break; 843 } 844 if (retval != STATUS_SUCCESS) { 845 rtsx_trace(chip); 846 return STATUS_FAIL; 847 } 848 849 retval = rtsx_write_register(chip, MS_CFG, 0x98, 850 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 851 if (retval) { 852 rtsx_trace(chip); 853 return retval; 854 } 855 ms_card->ms_type |= MS_8BIT; 856 retval = ms_set_init_para(chip); 857 if (retval != STATUS_SUCCESS) { 858 rtsx_trace(chip); 859 return STATUS_FAIL; 860 } 861 862 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 863 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 864 1, NO_WAIT_INT); 865 if (retval != STATUS_SUCCESS) { 866 rtsx_trace(chip); 867 return STATUS_FAIL; 868 } 869 } 870 871 return STATUS_SUCCESS; 872 } 873 874 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 875 { 876 struct ms_info *ms_card = &(chip->ms_card); 877 int retval, i; 878 879 for (i = 0; i < 3; i++) { 880 retval = ms_prepare_reset(chip); 881 if (retval != STATUS_SUCCESS) { 882 rtsx_trace(chip); 883 return STATUS_FAIL; 884 } 885 886 retval = ms_identify_media_type(chip, switch_8bit_bus); 887 if (retval != STATUS_SUCCESS) { 888 rtsx_trace(chip); 889 return STATUS_FAIL; 890 } 891 892 retval = ms_confirm_cpu_startup(chip); 893 if (retval != STATUS_SUCCESS) { 894 rtsx_trace(chip); 895 return STATUS_FAIL; 896 } 897 898 retval = ms_switch_parallel_bus(chip); 899 if (retval != STATUS_SUCCESS) { 900 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 901 ms_set_err_code(chip, MS_NO_CARD); 902 rtsx_trace(chip); 903 return STATUS_FAIL; 904 } 905 continue; 906 } else { 907 break; 908 } 909 } 910 911 if (retval != STATUS_SUCCESS) { 912 rtsx_trace(chip); 913 return STATUS_FAIL; 914 } 915 916 /* Switch MS-PRO into Parallel mode */ 917 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 918 if (retval) { 919 rtsx_trace(chip); 920 return retval; 921 } 922 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 923 PUSH_TIME_ODD); 924 if (retval) { 925 rtsx_trace(chip); 926 return retval; 927 } 928 929 retval = ms_set_init_para(chip); 930 if (retval != STATUS_SUCCESS) { 931 rtsx_trace(chip); 932 return STATUS_FAIL; 933 } 934 935 /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 936 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 937 retval = ms_switch_8bit_bus(chip); 938 if (retval != STATUS_SUCCESS) { 939 ms_card->switch_8bit_fail = 1; 940 rtsx_trace(chip); 941 return STATUS_FAIL; 942 } 943 } 944 945 return STATUS_SUCCESS; 946 } 947 948 #ifdef XC_POWERCLASS 949 static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 950 { 951 int retval; 952 u8 buf[6]; 953 954 ms_cleanup_work(chip); 955 956 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 957 if (retval != STATUS_SUCCESS) { 958 rtsx_trace(chip); 959 return STATUS_FAIL; 960 } 961 962 buf[0] = 0; 963 buf[1] = mode; 964 buf[2] = 0; 965 buf[3] = 0; 966 buf[4] = 0; 967 buf[5] = 0; 968 969 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 970 if (retval != STATUS_SUCCESS) { 971 rtsx_trace(chip); 972 return STATUS_FAIL; 973 } 974 975 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 976 if (retval != STATUS_SUCCESS) { 977 rtsx_trace(chip); 978 return STATUS_FAIL; 979 } 980 981 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 982 if (retval) { 983 rtsx_trace(chip); 984 return retval; 985 } 986 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) { 987 rtsx_trace(chip); 988 return STATUS_FAIL; 989 } 990 991 return STATUS_SUCCESS; 992 } 993 #endif 994 995 static int ms_read_attribute_info(struct rtsx_chip *chip) 996 { 997 struct ms_info *ms_card = &(chip->ms_card); 998 int retval, i; 999 u8 val, *buf, class_code, device_type, sub_class, data[16]; 1000 u16 total_blk = 0, blk_size = 0; 1001 #ifdef SUPPORT_MSXC 1002 u32 xc_total_blk = 0, xc_blk_size = 0; 1003 #endif 1004 u32 sys_info_addr = 0, sys_info_size; 1005 #ifdef SUPPORT_PCGL_1P18 1006 u32 model_name_addr = 0, model_name_size; 1007 int found_sys_info = 0, found_model_name = 0; 1008 #endif 1009 1010 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7); 1011 if (retval != STATUS_SUCCESS) { 1012 rtsx_trace(chip); 1013 return STATUS_FAIL; 1014 } 1015 1016 if (CHK_MS8BIT(ms_card)) 1017 data[0] = PARALLEL_8BIT_IF; 1018 else 1019 data[0] = PARALLEL_4BIT_IF; 1020 1021 data[1] = 0; 1022 1023 data[2] = 0x40; 1024 data[3] = 0; 1025 data[4] = 0; 1026 data[5] = 0; 1027 data[6] = 0; 1028 data[7] = 0; 1029 1030 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1031 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 1032 data, 8); 1033 if (retval == STATUS_SUCCESS) 1034 break; 1035 } 1036 if (retval != STATUS_SUCCESS) { 1037 rtsx_trace(chip); 1038 return STATUS_FAIL; 1039 } 1040 1041 buf = kmalloc(64 * 512, GFP_KERNEL); 1042 if (buf == NULL) { 1043 rtsx_trace(chip); 1044 return STATUS_ERROR; 1045 } 1046 1047 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1048 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 1049 if (retval != STATUS_SUCCESS) 1050 continue; 1051 1052 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1053 if (retval != STATUS_SUCCESS) { 1054 kfree(buf); 1055 rtsx_trace(chip); 1056 return STATUS_FAIL; 1057 } 1058 if (!(val & MS_INT_BREQ)) { 1059 kfree(buf); 1060 rtsx_trace(chip); 1061 return STATUS_FAIL; 1062 } 1063 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 1064 PRO_READ_LONG_DATA, 0x40, WAIT_INT, 1065 0, 0, buf, 64 * 512); 1066 if (retval == STATUS_SUCCESS) 1067 break; 1068 1069 rtsx_clear_ms_error(chip); 1070 } 1071 if (retval != STATUS_SUCCESS) { 1072 kfree(buf); 1073 rtsx_trace(chip); 1074 return STATUS_FAIL; 1075 } 1076 1077 i = 0; 1078 do { 1079 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 1080 if (retval != STATUS_SUCCESS) { 1081 kfree(buf); 1082 rtsx_trace(chip); 1083 return STATUS_FAIL; 1084 } 1085 1086 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 1087 break; 1088 1089 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 1090 PRO_READ_LONG_DATA, 0, WAIT_INT); 1091 if (retval != STATUS_SUCCESS) { 1092 kfree(buf); 1093 rtsx_trace(chip); 1094 return STATUS_FAIL; 1095 } 1096 1097 i++; 1098 } while (i < 1024); 1099 1100 if (retval != STATUS_SUCCESS) { 1101 kfree(buf); 1102 rtsx_trace(chip); 1103 return STATUS_FAIL; 1104 } 1105 1106 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) { 1107 /* Signature code is wrong */ 1108 kfree(buf); 1109 rtsx_trace(chip); 1110 return STATUS_FAIL; 1111 } 1112 1113 if ((buf[4] < 1) || (buf[4] > 12)) { 1114 kfree(buf); 1115 rtsx_trace(chip); 1116 return STATUS_FAIL; 1117 } 1118 1119 for (i = 0; i < buf[4]; i++) { 1120 int cur_addr_off = 16 + i * 12; 1121 1122 #ifdef SUPPORT_MSXC 1123 if ((buf[cur_addr_off + 8] == 0x10) || 1124 (buf[cur_addr_off + 8] == 0x13)) { 1125 #else 1126 if (buf[cur_addr_off + 8] == 0x10) { 1127 #endif 1128 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1129 ((u32)buf[cur_addr_off + 1] << 16) | 1130 ((u32)buf[cur_addr_off + 2] << 8) | 1131 buf[cur_addr_off + 3]; 1132 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 1133 ((u32)buf[cur_addr_off + 5] << 16) | 1134 ((u32)buf[cur_addr_off + 6] << 8) | 1135 buf[cur_addr_off + 7]; 1136 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 1137 sys_info_addr, sys_info_size); 1138 if (sys_info_size != 96) { 1139 kfree(buf); 1140 rtsx_trace(chip); 1141 return STATUS_FAIL; 1142 } 1143 if (sys_info_addr < 0x1A0) { 1144 kfree(buf); 1145 rtsx_trace(chip); 1146 return STATUS_FAIL; 1147 } 1148 if ((sys_info_size + sys_info_addr) > 0x8000) { 1149 kfree(buf); 1150 rtsx_trace(chip); 1151 return STATUS_FAIL; 1152 } 1153 1154 #ifdef SUPPORT_MSXC 1155 if (buf[cur_addr_off + 8] == 0x13) 1156 ms_card->ms_type |= MS_XC; 1157 #endif 1158 #ifdef SUPPORT_PCGL_1P18 1159 found_sys_info = 1; 1160 #else 1161 break; 1162 #endif 1163 } 1164 #ifdef SUPPORT_PCGL_1P18 1165 if (buf[cur_addr_off + 8] == 0x15) { 1166 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1167 ((u32)buf[cur_addr_off + 1] << 16) | 1168 ((u32)buf[cur_addr_off + 2] << 8) | 1169 buf[cur_addr_off + 3]; 1170 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1171 ((u32)buf[cur_addr_off + 5] << 16) | 1172 ((u32)buf[cur_addr_off + 6] << 8) | 1173 buf[cur_addr_off + 7]; 1174 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1175 model_name_addr, model_name_size); 1176 if (model_name_size != 48) { 1177 kfree(buf); 1178 rtsx_trace(chip); 1179 return STATUS_FAIL; 1180 } 1181 if (model_name_addr < 0x1A0) { 1182 kfree(buf); 1183 rtsx_trace(chip); 1184 return STATUS_FAIL; 1185 } 1186 if ((model_name_size + model_name_addr) > 0x8000) { 1187 kfree(buf); 1188 rtsx_trace(chip); 1189 return STATUS_FAIL; 1190 } 1191 1192 found_model_name = 1; 1193 } 1194 1195 if (found_sys_info && found_model_name) 1196 break; 1197 #endif 1198 } 1199 1200 if (i == buf[4]) { 1201 kfree(buf); 1202 rtsx_trace(chip); 1203 return STATUS_FAIL; 1204 } 1205 1206 class_code = buf[sys_info_addr + 0]; 1207 device_type = buf[sys_info_addr + 56]; 1208 sub_class = buf[sys_info_addr + 46]; 1209 #ifdef SUPPORT_MSXC 1210 if (CHK_MSXC(ms_card)) { 1211 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1212 ((u32)buf[sys_info_addr + 7] << 16) | 1213 ((u32)buf[sys_info_addr + 8] << 8) | 1214 buf[sys_info_addr + 9]; 1215 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1216 ((u32)buf[sys_info_addr + 33] << 16) | 1217 ((u32)buf[sys_info_addr + 34] << 8) | 1218 buf[sys_info_addr + 35]; 1219 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1220 xc_total_blk, xc_blk_size); 1221 } else { 1222 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1223 buf[sys_info_addr + 7]; 1224 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1225 buf[sys_info_addr + 3]; 1226 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1227 total_blk, blk_size); 1228 } 1229 #else 1230 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1231 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1232 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1233 total_blk, blk_size); 1234 #endif 1235 1236 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1237 class_code, device_type, sub_class); 1238 1239 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1240 #ifdef SUPPORT_PCGL_1P18 1241 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1242 #endif 1243 1244 kfree(buf); 1245 1246 #ifdef SUPPORT_MSXC 1247 if (CHK_MSXC(ms_card)) { 1248 if (class_code != 0x03) { 1249 rtsx_trace(chip); 1250 return STATUS_FAIL; 1251 } 1252 } else { 1253 if (class_code != 0x02) { 1254 rtsx_trace(chip); 1255 return STATUS_FAIL; 1256 } 1257 } 1258 #else 1259 if (class_code != 0x02) { 1260 rtsx_trace(chip); 1261 return STATUS_FAIL; 1262 } 1263 #endif 1264 1265 if (device_type != 0x00) { 1266 if ((device_type == 0x01) || (device_type == 0x02) || 1267 (device_type == 0x03)) { 1268 chip->card_wp |= MS_CARD; 1269 } else { 1270 rtsx_trace(chip); 1271 return STATUS_FAIL; 1272 } 1273 } 1274 1275 if (sub_class & 0xC0) { 1276 rtsx_trace(chip); 1277 return STATUS_FAIL; 1278 } 1279 1280 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1281 class_code, device_type, sub_class); 1282 1283 #ifdef SUPPORT_MSXC 1284 if (CHK_MSXC(ms_card)) { 1285 chip->capacity[chip->card2lun[MS_CARD]] = 1286 ms_card->capacity = xc_total_blk * xc_blk_size; 1287 } else { 1288 chip->capacity[chip->card2lun[MS_CARD]] = 1289 ms_card->capacity = total_blk * blk_size; 1290 } 1291 #else 1292 ms_card->capacity = total_blk * blk_size; 1293 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1294 #endif 1295 1296 return STATUS_SUCCESS; 1297 } 1298 1299 #ifdef SUPPORT_MAGIC_GATE 1300 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1301 int type, u8 mg_entry_num); 1302 #endif 1303 1304 static int reset_ms_pro(struct rtsx_chip *chip) 1305 { 1306 struct ms_info *ms_card = &(chip->ms_card); 1307 int retval; 1308 #ifdef XC_POWERCLASS 1309 u8 change_power_class; 1310 1311 if (chip->ms_power_class_en & 0x02) 1312 change_power_class = 2; 1313 else if (chip->ms_power_class_en & 0x01) 1314 change_power_class = 1; 1315 else 1316 change_power_class = 0; 1317 #endif 1318 1319 #ifdef XC_POWERCLASS 1320 Retry: 1321 #endif 1322 retval = ms_pro_reset_flow(chip, 1); 1323 if (retval != STATUS_SUCCESS) { 1324 if (ms_card->switch_8bit_fail) { 1325 retval = ms_pro_reset_flow(chip, 0); 1326 if (retval != STATUS_SUCCESS) { 1327 rtsx_trace(chip); 1328 return STATUS_FAIL; 1329 } 1330 } else { 1331 rtsx_trace(chip); 1332 return STATUS_FAIL; 1333 } 1334 } 1335 1336 retval = ms_read_attribute_info(chip); 1337 if (retval != STATUS_SUCCESS) { 1338 rtsx_trace(chip); 1339 return STATUS_FAIL; 1340 } 1341 1342 #ifdef XC_POWERCLASS 1343 if (CHK_HG8BIT(ms_card)) 1344 change_power_class = 0; 1345 1346 if (change_power_class && CHK_MSXC(ms_card)) { 1347 u8 power_class_en = chip->ms_power_class_en; 1348 1349 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1350 power_class_en); 1351 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1352 change_power_class); 1353 1354 if (change_power_class) 1355 power_class_en &= (1 << (change_power_class - 1)); 1356 else 1357 power_class_en = 0; 1358 1359 if (power_class_en) { 1360 u8 power_class_mode = 1361 (ms_card->raw_sys_info[46] & 0x18) >> 3; 1362 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1363 power_class_mode); 1364 if (change_power_class > power_class_mode) 1365 change_power_class = power_class_mode; 1366 if (change_power_class) { 1367 retval = msxc_change_power(chip, 1368 change_power_class); 1369 if (retval != STATUS_SUCCESS) { 1370 change_power_class--; 1371 goto Retry; 1372 } 1373 } 1374 } 1375 } 1376 #endif 1377 1378 #ifdef SUPPORT_MAGIC_GATE 1379 retval = mg_set_tpc_para_sub(chip, 0, 0); 1380 if (retval != STATUS_SUCCESS) { 1381 rtsx_trace(chip); 1382 return STATUS_FAIL; 1383 } 1384 #endif 1385 1386 if (CHK_HG8BIT(ms_card)) 1387 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1388 else 1389 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1390 1391 return STATUS_SUCCESS; 1392 } 1393 1394 static int ms_read_status_reg(struct rtsx_chip *chip) 1395 { 1396 int retval; 1397 u8 val[2]; 1398 1399 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0); 1400 if (retval != STATUS_SUCCESS) { 1401 rtsx_trace(chip); 1402 return STATUS_FAIL; 1403 } 1404 1405 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1406 if (retval != STATUS_SUCCESS) { 1407 rtsx_trace(chip); 1408 return STATUS_FAIL; 1409 } 1410 1411 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1412 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1413 rtsx_trace(chip); 1414 return STATUS_FAIL; 1415 } 1416 1417 return STATUS_SUCCESS; 1418 } 1419 1420 1421 static int ms_read_extra_data(struct rtsx_chip *chip, 1422 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1423 { 1424 struct ms_info *ms_card = &(chip->ms_card); 1425 int retval, i; 1426 u8 val, data[10]; 1427 1428 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1429 SystemParm, 6); 1430 if (retval != STATUS_SUCCESS) { 1431 rtsx_trace(chip); 1432 return STATUS_FAIL; 1433 } 1434 1435 if (CHK_MS4BIT(ms_card)) { 1436 /* Parallel interface */ 1437 data[0] = 0x88; 1438 } else { 1439 /* Serial interface */ 1440 data[0] = 0x80; 1441 } 1442 data[1] = 0; 1443 data[2] = (u8)(block_addr >> 8); 1444 data[3] = (u8)block_addr; 1445 data[4] = 0x40; 1446 data[5] = page_num; 1447 1448 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1449 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1450 data, 6); 1451 if (retval == STATUS_SUCCESS) 1452 break; 1453 } 1454 if (i == MS_MAX_RETRY_COUNT) { 1455 rtsx_trace(chip); 1456 return STATUS_FAIL; 1457 } 1458 1459 ms_set_err_code(chip, MS_NO_ERROR); 1460 1461 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1462 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1463 if (retval == STATUS_SUCCESS) 1464 break; 1465 } 1466 if (i == MS_MAX_RETRY_COUNT) { 1467 rtsx_trace(chip); 1468 return STATUS_FAIL; 1469 } 1470 1471 ms_set_err_code(chip, MS_NO_ERROR); 1472 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1473 if (retval != STATUS_SUCCESS) { 1474 rtsx_trace(chip); 1475 return STATUS_FAIL; 1476 } 1477 1478 if (val & INT_REG_CMDNK) { 1479 ms_set_err_code(chip, MS_CMD_NK); 1480 rtsx_trace(chip); 1481 return STATUS_FAIL; 1482 } 1483 if (val & INT_REG_CED) { 1484 if (val & INT_REG_ERR) { 1485 retval = ms_read_status_reg(chip); 1486 if (retval != STATUS_SUCCESS) { 1487 rtsx_trace(chip); 1488 return STATUS_FAIL; 1489 } 1490 1491 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1492 MS_EXTRA_SIZE, SystemParm, 6); 1493 if (retval != STATUS_SUCCESS) { 1494 rtsx_trace(chip); 1495 return STATUS_FAIL; 1496 } 1497 } 1498 } 1499 1500 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1501 data, MS_EXTRA_SIZE); 1502 if (retval != STATUS_SUCCESS) { 1503 rtsx_trace(chip); 1504 return STATUS_FAIL; 1505 } 1506 1507 if (buf && buf_len) { 1508 if (buf_len > MS_EXTRA_SIZE) 1509 buf_len = MS_EXTRA_SIZE; 1510 memcpy(buf, data, buf_len); 1511 } 1512 1513 return STATUS_SUCCESS; 1514 } 1515 1516 static int ms_write_extra_data(struct rtsx_chip *chip, 1517 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1518 { 1519 struct ms_info *ms_card = &(chip->ms_card); 1520 int retval, i; 1521 u8 val, data[16]; 1522 1523 if (!buf || (buf_len < MS_EXTRA_SIZE)) { 1524 rtsx_trace(chip); 1525 return STATUS_FAIL; 1526 } 1527 1528 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1529 SystemParm, 6 + MS_EXTRA_SIZE); 1530 if (retval != STATUS_SUCCESS) { 1531 rtsx_trace(chip); 1532 return STATUS_FAIL; 1533 } 1534 1535 if (CHK_MS4BIT(ms_card)) 1536 data[0] = 0x88; 1537 else 1538 data[0] = 0x80; 1539 1540 data[1] = 0; 1541 data[2] = (u8)(block_addr >> 8); 1542 data[3] = (u8)block_addr; 1543 data[4] = 0x40; 1544 data[5] = page_num; 1545 1546 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1547 data[i] = buf[i - 6]; 1548 1549 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1550 NO_WAIT_INT, data, 16); 1551 if (retval != STATUS_SUCCESS) { 1552 rtsx_trace(chip); 1553 return STATUS_FAIL; 1554 } 1555 1556 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1557 if (retval != STATUS_SUCCESS) { 1558 rtsx_trace(chip); 1559 return STATUS_FAIL; 1560 } 1561 1562 ms_set_err_code(chip, MS_NO_ERROR); 1563 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1564 if (retval != STATUS_SUCCESS) { 1565 rtsx_trace(chip); 1566 return STATUS_FAIL; 1567 } 1568 1569 if (val & INT_REG_CMDNK) { 1570 ms_set_err_code(chip, MS_CMD_NK); 1571 rtsx_trace(chip); 1572 return STATUS_FAIL; 1573 } 1574 if (val & INT_REG_CED) { 1575 if (val & INT_REG_ERR) { 1576 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1577 rtsx_trace(chip); 1578 return STATUS_FAIL; 1579 } 1580 } 1581 1582 return STATUS_SUCCESS; 1583 } 1584 1585 1586 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1587 { 1588 struct ms_info *ms_card = &(chip->ms_card); 1589 int retval; 1590 u8 val, data[6]; 1591 1592 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1593 SystemParm, 6); 1594 if (retval != STATUS_SUCCESS) { 1595 rtsx_trace(chip); 1596 return STATUS_FAIL; 1597 } 1598 1599 if (CHK_MS4BIT(ms_card)) 1600 data[0] = 0x88; 1601 else 1602 data[0] = 0x80; 1603 1604 data[1] = 0; 1605 data[2] = (u8)(block_addr >> 8); 1606 data[3] = (u8)block_addr; 1607 data[4] = 0x20; 1608 data[5] = page_num; 1609 1610 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1611 if (retval != STATUS_SUCCESS) { 1612 rtsx_trace(chip); 1613 return STATUS_FAIL; 1614 } 1615 1616 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1617 if (retval != STATUS_SUCCESS) { 1618 rtsx_trace(chip); 1619 return STATUS_FAIL; 1620 } 1621 1622 ms_set_err_code(chip, MS_NO_ERROR); 1623 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1624 if (retval != STATUS_SUCCESS) { 1625 rtsx_trace(chip); 1626 return STATUS_FAIL; 1627 } 1628 1629 if (val & INT_REG_CMDNK) { 1630 ms_set_err_code(chip, MS_CMD_NK); 1631 rtsx_trace(chip); 1632 return STATUS_FAIL; 1633 } 1634 1635 if (val & INT_REG_CED) { 1636 if (val & INT_REG_ERR) { 1637 if (!(val & INT_REG_BREQ)) { 1638 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1639 rtsx_trace(chip); 1640 return STATUS_FAIL; 1641 } 1642 retval = ms_read_status_reg(chip); 1643 if (retval != STATUS_SUCCESS) 1644 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1645 1646 } else { 1647 if (!(val & INT_REG_BREQ)) { 1648 ms_set_err_code(chip, MS_BREQ_ERROR); 1649 rtsx_trace(chip); 1650 return STATUS_FAIL; 1651 } 1652 } 1653 } 1654 1655 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1656 0, NO_WAIT_INT); 1657 if (retval != STATUS_SUCCESS) { 1658 rtsx_trace(chip); 1659 return STATUS_FAIL; 1660 } 1661 1662 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1663 rtsx_trace(chip); 1664 return STATUS_FAIL; 1665 } 1666 1667 return STATUS_SUCCESS; 1668 } 1669 1670 1671 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1672 { 1673 struct ms_info *ms_card = &(chip->ms_card); 1674 int retval; 1675 u8 val, data[8], extra[MS_EXTRA_SIZE]; 1676 1677 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1678 if (retval != STATUS_SUCCESS) { 1679 rtsx_trace(chip); 1680 return STATUS_FAIL; 1681 } 1682 1683 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1684 SystemParm, 7); 1685 if (retval != STATUS_SUCCESS) { 1686 rtsx_trace(chip); 1687 return STATUS_FAIL; 1688 } 1689 1690 ms_set_err_code(chip, MS_NO_ERROR); 1691 1692 if (CHK_MS4BIT(ms_card)) 1693 data[0] = 0x88; 1694 else 1695 data[0] = 0x80; 1696 1697 data[1] = 0; 1698 data[2] = (u8)(phy_blk >> 8); 1699 data[3] = (u8)phy_blk; 1700 data[4] = 0x80; 1701 data[5] = 0; 1702 data[6] = extra[0] & 0x7F; 1703 data[7] = 0xFF; 1704 1705 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1706 if (retval != STATUS_SUCCESS) { 1707 rtsx_trace(chip); 1708 return STATUS_FAIL; 1709 } 1710 1711 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1712 if (retval != STATUS_SUCCESS) { 1713 rtsx_trace(chip); 1714 return STATUS_FAIL; 1715 } 1716 1717 ms_set_err_code(chip, MS_NO_ERROR); 1718 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1719 if (retval != STATUS_SUCCESS) { 1720 rtsx_trace(chip); 1721 return STATUS_FAIL; 1722 } 1723 1724 if (val & INT_REG_CMDNK) { 1725 ms_set_err_code(chip, MS_CMD_NK); 1726 rtsx_trace(chip); 1727 return STATUS_FAIL; 1728 } 1729 1730 if (val & INT_REG_CED) { 1731 if (val & INT_REG_ERR) { 1732 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1733 rtsx_trace(chip); 1734 return STATUS_FAIL; 1735 } 1736 } 1737 1738 return STATUS_SUCCESS; 1739 } 1740 1741 1742 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1743 { 1744 struct ms_info *ms_card = &(chip->ms_card); 1745 int retval, i = 0; 1746 u8 val, data[6]; 1747 1748 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1749 SystemParm, 6); 1750 if (retval != STATUS_SUCCESS) { 1751 rtsx_trace(chip); 1752 return STATUS_FAIL; 1753 } 1754 1755 ms_set_err_code(chip, MS_NO_ERROR); 1756 1757 if (CHK_MS4BIT(ms_card)) 1758 data[0] = 0x88; 1759 else 1760 data[0] = 0x80; 1761 1762 data[1] = 0; 1763 data[2] = (u8)(phy_blk >> 8); 1764 data[3] = (u8)phy_blk; 1765 data[4] = 0; 1766 data[5] = 0; 1767 1768 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1769 if (retval != STATUS_SUCCESS) { 1770 rtsx_trace(chip); 1771 return STATUS_FAIL; 1772 } 1773 1774 ERASE_RTY: 1775 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1776 if (retval != STATUS_SUCCESS) { 1777 rtsx_trace(chip); 1778 return STATUS_FAIL; 1779 } 1780 1781 ms_set_err_code(chip, MS_NO_ERROR); 1782 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1783 if (retval != STATUS_SUCCESS) { 1784 rtsx_trace(chip); 1785 return STATUS_FAIL; 1786 } 1787 1788 if (val & INT_REG_CMDNK) { 1789 if (i < 3) { 1790 i++; 1791 goto ERASE_RTY; 1792 } 1793 1794 ms_set_err_code(chip, MS_CMD_NK); 1795 ms_set_bad_block(chip, phy_blk); 1796 rtsx_trace(chip); 1797 return STATUS_FAIL; 1798 } 1799 1800 if (val & INT_REG_CED) { 1801 if (val & INT_REG_ERR) { 1802 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1803 rtsx_trace(chip); 1804 return STATUS_FAIL; 1805 } 1806 } 1807 1808 return STATUS_SUCCESS; 1809 } 1810 1811 1812 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1813 { 1814 if (!extra || (extra_len < MS_EXTRA_SIZE)) 1815 return; 1816 1817 memset(extra, 0xFF, MS_EXTRA_SIZE); 1818 1819 if (type == setPS_NG) { 1820 /* set page status as 1:NG,and block status keep 1:OK */ 1821 extra[0] = 0xB8; 1822 } else { 1823 /* set page status as 0:Data Error,and block status keep 1:OK */ 1824 extra[0] = 0x98; 1825 } 1826 1827 extra[2] = (u8)(log_blk >> 8); 1828 extra[3] = (u8)log_blk; 1829 } 1830 1831 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1832 u8 start_page, u8 end_page) 1833 { 1834 int retval; 1835 u8 extra[MS_EXTRA_SIZE], i; 1836 1837 memset(extra, 0xff, MS_EXTRA_SIZE); 1838 1839 extra[0] = 0xf8; /* Block, page OK, data erased */ 1840 extra[1] = 0xff; 1841 extra[2] = (u8)(log_blk >> 8); 1842 extra[3] = (u8)log_blk; 1843 1844 for (i = start_page; i < end_page; i++) { 1845 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1846 ms_set_err_code(chip, MS_NO_CARD); 1847 rtsx_trace(chip); 1848 return STATUS_FAIL; 1849 } 1850 1851 retval = ms_write_extra_data(chip, phy_blk, i, 1852 extra, MS_EXTRA_SIZE); 1853 if (retval != STATUS_SUCCESS) { 1854 rtsx_trace(chip); 1855 return STATUS_FAIL; 1856 } 1857 } 1858 1859 return STATUS_SUCCESS; 1860 } 1861 1862 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1863 u16 log_blk, u8 start_page, u8 end_page) 1864 { 1865 struct ms_info *ms_card = &(chip->ms_card); 1866 bool uncorrect_flag = false; 1867 int retval, rty_cnt; 1868 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1869 1870 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1871 old_blk, new_blk, log_blk); 1872 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1873 start_page, end_page); 1874 1875 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1876 if (retval != STATUS_SUCCESS) { 1877 rtsx_trace(chip); 1878 return STATUS_FAIL; 1879 } 1880 1881 retval = ms_read_status_reg(chip); 1882 if (retval != STATUS_SUCCESS) { 1883 rtsx_trace(chip); 1884 return STATUS_FAIL; 1885 } 1886 1887 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1888 if (retval) { 1889 rtsx_trace(chip); 1890 return retval; 1891 } 1892 1893 if (val & BUF_FULL) { 1894 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1895 if (retval != STATUS_SUCCESS) { 1896 rtsx_trace(chip); 1897 return STATUS_FAIL; 1898 } 1899 1900 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1901 if (retval != STATUS_SUCCESS) { 1902 rtsx_trace(chip); 1903 return STATUS_FAIL; 1904 } 1905 1906 if (!(val & INT_REG_CED)) { 1907 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1908 rtsx_trace(chip); 1909 return STATUS_FAIL; 1910 } 1911 } 1912 1913 for (i = start_page; i < end_page; i++) { 1914 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1915 ms_set_err_code(chip, MS_NO_CARD); 1916 rtsx_trace(chip); 1917 return STATUS_FAIL; 1918 } 1919 1920 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE); 1921 1922 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1923 MS_EXTRA_SIZE, SystemParm, 6); 1924 if (retval != STATUS_SUCCESS) { 1925 rtsx_trace(chip); 1926 return STATUS_FAIL; 1927 } 1928 1929 ms_set_err_code(chip, MS_NO_ERROR); 1930 1931 if (CHK_MS4BIT(ms_card)) 1932 data[0] = 0x88; 1933 else 1934 data[0] = 0x80; 1935 1936 data[1] = 0; 1937 data[2] = (u8)(old_blk >> 8); 1938 data[3] = (u8)old_blk; 1939 data[4] = 0x20; 1940 data[5] = i; 1941 1942 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1943 data, 6); 1944 if (retval != STATUS_SUCCESS) { 1945 rtsx_trace(chip); 1946 return STATUS_FAIL; 1947 } 1948 1949 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1950 if (retval != STATUS_SUCCESS) { 1951 rtsx_trace(chip); 1952 return STATUS_FAIL; 1953 } 1954 1955 ms_set_err_code(chip, MS_NO_ERROR); 1956 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1957 if (retval != STATUS_SUCCESS) { 1958 rtsx_trace(chip); 1959 return STATUS_FAIL; 1960 } 1961 1962 if (val & INT_REG_CMDNK) { 1963 ms_set_err_code(chip, MS_CMD_NK); 1964 rtsx_trace(chip); 1965 return STATUS_FAIL; 1966 } 1967 1968 if (val & INT_REG_CED) { 1969 if (val & INT_REG_ERR) { 1970 retval = ms_read_status_reg(chip); 1971 if (retval != STATUS_SUCCESS) { 1972 uncorrect_flag = true; 1973 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1974 } else { 1975 uncorrect_flag = false; 1976 } 1977 1978 retval = ms_transfer_tpc(chip, 1979 MS_TM_NORMAL_READ, 1980 READ_PAGE_DATA, 1981 0, NO_WAIT_INT); 1982 if (retval != STATUS_SUCCESS) { 1983 rtsx_trace(chip); 1984 return STATUS_FAIL; 1985 } 1986 1987 if (uncorrect_flag) { 1988 ms_set_page_status(log_blk, setPS_NG, 1989 extra, MS_EXTRA_SIZE); 1990 if (i == 0) 1991 extra[0] &= 0xEF; 1992 1993 ms_write_extra_data(chip, old_blk, i, 1994 extra, MS_EXTRA_SIZE); 1995 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1996 i, extra[0]); 1997 MS_SET_BAD_BLOCK_FLG(ms_card); 1998 1999 ms_set_page_status(log_blk, setPS_Error, 2000 extra, MS_EXTRA_SIZE); 2001 ms_write_extra_data(chip, new_blk, i, 2002 extra, MS_EXTRA_SIZE); 2003 continue; 2004 } 2005 2006 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 2007 rty_cnt++) { 2008 retval = ms_transfer_tpc( 2009 chip, 2010 MS_TM_NORMAL_WRITE, 2011 WRITE_PAGE_DATA, 2012 0, NO_WAIT_INT); 2013 if (retval == STATUS_SUCCESS) 2014 break; 2015 } 2016 if (rty_cnt == MS_MAX_RETRY_COUNT) { 2017 rtsx_trace(chip); 2018 return STATUS_FAIL; 2019 } 2020 } 2021 2022 if (!(val & INT_REG_BREQ)) { 2023 ms_set_err_code(chip, MS_BREQ_ERROR); 2024 rtsx_trace(chip); 2025 return STATUS_FAIL; 2026 } 2027 } 2028 2029 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2030 MS_EXTRA_SIZE, SystemParm, (6 + MS_EXTRA_SIZE)); 2031 2032 ms_set_err_code(chip, MS_NO_ERROR); 2033 2034 if (CHK_MS4BIT(ms_card)) 2035 data[0] = 0x88; 2036 else 2037 data[0] = 0x80; 2038 2039 data[1] = 0; 2040 data[2] = (u8)(new_blk >> 8); 2041 data[3] = (u8)new_blk; 2042 data[4] = 0x20; 2043 data[5] = i; 2044 2045 if ((extra[0] & 0x60) != 0x60) 2046 data[6] = extra[0]; 2047 else 2048 data[6] = 0xF8; 2049 2050 data[6 + 1] = 0xFF; 2051 data[6 + 2] = (u8)(log_blk >> 8); 2052 data[6 + 3] = (u8)log_blk; 2053 2054 for (j = 4; j <= MS_EXTRA_SIZE; j++) 2055 data[6 + j] = 0xFF; 2056 2057 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 2058 NO_WAIT_INT, data, 16); 2059 if (retval != STATUS_SUCCESS) { 2060 rtsx_trace(chip); 2061 return STATUS_FAIL; 2062 } 2063 2064 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2065 if (retval != STATUS_SUCCESS) { 2066 rtsx_trace(chip); 2067 return STATUS_FAIL; 2068 } 2069 2070 ms_set_err_code(chip, MS_NO_ERROR); 2071 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 2072 if (retval != STATUS_SUCCESS) { 2073 rtsx_trace(chip); 2074 return STATUS_FAIL; 2075 } 2076 2077 if (val & INT_REG_CMDNK) { 2078 ms_set_err_code(chip, MS_CMD_NK); 2079 rtsx_trace(chip); 2080 return STATUS_FAIL; 2081 } 2082 2083 if (val & INT_REG_CED) { 2084 if (val & INT_REG_ERR) { 2085 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 2086 rtsx_trace(chip); 2087 return STATUS_FAIL; 2088 } 2089 } 2090 2091 if (i == 0) { 2092 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 2093 MS_EXTRA_SIZE, SystemParm, 7); 2094 if (retval != STATUS_SUCCESS) { 2095 rtsx_trace(chip); 2096 return STATUS_FAIL; 2097 } 2098 2099 ms_set_err_code(chip, MS_NO_ERROR); 2100 2101 if (CHK_MS4BIT(ms_card)) 2102 data[0] = 0x88; 2103 else 2104 data[0] = 0x80; 2105 2106 data[1] = 0; 2107 data[2] = (u8)(old_blk >> 8); 2108 data[3] = (u8)old_blk; 2109 data[4] = 0x80; 2110 data[5] = 0; 2111 data[6] = 0xEF; 2112 data[7] = 0xFF; 2113 2114 retval = ms_write_bytes(chip, WRITE_REG, 7, 2115 NO_WAIT_INT, data, 8); 2116 if (retval != STATUS_SUCCESS) { 2117 rtsx_trace(chip); 2118 return STATUS_FAIL; 2119 } 2120 2121 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 2122 if (retval != STATUS_SUCCESS) { 2123 rtsx_trace(chip); 2124 return STATUS_FAIL; 2125 } 2126 2127 ms_set_err_code(chip, MS_NO_ERROR); 2128 retval = ms_read_bytes(chip, GET_INT, 1, 2129 NO_WAIT_INT, &val, 1); 2130 if (retval != STATUS_SUCCESS) { 2131 rtsx_trace(chip); 2132 return STATUS_FAIL; 2133 } 2134 2135 if (val & INT_REG_CMDNK) { 2136 ms_set_err_code(chip, MS_CMD_NK); 2137 rtsx_trace(chip); 2138 return STATUS_FAIL; 2139 } 2140 2141 if (val & INT_REG_CED) { 2142 if (val & INT_REG_ERR) { 2143 ms_set_err_code(chip, 2144 MS_FLASH_WRITE_ERROR); 2145 rtsx_trace(chip); 2146 return STATUS_FAIL; 2147 } 2148 } 2149 } 2150 } 2151 2152 return STATUS_SUCCESS; 2153 } 2154 2155 2156 static int reset_ms(struct rtsx_chip *chip) 2157 { 2158 struct ms_info *ms_card = &(chip->ms_card); 2159 int retval; 2160 u16 i, reg_addr, block_size; 2161 u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 2162 #ifndef SUPPORT_MAGIC_GATE 2163 u16 eblock_cnt; 2164 #endif 2165 2166 retval = ms_prepare_reset(chip); 2167 if (retval != STATUS_SUCCESS) { 2168 rtsx_trace(chip); 2169 return STATUS_FAIL; 2170 } 2171 2172 ms_card->ms_type |= TYPE_MS; 2173 2174 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 2175 if (retval != STATUS_SUCCESS) { 2176 rtsx_trace(chip); 2177 return STATUS_FAIL; 2178 } 2179 2180 retval = ms_read_status_reg(chip); 2181 if (retval != STATUS_SUCCESS) { 2182 rtsx_trace(chip); 2183 return STATUS_FAIL; 2184 } 2185 2186 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 2187 if (retval) { 2188 rtsx_trace(chip); 2189 return retval; 2190 } 2191 if (val & WRT_PRTCT) 2192 chip->card_wp |= MS_CARD; 2193 else 2194 chip->card_wp &= ~MS_CARD; 2195 2196 i = 0; 2197 2198 RE_SEARCH: 2199 /* Search Boot Block */ 2200 while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 2201 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2202 ms_set_err_code(chip, MS_NO_CARD); 2203 rtsx_trace(chip); 2204 return STATUS_FAIL; 2205 } 2206 2207 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 2208 if (retval != STATUS_SUCCESS) { 2209 i++; 2210 continue; 2211 } 2212 2213 if (extra[0] & BLOCK_OK) { 2214 if (!(extra[1] & NOT_BOOT_BLOCK)) { 2215 ms_card->boot_block = i; 2216 break; 2217 } 2218 } 2219 i++; 2220 } 2221 2222 if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 2223 dev_dbg(rtsx_dev(chip), "No boot block found!"); 2224 rtsx_trace(chip); 2225 return STATUS_FAIL; 2226 } 2227 2228 for (j = 0; j < 3; j++) { 2229 retval = ms_read_page(chip, ms_card->boot_block, j); 2230 if (retval != STATUS_SUCCESS) { 2231 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 2232 i = ms_card->boot_block + 1; 2233 ms_set_err_code(chip, MS_NO_ERROR); 2234 goto RE_SEARCH; 2235 } 2236 } 2237 } 2238 2239 retval = ms_read_page(chip, ms_card->boot_block, 0); 2240 if (retval != STATUS_SUCCESS) { 2241 rtsx_trace(chip); 2242 return STATUS_FAIL; 2243 } 2244 2245 /* Read MS system information as sys_info */ 2246 rtsx_init_cmd(chip); 2247 2248 for (i = 0; i < 96; i++) 2249 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 2250 2251 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2252 if (retval < 0) { 2253 rtsx_trace(chip); 2254 return STATUS_FAIL; 2255 } 2256 2257 ptr = rtsx_get_cmd_data(chip); 2258 memcpy(ms_card->raw_sys_info, ptr, 96); 2259 2260 /* Read useful block contents */ 2261 rtsx_init_cmd(chip); 2262 2263 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 2264 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 2265 2266 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 2267 reg_addr++) 2268 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2269 2270 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 2271 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 2272 2273 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0); 2274 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0); 2275 2276 retval = rtsx_send_cmd(chip, MS_CARD, 100); 2277 if (retval < 0) { 2278 rtsx_trace(chip); 2279 return STATUS_FAIL; 2280 } 2281 2282 ptr = rtsx_get_cmd_data(chip); 2283 2284 dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 2285 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 2286 2287 /* Block ID error 2288 * HEADER_ID0, HEADER_ID1 2289 */ 2290 if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2291 i = ms_card->boot_block + 1; 2292 goto RE_SEARCH; 2293 } 2294 2295 /* Page size error 2296 * PAGE_SIZE_0, PAGE_SIZE_1 2297 */ 2298 if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2299 i = ms_card->boot_block + 1; 2300 goto RE_SEARCH; 2301 } 2302 2303 if ((ptr[14] == 1) || (ptr[14] == 3)) 2304 chip->card_wp |= MS_CARD; 2305 2306 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2307 block_size = ((u16)ptr[6] << 8) | ptr[7]; 2308 if (block_size == 0x0010) { 2309 /* Block size 16KB */ 2310 ms_card->block_shift = 5; 2311 ms_card->page_off = 0x1F; 2312 } else if (block_size == 0x0008) { 2313 /* Block size 8KB */ 2314 ms_card->block_shift = 4; 2315 ms_card->page_off = 0x0F; 2316 } 2317 2318 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2319 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2320 2321 #ifdef SUPPORT_MAGIC_GATE 2322 j = ptr[10]; 2323 2324 if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2325 if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2326 ms_card->capacity = 0x1EE0; 2327 } else { /* Effective block for 8MB: 0x3E0 */ 2328 ms_card->capacity = 0x3DE0; 2329 } 2330 } else { /* 16MB, 32MB, 64MB or 128MB */ 2331 if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2332 ms_card->capacity = 0x7BC0; 2333 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2334 ms_card->capacity = 0xF7C0; 2335 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2336 ms_card->capacity = 0x1EF80; 2337 } else { /* Effective block for 128MB: 0x1F00 */ 2338 ms_card->capacity = 0x3DF00; 2339 } 2340 } 2341 #else 2342 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2343 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2344 2345 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2346 #endif 2347 2348 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2349 2350 /* Switch I/F Mode */ 2351 if (ptr[15]) { 2352 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1); 2353 if (retval != STATUS_SUCCESS) { 2354 rtsx_trace(chip); 2355 return STATUS_FAIL; 2356 } 2357 2358 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2359 if (retval) { 2360 rtsx_trace(chip); 2361 return retval; 2362 } 2363 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2364 if (retval) { 2365 rtsx_trace(chip); 2366 return retval; 2367 } 2368 2369 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2370 NO_WAIT_INT); 2371 if (retval != STATUS_SUCCESS) { 2372 rtsx_trace(chip); 2373 return STATUS_FAIL; 2374 } 2375 2376 retval = rtsx_write_register(chip, MS_CFG, 2377 0x58 | MS_NO_CHECK_INT, 2378 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT); 2379 if (retval) { 2380 rtsx_trace(chip); 2381 return retval; 2382 } 2383 2384 ms_card->ms_type |= MS_4BIT; 2385 } 2386 2387 if (CHK_MS4BIT(ms_card)) 2388 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2389 else 2390 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2391 2392 return STATUS_SUCCESS; 2393 } 2394 2395 static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2396 { 2397 struct ms_info *ms_card = &(chip->ms_card); 2398 int size, i, seg_no, retval; 2399 u16 defect_block, reg_addr; 2400 u8 val1, val2; 2401 2402 ms_card->segment_cnt = ms_card->total_block >> 9; 2403 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2404 ms_card->segment_cnt); 2405 2406 size = ms_card->segment_cnt * sizeof(struct zone_entry); 2407 ms_card->segment = vzalloc(size); 2408 if (ms_card->segment == NULL) { 2409 rtsx_trace(chip); 2410 return STATUS_FAIL; 2411 } 2412 2413 retval = ms_read_page(chip, ms_card->boot_block, 1); 2414 if (retval != STATUS_SUCCESS) { 2415 rtsx_trace(chip); 2416 goto INIT_FAIL; 2417 } 2418 2419 reg_addr = PPBUF_BASE2; 2420 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2421 int block_no; 2422 2423 retval = rtsx_read_register(chip, reg_addr++, &val1); 2424 if (retval != STATUS_SUCCESS) { 2425 rtsx_trace(chip); 2426 goto INIT_FAIL; 2427 } 2428 2429 retval = rtsx_read_register(chip, reg_addr++, &val2); 2430 if (retval != STATUS_SUCCESS) { 2431 rtsx_trace(chip); 2432 goto INIT_FAIL; 2433 } 2434 2435 defect_block = ((u16)val1 << 8) | val2; 2436 if (defect_block == 0xFFFF) 2437 break; 2438 2439 seg_no = defect_block / 512; 2440 2441 block_no = ms_card->segment[seg_no].disable_count++; 2442 ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2443 } 2444 2445 for (i = 0; i < ms_card->segment_cnt; i++) { 2446 ms_card->segment[i].build_flag = 0; 2447 ms_card->segment[i].l2p_table = NULL; 2448 ms_card->segment[i].free_table = NULL; 2449 ms_card->segment[i].get_index = 0; 2450 ms_card->segment[i].set_index = 0; 2451 ms_card->segment[i].unused_blk_cnt = 0; 2452 2453 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2454 i, ms_card->segment[i].disable_count); 2455 } 2456 2457 return STATUS_SUCCESS; 2458 2459 INIT_FAIL: 2460 if (ms_card->segment) { 2461 vfree(ms_card->segment); 2462 ms_card->segment = NULL; 2463 } 2464 2465 return STATUS_FAIL; 2466 } 2467 2468 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2469 { 2470 struct ms_info *ms_card = &(chip->ms_card); 2471 struct zone_entry *segment; 2472 2473 if (ms_card->segment == NULL) 2474 return 0xFFFF; 2475 2476 segment = &(ms_card->segment[seg_no]); 2477 2478 if (segment->l2p_table) 2479 return segment->l2p_table[log_off]; 2480 2481 return 0xFFFF; 2482 } 2483 2484 static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2485 int seg_no, u16 log_off, u16 phy_blk) 2486 { 2487 struct ms_info *ms_card = &(chip->ms_card); 2488 struct zone_entry *segment; 2489 2490 if (ms_card->segment == NULL) 2491 return; 2492 2493 segment = &(ms_card->segment[seg_no]); 2494 if (segment->l2p_table) 2495 segment->l2p_table[log_off] = phy_blk; 2496 } 2497 2498 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2499 { 2500 struct ms_info *ms_card = &(chip->ms_card); 2501 struct zone_entry *segment; 2502 int seg_no; 2503 2504 seg_no = (int)phy_blk >> 9; 2505 segment = &(ms_card->segment[seg_no]); 2506 2507 segment->free_table[segment->set_index++] = phy_blk; 2508 if (segment->set_index >= MS_FREE_TABLE_CNT) 2509 segment->set_index = 0; 2510 2511 segment->unused_blk_cnt++; 2512 } 2513 2514 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2515 { 2516 struct ms_info *ms_card = &(chip->ms_card); 2517 struct zone_entry *segment; 2518 u16 phy_blk; 2519 2520 segment = &(ms_card->segment[seg_no]); 2521 2522 if (segment->unused_blk_cnt <= 0) 2523 return 0xFFFF; 2524 2525 phy_blk = segment->free_table[segment->get_index]; 2526 segment->free_table[segment->get_index++] = 0xFFFF; 2527 if (segment->get_index >= MS_FREE_TABLE_CNT) 2528 segment->get_index = 0; 2529 2530 segment->unused_blk_cnt--; 2531 2532 return phy_blk; 2533 } 2534 2535 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2536 2974, 3470, 3966, 4462, 4958, 2537 5454, 5950, 6446, 6942, 7438, 2538 7934}; 2539 2540 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2541 u16 log_off, u8 us1, u8 us2) 2542 { 2543 struct ms_info *ms_card = &(chip->ms_card); 2544 struct zone_entry *segment; 2545 int seg_no; 2546 u16 tmp_blk; 2547 2548 seg_no = (int)phy_blk >> 9; 2549 segment = &(ms_card->segment[seg_no]); 2550 tmp_blk = segment->l2p_table[log_off]; 2551 2552 if (us1 != us2) { 2553 if (us1 == 0) { 2554 if (!(chip->card_wp & MS_CARD)) 2555 ms_erase_block(chip, tmp_blk); 2556 2557 ms_set_unused_block(chip, tmp_blk); 2558 segment->l2p_table[log_off] = phy_blk; 2559 } else { 2560 if (!(chip->card_wp & MS_CARD)) 2561 ms_erase_block(chip, phy_blk); 2562 2563 ms_set_unused_block(chip, phy_blk); 2564 } 2565 } else { 2566 if (phy_blk < tmp_blk) { 2567 if (!(chip->card_wp & MS_CARD)) 2568 ms_erase_block(chip, phy_blk); 2569 2570 ms_set_unused_block(chip, phy_blk); 2571 } else { 2572 if (!(chip->card_wp & MS_CARD)) 2573 ms_erase_block(chip, tmp_blk); 2574 2575 ms_set_unused_block(chip, tmp_blk); 2576 segment->l2p_table[log_off] = phy_blk; 2577 } 2578 } 2579 2580 return STATUS_SUCCESS; 2581 } 2582 2583 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2584 { 2585 struct ms_info *ms_card = &(chip->ms_card); 2586 struct zone_entry *segment; 2587 bool defect_flag; 2588 int retval, table_size, disable_cnt, i; 2589 u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2590 u8 extra[MS_EXTRA_SIZE], us1, us2; 2591 2592 dev_dbg(rtsx_dev(chip), "ms_build_l2p_tbl: %d\n", seg_no); 2593 2594 if (ms_card->segment == NULL) { 2595 retval = ms_init_l2p_tbl(chip); 2596 if (retval != STATUS_SUCCESS) { 2597 rtsx_trace(chip); 2598 return retval; 2599 } 2600 } 2601 2602 if (ms_card->segment[seg_no].build_flag) { 2603 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2604 seg_no); 2605 return STATUS_SUCCESS; 2606 } 2607 2608 if (seg_no == 0) 2609 table_size = 494; 2610 else 2611 table_size = 496; 2612 2613 segment = &(ms_card->segment[seg_no]); 2614 2615 if (segment->l2p_table == NULL) { 2616 segment->l2p_table = vmalloc(table_size * 2); 2617 if (segment->l2p_table == NULL) { 2618 rtsx_trace(chip); 2619 goto BUILD_FAIL; 2620 } 2621 } 2622 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2); 2623 2624 if (segment->free_table == NULL) { 2625 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2); 2626 if (segment->free_table == NULL) { 2627 rtsx_trace(chip); 2628 goto BUILD_FAIL; 2629 } 2630 } 2631 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2); 2632 2633 start = (u16)seg_no << 9; 2634 end = (u16)(seg_no + 1) << 9; 2635 2636 disable_cnt = segment->disable_count; 2637 2638 segment->get_index = segment->set_index = 0; 2639 segment->unused_blk_cnt = 0; 2640 2641 for (phy_blk = start; phy_blk < end; phy_blk++) { 2642 if (disable_cnt) { 2643 defect_flag = false; 2644 for (i = 0; i < segment->disable_count; i++) { 2645 if (phy_blk == segment->defect_list[i]) { 2646 defect_flag = true; 2647 break; 2648 } 2649 } 2650 if (defect_flag) { 2651 disable_cnt--; 2652 continue; 2653 } 2654 } 2655 2656 retval = ms_read_extra_data(chip, phy_blk, 0, 2657 extra, MS_EXTRA_SIZE); 2658 if (retval != STATUS_SUCCESS) { 2659 dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2660 ms_set_bad_block(chip, phy_blk); 2661 continue; 2662 } 2663 2664 if (seg_no == ms_card->segment_cnt - 1) { 2665 if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2666 if (!(chip->card_wp & MS_CARD)) { 2667 retval = ms_erase_block(chip, phy_blk); 2668 if (retval != STATUS_SUCCESS) 2669 continue; 2670 extra[2] = 0xff; 2671 extra[3] = 0xff; 2672 } 2673 } 2674 } 2675 2676 if (!(extra[0] & BLOCK_OK)) 2677 continue; 2678 if (!(extra[1] & NOT_BOOT_BLOCK)) 2679 continue; 2680 if ((extra[0] & PAGE_OK) != PAGE_OK) 2681 continue; 2682 2683 log_blk = ((u16)extra[2] << 8) | extra[3]; 2684 2685 if (log_blk == 0xFFFF) { 2686 if (!(chip->card_wp & MS_CARD)) { 2687 retval = ms_erase_block(chip, phy_blk); 2688 if (retval != STATUS_SUCCESS) 2689 continue; 2690 } 2691 ms_set_unused_block(chip, phy_blk); 2692 continue; 2693 } 2694 2695 if ((log_blk < ms_start_idx[seg_no]) || 2696 (log_blk >= ms_start_idx[seg_no+1])) { 2697 if (!(chip->card_wp & MS_CARD)) { 2698 retval = ms_erase_block(chip, phy_blk); 2699 if (retval != STATUS_SUCCESS) 2700 continue; 2701 } 2702 ms_set_unused_block(chip, phy_blk); 2703 continue; 2704 } 2705 2706 idx = log_blk - ms_start_idx[seg_no]; 2707 2708 if (segment->l2p_table[idx] == 0xFFFF) { 2709 segment->l2p_table[idx] = phy_blk; 2710 continue; 2711 } 2712 2713 us1 = extra[0] & 0x10; 2714 tmp_blk = segment->l2p_table[idx]; 2715 retval = ms_read_extra_data(chip, tmp_blk, 0, 2716 extra, MS_EXTRA_SIZE); 2717 if (retval != STATUS_SUCCESS) 2718 continue; 2719 us2 = extra[0] & 0x10; 2720 2721 (void)ms_arbitrate_l2p(chip, phy_blk, 2722 log_blk-ms_start_idx[seg_no], us1, us2); 2723 continue; 2724 } 2725 2726 segment->build_flag = 1; 2727 2728 dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2729 segment->unused_blk_cnt); 2730 2731 /* Logical Address Confirmation Process */ 2732 if (seg_no == ms_card->segment_cnt - 1) { 2733 if (segment->unused_blk_cnt < 2) 2734 chip->card_wp |= MS_CARD; 2735 } else { 2736 if (segment->unused_blk_cnt < 1) 2737 chip->card_wp |= MS_CARD; 2738 } 2739 2740 if (chip->card_wp & MS_CARD) 2741 return STATUS_SUCCESS; 2742 2743 for (log_blk = ms_start_idx[seg_no]; 2744 log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2745 idx = log_blk - ms_start_idx[seg_no]; 2746 if (segment->l2p_table[idx] == 0xFFFF) { 2747 phy_blk = ms_get_unused_block(chip, seg_no); 2748 if (phy_blk == 0xFFFF) { 2749 chip->card_wp |= MS_CARD; 2750 return STATUS_SUCCESS; 2751 } 2752 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2753 if (retval != STATUS_SUCCESS) { 2754 rtsx_trace(chip); 2755 goto BUILD_FAIL; 2756 } 2757 2758 segment->l2p_table[idx] = phy_blk; 2759 if (seg_no == ms_card->segment_cnt - 1) { 2760 if (segment->unused_blk_cnt < 2) { 2761 chip->card_wp |= MS_CARD; 2762 return STATUS_SUCCESS; 2763 } 2764 } else { 2765 if (segment->unused_blk_cnt < 1) { 2766 chip->card_wp |= MS_CARD; 2767 return STATUS_SUCCESS; 2768 } 2769 } 2770 } 2771 } 2772 2773 /* Make boot block be the first normal block */ 2774 if (seg_no == 0) { 2775 for (log_blk = 0; log_blk < 494; log_blk++) { 2776 tmp_blk = segment->l2p_table[log_blk]; 2777 if (tmp_blk < ms_card->boot_block) { 2778 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2779 2780 if (chip->card_wp & MS_CARD) 2781 break; 2782 2783 phy_blk = ms_get_unused_block(chip, 0); 2784 retval = ms_copy_page(chip, tmp_blk, phy_blk, 2785 log_blk, 0, ms_card->page_off + 1); 2786 if (retval != STATUS_SUCCESS) { 2787 rtsx_trace(chip); 2788 return STATUS_FAIL; 2789 } 2790 2791 segment->l2p_table[log_blk] = phy_blk; 2792 2793 retval = ms_set_bad_block(chip, tmp_blk); 2794 if (retval != STATUS_SUCCESS) { 2795 rtsx_trace(chip); 2796 return STATUS_FAIL; 2797 } 2798 } 2799 } 2800 } 2801 2802 return STATUS_SUCCESS; 2803 2804 BUILD_FAIL: 2805 segment->build_flag = 0; 2806 if (segment->l2p_table) { 2807 vfree(segment->l2p_table); 2808 segment->l2p_table = NULL; 2809 } 2810 if (segment->free_table) { 2811 vfree(segment->free_table); 2812 segment->free_table = NULL; 2813 } 2814 2815 return STATUS_FAIL; 2816 } 2817 2818 2819 int reset_ms_card(struct rtsx_chip *chip) 2820 { 2821 struct ms_info *ms_card = &(chip->ms_card); 2822 int retval; 2823 2824 memset(ms_card, 0, sizeof(struct ms_info)); 2825 2826 retval = enable_card_clock(chip, MS_CARD); 2827 if (retval != STATUS_SUCCESS) { 2828 rtsx_trace(chip); 2829 return STATUS_FAIL; 2830 } 2831 2832 retval = select_card(chip, MS_CARD); 2833 if (retval != STATUS_SUCCESS) { 2834 rtsx_trace(chip); 2835 return STATUS_FAIL; 2836 } 2837 2838 ms_card->ms_type = 0; 2839 2840 retval = reset_ms_pro(chip); 2841 if (retval != STATUS_SUCCESS) { 2842 if (ms_card->check_ms_flow) { 2843 retval = reset_ms(chip); 2844 if (retval != STATUS_SUCCESS) { 2845 rtsx_trace(chip); 2846 return STATUS_FAIL; 2847 } 2848 } else { 2849 rtsx_trace(chip); 2850 return STATUS_FAIL; 2851 } 2852 } 2853 2854 retval = ms_set_init_para(chip); 2855 if (retval != STATUS_SUCCESS) { 2856 rtsx_trace(chip); 2857 return STATUS_FAIL; 2858 } 2859 2860 if (!CHK_MSPRO(ms_card)) { 2861 /* Build table for the last segment, 2862 * to check if L2P table block exists, erasing it 2863 */ 2864 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1); 2865 if (retval != STATUS_SUCCESS) { 2866 rtsx_trace(chip); 2867 return STATUS_FAIL; 2868 } 2869 } 2870 2871 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2872 2873 return STATUS_SUCCESS; 2874 } 2875 2876 static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2877 u32 start_sec, u16 sec_cnt, u8 cmd) 2878 { 2879 int retval, i; 2880 u8 data[8]; 2881 2882 data[0] = cmd; 2883 data[1] = (u8)(sec_cnt >> 8); 2884 data[2] = (u8)sec_cnt; 2885 data[3] = (u8)(start_sec >> 24); 2886 data[4] = (u8)(start_sec >> 16); 2887 data[5] = (u8)(start_sec >> 8); 2888 data[6] = (u8)start_sec; 2889 data[7] = 0; 2890 2891 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2892 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2893 WAIT_INT, data, 8); 2894 if (retval == STATUS_SUCCESS) 2895 break; 2896 } 2897 if (i == MS_MAX_RETRY_COUNT) { 2898 rtsx_trace(chip); 2899 return STATUS_FAIL; 2900 } 2901 2902 return STATUS_SUCCESS; 2903 } 2904 2905 2906 void mspro_stop_seq_mode(struct rtsx_chip *chip) 2907 { 2908 struct ms_info *ms_card = &(chip->ms_card); 2909 int retval; 2910 2911 if (ms_card->seq_mode) { 2912 retval = ms_switch_clock(chip); 2913 if (retval != STATUS_SUCCESS) 2914 return; 2915 2916 ms_card->seq_mode = 0; 2917 ms_card->total_sec_cnt = 0; 2918 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2919 2920 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2921 } 2922 } 2923 2924 static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2925 { 2926 struct ms_info *ms_card = &(chip->ms_card); 2927 int retval; 2928 2929 if (chip->asic_code) { 2930 if (ms_card->ms_clock > 30) 2931 ms_card->ms_clock -= 20; 2932 } else { 2933 if (ms_card->ms_clock == CLK_80) 2934 ms_card->ms_clock = CLK_60; 2935 else if (ms_card->ms_clock == CLK_60) 2936 ms_card->ms_clock = CLK_40; 2937 } 2938 2939 retval = ms_switch_clock(chip); 2940 if (retval != STATUS_SUCCESS) { 2941 rtsx_trace(chip); 2942 return STATUS_FAIL; 2943 } 2944 2945 return STATUS_SUCCESS; 2946 } 2947 2948 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2949 struct rtsx_chip *chip, u32 start_sector, 2950 u16 sector_cnt) 2951 { 2952 struct ms_info *ms_card = &(chip->ms_card); 2953 bool mode_2k = false; 2954 int retval; 2955 u16 count; 2956 u8 val, trans_mode, rw_tpc, rw_cmd; 2957 2958 ms_set_err_code(chip, MS_NO_ERROR); 2959 2960 ms_card->cleanup_counter = 0; 2961 2962 if (CHK_MSHG(ms_card)) { 2963 if ((start_sector % 4) || (sector_cnt % 4)) { 2964 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2965 rw_tpc = PRO_READ_LONG_DATA; 2966 rw_cmd = PRO_READ_DATA; 2967 } else { 2968 rw_tpc = PRO_WRITE_LONG_DATA; 2969 rw_cmd = PRO_WRITE_DATA; 2970 } 2971 } else { 2972 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2973 rw_tpc = PRO_READ_QUAD_DATA; 2974 rw_cmd = PRO_READ_2K_DATA; 2975 } else { 2976 rw_tpc = PRO_WRITE_QUAD_DATA; 2977 rw_cmd = PRO_WRITE_2K_DATA; 2978 } 2979 mode_2k = true; 2980 } 2981 } else { 2982 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2983 rw_tpc = PRO_READ_LONG_DATA; 2984 rw_cmd = PRO_READ_DATA; 2985 } else { 2986 rw_tpc = PRO_WRITE_LONG_DATA; 2987 rw_cmd = PRO_WRITE_DATA; 2988 } 2989 } 2990 2991 retval = ms_switch_clock(chip); 2992 if (retval != STATUS_SUCCESS) { 2993 rtsx_trace(chip); 2994 return STATUS_FAIL; 2995 } 2996 2997 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2998 trans_mode = MS_TM_AUTO_READ; 2999 else 3000 trans_mode = MS_TM_AUTO_WRITE; 3001 3002 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3003 if (retval) { 3004 rtsx_trace(chip); 3005 return retval; 3006 } 3007 3008 if (ms_card->seq_mode) { 3009 if ((ms_card->pre_dir != srb->sc_data_direction) 3010 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector) 3011 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) 3012 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) 3013 || !(val & MS_INT_BREQ) 3014 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 3015 ms_card->seq_mode = 0; 3016 ms_card->total_sec_cnt = 0; 3017 if (val & MS_INT_BREQ) { 3018 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3019 if (retval != STATUS_SUCCESS) { 3020 rtsx_trace(chip); 3021 return STATUS_FAIL; 3022 } 3023 3024 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 3025 } 3026 } 3027 } 3028 3029 if (!ms_card->seq_mode) { 3030 ms_card->total_sec_cnt = 0; 3031 if (sector_cnt >= SEQ_START_CRITERIA) { 3032 if ((ms_card->capacity - start_sector) > 0xFE00) 3033 count = 0xFE00; 3034 else 3035 count = (u16)(ms_card->capacity - start_sector); 3036 3037 if (count > sector_cnt) { 3038 if (mode_2k) 3039 ms_card->seq_mode = MODE_2K_SEQ; 3040 else 3041 ms_card->seq_mode = MODE_512_SEQ; 3042 } 3043 } else { 3044 count = sector_cnt; 3045 } 3046 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 3047 if (retval != STATUS_SUCCESS) { 3048 ms_card->seq_mode = 0; 3049 rtsx_trace(chip); 3050 return STATUS_FAIL; 3051 } 3052 } 3053 3054 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 3055 WAIT_INT, mode_2k, scsi_sg_count(srb), 3056 scsi_sglist(srb), scsi_bufflen(srb)); 3057 if (retval != STATUS_SUCCESS) { 3058 ms_card->seq_mode = 0; 3059 rtsx_read_register(chip, MS_TRANS_CFG, &val); 3060 rtsx_clear_ms_error(chip); 3061 3062 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3063 chip->rw_need_retry = 0; 3064 dev_dbg(rtsx_dev(chip), "No card exist, exit mspro_rw_multi_sector\n"); 3065 rtsx_trace(chip); 3066 return STATUS_FAIL; 3067 } 3068 3069 if (val & MS_INT_BREQ) 3070 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 3071 3072 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3073 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 3074 chip->rw_need_retry = 1; 3075 ms_auto_tune_clock(chip); 3076 } 3077 3078 rtsx_trace(chip); 3079 return retval; 3080 } 3081 3082 if (ms_card->seq_mode) { 3083 ms_card->pre_sec_addr = start_sector; 3084 ms_card->pre_sec_cnt = sector_cnt; 3085 ms_card->pre_dir = srb->sc_data_direction; 3086 ms_card->total_sec_cnt += sector_cnt; 3087 } 3088 3089 return STATUS_SUCCESS; 3090 } 3091 3092 static int mspro_read_format_progress(struct rtsx_chip *chip, 3093 const int short_data_len) 3094 { 3095 struct ms_info *ms_card = &(chip->ms_card); 3096 int retval, i; 3097 u32 total_progress, cur_progress; 3098 u8 cnt, tmp; 3099 u8 data[8]; 3100 3101 dev_dbg(rtsx_dev(chip), "mspro_read_format_progress, short_data_len = %d\n", 3102 short_data_len); 3103 3104 retval = ms_switch_clock(chip); 3105 if (retval != STATUS_SUCCESS) { 3106 ms_card->format_status = FORMAT_FAIL; 3107 rtsx_trace(chip); 3108 return STATUS_FAIL; 3109 } 3110 3111 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3112 if (retval != STATUS_SUCCESS) { 3113 ms_card->format_status = FORMAT_FAIL; 3114 rtsx_trace(chip); 3115 return STATUS_FAIL; 3116 } 3117 3118 if (!(tmp & MS_INT_BREQ)) { 3119 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) { 3120 ms_card->format_status = FORMAT_SUCCESS; 3121 return STATUS_SUCCESS; 3122 } 3123 ms_card->format_status = FORMAT_FAIL; 3124 rtsx_trace(chip); 3125 return STATUS_FAIL; 3126 } 3127 3128 if (short_data_len >= 256) 3129 cnt = 0; 3130 else 3131 cnt = (u8)short_data_len; 3132 3133 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 3134 MS_NO_CHECK_INT); 3135 if (retval != STATUS_SUCCESS) { 3136 ms_card->format_status = FORMAT_FAIL; 3137 rtsx_trace(chip); 3138 return STATUS_FAIL; 3139 } 3140 3141 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 3142 data, 8); 3143 if (retval != STATUS_SUCCESS) { 3144 ms_card->format_status = FORMAT_FAIL; 3145 rtsx_trace(chip); 3146 return STATUS_FAIL; 3147 } 3148 3149 total_progress = (data[0] << 24) | (data[1] << 16) | 3150 (data[2] << 8) | data[3]; 3151 cur_progress = (data[4] << 24) | (data[5] << 16) | 3152 (data[6] << 8) | data[7]; 3153 3154 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 3155 total_progress, cur_progress); 3156 3157 if (total_progress == 0) { 3158 ms_card->progress = 0; 3159 } else { 3160 u64 ulltmp = (u64)cur_progress * (u64)65535; 3161 3162 do_div(ulltmp, total_progress); 3163 ms_card->progress = (u16)ulltmp; 3164 } 3165 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 3166 3167 for (i = 0; i < 5000; i++) { 3168 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3169 if (retval != STATUS_SUCCESS) { 3170 ms_card->format_status = FORMAT_FAIL; 3171 rtsx_trace(chip); 3172 return STATUS_FAIL; 3173 } 3174 if (tmp & (MS_INT_CED | MS_INT_CMDNK | 3175 MS_INT_BREQ | MS_INT_ERR)) 3176 break; 3177 3178 wait_timeout(1); 3179 } 3180 3181 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 3182 if (retval != STATUS_SUCCESS) { 3183 ms_card->format_status = FORMAT_FAIL; 3184 rtsx_trace(chip); 3185 return STATUS_FAIL; 3186 } 3187 3188 if (i == 5000) { 3189 ms_card->format_status = FORMAT_FAIL; 3190 rtsx_trace(chip); 3191 return STATUS_FAIL; 3192 } 3193 3194 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3195 ms_card->format_status = FORMAT_FAIL; 3196 rtsx_trace(chip); 3197 return STATUS_FAIL; 3198 } 3199 3200 if (tmp & MS_INT_CED) { 3201 ms_card->format_status = FORMAT_SUCCESS; 3202 ms_card->pro_under_formatting = 0; 3203 } else if (tmp & MS_INT_BREQ) { 3204 ms_card->format_status = FORMAT_IN_PROGRESS; 3205 } else { 3206 ms_card->format_status = FORMAT_FAIL; 3207 ms_card->pro_under_formatting = 0; 3208 rtsx_trace(chip); 3209 return STATUS_FAIL; 3210 } 3211 3212 return STATUS_SUCCESS; 3213 } 3214 3215 void mspro_polling_format_status(struct rtsx_chip *chip) 3216 { 3217 struct ms_info *ms_card = &(chip->ms_card); 3218 int i; 3219 3220 if (ms_card->pro_under_formatting && 3221 (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 3222 rtsx_set_stat(chip, RTSX_STAT_RUN); 3223 3224 for (i = 0; i < 65535; i++) { 3225 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 3226 if (ms_card->format_status != FORMAT_IN_PROGRESS) 3227 break; 3228 } 3229 } 3230 } 3231 3232 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3233 int short_data_len, bool quick_format) 3234 { 3235 struct ms_info *ms_card = &(chip->ms_card); 3236 int retval, i; 3237 u8 buf[8], tmp; 3238 u16 para; 3239 3240 retval = ms_switch_clock(chip); 3241 if (retval != STATUS_SUCCESS) { 3242 rtsx_trace(chip); 3243 return STATUS_FAIL; 3244 } 3245 3246 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01); 3247 if (retval != STATUS_SUCCESS) { 3248 rtsx_trace(chip); 3249 return STATUS_FAIL; 3250 } 3251 3252 memset(buf, 0, 2); 3253 switch (short_data_len) { 3254 case 32: 3255 buf[0] = 0; 3256 break; 3257 case 64: 3258 buf[0] = 1; 3259 break; 3260 case 128: 3261 buf[0] = 2; 3262 break; 3263 case 256: 3264 default: 3265 buf[0] = 3; 3266 break; 3267 } 3268 3269 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3270 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 3271 NO_WAIT_INT, buf, 2); 3272 if (retval == STATUS_SUCCESS) 3273 break; 3274 } 3275 if (i == MS_MAX_RETRY_COUNT) { 3276 rtsx_trace(chip); 3277 return STATUS_FAIL; 3278 } 3279 3280 if (quick_format) 3281 para = 0x0000; 3282 else 3283 para = 0x0001; 3284 3285 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 3286 if (retval != STATUS_SUCCESS) { 3287 rtsx_trace(chip); 3288 return STATUS_FAIL; 3289 } 3290 3291 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 3292 if (retval) { 3293 rtsx_trace(chip); 3294 return retval; 3295 } 3296 3297 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 3298 rtsx_trace(chip); 3299 return STATUS_FAIL; 3300 } 3301 3302 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 3303 ms_card->pro_under_formatting = 1; 3304 ms_card->progress = 0; 3305 ms_card->format_status = FORMAT_IN_PROGRESS; 3306 return STATUS_SUCCESS; 3307 } 3308 3309 if (tmp & MS_INT_CED) { 3310 ms_card->pro_under_formatting = 0; 3311 ms_card->progress = 0; 3312 ms_card->format_status = FORMAT_SUCCESS; 3313 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 3314 return STATUS_SUCCESS; 3315 } 3316 3317 rtsx_trace(chip); 3318 return STATUS_FAIL; 3319 } 3320 3321 3322 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 3323 u16 log_blk, u8 start_page, u8 end_page, 3324 u8 *buf, unsigned int *index, 3325 unsigned int *offset) 3326 { 3327 struct ms_info *ms_card = &(chip->ms_card); 3328 int retval, i; 3329 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 3330 u8 *ptr; 3331 3332 retval = ms_read_extra_data(chip, phy_blk, start_page, 3333 extra, MS_EXTRA_SIZE); 3334 if (retval == STATUS_SUCCESS) { 3335 if ((extra[1] & 0x30) != 0x30) { 3336 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3337 rtsx_trace(chip); 3338 return STATUS_FAIL; 3339 } 3340 } 3341 3342 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3343 SystemParm, 6); 3344 if (retval != STATUS_SUCCESS) { 3345 rtsx_trace(chip); 3346 return STATUS_FAIL; 3347 } 3348 3349 if (CHK_MS4BIT(ms_card)) 3350 data[0] = 0x88; 3351 else 3352 data[0] = 0x80; 3353 3354 data[1] = 0; 3355 data[2] = (u8)(phy_blk >> 8); 3356 data[3] = (u8)phy_blk; 3357 data[4] = 0; 3358 data[5] = start_page; 3359 3360 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3361 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 3362 data, 6); 3363 if (retval == STATUS_SUCCESS) 3364 break; 3365 } 3366 if (i == MS_MAX_RETRY_COUNT) { 3367 rtsx_trace(chip); 3368 return STATUS_FAIL; 3369 } 3370 3371 ms_set_err_code(chip, MS_NO_ERROR); 3372 3373 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3374 if (retval != STATUS_SUCCESS) { 3375 rtsx_trace(chip); 3376 return STATUS_FAIL; 3377 } 3378 3379 ptr = buf; 3380 3381 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3382 ms_set_err_code(chip, MS_NO_ERROR); 3383 3384 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3385 ms_set_err_code(chip, MS_NO_CARD); 3386 rtsx_trace(chip); 3387 return STATUS_FAIL; 3388 } 3389 3390 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3391 if (retval != STATUS_SUCCESS) { 3392 rtsx_trace(chip); 3393 return STATUS_FAIL; 3394 } 3395 3396 if (val & INT_REG_CMDNK) { 3397 ms_set_err_code(chip, MS_CMD_NK); 3398 rtsx_trace(chip); 3399 return STATUS_FAIL; 3400 } 3401 if (val & INT_REG_ERR) { 3402 if (val & INT_REG_BREQ) { 3403 retval = ms_read_status_reg(chip); 3404 if (retval != STATUS_SUCCESS) { 3405 if (!(chip->card_wp & MS_CARD)) { 3406 reset_ms(chip); 3407 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE); 3408 ms_write_extra_data(chip, phy_blk, 3409 page_addr, extra, MS_EXTRA_SIZE); 3410 } 3411 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3412 rtsx_trace(chip); 3413 return STATUS_FAIL; 3414 } 3415 } else { 3416 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3417 rtsx_trace(chip); 3418 return STATUS_FAIL; 3419 } 3420 } else { 3421 if (!(val & INT_REG_BREQ)) { 3422 ms_set_err_code(chip, MS_BREQ_ERROR); 3423 rtsx_trace(chip); 3424 return STATUS_FAIL; 3425 } 3426 } 3427 3428 if (page_addr == (end_page - 1)) { 3429 if (!(val & INT_REG_CED)) { 3430 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3431 if (retval != STATUS_SUCCESS) { 3432 rtsx_trace(chip); 3433 return STATUS_FAIL; 3434 } 3435 } 3436 3437 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3438 &val, 1); 3439 if (retval != STATUS_SUCCESS) { 3440 rtsx_trace(chip); 3441 return STATUS_FAIL; 3442 } 3443 3444 if (!(val & INT_REG_CED)) { 3445 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3446 rtsx_trace(chip); 3447 return STATUS_FAIL; 3448 } 3449 3450 trans_cfg = NO_WAIT_INT; 3451 } else { 3452 trans_cfg = WAIT_INT; 3453 } 3454 3455 rtsx_init_cmd(chip); 3456 3457 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3458 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3459 0xFF, trans_cfg); 3460 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3461 0x01, RING_BUFFER); 3462 3463 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3464 3465 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3466 MS_TRANSFER_START | MS_TM_NORMAL_READ); 3467 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3468 MS_TRANSFER_END, MS_TRANSFER_END); 3469 3470 rtsx_send_cmd_no_wait(chip); 3471 3472 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3473 512, scsi_sg_count(chip->srb), 3474 index, offset, DMA_FROM_DEVICE, 3475 chip->ms_timeout); 3476 if (retval < 0) { 3477 if (retval == -ETIMEDOUT) { 3478 ms_set_err_code(chip, MS_TO_ERROR); 3479 rtsx_clear_ms_error(chip); 3480 rtsx_trace(chip); 3481 return STATUS_TIMEDOUT; 3482 } 3483 3484 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3485 if (retval != STATUS_SUCCESS) { 3486 ms_set_err_code(chip, MS_TO_ERROR); 3487 rtsx_clear_ms_error(chip); 3488 rtsx_trace(chip); 3489 return STATUS_TIMEDOUT; 3490 } 3491 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3492 ms_set_err_code(chip, MS_CRC16_ERROR); 3493 rtsx_clear_ms_error(chip); 3494 rtsx_trace(chip); 3495 return STATUS_FAIL; 3496 } 3497 } 3498 3499 if (scsi_sg_count(chip->srb) == 0) 3500 ptr += 512; 3501 } 3502 3503 return STATUS_SUCCESS; 3504 } 3505 3506 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3507 u16 new_blk, u16 log_blk, u8 start_page, 3508 u8 end_page, u8 *buf, unsigned int *index, 3509 unsigned int *offset) 3510 { 3511 struct ms_info *ms_card = &(chip->ms_card); 3512 int retval, i; 3513 u8 page_addr, val, data[16]; 3514 u8 *ptr; 3515 3516 if (!start_page) { 3517 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3518 SystemParm, 7); 3519 if (retval != STATUS_SUCCESS) { 3520 rtsx_trace(chip); 3521 return STATUS_FAIL; 3522 } 3523 3524 if (CHK_MS4BIT(ms_card)) 3525 data[0] = 0x88; 3526 else 3527 data[0] = 0x80; 3528 3529 data[1] = 0; 3530 data[2] = (u8)(old_blk >> 8); 3531 data[3] = (u8)old_blk; 3532 data[4] = 0x80; 3533 data[5] = 0; 3534 data[6] = 0xEF; 3535 data[7] = 0xFF; 3536 3537 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3538 data, 8); 3539 if (retval != STATUS_SUCCESS) { 3540 rtsx_trace(chip); 3541 return STATUS_FAIL; 3542 } 3543 3544 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3545 if (retval != STATUS_SUCCESS) { 3546 rtsx_trace(chip); 3547 return STATUS_FAIL; 3548 } 3549 3550 ms_set_err_code(chip, MS_NO_ERROR); 3551 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3552 NO_WAIT_INT); 3553 if (retval != STATUS_SUCCESS) { 3554 rtsx_trace(chip); 3555 return STATUS_FAIL; 3556 } 3557 } 3558 3559 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3560 SystemParm, (6 + MS_EXTRA_SIZE)); 3561 if (retval != STATUS_SUCCESS) { 3562 rtsx_trace(chip); 3563 return STATUS_FAIL; 3564 } 3565 3566 ms_set_err_code(chip, MS_NO_ERROR); 3567 3568 if (CHK_MS4BIT(ms_card)) 3569 data[0] = 0x88; 3570 else 3571 data[0] = 0x80; 3572 3573 data[1] = 0; 3574 data[2] = (u8)(new_blk >> 8); 3575 data[3] = (u8)new_blk; 3576 if ((end_page - start_page) == 1) 3577 data[4] = 0x20; 3578 else 3579 data[4] = 0; 3580 3581 data[5] = start_page; 3582 data[6] = 0xF8; 3583 data[7] = 0xFF; 3584 data[8] = (u8)(log_blk >> 8); 3585 data[9] = (u8)log_blk; 3586 3587 for (i = 0x0A; i < 0x10; i++) 3588 data[i] = 0xFF; 3589 3590 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3591 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3592 NO_WAIT_INT, data, 16); 3593 if (retval == STATUS_SUCCESS) 3594 break; 3595 } 3596 if (i == MS_MAX_RETRY_COUNT) { 3597 rtsx_trace(chip); 3598 return STATUS_FAIL; 3599 } 3600 3601 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3602 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3603 if (retval == STATUS_SUCCESS) 3604 break; 3605 } 3606 if (i == MS_MAX_RETRY_COUNT) { 3607 rtsx_trace(chip); 3608 return STATUS_FAIL; 3609 } 3610 3611 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3612 if (retval != STATUS_SUCCESS) { 3613 rtsx_trace(chip); 3614 return STATUS_FAIL; 3615 } 3616 3617 ptr = buf; 3618 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3619 ms_set_err_code(chip, MS_NO_ERROR); 3620 3621 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3622 ms_set_err_code(chip, MS_NO_CARD); 3623 rtsx_trace(chip); 3624 return STATUS_FAIL; 3625 } 3626 3627 if (val & INT_REG_CMDNK) { 3628 ms_set_err_code(chip, MS_CMD_NK); 3629 rtsx_trace(chip); 3630 return STATUS_FAIL; 3631 } 3632 if (val & INT_REG_ERR) { 3633 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3634 rtsx_trace(chip); 3635 return STATUS_FAIL; 3636 } 3637 if (!(val & INT_REG_BREQ)) { 3638 ms_set_err_code(chip, MS_BREQ_ERROR); 3639 rtsx_trace(chip); 3640 return STATUS_FAIL; 3641 } 3642 3643 udelay(30); 3644 3645 rtsx_init_cmd(chip); 3646 3647 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3648 0xFF, WRITE_PAGE_DATA); 3649 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3650 0xFF, WAIT_INT); 3651 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3652 0x01, RING_BUFFER); 3653 3654 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3655 3656 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3657 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3658 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3659 MS_TRANSFER_END, MS_TRANSFER_END); 3660 3661 rtsx_send_cmd_no_wait(chip); 3662 3663 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 3664 512, scsi_sg_count(chip->srb), 3665 index, offset, DMA_TO_DEVICE, 3666 chip->ms_timeout); 3667 if (retval < 0) { 3668 ms_set_err_code(chip, MS_TO_ERROR); 3669 rtsx_clear_ms_error(chip); 3670 3671 if (retval == -ETIMEDOUT) { 3672 rtsx_trace(chip); 3673 return STATUS_TIMEDOUT; 3674 } 3675 rtsx_trace(chip); 3676 return STATUS_FAIL; 3677 } 3678 3679 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3680 if (retval != STATUS_SUCCESS) { 3681 rtsx_trace(chip); 3682 return STATUS_FAIL; 3683 } 3684 3685 if ((end_page - start_page) == 1) { 3686 if (!(val & INT_REG_CED)) { 3687 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3688 rtsx_trace(chip); 3689 return STATUS_FAIL; 3690 } 3691 } else { 3692 if (page_addr == (end_page - 1)) { 3693 if (!(val & INT_REG_CED)) { 3694 retval = ms_send_cmd(chip, BLOCK_END, 3695 WAIT_INT); 3696 if (retval != STATUS_SUCCESS) { 3697 rtsx_trace(chip); 3698 return STATUS_FAIL; 3699 } 3700 } 3701 3702 retval = ms_read_bytes(chip, GET_INT, 1, 3703 NO_WAIT_INT, &val, 1); 3704 if (retval != STATUS_SUCCESS) { 3705 rtsx_trace(chip); 3706 return STATUS_FAIL; 3707 } 3708 } 3709 3710 if ((page_addr == (end_page - 1)) || 3711 (page_addr == ms_card->page_off)) { 3712 if (!(val & INT_REG_CED)) { 3713 ms_set_err_code(chip, 3714 MS_FLASH_WRITE_ERROR); 3715 rtsx_trace(chip); 3716 return STATUS_FAIL; 3717 } 3718 } 3719 } 3720 3721 if (scsi_sg_count(chip->srb) == 0) 3722 ptr += 512; 3723 } 3724 3725 return STATUS_SUCCESS; 3726 } 3727 3728 3729 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3730 u16 log_blk, u8 page_off) 3731 { 3732 struct ms_info *ms_card = &(chip->ms_card); 3733 int retval, seg_no; 3734 3735 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3736 page_off, ms_card->page_off + 1); 3737 if (retval != STATUS_SUCCESS) { 3738 rtsx_trace(chip); 3739 return STATUS_FAIL; 3740 } 3741 3742 seg_no = old_blk >> 9; 3743 3744 if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3745 MS_CLR_BAD_BLOCK_FLG(ms_card); 3746 ms_set_bad_block(chip, old_blk); 3747 } else { 3748 retval = ms_erase_block(chip, old_blk); 3749 if (retval == STATUS_SUCCESS) 3750 ms_set_unused_block(chip, old_blk); 3751 } 3752 3753 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3754 3755 return STATUS_SUCCESS; 3756 } 3757 3758 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3759 u16 log_blk, u8 start_page) 3760 { 3761 int retval; 3762 3763 if (start_page) { 3764 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3765 0, start_page); 3766 if (retval != STATUS_SUCCESS) { 3767 rtsx_trace(chip); 3768 return STATUS_FAIL; 3769 } 3770 } 3771 3772 return STATUS_SUCCESS; 3773 } 3774 3775 #ifdef MS_DELAY_WRITE 3776 int ms_delay_write(struct rtsx_chip *chip) 3777 { 3778 struct ms_info *ms_card = &(chip->ms_card); 3779 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write); 3780 int retval; 3781 3782 if (delay_write->delay_write_flag) { 3783 retval = ms_set_init_para(chip); 3784 if (retval != STATUS_SUCCESS) { 3785 rtsx_trace(chip); 3786 return STATUS_FAIL; 3787 } 3788 3789 delay_write->delay_write_flag = 0; 3790 retval = ms_finish_write(chip, 3791 delay_write->old_phyblock, 3792 delay_write->new_phyblock, 3793 delay_write->logblock, 3794 delay_write->pageoff); 3795 if (retval != STATUS_SUCCESS) { 3796 rtsx_trace(chip); 3797 return STATUS_FAIL; 3798 } 3799 } 3800 3801 return STATUS_SUCCESS; 3802 } 3803 #endif 3804 3805 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3806 { 3807 if (srb->sc_data_direction == DMA_FROM_DEVICE) 3808 set_sense_type(chip, SCSI_LUN(srb), 3809 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3810 else 3811 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3812 } 3813 3814 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3815 u32 start_sector, u16 sector_cnt) 3816 { 3817 struct ms_info *ms_card = &(chip->ms_card); 3818 unsigned int lun = SCSI_LUN(srb); 3819 int retval, seg_no; 3820 unsigned int index = 0, offset = 0; 3821 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3822 u8 start_page, end_page = 0, page_cnt; 3823 u8 *ptr; 3824 #ifdef MS_DELAY_WRITE 3825 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write); 3826 #endif 3827 3828 ms_set_err_code(chip, MS_NO_ERROR); 3829 3830 ms_card->cleanup_counter = 0; 3831 3832 ptr = (u8 *)scsi_sglist(srb); 3833 3834 retval = ms_switch_clock(chip); 3835 if (retval != STATUS_SUCCESS) { 3836 ms_rw_fail(srb, chip); 3837 rtsx_trace(chip); 3838 return STATUS_FAIL; 3839 } 3840 3841 log_blk = (u16)(start_sector >> ms_card->block_shift); 3842 start_page = (u8)(start_sector & ms_card->page_off); 3843 3844 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3845 if (log_blk < ms_start_idx[seg_no+1]) 3846 break; 3847 } 3848 3849 if (ms_card->segment[seg_no].build_flag == 0) { 3850 retval = ms_build_l2p_tbl(chip, seg_no); 3851 if (retval != STATUS_SUCCESS) { 3852 chip->card_fail |= MS_CARD; 3853 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3854 rtsx_trace(chip); 3855 return STATUS_FAIL; 3856 } 3857 } 3858 3859 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3860 #ifdef MS_DELAY_WRITE 3861 if (delay_write->delay_write_flag && 3862 (delay_write->logblock == log_blk) && 3863 (start_page > delay_write->pageoff)) { 3864 delay_write->delay_write_flag = 0; 3865 retval = ms_copy_page(chip, 3866 delay_write->old_phyblock, 3867 delay_write->new_phyblock, log_blk, 3868 delay_write->pageoff, start_page); 3869 if (retval != STATUS_SUCCESS) { 3870 set_sense_type(chip, lun, 3871 SENSE_TYPE_MEDIA_WRITE_ERR); 3872 rtsx_trace(chip); 3873 return STATUS_FAIL; 3874 } 3875 old_blk = delay_write->old_phyblock; 3876 new_blk = delay_write->new_phyblock; 3877 } else if (delay_write->delay_write_flag && 3878 (delay_write->logblock == log_blk) && 3879 (start_page == delay_write->pageoff)) { 3880 delay_write->delay_write_flag = 0; 3881 old_blk = delay_write->old_phyblock; 3882 new_blk = delay_write->new_phyblock; 3883 } else { 3884 retval = ms_delay_write(chip); 3885 if (retval != STATUS_SUCCESS) { 3886 set_sense_type(chip, lun, 3887 SENSE_TYPE_MEDIA_WRITE_ERR); 3888 rtsx_trace(chip); 3889 return STATUS_FAIL; 3890 } 3891 #endif 3892 old_blk = ms_get_l2p_tbl(chip, seg_no, 3893 log_blk - ms_start_idx[seg_no]); 3894 new_blk = ms_get_unused_block(chip, seg_no); 3895 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) { 3896 set_sense_type(chip, lun, 3897 SENSE_TYPE_MEDIA_WRITE_ERR); 3898 rtsx_trace(chip); 3899 return STATUS_FAIL; 3900 } 3901 3902 retval = ms_prepare_write(chip, old_blk, new_blk, 3903 log_blk, start_page); 3904 if (retval != STATUS_SUCCESS) { 3905 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3906 set_sense_type(chip, lun, 3907 SENSE_TYPE_MEDIA_NOT_PRESENT); 3908 rtsx_trace(chip); 3909 return STATUS_FAIL; 3910 } 3911 set_sense_type(chip, lun, 3912 SENSE_TYPE_MEDIA_WRITE_ERR); 3913 rtsx_trace(chip); 3914 return STATUS_FAIL; 3915 } 3916 #ifdef MS_DELAY_WRITE 3917 } 3918 #endif 3919 } else { 3920 #ifdef MS_DELAY_WRITE 3921 retval = ms_delay_write(chip); 3922 if (retval != STATUS_SUCCESS) { 3923 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3924 set_sense_type(chip, lun, 3925 SENSE_TYPE_MEDIA_NOT_PRESENT); 3926 rtsx_trace(chip); 3927 return STATUS_FAIL; 3928 } 3929 set_sense_type(chip, lun, 3930 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3931 rtsx_trace(chip); 3932 return STATUS_FAIL; 3933 } 3934 #endif 3935 old_blk = ms_get_l2p_tbl(chip, seg_no, 3936 log_blk - ms_start_idx[seg_no]); 3937 if (old_blk == 0xFFFF) { 3938 set_sense_type(chip, lun, 3939 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3940 rtsx_trace(chip); 3941 return STATUS_FAIL; 3942 } 3943 } 3944 3945 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3946 seg_no, old_blk, new_blk); 3947 3948 while (total_sec_cnt) { 3949 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3950 end_page = ms_card->page_off + 1; 3951 else 3952 end_page = start_page + (u8)total_sec_cnt; 3953 3954 page_cnt = end_page - start_page; 3955 3956 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3957 start_page, end_page, page_cnt); 3958 3959 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3960 retval = ms_read_multiple_pages(chip, 3961 old_blk, log_blk, start_page, end_page, 3962 ptr, &index, &offset); 3963 } else { 3964 retval = ms_write_multiple_pages(chip, old_blk, 3965 new_blk, log_blk, start_page, end_page, 3966 ptr, &index, &offset); 3967 } 3968 3969 if (retval != STATUS_SUCCESS) { 3970 toggle_gpio(chip, 1); 3971 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3972 set_sense_type(chip, lun, 3973 SENSE_TYPE_MEDIA_NOT_PRESENT); 3974 rtsx_trace(chip); 3975 return STATUS_FAIL; 3976 } 3977 ms_rw_fail(srb, chip); 3978 rtsx_trace(chip); 3979 return STATUS_FAIL; 3980 } 3981 3982 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3983 if (end_page == (ms_card->page_off + 1)) { 3984 retval = ms_erase_block(chip, old_blk); 3985 if (retval == STATUS_SUCCESS) 3986 ms_set_unused_block(chip, old_blk); 3987 3988 ms_set_l2p_tbl(chip, seg_no, 3989 log_blk - ms_start_idx[seg_no], 3990 new_blk); 3991 } 3992 } 3993 3994 total_sec_cnt -= page_cnt; 3995 if (scsi_sg_count(srb) == 0) 3996 ptr += page_cnt * 512; 3997 3998 if (total_sec_cnt == 0) 3999 break; 4000 4001 log_blk++; 4002 4003 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 4004 seg_no++) { 4005 if (log_blk < ms_start_idx[seg_no+1]) 4006 break; 4007 } 4008 4009 if (ms_card->segment[seg_no].build_flag == 0) { 4010 retval = ms_build_l2p_tbl(chip, seg_no); 4011 if (retval != STATUS_SUCCESS) { 4012 chip->card_fail |= MS_CARD; 4013 set_sense_type(chip, lun, 4014 SENSE_TYPE_MEDIA_NOT_PRESENT); 4015 rtsx_trace(chip); 4016 return STATUS_FAIL; 4017 } 4018 } 4019 4020 old_blk = ms_get_l2p_tbl(chip, seg_no, 4021 log_blk - ms_start_idx[seg_no]); 4022 if (old_blk == 0xFFFF) { 4023 ms_rw_fail(srb, chip); 4024 rtsx_trace(chip); 4025 return STATUS_FAIL; 4026 } 4027 4028 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4029 new_blk = ms_get_unused_block(chip, seg_no); 4030 if (new_blk == 0xFFFF) { 4031 ms_rw_fail(srb, chip); 4032 rtsx_trace(chip); 4033 return STATUS_FAIL; 4034 } 4035 } 4036 4037 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 4038 seg_no, old_blk, new_blk); 4039 4040 start_page = 0; 4041 } 4042 4043 if (srb->sc_data_direction == DMA_TO_DEVICE) { 4044 if (end_page < (ms_card->page_off + 1)) { 4045 #ifdef MS_DELAY_WRITE 4046 delay_write->delay_write_flag = 1; 4047 delay_write->old_phyblock = old_blk; 4048 delay_write->new_phyblock = new_blk; 4049 delay_write->logblock = log_blk; 4050 delay_write->pageoff = end_page; 4051 #else 4052 retval = ms_finish_write(chip, old_blk, new_blk, 4053 log_blk, end_page); 4054 if (retval != STATUS_SUCCESS) { 4055 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 4056 set_sense_type(chip, lun, 4057 SENSE_TYPE_MEDIA_NOT_PRESENT); 4058 rtsx_trace(chip); 4059 return STATUS_FAIL; 4060 } 4061 4062 ms_rw_fail(srb, chip); 4063 rtsx_trace(chip); 4064 return STATUS_FAIL; 4065 } 4066 #endif 4067 } 4068 } 4069 4070 scsi_set_resid(srb, 0); 4071 4072 return STATUS_SUCCESS; 4073 } 4074 4075 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 4076 u32 start_sector, u16 sector_cnt) 4077 { 4078 struct ms_info *ms_card = &(chip->ms_card); 4079 int retval; 4080 4081 if (CHK_MSPRO(ms_card)) 4082 retval = mspro_rw_multi_sector(srb, chip, start_sector, 4083 sector_cnt); 4084 else 4085 retval = ms_rw_multi_sector(srb, chip, start_sector, 4086 sector_cnt); 4087 4088 return retval; 4089 } 4090 4091 4092 void ms_free_l2p_tbl(struct rtsx_chip *chip) 4093 { 4094 struct ms_info *ms_card = &(chip->ms_card); 4095 int i = 0; 4096 4097 if (ms_card->segment != NULL) { 4098 for (i = 0; i < ms_card->segment_cnt; i++) { 4099 if (ms_card->segment[i].l2p_table != NULL) { 4100 vfree(ms_card->segment[i].l2p_table); 4101 ms_card->segment[i].l2p_table = NULL; 4102 } 4103 if (ms_card->segment[i].free_table != NULL) { 4104 vfree(ms_card->segment[i].free_table); 4105 ms_card->segment[i].free_table = NULL; 4106 } 4107 } 4108 vfree(ms_card->segment); 4109 ms_card->segment = NULL; 4110 } 4111 } 4112 4113 #ifdef SUPPORT_MAGIC_GATE 4114 4115 #ifdef READ_BYTES_WAIT_INT 4116 static int ms_poll_int(struct rtsx_chip *chip) 4117 { 4118 int retval; 4119 u8 val; 4120 4121 rtsx_init_cmd(chip); 4122 4123 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 4124 4125 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 4126 if (retval != STATUS_SUCCESS) { 4127 rtsx_trace(chip); 4128 return STATUS_FAIL; 4129 } 4130 4131 val = *rtsx_get_cmd_data(chip); 4132 if (val & MS_INT_ERR) { 4133 rtsx_trace(chip); 4134 return STATUS_FAIL; 4135 } 4136 4137 return STATUS_SUCCESS; 4138 } 4139 #endif 4140 4141 #ifdef MS_SAMPLE_INT_ERR 4142 static int check_ms_err(struct rtsx_chip *chip) 4143 { 4144 int retval; 4145 u8 val; 4146 4147 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4148 if (retval != STATUS_SUCCESS) 4149 return 1; 4150 if (val & MS_TRANSFER_ERR) 4151 return 1; 4152 4153 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 4154 if (retval != STATUS_SUCCESS) 4155 return 1; 4156 4157 if (val & (MS_INT_ERR | MS_INT_CMDNK)) 4158 return 1; 4159 4160 return 0; 4161 } 4162 #else 4163 static int check_ms_err(struct rtsx_chip *chip) 4164 { 4165 int retval; 4166 u8 val; 4167 4168 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 4169 if (retval != STATUS_SUCCESS) 4170 return 1; 4171 if (val & MS_TRANSFER_ERR) 4172 return 1; 4173 4174 return 0; 4175 } 4176 #endif 4177 4178 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 4179 { 4180 int retval, i; 4181 u8 data[8]; 4182 4183 data[0] = cmd; 4184 data[1] = 0; 4185 data[2] = 0; 4186 data[3] = 0; 4187 data[4] = 0; 4188 data[5] = 0; 4189 data[6] = entry_num; 4190 data[7] = 0; 4191 4192 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 4193 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 4194 data, 8); 4195 if (retval == STATUS_SUCCESS) 4196 break; 4197 } 4198 if (i == MS_MAX_RETRY_COUNT) { 4199 rtsx_trace(chip); 4200 return STATUS_FAIL; 4201 } 4202 4203 if (check_ms_err(chip)) { 4204 rtsx_clear_ms_error(chip); 4205 rtsx_trace(chip); 4206 return STATUS_FAIL; 4207 } 4208 4209 return STATUS_SUCCESS; 4210 } 4211 4212 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 4213 u8 mg_entry_num) 4214 { 4215 int retval; 4216 u8 buf[6]; 4217 4218 if (type == 0) 4219 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1); 4220 else 4221 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 4222 4223 if (retval != STATUS_SUCCESS) { 4224 rtsx_trace(chip); 4225 return STATUS_FAIL; 4226 } 4227 4228 buf[0] = 0; 4229 buf[1] = 0; 4230 if (type == 1) { 4231 buf[2] = 0; 4232 buf[3] = 0; 4233 buf[4] = 0; 4234 buf[5] = mg_entry_num; 4235 } 4236 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 4237 NO_WAIT_INT, buf, 6); 4238 if (retval != STATUS_SUCCESS) { 4239 rtsx_trace(chip); 4240 return STATUS_FAIL; 4241 } 4242 4243 return STATUS_SUCCESS; 4244 } 4245 4246 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4247 { 4248 int retval; 4249 int i; 4250 unsigned int lun = SCSI_LUN(srb); 4251 u8 buf1[32], buf2[12]; 4252 4253 if (scsi_bufflen(srb) < 12) { 4254 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 4255 rtsx_trace(chip); 4256 return STATUS_FAIL; 4257 } 4258 4259 ms_cleanup_work(chip); 4260 4261 retval = ms_switch_clock(chip); 4262 if (retval != STATUS_SUCCESS) { 4263 rtsx_trace(chip); 4264 return STATUS_FAIL; 4265 } 4266 4267 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 4268 if (retval != STATUS_SUCCESS) { 4269 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4270 rtsx_trace(chip); 4271 return STATUS_FAIL; 4272 } 4273 4274 memset(buf1, 0, 32); 4275 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 4276 for (i = 0; i < 8; i++) 4277 buf1[8+i] = buf2[4+i]; 4278 4279 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4280 buf1, 32); 4281 if (retval != STATUS_SUCCESS) { 4282 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4283 rtsx_trace(chip); 4284 return STATUS_FAIL; 4285 } 4286 if (check_ms_err(chip)) { 4287 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4288 rtsx_clear_ms_error(chip); 4289 rtsx_trace(chip); 4290 return STATUS_FAIL; 4291 } 4292 4293 return STATUS_SUCCESS; 4294 } 4295 4296 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4297 { 4298 int retval = STATUS_FAIL; 4299 int bufflen; 4300 unsigned int lun = SCSI_LUN(srb); 4301 u8 *buf = NULL; 4302 4303 ms_cleanup_work(chip); 4304 4305 retval = ms_switch_clock(chip); 4306 if (retval != STATUS_SUCCESS) { 4307 rtsx_trace(chip); 4308 return STATUS_FAIL; 4309 } 4310 4311 buf = kmalloc(1540, GFP_KERNEL); 4312 if (!buf) { 4313 rtsx_trace(chip); 4314 return STATUS_ERROR; 4315 } 4316 4317 buf[0] = 0x04; 4318 buf[1] = 0x1A; 4319 buf[2] = 0x00; 4320 buf[3] = 0x00; 4321 4322 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 4323 if (retval != STATUS_SUCCESS) { 4324 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4325 rtsx_trace(chip); 4326 goto GetEKBFinish; 4327 } 4328 4329 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4330 3, WAIT_INT, 0, 0, buf + 4, 1536); 4331 if (retval != STATUS_SUCCESS) { 4332 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4333 rtsx_clear_ms_error(chip); 4334 rtsx_trace(chip); 4335 goto GetEKBFinish; 4336 } 4337 if (check_ms_err(chip)) { 4338 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4339 rtsx_clear_ms_error(chip); 4340 rtsx_trace(chip); 4341 return STATUS_FAIL; 4342 } 4343 4344 bufflen = min_t(int, 1052, scsi_bufflen(srb)); 4345 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4346 4347 GetEKBFinish: 4348 kfree(buf); 4349 return retval; 4350 } 4351 4352 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4353 { 4354 struct ms_info *ms_card = &(chip->ms_card); 4355 int retval; 4356 int bufflen; 4357 int i; 4358 unsigned int lun = SCSI_LUN(srb); 4359 u8 buf[32]; 4360 4361 ms_cleanup_work(chip); 4362 4363 retval = ms_switch_clock(chip); 4364 if (retval != STATUS_SUCCESS) { 4365 rtsx_trace(chip); 4366 return STATUS_FAIL; 4367 } 4368 4369 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 4370 if (retval != STATUS_SUCCESS) { 4371 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4372 rtsx_trace(chip); 4373 return STATUS_FAIL; 4374 } 4375 4376 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4377 buf, 32); 4378 if (retval != STATUS_SUCCESS) { 4379 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4380 rtsx_trace(chip); 4381 return STATUS_FAIL; 4382 } 4383 if (check_ms_err(chip)) { 4384 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4385 rtsx_clear_ms_error(chip); 4386 rtsx_trace(chip); 4387 return STATUS_FAIL; 4388 } 4389 4390 memcpy(ms_card->magic_gate_id, buf, 16); 4391 4392 #ifdef READ_BYTES_WAIT_INT 4393 retval = ms_poll_int(chip); 4394 if (retval != STATUS_SUCCESS) { 4395 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4396 rtsx_trace(chip); 4397 return STATUS_FAIL; 4398 } 4399 #endif 4400 4401 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 4402 if (retval != STATUS_SUCCESS) { 4403 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4404 rtsx_trace(chip); 4405 return STATUS_FAIL; 4406 } 4407 4408 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4409 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4410 4411 for (i = 0; i < 8; i++) 4412 buf[i] = buf[4+i]; 4413 4414 for (i = 0; i < 24; i++) 4415 buf[8+i] = 0; 4416 4417 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 4418 32, WAIT_INT, buf, 32); 4419 if (retval != STATUS_SUCCESS) { 4420 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4421 rtsx_trace(chip); 4422 return STATUS_FAIL; 4423 } 4424 if (check_ms_err(chip)) { 4425 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 4426 rtsx_clear_ms_error(chip); 4427 rtsx_trace(chip); 4428 return STATUS_FAIL; 4429 } 4430 4431 ms_card->mg_auth = 0; 4432 4433 return STATUS_SUCCESS; 4434 } 4435 4436 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4437 { 4438 struct ms_info *ms_card = &(chip->ms_card); 4439 int retval; 4440 int bufflen; 4441 unsigned int lun = SCSI_LUN(srb); 4442 u8 buf1[32], buf2[36]; 4443 4444 ms_cleanup_work(chip); 4445 4446 retval = ms_switch_clock(chip); 4447 if (retval != STATUS_SUCCESS) { 4448 rtsx_trace(chip); 4449 return STATUS_FAIL; 4450 } 4451 4452 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 4453 if (retval != STATUS_SUCCESS) { 4454 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4455 rtsx_trace(chip); 4456 return STATUS_FAIL; 4457 } 4458 4459 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 4460 buf1, 32); 4461 if (retval != STATUS_SUCCESS) { 4462 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4463 rtsx_trace(chip); 4464 return STATUS_FAIL; 4465 } 4466 if (check_ms_err(chip)) { 4467 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4468 rtsx_clear_ms_error(chip); 4469 rtsx_trace(chip); 4470 return STATUS_FAIL; 4471 } 4472 4473 buf2[0] = 0x00; 4474 buf2[1] = 0x22; 4475 buf2[2] = 0x00; 4476 buf2[3] = 0x00; 4477 4478 memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4479 memcpy(buf2 + 20, buf1, 16); 4480 4481 bufflen = min_t(int, 36, scsi_bufflen(srb)); 4482 rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4483 4484 #ifdef READ_BYTES_WAIT_INT 4485 retval = ms_poll_int(chip); 4486 if (retval != STATUS_SUCCESS) { 4487 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4488 rtsx_trace(chip); 4489 return STATUS_FAIL; 4490 } 4491 #endif 4492 4493 return STATUS_SUCCESS; 4494 } 4495 4496 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4497 { 4498 struct ms_info *ms_card = &(chip->ms_card); 4499 int retval; 4500 int i; 4501 int bufflen; 4502 unsigned int lun = SCSI_LUN(srb); 4503 u8 buf[32]; 4504 4505 ms_cleanup_work(chip); 4506 4507 retval = ms_switch_clock(chip); 4508 if (retval != STATUS_SUCCESS) { 4509 rtsx_trace(chip); 4510 return STATUS_FAIL; 4511 } 4512 4513 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4514 if (retval != STATUS_SUCCESS) { 4515 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4516 rtsx_trace(chip); 4517 return STATUS_FAIL; 4518 } 4519 4520 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4521 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4522 4523 for (i = 0; i < 8; i++) 4524 buf[i] = buf[4+i]; 4525 4526 for (i = 0; i < 24; i++) 4527 buf[8+i] = 0; 4528 4529 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4530 buf, 32); 4531 if (retval != STATUS_SUCCESS) { 4532 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4533 rtsx_trace(chip); 4534 return STATUS_FAIL; 4535 } 4536 if (check_ms_err(chip)) { 4537 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4538 rtsx_clear_ms_error(chip); 4539 rtsx_trace(chip); 4540 return STATUS_FAIL; 4541 } 4542 4543 ms_card->mg_auth = 1; 4544 4545 return STATUS_SUCCESS; 4546 } 4547 4548 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4549 { 4550 struct ms_info *ms_card = &(chip->ms_card); 4551 int retval; 4552 int bufflen; 4553 unsigned int lun = SCSI_LUN(srb); 4554 u8 *buf = NULL; 4555 4556 ms_cleanup_work(chip); 4557 4558 retval = ms_switch_clock(chip); 4559 if (retval != STATUS_SUCCESS) { 4560 rtsx_trace(chip); 4561 return STATUS_FAIL; 4562 } 4563 4564 buf = kmalloc(1028, GFP_KERNEL); 4565 if (!buf) { 4566 rtsx_trace(chip); 4567 return STATUS_ERROR; 4568 } 4569 4570 buf[0] = 0x04; 4571 buf[1] = 0x02; 4572 buf[2] = 0x00; 4573 buf[3] = 0x00; 4574 4575 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4576 if (retval != STATUS_SUCCESS) { 4577 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4578 rtsx_trace(chip); 4579 goto GetICVFinish; 4580 } 4581 4582 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4583 2, WAIT_INT, 0, 0, buf + 4, 1024); 4584 if (retval != STATUS_SUCCESS) { 4585 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4586 rtsx_clear_ms_error(chip); 4587 rtsx_trace(chip); 4588 goto GetICVFinish; 4589 } 4590 if (check_ms_err(chip)) { 4591 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4592 rtsx_clear_ms_error(chip); 4593 rtsx_trace(chip); 4594 return STATUS_FAIL; 4595 } 4596 4597 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4598 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4599 4600 GetICVFinish: 4601 kfree(buf); 4602 return retval; 4603 } 4604 4605 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4606 { 4607 struct ms_info *ms_card = &(chip->ms_card); 4608 int retval; 4609 int bufflen; 4610 #ifdef MG_SET_ICV_SLOW 4611 int i; 4612 #endif 4613 unsigned int lun = SCSI_LUN(srb); 4614 u8 *buf = NULL; 4615 4616 ms_cleanup_work(chip); 4617 4618 retval = ms_switch_clock(chip); 4619 if (retval != STATUS_SUCCESS) { 4620 rtsx_trace(chip); 4621 return STATUS_FAIL; 4622 } 4623 4624 buf = kmalloc(1028, GFP_KERNEL); 4625 if (!buf) { 4626 rtsx_trace(chip); 4627 return STATUS_ERROR; 4628 } 4629 4630 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4631 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4632 4633 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4634 if (retval != STATUS_SUCCESS) { 4635 if (ms_card->mg_auth == 0) { 4636 if ((buf[5] & 0xC0) != 0) 4637 set_sense_type(chip, lun, 4638 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4639 else 4640 set_sense_type(chip, lun, 4641 SENSE_TYPE_MG_WRITE_ERR); 4642 } else { 4643 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4644 } 4645 rtsx_trace(chip); 4646 goto SetICVFinish; 4647 } 4648 4649 #ifdef MG_SET_ICV_SLOW 4650 for (i = 0; i < 2; i++) { 4651 udelay(50); 4652 4653 rtsx_init_cmd(chip); 4654 4655 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4656 0xFF, PRO_WRITE_LONG_DATA); 4657 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4658 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4659 0x01, RING_BUFFER); 4660 4661 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4662 4663 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4664 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4665 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4666 MS_TRANSFER_END, MS_TRANSFER_END); 4667 4668 rtsx_send_cmd_no_wait(chip); 4669 4670 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512, 4671 512, 0, DMA_TO_DEVICE, 3000); 4672 if ((retval < 0) || check_ms_err(chip)) { 4673 rtsx_clear_ms_error(chip); 4674 if (ms_card->mg_auth == 0) { 4675 if ((buf[5] & 0xC0) != 0) 4676 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4677 else 4678 set_sense_type(chip, lun, 4679 SENSE_TYPE_MG_WRITE_ERR); 4680 } else { 4681 set_sense_type(chip, lun, 4682 SENSE_TYPE_MG_WRITE_ERR); 4683 } 4684 retval = STATUS_FAIL; 4685 rtsx_trace(chip); 4686 goto SetICVFinish; 4687 } 4688 } 4689 #else 4690 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4691 2, WAIT_INT, 0, 0, buf + 4, 1024); 4692 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) { 4693 rtsx_clear_ms_error(chip); 4694 if (ms_card->mg_auth == 0) { 4695 if ((buf[5] & 0xC0) != 0) 4696 set_sense_type(chip, lun, 4697 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4698 else 4699 set_sense_type(chip, lun, 4700 SENSE_TYPE_MG_WRITE_ERR); 4701 } else { 4702 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4703 } 4704 rtsx_trace(chip); 4705 goto SetICVFinish; 4706 } 4707 #endif 4708 4709 SetICVFinish: 4710 kfree(buf); 4711 return retval; 4712 } 4713 4714 #endif /* SUPPORT_MAGIC_GATE */ 4715 4716 void ms_cleanup_work(struct rtsx_chip *chip) 4717 { 4718 struct ms_info *ms_card = &(chip->ms_card); 4719 4720 if (CHK_MSPRO(ms_card)) { 4721 if (ms_card->seq_mode) { 4722 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4723 mspro_stop_seq_mode(chip); 4724 ms_card->cleanup_counter = 0; 4725 } 4726 if (CHK_MSHG(ms_card)) { 4727 rtsx_write_register(chip, MS_CFG, 4728 MS_2K_SECTOR_MODE, 0x00); 4729 } 4730 } 4731 #ifdef MS_DELAY_WRITE 4732 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) { 4733 dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4734 ms_delay_write(chip); 4735 ms_card->cleanup_counter = 0; 4736 } 4737 #endif 4738 } 4739 4740 int ms_power_off_card3v3(struct rtsx_chip *chip) 4741 { 4742 int retval; 4743 4744 retval = disable_card_clock(chip, MS_CARD); 4745 if (retval != STATUS_SUCCESS) { 4746 rtsx_trace(chip); 4747 return STATUS_FAIL; 4748 } 4749 4750 if (chip->asic_code) { 4751 retval = ms_pull_ctl_disable(chip); 4752 if (retval != STATUS_SUCCESS) { 4753 rtsx_trace(chip); 4754 return STATUS_FAIL; 4755 } 4756 } else { 4757 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4758 FPGA_MS_PULL_CTL_BIT | 0x20, 4759 FPGA_MS_PULL_CTL_BIT); 4760 if (retval) { 4761 rtsx_trace(chip); 4762 return retval; 4763 } 4764 } 4765 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4766 if (retval) { 4767 rtsx_trace(chip); 4768 return retval; 4769 } 4770 if (!chip->ft2_fast_mode) { 4771 retval = card_power_off(chip, MS_CARD); 4772 if (retval != STATUS_SUCCESS) { 4773 rtsx_trace(chip); 4774 return STATUS_FAIL; 4775 } 4776 } 4777 4778 return STATUS_SUCCESS; 4779 } 4780 4781 int release_ms_card(struct rtsx_chip *chip) 4782 { 4783 struct ms_info *ms_card = &(chip->ms_card); 4784 int retval; 4785 4786 #ifdef MS_DELAY_WRITE 4787 ms_card->delay_write.delay_write_flag = 0; 4788 #endif 4789 ms_card->pro_under_formatting = 0; 4790 4791 chip->card_ready &= ~MS_CARD; 4792 chip->card_fail &= ~MS_CARD; 4793 chip->card_wp &= ~MS_CARD; 4794 4795 ms_free_l2p_tbl(chip); 4796 4797 memset(ms_card->raw_sys_info, 0, 96); 4798 #ifdef SUPPORT_PCGL_1P18 4799 memset(ms_card->raw_model_name, 0, 48); 4800 #endif 4801 4802 retval = ms_power_off_card3v3(chip); 4803 if (retval != STATUS_SUCCESS) { 4804 rtsx_trace(chip); 4805 return STATUS_FAIL; 4806 } 4807 4808 return STATUS_SUCCESS; 4809 } 4810