1 /* Driver for Realtek PCI-Express card reader 2 * 3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2, or (at your option) any 8 * later version. 9 * 10 * This program is distributed in the hope that it will be useful, but 11 * WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 * General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, see <http://www.gnu.org/licenses/>. 17 * 18 * Author: 19 * Wei WANG (wei_wang@realsil.com.cn) 20 * Micky Ching (micky_ching@realsil.com.cn) 21 */ 22 23 #include <linux/blkdev.h> 24 #include <linux/kthread.h> 25 #include <linux/sched.h> 26 #include <linux/vmalloc.h> 27 28 #include "rtsx.h" 29 #include "ms.h" 30 31 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code) 32 { 33 struct ms_info *ms_card = &chip->ms_card; 34 35 ms_card->err_code = err_code; 36 } 37 38 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code) 39 { 40 struct ms_info *ms_card = &chip->ms_card; 41 42 return (ms_card->err_code == err_code); 43 } 44 45 static int ms_parse_err_code(struct rtsx_chip *chip) 46 { 47 return STATUS_FAIL; 48 } 49 50 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode, 51 u8 tpc, u8 cnt, u8 cfg) 52 { 53 struct ms_info *ms_card = &chip->ms_card; 54 int retval; 55 u8 *ptr; 56 57 dev_dbg(rtsx_dev(chip), "%s: tpc = 0x%x\n", __func__, tpc); 58 59 rtsx_init_cmd(chip); 60 61 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 62 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 63 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 64 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 65 0x01, PINGPONG_BUFFER); 66 67 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 68 0xFF, MS_TRANSFER_START | trans_mode); 69 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 70 MS_TRANSFER_END, MS_TRANSFER_END); 71 72 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0); 73 74 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 75 if (retval < 0) { 76 rtsx_clear_ms_error(chip); 77 ms_set_err_code(chip, MS_TO_ERROR); 78 return ms_parse_err_code(chip); 79 } 80 81 ptr = rtsx_get_cmd_data(chip) + 1; 82 83 if (!(tpc & 0x08)) { /* Read Packet */ 84 if (*ptr & MS_CRC16_ERR) { 85 ms_set_err_code(chip, MS_CRC16_ERROR); 86 return ms_parse_err_code(chip); 87 } 88 } else { /* Write Packet */ 89 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) { 90 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) { 91 ms_set_err_code(chip, MS_CMD_NK); 92 return ms_parse_err_code(chip); 93 } 94 } 95 } 96 97 if (*ptr & MS_RDY_TIMEOUT) { 98 rtsx_clear_ms_error(chip); 99 ms_set_err_code(chip, MS_TO_ERROR); 100 return ms_parse_err_code(chip); 101 } 102 103 return STATUS_SUCCESS; 104 } 105 106 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode, 107 u8 tpc, u16 sec_cnt, u8 cfg, bool mode_2k, 108 int use_sg, void *buf, int buf_len) 109 { 110 int retval; 111 u8 val, err_code = 0; 112 enum dma_data_direction dir; 113 114 if (!buf || !buf_len) 115 return STATUS_FAIL; 116 117 if (trans_mode == MS_TM_AUTO_READ) { 118 dir = DMA_FROM_DEVICE; 119 err_code = MS_FLASH_READ_ERROR; 120 } else if (trans_mode == MS_TM_AUTO_WRITE) { 121 dir = DMA_TO_DEVICE; 122 err_code = MS_FLASH_WRITE_ERROR; 123 } else { 124 return STATUS_FAIL; 125 } 126 127 rtsx_init_cmd(chip); 128 129 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 130 rtsx_add_cmd(chip, WRITE_REG_CMD, 131 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8)); 132 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt); 133 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 134 135 if (mode_2k) { 136 rtsx_add_cmd(chip, WRITE_REG_CMD, 137 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE); 138 } else { 139 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0); 140 } 141 142 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512); 143 144 rtsx_add_cmd(chip, WRITE_REG_CMD, 145 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode); 146 rtsx_add_cmd(chip, CHECK_REG_CMD, 147 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 148 149 rtsx_send_cmd_no_wait(chip); 150 151 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len, 152 use_sg, dir, chip->mspro_timeout); 153 if (retval < 0) { 154 ms_set_err_code(chip, err_code); 155 if (retval == -ETIMEDOUT) 156 retval = STATUS_TIMEDOUT; 157 else 158 retval = STATUS_FAIL; 159 160 return retval; 161 } 162 163 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 164 if (retval) 165 return retval; 166 167 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT)) 168 return STATUS_FAIL; 169 170 return STATUS_SUCCESS; 171 } 172 173 static int ms_write_bytes(struct rtsx_chip *chip, 174 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 175 { 176 struct ms_info *ms_card = &chip->ms_card; 177 int retval, i; 178 179 if (!data || (data_len < cnt)) 180 return STATUS_ERROR; 181 182 rtsx_init_cmd(chip); 183 184 for (i = 0; i < cnt; i++) { 185 rtsx_add_cmd(chip, WRITE_REG_CMD, 186 PPBUF_BASE2 + i, 0xFF, data[i]); 187 } 188 if (cnt % 2) 189 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF); 190 191 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 192 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 193 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 194 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 195 0x01, PINGPONG_BUFFER); 196 197 rtsx_add_cmd(chip, WRITE_REG_CMD, 198 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES); 199 rtsx_add_cmd(chip, CHECK_REG_CMD, 200 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END); 201 202 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 203 if (retval < 0) { 204 u8 val = 0; 205 206 rtsx_read_register(chip, MS_TRANS_CFG, &val); 207 dev_dbg(rtsx_dev(chip), "MS_TRANS_CFG: 0x%02x\n", val); 208 209 rtsx_clear_ms_error(chip); 210 211 if (!(tpc & 0x08)) { 212 if (val & MS_CRC16_ERR) { 213 ms_set_err_code(chip, MS_CRC16_ERROR); 214 return ms_parse_err_code(chip); 215 } 216 } else { 217 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 218 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 219 ms_set_err_code(chip, MS_CMD_NK); 220 return ms_parse_err_code(chip); 221 } 222 } 223 } 224 225 if (val & MS_RDY_TIMEOUT) { 226 ms_set_err_code(chip, MS_TO_ERROR); 227 return ms_parse_err_code(chip); 228 } 229 230 ms_set_err_code(chip, MS_TO_ERROR); 231 return ms_parse_err_code(chip); 232 } 233 234 return STATUS_SUCCESS; 235 } 236 237 static int ms_read_bytes(struct rtsx_chip *chip, 238 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len) 239 { 240 struct ms_info *ms_card = &chip->ms_card; 241 int retval, i; 242 u8 *ptr; 243 244 if (!data) 245 return STATUS_ERROR; 246 247 rtsx_init_cmd(chip); 248 249 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc); 250 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt); 251 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg); 252 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 253 0x01, PINGPONG_BUFFER); 254 255 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 256 MS_TRANSFER_START | MS_TM_READ_BYTES); 257 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 258 MS_TRANSFER_END, MS_TRANSFER_END); 259 260 for (i = 0; i < data_len - 1; i++) 261 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0); 262 263 if (data_len % 2) 264 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0); 265 else 266 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1, 267 0, 0); 268 269 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 270 if (retval < 0) { 271 u8 val = 0; 272 273 rtsx_read_register(chip, MS_TRANS_CFG, &val); 274 rtsx_clear_ms_error(chip); 275 276 if (!(tpc & 0x08)) { 277 if (val & MS_CRC16_ERR) { 278 ms_set_err_code(chip, MS_CRC16_ERROR); 279 return ms_parse_err_code(chip); 280 } 281 } else { 282 if (CHK_MSPRO(ms_card) && !(val & 0x80)) { 283 if (val & (MS_INT_ERR | MS_INT_CMDNK)) { 284 ms_set_err_code(chip, MS_CMD_NK); 285 return ms_parse_err_code(chip); 286 } 287 } 288 } 289 290 if (val & MS_RDY_TIMEOUT) { 291 ms_set_err_code(chip, MS_TO_ERROR); 292 return ms_parse_err_code(chip); 293 } 294 295 ms_set_err_code(chip, MS_TO_ERROR); 296 return ms_parse_err_code(chip); 297 } 298 299 ptr = rtsx_get_cmd_data(chip) + 1; 300 301 for (i = 0; i < data_len; i++) 302 data[i] = ptr[i]; 303 304 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) { 305 dev_dbg(rtsx_dev(chip), "Read format progress:\n"); 306 print_hex_dump_bytes(KBUILD_MODNAME ": ", DUMP_PREFIX_NONE, ptr, 307 cnt); 308 } 309 310 return STATUS_SUCCESS; 311 } 312 313 static int ms_set_rw_reg_addr(struct rtsx_chip *chip, u8 read_start, 314 u8 read_cnt, u8 write_start, u8 write_cnt) 315 { 316 int retval, i; 317 u8 data[4]; 318 319 data[0] = read_start; 320 data[1] = read_cnt; 321 data[2] = write_start; 322 data[3] = write_cnt; 323 324 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 325 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4, 326 NO_WAIT_INT, data, 4); 327 if (retval == STATUS_SUCCESS) 328 return STATUS_SUCCESS; 329 rtsx_clear_ms_error(chip); 330 } 331 332 return STATUS_FAIL; 333 } 334 335 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg) 336 { 337 u8 data[2]; 338 339 data[0] = cmd; 340 data[1] = 0; 341 342 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1); 343 } 344 345 static int ms_set_init_para(struct rtsx_chip *chip) 346 { 347 struct ms_info *ms_card = &chip->ms_card; 348 int retval; 349 350 if (CHK_HG8BIT(ms_card)) { 351 if (chip->asic_code) 352 ms_card->ms_clock = chip->asic_ms_hg_clk; 353 else 354 ms_card->ms_clock = chip->fpga_ms_hg_clk; 355 356 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) { 357 if (chip->asic_code) 358 ms_card->ms_clock = chip->asic_ms_4bit_clk; 359 else 360 ms_card->ms_clock = chip->fpga_ms_4bit_clk; 361 362 } else { 363 if (chip->asic_code) 364 ms_card->ms_clock = chip->asic_ms_1bit_clk; 365 else 366 ms_card->ms_clock = chip->fpga_ms_1bit_clk; 367 } 368 369 retval = switch_clock(chip, ms_card->ms_clock); 370 if (retval != STATUS_SUCCESS) 371 return STATUS_FAIL; 372 373 retval = select_card(chip, MS_CARD); 374 if (retval != STATUS_SUCCESS) 375 return STATUS_FAIL; 376 377 return STATUS_SUCCESS; 378 } 379 380 static int ms_switch_clock(struct rtsx_chip *chip) 381 { 382 struct ms_info *ms_card = &chip->ms_card; 383 int retval; 384 385 retval = select_card(chip, MS_CARD); 386 if (retval != STATUS_SUCCESS) 387 return STATUS_FAIL; 388 389 retval = switch_clock(chip, ms_card->ms_clock); 390 if (retval != STATUS_SUCCESS) 391 return STATUS_FAIL; 392 393 return STATUS_SUCCESS; 394 } 395 396 static int ms_pull_ctl_disable(struct rtsx_chip *chip) 397 { 398 int retval; 399 400 if (CHECK_PID(chip, 0x5208)) { 401 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF, 402 MS_D1_PD | MS_D2_PD | MS_CLK_PD | 403 MS_D6_PD); 404 if (retval) 405 return retval; 406 407 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 408 MS_D3_PD | MS_D0_PD | MS_BS_PD | 409 XD_D4_PD); 410 if (retval) 411 return retval; 412 413 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF, 414 MS_D7_PD | XD_CE_PD | XD_CLE_PD | 415 XD_CD_PU); 416 if (retval) 417 return retval; 418 419 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF, 420 XD_RDY_PD | SD_D3_PD | SD_D2_PD | 421 XD_ALE_PD); 422 if (retval) 423 return retval; 424 425 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF, 426 MS_INS_PU | SD_WP_PD | SD_CD_PU | 427 SD_CMD_PD); 428 if (retval) 429 return retval; 430 431 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF, 432 MS_D5_PD | MS_D4_PD); 433 if (retval) 434 return retval; 435 436 } else if (CHECK_PID(chip, 0x5288)) { 437 if (CHECK_BARO_PKG(chip, QFN)) { 438 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 439 0xFF, 0x55); 440 if (retval) 441 return retval; 442 443 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 444 0xFF, 0x55); 445 if (retval) 446 return retval; 447 448 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 449 0xFF, 0x4B); 450 if (retval) 451 return retval; 452 453 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 454 0xFF, 0x69); 455 if (retval) 456 return retval; 457 } 458 } 459 460 return STATUS_SUCCESS; 461 } 462 463 static int ms_pull_ctl_enable(struct rtsx_chip *chip) 464 { 465 int retval; 466 467 rtsx_init_cmd(chip); 468 469 if (CHECK_PID(chip, 0x5208)) { 470 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 471 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD); 472 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 473 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD); 474 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 475 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU); 476 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 477 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD); 478 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 479 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD); 480 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 481 MS_D5_PD | MS_D4_PD); 482 } else if (CHECK_PID(chip, 0x5288)) { 483 if (CHECK_BARO_PKG(chip, QFN)) { 484 rtsx_add_cmd(chip, WRITE_REG_CMD, 485 CARD_PULL_CTL1, 0xFF, 0x55); 486 rtsx_add_cmd(chip, WRITE_REG_CMD, 487 CARD_PULL_CTL2, 0xFF, 0x45); 488 rtsx_add_cmd(chip, WRITE_REG_CMD, 489 CARD_PULL_CTL3, 0xFF, 0x4B); 490 rtsx_add_cmd(chip, WRITE_REG_CMD, 491 CARD_PULL_CTL4, 0xFF, 0x29); 492 } 493 } 494 495 retval = rtsx_send_cmd(chip, MS_CARD, 100); 496 if (retval < 0) 497 return STATUS_FAIL; 498 499 return STATUS_SUCCESS; 500 } 501 502 static int ms_prepare_reset(struct rtsx_chip *chip) 503 { 504 struct ms_info *ms_card = &chip->ms_card; 505 int retval; 506 u8 oc_mask = 0; 507 508 ms_card->ms_type = 0; 509 ms_card->check_ms_flow = 0; 510 ms_card->switch_8bit_fail = 0; 511 ms_card->delay_write.delay_write_flag = 0; 512 513 ms_card->pro_under_formatting = 0; 514 515 retval = ms_power_off_card3v3(chip); 516 if (retval != STATUS_SUCCESS) 517 return STATUS_FAIL; 518 519 if (!chip->ft2_fast_mode) 520 wait_timeout(250); 521 522 retval = enable_card_clock(chip, MS_CARD); 523 if (retval != STATUS_SUCCESS) 524 return STATUS_FAIL; 525 526 if (chip->asic_code) { 527 retval = ms_pull_ctl_enable(chip); 528 if (retval != STATUS_SUCCESS) 529 return STATUS_FAIL; 530 } else { 531 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 532 FPGA_MS_PULL_CTL_BIT | 0x20, 0); 533 if (retval) 534 return retval; 535 } 536 537 if (!chip->ft2_fast_mode) { 538 retval = card_power_on(chip, MS_CARD); 539 if (retval != STATUS_SUCCESS) 540 return STATUS_FAIL; 541 542 wait_timeout(150); 543 544 #ifdef SUPPORT_OCP 545 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) 546 oc_mask = MS_OC_NOW | MS_OC_EVER; 547 else 548 oc_mask = SD_OC_NOW | SD_OC_EVER; 549 550 if (chip->ocp_stat & oc_mask) { 551 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n", 552 chip->ocp_stat); 553 return STATUS_FAIL; 554 } 555 #endif 556 } 557 558 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 559 MS_OUTPUT_EN); 560 if (retval) 561 return retval; 562 563 if (chip->asic_code) { 564 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 565 SAMPLE_TIME_RISING | 566 PUSH_TIME_DEFAULT | 567 NO_EXTEND_TOGGLE | 568 MS_BUS_WIDTH_1); 569 if (retval) 570 return retval; 571 572 } else { 573 retval = rtsx_write_register(chip, MS_CFG, 0xFF, 574 SAMPLE_TIME_FALLING | 575 PUSH_TIME_DEFAULT | 576 NO_EXTEND_TOGGLE | 577 MS_BUS_WIDTH_1); 578 if (retval) 579 return retval; 580 } 581 retval = rtsx_write_register(chip, MS_TRANS_CFG, 0xFF, 582 NO_WAIT_INT | NO_AUTO_READ_INT_REG); 583 if (retval) 584 return retval; 585 586 retval = rtsx_write_register(chip, CARD_STOP, MS_STOP | MS_CLR_ERR, 587 MS_STOP | MS_CLR_ERR); 588 if (retval) 589 return retval; 590 591 retval = ms_set_init_para(chip); 592 if (retval != STATUS_SUCCESS) 593 return STATUS_FAIL; 594 595 return STATUS_SUCCESS; 596 } 597 598 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus) 599 { 600 struct ms_info *ms_card = &chip->ms_card; 601 int retval, i; 602 u8 val; 603 604 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1); 605 if (retval != STATUS_SUCCESS) 606 return STATUS_FAIL; 607 608 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 609 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG, 610 6, NO_WAIT_INT); 611 if (retval == STATUS_SUCCESS) 612 break; 613 } 614 if (i == MS_MAX_RETRY_COUNT) 615 return STATUS_FAIL; 616 617 retval = rtsx_read_register(chip, PPBUF_BASE2 + 2, &val); 618 if (retval) 619 return retval; 620 621 dev_dbg(rtsx_dev(chip), "Type register: 0x%x\n", val); 622 if (val != 0x01) { 623 if (val != 0x02) 624 ms_card->check_ms_flow = 1; 625 626 return STATUS_FAIL; 627 } 628 629 retval = rtsx_read_register(chip, PPBUF_BASE2 + 4, &val); 630 if (retval) 631 return retval; 632 633 dev_dbg(rtsx_dev(chip), "Category register: 0x%x\n", val); 634 if (val != 0) { 635 ms_card->check_ms_flow = 1; 636 return STATUS_FAIL; 637 } 638 639 retval = rtsx_read_register(chip, PPBUF_BASE2 + 5, &val); 640 if (retval) 641 return retval; 642 643 dev_dbg(rtsx_dev(chip), "Class register: 0x%x\n", val); 644 if (val == 0) { 645 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 646 if (retval) 647 return retval; 648 649 if (val & WRT_PRTCT) 650 chip->card_wp |= MS_CARD; 651 else 652 chip->card_wp &= ~MS_CARD; 653 654 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) { 655 chip->card_wp |= MS_CARD; 656 } else { 657 ms_card->check_ms_flow = 1; 658 return STATUS_FAIL; 659 } 660 661 ms_card->ms_type |= TYPE_MSPRO; 662 663 retval = rtsx_read_register(chip, PPBUF_BASE2 + 3, &val); 664 if (retval) 665 return retval; 666 667 dev_dbg(rtsx_dev(chip), "IF Mode register: 0x%x\n", val); 668 if (val == 0) { 669 ms_card->ms_type &= 0x0F; 670 } else if (val == 7) { 671 if (switch_8bit_bus) 672 ms_card->ms_type |= MS_HG; 673 else 674 ms_card->ms_type &= 0x0F; 675 676 } else { 677 return STATUS_FAIL; 678 } 679 680 return STATUS_SUCCESS; 681 } 682 683 static int ms_confirm_cpu_startup(struct rtsx_chip *chip) 684 { 685 int retval, i, k; 686 u8 val; 687 688 /* Confirm CPU StartUp */ 689 k = 0; 690 do { 691 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 692 ms_set_err_code(chip, MS_NO_CARD); 693 return STATUS_FAIL; 694 } 695 696 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 697 retval = ms_read_bytes(chip, GET_INT, 1, 698 NO_WAIT_INT, &val, 1); 699 if (retval == STATUS_SUCCESS) 700 break; 701 } 702 if (i == MS_MAX_RETRY_COUNT) 703 return STATUS_FAIL; 704 705 if (k > 100) 706 return STATUS_FAIL; 707 708 k++; 709 wait_timeout(100); 710 } while (!(val & INT_REG_CED)); 711 712 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 713 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 714 if (retval == STATUS_SUCCESS) 715 break; 716 } 717 if (i == MS_MAX_RETRY_COUNT) 718 return STATUS_FAIL; 719 720 if (val & INT_REG_ERR) { 721 if (val & INT_REG_CMDNK) 722 chip->card_wp |= (MS_CARD); 723 else 724 return STATUS_FAIL; 725 } 726 /* -- end confirm CPU startup */ 727 728 return STATUS_SUCCESS; 729 } 730 731 static int ms_switch_parallel_bus(struct rtsx_chip *chip) 732 { 733 int retval, i; 734 u8 data[2]; 735 736 data[0] = PARALLEL_4BIT_IF; 737 data[1] = 0; 738 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 739 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT, 740 data, 2); 741 if (retval == STATUS_SUCCESS) 742 break; 743 } 744 if (retval != STATUS_SUCCESS) 745 return STATUS_FAIL; 746 747 return STATUS_SUCCESS; 748 } 749 750 static int ms_switch_8bit_bus(struct rtsx_chip *chip) 751 { 752 struct ms_info *ms_card = &chip->ms_card; 753 int retval, i; 754 u8 data[2]; 755 756 data[0] = PARALLEL_8BIT_IF; 757 data[1] = 0; 758 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 759 retval = ms_write_bytes(chip, WRITE_REG, 1, 760 NO_WAIT_INT, data, 2); 761 if (retval == STATUS_SUCCESS) 762 break; 763 } 764 if (retval != STATUS_SUCCESS) 765 return STATUS_FAIL; 766 767 retval = rtsx_write_register(chip, MS_CFG, 0x98, 768 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING); 769 if (retval) 770 return retval; 771 772 ms_card->ms_type |= MS_8BIT; 773 retval = ms_set_init_para(chip); 774 if (retval != STATUS_SUCCESS) 775 return STATUS_FAIL; 776 777 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 778 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 779 1, NO_WAIT_INT); 780 if (retval != STATUS_SUCCESS) 781 return STATUS_FAIL; 782 } 783 784 return STATUS_SUCCESS; 785 } 786 787 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus) 788 { 789 struct ms_info *ms_card = &chip->ms_card; 790 int retval, i; 791 792 for (i = 0; i < 3; i++) { 793 retval = ms_prepare_reset(chip); 794 if (retval != STATUS_SUCCESS) 795 return STATUS_FAIL; 796 797 retval = ms_identify_media_type(chip, switch_8bit_bus); 798 if (retval != STATUS_SUCCESS) 799 return STATUS_FAIL; 800 801 retval = ms_confirm_cpu_startup(chip); 802 if (retval != STATUS_SUCCESS) 803 return STATUS_FAIL; 804 805 retval = ms_switch_parallel_bus(chip); 806 if (retval != STATUS_SUCCESS) { 807 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 808 ms_set_err_code(chip, MS_NO_CARD); 809 return STATUS_FAIL; 810 } 811 continue; 812 } else { 813 break; 814 } 815 } 816 817 if (retval != STATUS_SUCCESS) 818 return STATUS_FAIL; 819 820 /* Switch MS-PRO into Parallel mode */ 821 retval = rtsx_write_register(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4); 822 if (retval) 823 return retval; 824 825 retval = rtsx_write_register(chip, MS_CFG, PUSH_TIME_ODD, 826 PUSH_TIME_ODD); 827 if (retval) 828 return retval; 829 830 retval = ms_set_init_para(chip); 831 if (retval != STATUS_SUCCESS) 832 return STATUS_FAIL; 833 834 /* If MSPro HG Card, We shall try to switch to 8-bit bus */ 835 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) { 836 retval = ms_switch_8bit_bus(chip); 837 if (retval != STATUS_SUCCESS) { 838 ms_card->switch_8bit_fail = 1; 839 return STATUS_FAIL; 840 } 841 } 842 843 return STATUS_SUCCESS; 844 } 845 846 #ifdef XC_POWERCLASS 847 static int msxc_change_power(struct rtsx_chip *chip, u8 mode) 848 { 849 int retval; 850 u8 buf[6]; 851 852 ms_cleanup_work(chip); 853 854 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 855 if (retval != STATUS_SUCCESS) 856 return STATUS_FAIL; 857 858 buf[0] = 0; 859 buf[1] = mode; 860 buf[2] = 0; 861 buf[3] = 0; 862 buf[4] = 0; 863 buf[5] = 0; 864 865 retval = ms_write_bytes(chip, PRO_WRITE_REG, 6, NO_WAIT_INT, buf, 6); 866 if (retval != STATUS_SUCCESS) 867 return STATUS_FAIL; 868 869 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT); 870 if (retval != STATUS_SUCCESS) 871 return STATUS_FAIL; 872 873 retval = rtsx_read_register(chip, MS_TRANS_CFG, buf); 874 if (retval) 875 return retval; 876 877 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR)) 878 return STATUS_FAIL; 879 880 return STATUS_SUCCESS; 881 } 882 #endif 883 884 static int ms_read_attribute_info(struct rtsx_chip *chip) 885 { 886 struct ms_info *ms_card = &chip->ms_card; 887 int retval, i; 888 u8 val, *buf, class_code, device_type, sub_class, data[16]; 889 u16 total_blk = 0, blk_size = 0; 890 #ifdef SUPPORT_MSXC 891 u32 xc_total_blk = 0, xc_blk_size = 0; 892 #endif 893 u32 sys_info_addr = 0, sys_info_size; 894 #ifdef SUPPORT_PCGL_1P18 895 u32 model_name_addr = 0, model_name_size; 896 int found_sys_info = 0, found_model_name = 0; 897 #endif 898 899 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7); 900 if (retval != STATUS_SUCCESS) 901 return STATUS_FAIL; 902 903 if (CHK_MS8BIT(ms_card)) 904 data[0] = PARALLEL_8BIT_IF; 905 else 906 data[0] = PARALLEL_4BIT_IF; 907 908 data[1] = 0; 909 910 data[2] = 0x40; 911 data[3] = 0; 912 data[4] = 0; 913 data[5] = 0; 914 data[6] = 0; 915 data[7] = 0; 916 917 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 918 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT, 919 data, 8); 920 if (retval == STATUS_SUCCESS) 921 break; 922 } 923 if (retval != STATUS_SUCCESS) 924 return STATUS_FAIL; 925 926 buf = kmalloc(64 * 512, GFP_KERNEL); 927 if (!buf) 928 return STATUS_ERROR; 929 930 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 931 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT); 932 if (retval != STATUS_SUCCESS) 933 continue; 934 935 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 936 if (retval != STATUS_SUCCESS) { 937 kfree(buf); 938 return STATUS_FAIL; 939 } 940 if (!(val & MS_INT_BREQ)) { 941 kfree(buf); 942 return STATUS_FAIL; 943 } 944 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, 945 PRO_READ_LONG_DATA, 0x40, WAIT_INT, 946 0, 0, buf, 64 * 512); 947 if (retval == STATUS_SUCCESS) 948 break; 949 950 rtsx_clear_ms_error(chip); 951 } 952 if (retval != STATUS_SUCCESS) { 953 kfree(buf); 954 return STATUS_FAIL; 955 } 956 957 i = 0; 958 do { 959 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 960 if (retval != STATUS_SUCCESS) { 961 kfree(buf); 962 return STATUS_FAIL; 963 } 964 965 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ)) 966 break; 967 968 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, 969 PRO_READ_LONG_DATA, 0, WAIT_INT); 970 if (retval != STATUS_SUCCESS) { 971 kfree(buf); 972 return STATUS_FAIL; 973 } 974 975 i++; 976 } while (i < 1024); 977 978 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) { 979 /* Signature code is wrong */ 980 kfree(buf); 981 return STATUS_FAIL; 982 } 983 984 if ((buf[4] < 1) || (buf[4] > 12)) { 985 kfree(buf); 986 return STATUS_FAIL; 987 } 988 989 for (i = 0; i < buf[4]; i++) { 990 int cur_addr_off = 16 + i * 12; 991 992 #ifdef SUPPORT_MSXC 993 if ((buf[cur_addr_off + 8] == 0x10) || 994 (buf[cur_addr_off + 8] == 0x13)) { 995 #else 996 if (buf[cur_addr_off + 8] == 0x10) { 997 #endif 998 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) | 999 ((u32)buf[cur_addr_off + 1] << 16) | 1000 ((u32)buf[cur_addr_off + 2] << 8) | 1001 buf[cur_addr_off + 3]; 1002 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) | 1003 ((u32)buf[cur_addr_off + 5] << 16) | 1004 ((u32)buf[cur_addr_off + 6] << 8) | 1005 buf[cur_addr_off + 7]; 1006 dev_dbg(rtsx_dev(chip), "sys_info_addr = 0x%x, sys_info_size = 0x%x\n", 1007 sys_info_addr, sys_info_size); 1008 if (sys_info_size != 96) { 1009 kfree(buf); 1010 return STATUS_FAIL; 1011 } 1012 if (sys_info_addr < 0x1A0) { 1013 kfree(buf); 1014 return STATUS_FAIL; 1015 } 1016 if ((sys_info_size + sys_info_addr) > 0x8000) { 1017 kfree(buf); 1018 return STATUS_FAIL; 1019 } 1020 1021 #ifdef SUPPORT_MSXC 1022 if (buf[cur_addr_off + 8] == 0x13) 1023 ms_card->ms_type |= MS_XC; 1024 #endif 1025 #ifdef SUPPORT_PCGL_1P18 1026 found_sys_info = 1; 1027 #else 1028 break; 1029 #endif 1030 } 1031 #ifdef SUPPORT_PCGL_1P18 1032 if (buf[cur_addr_off + 8] == 0x15) { 1033 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) | 1034 ((u32)buf[cur_addr_off + 1] << 16) | 1035 ((u32)buf[cur_addr_off + 2] << 8) | 1036 buf[cur_addr_off + 3]; 1037 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) | 1038 ((u32)buf[cur_addr_off + 5] << 16) | 1039 ((u32)buf[cur_addr_off + 6] << 8) | 1040 buf[cur_addr_off + 7]; 1041 dev_dbg(rtsx_dev(chip), "model_name_addr = 0x%x, model_name_size = 0x%x\n", 1042 model_name_addr, model_name_size); 1043 if (model_name_size != 48) { 1044 kfree(buf); 1045 return STATUS_FAIL; 1046 } 1047 if (model_name_addr < 0x1A0) { 1048 kfree(buf); 1049 return STATUS_FAIL; 1050 } 1051 if ((model_name_size + model_name_addr) > 0x8000) { 1052 kfree(buf); 1053 return STATUS_FAIL; 1054 } 1055 1056 found_model_name = 1; 1057 } 1058 1059 if (found_sys_info && found_model_name) 1060 break; 1061 #endif 1062 } 1063 1064 if (i == buf[4]) { 1065 kfree(buf); 1066 return STATUS_FAIL; 1067 } 1068 1069 class_code = buf[sys_info_addr + 0]; 1070 device_type = buf[sys_info_addr + 56]; 1071 sub_class = buf[sys_info_addr + 46]; 1072 #ifdef SUPPORT_MSXC 1073 if (CHK_MSXC(ms_card)) { 1074 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) | 1075 ((u32)buf[sys_info_addr + 7] << 16) | 1076 ((u32)buf[sys_info_addr + 8] << 8) | 1077 buf[sys_info_addr + 9]; 1078 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) | 1079 ((u32)buf[sys_info_addr + 33] << 16) | 1080 ((u32)buf[sys_info_addr + 34] << 8) | 1081 buf[sys_info_addr + 35]; 1082 dev_dbg(rtsx_dev(chip), "xc_total_blk = 0x%x, xc_blk_size = 0x%x\n", 1083 xc_total_blk, xc_blk_size); 1084 } else { 1085 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | 1086 buf[sys_info_addr + 7]; 1087 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | 1088 buf[sys_info_addr + 3]; 1089 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1090 total_blk, blk_size); 1091 } 1092 #else 1093 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7]; 1094 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3]; 1095 dev_dbg(rtsx_dev(chip), "total_blk = 0x%x, blk_size = 0x%x\n", 1096 total_blk, blk_size); 1097 #endif 1098 1099 dev_dbg(rtsx_dev(chip), "class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n", 1100 class_code, device_type, sub_class); 1101 1102 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96); 1103 #ifdef SUPPORT_PCGL_1P18 1104 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48); 1105 #endif 1106 1107 kfree(buf); 1108 1109 #ifdef SUPPORT_MSXC 1110 if (CHK_MSXC(ms_card)) { 1111 if (class_code != 0x03) 1112 return STATUS_FAIL; 1113 } else { 1114 if (class_code != 0x02) 1115 return STATUS_FAIL; 1116 } 1117 #else 1118 if (class_code != 0x02) 1119 return STATUS_FAIL; 1120 #endif 1121 1122 if (device_type != 0x00) { 1123 if ((device_type == 0x01) || (device_type == 0x02) || 1124 (device_type == 0x03)) { 1125 chip->card_wp |= MS_CARD; 1126 } else { 1127 return STATUS_FAIL; 1128 } 1129 } 1130 1131 if (sub_class & 0xC0) 1132 return STATUS_FAIL; 1133 1134 dev_dbg(rtsx_dev(chip), "class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n", 1135 class_code, device_type, sub_class); 1136 1137 #ifdef SUPPORT_MSXC 1138 if (CHK_MSXC(ms_card)) { 1139 chip->capacity[chip->card2lun[MS_CARD]] = 1140 ms_card->capacity = xc_total_blk * xc_blk_size; 1141 } else { 1142 chip->capacity[chip->card2lun[MS_CARD]] = 1143 ms_card->capacity = total_blk * blk_size; 1144 } 1145 #else 1146 ms_card->capacity = total_blk * blk_size; 1147 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 1148 #endif 1149 1150 return STATUS_SUCCESS; 1151 } 1152 1153 #ifdef SUPPORT_MAGIC_GATE 1154 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, 1155 int type, u8 mg_entry_num); 1156 #endif 1157 1158 static int reset_ms_pro(struct rtsx_chip *chip) 1159 { 1160 struct ms_info *ms_card = &chip->ms_card; 1161 int retval; 1162 #ifdef XC_POWERCLASS 1163 u8 change_power_class; 1164 1165 if (chip->ms_power_class_en & 0x02) 1166 change_power_class = 2; 1167 else if (chip->ms_power_class_en & 0x01) 1168 change_power_class = 1; 1169 else 1170 change_power_class = 0; 1171 #endif 1172 1173 #ifdef XC_POWERCLASS 1174 retry: 1175 #endif 1176 retval = ms_pro_reset_flow(chip, 1); 1177 if (retval != STATUS_SUCCESS) { 1178 if (ms_card->switch_8bit_fail) { 1179 retval = ms_pro_reset_flow(chip, 0); 1180 if (retval != STATUS_SUCCESS) 1181 return STATUS_FAIL; 1182 } else { 1183 return STATUS_FAIL; 1184 } 1185 } 1186 1187 retval = ms_read_attribute_info(chip); 1188 if (retval != STATUS_SUCCESS) 1189 return STATUS_FAIL; 1190 1191 #ifdef XC_POWERCLASS 1192 if (CHK_HG8BIT(ms_card)) 1193 change_power_class = 0; 1194 1195 if (change_power_class && CHK_MSXC(ms_card)) { 1196 u8 power_class_en = chip->ms_power_class_en; 1197 1198 dev_dbg(rtsx_dev(chip), "power_class_en = 0x%x\n", 1199 power_class_en); 1200 dev_dbg(rtsx_dev(chip), "change_power_class = %d\n", 1201 change_power_class); 1202 1203 if (change_power_class) 1204 power_class_en &= (1 << (change_power_class - 1)); 1205 else 1206 power_class_en = 0; 1207 1208 if (power_class_en) { 1209 u8 power_class_mode = 1210 (ms_card->raw_sys_info[46] & 0x18) >> 3; 1211 dev_dbg(rtsx_dev(chip), "power_class_mode = 0x%x", 1212 power_class_mode); 1213 if (change_power_class > power_class_mode) 1214 change_power_class = power_class_mode; 1215 if (change_power_class) { 1216 retval = msxc_change_power(chip, 1217 change_power_class); 1218 if (retval != STATUS_SUCCESS) { 1219 change_power_class--; 1220 goto retry; 1221 } 1222 } 1223 } 1224 } 1225 #endif 1226 1227 #ifdef SUPPORT_MAGIC_GATE 1228 retval = mg_set_tpc_para_sub(chip, 0, 0); 1229 if (retval != STATUS_SUCCESS) 1230 return STATUS_FAIL; 1231 #endif 1232 1233 if (CHK_HG8BIT(ms_card)) 1234 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8; 1235 else 1236 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 1237 1238 return STATUS_SUCCESS; 1239 } 1240 1241 static int ms_read_status_reg(struct rtsx_chip *chip) 1242 { 1243 int retval; 1244 u8 val[2]; 1245 1246 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0); 1247 if (retval != STATUS_SUCCESS) 1248 return STATUS_FAIL; 1249 1250 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2); 1251 if (retval != STATUS_SUCCESS) 1252 return STATUS_FAIL; 1253 1254 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) { 1255 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1256 return STATUS_FAIL; 1257 } 1258 1259 return STATUS_SUCCESS; 1260 } 1261 1262 static int ms_read_extra_data(struct rtsx_chip *chip, 1263 u16 block_addr, u8 page_num, u8 *buf, int buf_len) 1264 { 1265 struct ms_info *ms_card = &chip->ms_card; 1266 int retval, i; 1267 u8 val, data[10]; 1268 1269 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1270 SystemParm, 6); 1271 if (retval != STATUS_SUCCESS) 1272 return STATUS_FAIL; 1273 1274 if (CHK_MS4BIT(ms_card)) { 1275 /* Parallel interface */ 1276 data[0] = 0x88; 1277 } else { 1278 /* Serial interface */ 1279 data[0] = 0x80; 1280 } 1281 data[1] = 0; 1282 data[2] = (u8)(block_addr >> 8); 1283 data[3] = (u8)block_addr; 1284 data[4] = 0x40; 1285 data[5] = page_num; 1286 1287 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1288 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1289 data, 6); 1290 if (retval == STATUS_SUCCESS) 1291 break; 1292 } 1293 if (i == MS_MAX_RETRY_COUNT) 1294 return STATUS_FAIL; 1295 1296 ms_set_err_code(chip, MS_NO_ERROR); 1297 1298 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 1299 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1300 if (retval == STATUS_SUCCESS) 1301 break; 1302 } 1303 if (i == MS_MAX_RETRY_COUNT) 1304 return STATUS_FAIL; 1305 1306 ms_set_err_code(chip, MS_NO_ERROR); 1307 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1308 if (retval != STATUS_SUCCESS) 1309 return STATUS_FAIL; 1310 1311 if (val & INT_REG_CMDNK) { 1312 ms_set_err_code(chip, MS_CMD_NK); 1313 return STATUS_FAIL; 1314 } 1315 if (val & INT_REG_CED) { 1316 if (val & INT_REG_ERR) { 1317 retval = ms_read_status_reg(chip); 1318 if (retval != STATUS_SUCCESS) 1319 return STATUS_FAIL; 1320 1321 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1322 MS_EXTRA_SIZE, SystemParm, 1323 6); 1324 if (retval != STATUS_SUCCESS) 1325 return STATUS_FAIL; 1326 } 1327 } 1328 1329 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT, 1330 data, MS_EXTRA_SIZE); 1331 if (retval != STATUS_SUCCESS) 1332 return STATUS_FAIL; 1333 1334 if (buf && buf_len) { 1335 if (buf_len > MS_EXTRA_SIZE) 1336 buf_len = MS_EXTRA_SIZE; 1337 memcpy(buf, data, buf_len); 1338 } 1339 1340 return STATUS_SUCCESS; 1341 } 1342 1343 static int ms_write_extra_data(struct rtsx_chip *chip, u16 block_addr, 1344 u8 page_num, u8 *buf, int buf_len) 1345 { 1346 struct ms_info *ms_card = &chip->ms_card; 1347 int retval, i; 1348 u8 val, data[16]; 1349 1350 if (!buf || (buf_len < MS_EXTRA_SIZE)) 1351 return STATUS_FAIL; 1352 1353 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1354 SystemParm, 6 + MS_EXTRA_SIZE); 1355 if (retval != STATUS_SUCCESS) 1356 return STATUS_FAIL; 1357 1358 if (CHK_MS4BIT(ms_card)) 1359 data[0] = 0x88; 1360 else 1361 data[0] = 0x80; 1362 1363 data[1] = 0; 1364 data[2] = (u8)(block_addr >> 8); 1365 data[3] = (u8)block_addr; 1366 data[4] = 0x40; 1367 data[5] = page_num; 1368 1369 for (i = 6; i < MS_EXTRA_SIZE + 6; i++) 1370 data[i] = buf[i - 6]; 1371 1372 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1373 NO_WAIT_INT, data, 16); 1374 if (retval != STATUS_SUCCESS) 1375 return STATUS_FAIL; 1376 1377 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1378 if (retval != STATUS_SUCCESS) 1379 return STATUS_FAIL; 1380 1381 ms_set_err_code(chip, MS_NO_ERROR); 1382 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1383 if (retval != STATUS_SUCCESS) 1384 return STATUS_FAIL; 1385 1386 if (val & INT_REG_CMDNK) { 1387 ms_set_err_code(chip, MS_CMD_NK); 1388 return STATUS_FAIL; 1389 } 1390 if (val & INT_REG_CED) { 1391 if (val & INT_REG_ERR) { 1392 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1393 return STATUS_FAIL; 1394 } 1395 } 1396 1397 return STATUS_SUCCESS; 1398 } 1399 1400 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num) 1401 { 1402 struct ms_info *ms_card = &chip->ms_card; 1403 int retval; 1404 u8 val, data[6]; 1405 1406 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1407 SystemParm, 6); 1408 if (retval != STATUS_SUCCESS) 1409 return STATUS_FAIL; 1410 1411 if (CHK_MS4BIT(ms_card)) 1412 data[0] = 0x88; 1413 else 1414 data[0] = 0x80; 1415 1416 data[1] = 0; 1417 data[2] = (u8)(block_addr >> 8); 1418 data[3] = (u8)block_addr; 1419 data[4] = 0x20; 1420 data[5] = page_num; 1421 1422 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1423 if (retval != STATUS_SUCCESS) 1424 return STATUS_FAIL; 1425 1426 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1427 if (retval != STATUS_SUCCESS) 1428 return STATUS_FAIL; 1429 1430 ms_set_err_code(chip, MS_NO_ERROR); 1431 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1432 if (retval != STATUS_SUCCESS) 1433 return STATUS_FAIL; 1434 1435 if (val & INT_REG_CMDNK) { 1436 ms_set_err_code(chip, MS_CMD_NK); 1437 return STATUS_FAIL; 1438 } 1439 1440 if (val & INT_REG_CED) { 1441 if (val & INT_REG_ERR) { 1442 if (!(val & INT_REG_BREQ)) { 1443 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 1444 return STATUS_FAIL; 1445 } 1446 retval = ms_read_status_reg(chip); 1447 if (retval != STATUS_SUCCESS) 1448 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1449 1450 } else { 1451 if (!(val & INT_REG_BREQ)) { 1452 ms_set_err_code(chip, MS_BREQ_ERROR); 1453 return STATUS_FAIL; 1454 } 1455 } 1456 } 1457 1458 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA, 1459 0, NO_WAIT_INT); 1460 if (retval != STATUS_SUCCESS) 1461 return STATUS_FAIL; 1462 1463 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) 1464 return STATUS_FAIL; 1465 1466 return STATUS_SUCCESS; 1467 } 1468 1469 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk) 1470 { 1471 struct ms_info *ms_card = &chip->ms_card; 1472 int retval; 1473 u8 val, data[8], extra[MS_EXTRA_SIZE]; 1474 1475 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE); 1476 if (retval != STATUS_SUCCESS) 1477 return STATUS_FAIL; 1478 1479 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1480 SystemParm, 7); 1481 if (retval != STATUS_SUCCESS) 1482 return STATUS_FAIL; 1483 1484 ms_set_err_code(chip, MS_NO_ERROR); 1485 1486 if (CHK_MS4BIT(ms_card)) 1487 data[0] = 0x88; 1488 else 1489 data[0] = 0x80; 1490 1491 data[1] = 0; 1492 data[2] = (u8)(phy_blk >> 8); 1493 data[3] = (u8)phy_blk; 1494 data[4] = 0x80; 1495 data[5] = 0; 1496 data[6] = extra[0] & 0x7F; 1497 data[7] = 0xFF; 1498 1499 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7); 1500 if (retval != STATUS_SUCCESS) 1501 return STATUS_FAIL; 1502 1503 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1504 if (retval != STATUS_SUCCESS) 1505 return STATUS_FAIL; 1506 1507 ms_set_err_code(chip, MS_NO_ERROR); 1508 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1509 if (retval != STATUS_SUCCESS) 1510 return STATUS_FAIL; 1511 1512 if (val & INT_REG_CMDNK) { 1513 ms_set_err_code(chip, MS_CMD_NK); 1514 return STATUS_FAIL; 1515 } 1516 1517 if (val & INT_REG_CED) { 1518 if (val & INT_REG_ERR) { 1519 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1520 return STATUS_FAIL; 1521 } 1522 } 1523 1524 return STATUS_SUCCESS; 1525 } 1526 1527 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk) 1528 { 1529 struct ms_info *ms_card = &chip->ms_card; 1530 int retval, i = 0; 1531 u8 val, data[6]; 1532 1533 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1534 SystemParm, 6); 1535 if (retval != STATUS_SUCCESS) 1536 return STATUS_FAIL; 1537 1538 ms_set_err_code(chip, MS_NO_ERROR); 1539 1540 if (CHK_MS4BIT(ms_card)) 1541 data[0] = 0x88; 1542 else 1543 data[0] = 0x80; 1544 1545 data[1] = 0; 1546 data[2] = (u8)(phy_blk >> 8); 1547 data[3] = (u8)phy_blk; 1548 data[4] = 0; 1549 data[5] = 0; 1550 1551 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6); 1552 if (retval != STATUS_SUCCESS) 1553 return STATUS_FAIL; 1554 1555 ERASE_RTY: 1556 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT); 1557 if (retval != STATUS_SUCCESS) 1558 return STATUS_FAIL; 1559 1560 ms_set_err_code(chip, MS_NO_ERROR); 1561 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1562 if (retval != STATUS_SUCCESS) 1563 return STATUS_FAIL; 1564 1565 if (val & INT_REG_CMDNK) { 1566 if (i < 3) { 1567 i++; 1568 goto ERASE_RTY; 1569 } 1570 1571 ms_set_err_code(chip, MS_CMD_NK); 1572 ms_set_bad_block(chip, phy_blk); 1573 return STATUS_FAIL; 1574 } 1575 1576 if (val & INT_REG_CED) { 1577 if (val & INT_REG_ERR) { 1578 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1579 return STATUS_FAIL; 1580 } 1581 } 1582 1583 return STATUS_SUCCESS; 1584 } 1585 1586 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len) 1587 { 1588 if (!extra || (extra_len < MS_EXTRA_SIZE)) 1589 return; 1590 1591 memset(extra, 0xFF, MS_EXTRA_SIZE); 1592 1593 if (type == setPS_NG) { 1594 /* set page status as 1:NG,and block status keep 1:OK */ 1595 extra[0] = 0xB8; 1596 } else { 1597 /* set page status as 0:Data Error,and block status keep 1:OK */ 1598 extra[0] = 0x98; 1599 } 1600 1601 extra[2] = (u8)(log_blk >> 8); 1602 extra[3] = (u8)log_blk; 1603 } 1604 1605 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk, 1606 u8 start_page, u8 end_page) 1607 { 1608 int retval; 1609 u8 extra[MS_EXTRA_SIZE], i; 1610 1611 memset(extra, 0xff, MS_EXTRA_SIZE); 1612 1613 extra[0] = 0xf8; /* Block, page OK, data erased */ 1614 extra[1] = 0xff; 1615 extra[2] = (u8)(log_blk >> 8); 1616 extra[3] = (u8)log_blk; 1617 1618 for (i = start_page; i < end_page; i++) { 1619 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1620 ms_set_err_code(chip, MS_NO_CARD); 1621 return STATUS_FAIL; 1622 } 1623 1624 retval = ms_write_extra_data(chip, phy_blk, i, 1625 extra, MS_EXTRA_SIZE); 1626 if (retval != STATUS_SUCCESS) 1627 return STATUS_FAIL; 1628 } 1629 1630 return STATUS_SUCCESS; 1631 } 1632 1633 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 1634 u16 log_blk, u8 start_page, u8 end_page) 1635 { 1636 struct ms_info *ms_card = &chip->ms_card; 1637 bool uncorrect_flag = false; 1638 int retval, rty_cnt; 1639 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16]; 1640 1641 dev_dbg(rtsx_dev(chip), "Copy page from 0x%x to 0x%x, logical block is 0x%x\n", 1642 old_blk, new_blk, log_blk); 1643 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d\n", 1644 start_page, end_page); 1645 1646 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE); 1647 if (retval != STATUS_SUCCESS) 1648 return STATUS_FAIL; 1649 1650 retval = ms_read_status_reg(chip); 1651 if (retval != STATUS_SUCCESS) 1652 return STATUS_FAIL; 1653 1654 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1655 if (retval) 1656 return retval; 1657 1658 if (val & BUF_FULL) { 1659 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT); 1660 if (retval != STATUS_SUCCESS) 1661 return STATUS_FAIL; 1662 1663 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1664 if (retval != STATUS_SUCCESS) 1665 return STATUS_FAIL; 1666 1667 if (!(val & INT_REG_CED)) { 1668 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1669 return STATUS_FAIL; 1670 } 1671 } 1672 1673 for (i = start_page; i < end_page; i++) { 1674 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1675 ms_set_err_code(chip, MS_NO_CARD); 1676 return STATUS_FAIL; 1677 } 1678 1679 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE); 1680 1681 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1682 MS_EXTRA_SIZE, SystemParm, 6); 1683 if (retval != STATUS_SUCCESS) 1684 return STATUS_FAIL; 1685 1686 ms_set_err_code(chip, MS_NO_ERROR); 1687 1688 if (CHK_MS4BIT(ms_card)) 1689 data[0] = 0x88; 1690 else 1691 data[0] = 0x80; 1692 1693 data[1] = 0; 1694 data[2] = (u8)(old_blk >> 8); 1695 data[3] = (u8)old_blk; 1696 data[4] = 0x20; 1697 data[5] = i; 1698 1699 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 1700 data, 6); 1701 if (retval != STATUS_SUCCESS) 1702 return STATUS_FAIL; 1703 1704 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 1705 if (retval != STATUS_SUCCESS) 1706 return STATUS_FAIL; 1707 1708 ms_set_err_code(chip, MS_NO_ERROR); 1709 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1710 if (retval != STATUS_SUCCESS) 1711 return STATUS_FAIL; 1712 1713 if (val & INT_REG_CMDNK) { 1714 ms_set_err_code(chip, MS_CMD_NK); 1715 return STATUS_FAIL; 1716 } 1717 1718 if (val & INT_REG_CED) { 1719 if (val & INT_REG_ERR) { 1720 retval = ms_read_status_reg(chip); 1721 if (retval != STATUS_SUCCESS) { 1722 uncorrect_flag = true; 1723 dev_dbg(rtsx_dev(chip), "Uncorrectable error\n"); 1724 } else { 1725 uncorrect_flag = false; 1726 } 1727 1728 retval = ms_transfer_tpc(chip, 1729 MS_TM_NORMAL_READ, 1730 READ_PAGE_DATA, 1731 0, NO_WAIT_INT); 1732 if (retval != STATUS_SUCCESS) 1733 return STATUS_FAIL; 1734 1735 if (uncorrect_flag) { 1736 ms_set_page_status(log_blk, setPS_NG, 1737 extra, 1738 MS_EXTRA_SIZE); 1739 if (i == 0) 1740 extra[0] &= 0xEF; 1741 1742 ms_write_extra_data(chip, old_blk, i, 1743 extra, 1744 MS_EXTRA_SIZE); 1745 dev_dbg(rtsx_dev(chip), "page %d : extra[0] = 0x%x\n", 1746 i, extra[0]); 1747 MS_SET_BAD_BLOCK_FLG(ms_card); 1748 1749 ms_set_page_status(log_blk, setPS_Error, 1750 extra, 1751 MS_EXTRA_SIZE); 1752 ms_write_extra_data(chip, new_blk, i, 1753 extra, 1754 MS_EXTRA_SIZE); 1755 continue; 1756 } 1757 1758 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT; 1759 rty_cnt++) { 1760 retval = ms_transfer_tpc( 1761 chip, 1762 MS_TM_NORMAL_WRITE, 1763 WRITE_PAGE_DATA, 1764 0, NO_WAIT_INT); 1765 if (retval == STATUS_SUCCESS) 1766 break; 1767 } 1768 if (rty_cnt == MS_MAX_RETRY_COUNT) 1769 return STATUS_FAIL; 1770 } 1771 1772 if (!(val & INT_REG_BREQ)) { 1773 ms_set_err_code(chip, MS_BREQ_ERROR); 1774 return STATUS_FAIL; 1775 } 1776 } 1777 1778 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 1779 SystemParm, (6 + MS_EXTRA_SIZE)); 1780 1781 ms_set_err_code(chip, MS_NO_ERROR); 1782 1783 if (CHK_MS4BIT(ms_card)) 1784 data[0] = 0x88; 1785 else 1786 data[0] = 0x80; 1787 1788 data[1] = 0; 1789 data[2] = (u8)(new_blk >> 8); 1790 data[3] = (u8)new_blk; 1791 data[4] = 0x20; 1792 data[5] = i; 1793 1794 if ((extra[0] & 0x60) != 0x60) 1795 data[6] = extra[0]; 1796 else 1797 data[6] = 0xF8; 1798 1799 data[6 + 1] = 0xFF; 1800 data[6 + 2] = (u8)(log_blk >> 8); 1801 data[6 + 3] = (u8)log_blk; 1802 1803 for (j = 4; j <= MS_EXTRA_SIZE; j++) 1804 data[6 + j] = 0xFF; 1805 1806 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE), 1807 NO_WAIT_INT, data, 16); 1808 if (retval != STATUS_SUCCESS) 1809 return STATUS_FAIL; 1810 1811 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1812 if (retval != STATUS_SUCCESS) 1813 return STATUS_FAIL; 1814 1815 ms_set_err_code(chip, MS_NO_ERROR); 1816 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 1817 if (retval != STATUS_SUCCESS) 1818 return STATUS_FAIL; 1819 1820 if (val & INT_REG_CMDNK) { 1821 ms_set_err_code(chip, MS_CMD_NK); 1822 return STATUS_FAIL; 1823 } 1824 1825 if (val & INT_REG_CED) { 1826 if (val & INT_REG_ERR) { 1827 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 1828 return STATUS_FAIL; 1829 } 1830 } 1831 1832 if (i == 0) { 1833 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, 1834 MS_EXTRA_SIZE, SystemParm, 1835 7); 1836 if (retval != STATUS_SUCCESS) 1837 return STATUS_FAIL; 1838 1839 ms_set_err_code(chip, MS_NO_ERROR); 1840 1841 if (CHK_MS4BIT(ms_card)) 1842 data[0] = 0x88; 1843 else 1844 data[0] = 0x80; 1845 1846 data[1] = 0; 1847 data[2] = (u8)(old_blk >> 8); 1848 data[3] = (u8)old_blk; 1849 data[4] = 0x80; 1850 data[5] = 0; 1851 data[6] = 0xEF; 1852 data[7] = 0xFF; 1853 1854 retval = ms_write_bytes(chip, WRITE_REG, 7, 1855 NO_WAIT_INT, data, 8); 1856 if (retval != STATUS_SUCCESS) 1857 return STATUS_FAIL; 1858 1859 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 1860 if (retval != STATUS_SUCCESS) 1861 return STATUS_FAIL; 1862 1863 ms_set_err_code(chip, MS_NO_ERROR); 1864 retval = ms_read_bytes(chip, GET_INT, 1, 1865 NO_WAIT_INT, &val, 1); 1866 if (retval != STATUS_SUCCESS) 1867 return STATUS_FAIL; 1868 1869 if (val & INT_REG_CMDNK) { 1870 ms_set_err_code(chip, MS_CMD_NK); 1871 return STATUS_FAIL; 1872 } 1873 1874 if (val & INT_REG_CED) { 1875 if (val & INT_REG_ERR) { 1876 ms_set_err_code(chip, 1877 MS_FLASH_WRITE_ERROR); 1878 return STATUS_FAIL; 1879 } 1880 } 1881 } 1882 } 1883 1884 return STATUS_SUCCESS; 1885 } 1886 1887 static int reset_ms(struct rtsx_chip *chip) 1888 { 1889 struct ms_info *ms_card = &chip->ms_card; 1890 int retval; 1891 u16 i, reg_addr, block_size; 1892 u8 val, extra[MS_EXTRA_SIZE], j, *ptr; 1893 #ifndef SUPPORT_MAGIC_GATE 1894 u16 eblock_cnt; 1895 #endif 1896 1897 retval = ms_prepare_reset(chip); 1898 if (retval != STATUS_SUCCESS) 1899 return STATUS_FAIL; 1900 1901 ms_card->ms_type |= TYPE_MS; 1902 1903 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT); 1904 if (retval != STATUS_SUCCESS) 1905 return STATUS_FAIL; 1906 1907 retval = ms_read_status_reg(chip); 1908 if (retval != STATUS_SUCCESS) 1909 return STATUS_FAIL; 1910 1911 retval = rtsx_read_register(chip, PPBUF_BASE2, &val); 1912 if (retval) 1913 return retval; 1914 1915 if (val & WRT_PRTCT) 1916 chip->card_wp |= MS_CARD; 1917 else 1918 chip->card_wp &= ~MS_CARD; 1919 1920 i = 0; 1921 1922 RE_SEARCH: 1923 /* Search Boot Block */ 1924 while (i < (MAX_DEFECTIVE_BLOCK + 2)) { 1925 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 1926 ms_set_err_code(chip, MS_NO_CARD); 1927 return STATUS_FAIL; 1928 } 1929 1930 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE); 1931 if (retval != STATUS_SUCCESS) { 1932 i++; 1933 continue; 1934 } 1935 1936 if (extra[0] & BLOCK_OK) { 1937 if (!(extra[1] & NOT_BOOT_BLOCK)) { 1938 ms_card->boot_block = i; 1939 break; 1940 } 1941 } 1942 i++; 1943 } 1944 1945 if (i == (MAX_DEFECTIVE_BLOCK + 2)) { 1946 dev_dbg(rtsx_dev(chip), "No boot block found!"); 1947 return STATUS_FAIL; 1948 } 1949 1950 for (j = 0; j < 3; j++) { 1951 retval = ms_read_page(chip, ms_card->boot_block, j); 1952 if (retval != STATUS_SUCCESS) { 1953 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) { 1954 i = ms_card->boot_block + 1; 1955 ms_set_err_code(chip, MS_NO_ERROR); 1956 goto RE_SEARCH; 1957 } 1958 } 1959 } 1960 1961 retval = ms_read_page(chip, ms_card->boot_block, 0); 1962 if (retval != STATUS_SUCCESS) 1963 return STATUS_FAIL; 1964 1965 /* Read MS system information as sys_info */ 1966 rtsx_init_cmd(chip); 1967 1968 for (i = 0; i < 96; i++) 1969 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0); 1970 1971 retval = rtsx_send_cmd(chip, MS_CARD, 100); 1972 if (retval < 0) 1973 return STATUS_FAIL; 1974 1975 ptr = rtsx_get_cmd_data(chip); 1976 memcpy(ms_card->raw_sys_info, ptr, 96); 1977 1978 /* Read useful block contents */ 1979 rtsx_init_cmd(chip); 1980 1981 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0); 1982 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0); 1983 1984 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3; 1985 reg_addr++) 1986 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 1987 1988 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++) 1989 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0); 1990 1991 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0); 1992 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0); 1993 1994 retval = rtsx_send_cmd(chip, MS_CARD, 100); 1995 if (retval < 0) 1996 return STATUS_FAIL; 1997 1998 ptr = rtsx_get_cmd_data(chip); 1999 2000 dev_dbg(rtsx_dev(chip), "Boot block data:\n"); 2001 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, ptr); 2002 2003 /* Block ID error 2004 * HEADER_ID0, HEADER_ID1 2005 */ 2006 if (ptr[0] != 0x00 || ptr[1] != 0x01) { 2007 i = ms_card->boot_block + 1; 2008 goto RE_SEARCH; 2009 } 2010 2011 /* Page size error 2012 * PAGE_SIZE_0, PAGE_SIZE_1 2013 */ 2014 if (ptr[12] != 0x02 || ptr[13] != 0x00) { 2015 i = ms_card->boot_block + 1; 2016 goto RE_SEARCH; 2017 } 2018 2019 if ((ptr[14] == 1) || (ptr[14] == 3)) 2020 chip->card_wp |= MS_CARD; 2021 2022 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */ 2023 block_size = ((u16)ptr[6] << 8) | ptr[7]; 2024 if (block_size == 0x0010) { 2025 /* Block size 16KB */ 2026 ms_card->block_shift = 5; 2027 ms_card->page_off = 0x1F; 2028 } else if (block_size == 0x0008) { 2029 /* Block size 8KB */ 2030 ms_card->block_shift = 4; 2031 ms_card->page_off = 0x0F; 2032 } 2033 2034 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */ 2035 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9]; 2036 2037 #ifdef SUPPORT_MAGIC_GATE 2038 j = ptr[10]; 2039 2040 if (ms_card->block_shift == 4) { /* 4MB or 8MB */ 2041 if (j < 2) { /* Effective block for 4MB: 0x1F0 */ 2042 ms_card->capacity = 0x1EE0; 2043 } else { /* Effective block for 8MB: 0x3E0 */ 2044 ms_card->capacity = 0x3DE0; 2045 } 2046 } else { /* 16MB, 32MB, 64MB or 128MB */ 2047 if (j < 5) { /* Effective block for 16MB: 0x3E0 */ 2048 ms_card->capacity = 0x7BC0; 2049 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */ 2050 ms_card->capacity = 0xF7C0; 2051 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */ 2052 ms_card->capacity = 0x1EF80; 2053 } else { /* Effective block for 128MB: 0x1F00 */ 2054 ms_card->capacity = 0x3DF00; 2055 } 2056 } 2057 #else 2058 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */ 2059 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11]; 2060 2061 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift; 2062 #endif 2063 2064 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity; 2065 2066 /* Switch I/F Mode */ 2067 if (ptr[15]) { 2068 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1); 2069 if (retval != STATUS_SUCCESS) 2070 return STATUS_FAIL; 2071 2072 retval = rtsx_write_register(chip, PPBUF_BASE2, 0xFF, 0x88); 2073 if (retval) 2074 return retval; 2075 2076 retval = rtsx_write_register(chip, PPBUF_BASE2 + 1, 0xFF, 0); 2077 if (retval) 2078 return retval; 2079 2080 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG, 1, 2081 NO_WAIT_INT); 2082 if (retval != STATUS_SUCCESS) 2083 return STATUS_FAIL; 2084 2085 retval = rtsx_write_register(chip, MS_CFG, 2086 0x58 | MS_NO_CHECK_INT, 2087 MS_BUS_WIDTH_4 | 2088 PUSH_TIME_ODD | 2089 MS_NO_CHECK_INT); 2090 if (retval) 2091 return retval; 2092 2093 ms_card->ms_type |= MS_4BIT; 2094 } 2095 2096 if (CHK_MS4BIT(ms_card)) 2097 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4; 2098 else 2099 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1; 2100 2101 return STATUS_SUCCESS; 2102 } 2103 2104 static int ms_init_l2p_tbl(struct rtsx_chip *chip) 2105 { 2106 struct ms_info *ms_card = &chip->ms_card; 2107 int size, i, seg_no, retval; 2108 u16 defect_block, reg_addr; 2109 u8 val1, val2; 2110 2111 ms_card->segment_cnt = ms_card->total_block >> 9; 2112 dev_dbg(rtsx_dev(chip), "ms_card->segment_cnt = %d\n", 2113 ms_card->segment_cnt); 2114 2115 size = ms_card->segment_cnt * sizeof(struct zone_entry); 2116 ms_card->segment = vzalloc(size); 2117 if (!ms_card->segment) 2118 return STATUS_FAIL; 2119 2120 retval = ms_read_page(chip, ms_card->boot_block, 1); 2121 if (retval != STATUS_SUCCESS) 2122 goto INIT_FAIL; 2123 2124 reg_addr = PPBUF_BASE2; 2125 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) { 2126 int block_no; 2127 2128 retval = rtsx_read_register(chip, reg_addr++, &val1); 2129 if (retval != STATUS_SUCCESS) 2130 goto INIT_FAIL; 2131 2132 retval = rtsx_read_register(chip, reg_addr++, &val2); 2133 if (retval != STATUS_SUCCESS) 2134 goto INIT_FAIL; 2135 2136 defect_block = ((u16)val1 << 8) | val2; 2137 if (defect_block == 0xFFFF) 2138 break; 2139 2140 seg_no = defect_block / 512; 2141 2142 block_no = ms_card->segment[seg_no].disable_count++; 2143 ms_card->segment[seg_no].defect_list[block_no] = defect_block; 2144 } 2145 2146 for (i = 0; i < ms_card->segment_cnt; i++) { 2147 ms_card->segment[i].build_flag = 0; 2148 ms_card->segment[i].l2p_table = NULL; 2149 ms_card->segment[i].free_table = NULL; 2150 ms_card->segment[i].get_index = 0; 2151 ms_card->segment[i].set_index = 0; 2152 ms_card->segment[i].unused_blk_cnt = 0; 2153 2154 dev_dbg(rtsx_dev(chip), "defective block count of segment %d is %d\n", 2155 i, ms_card->segment[i].disable_count); 2156 } 2157 2158 return STATUS_SUCCESS; 2159 2160 INIT_FAIL: 2161 vfree(ms_card->segment); 2162 ms_card->segment = NULL; 2163 2164 return STATUS_FAIL; 2165 } 2166 2167 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off) 2168 { 2169 struct ms_info *ms_card = &chip->ms_card; 2170 struct zone_entry *segment; 2171 2172 if (!ms_card->segment) 2173 return 0xFFFF; 2174 2175 segment = &ms_card->segment[seg_no]; 2176 2177 if (segment->l2p_table) 2178 return segment->l2p_table[log_off]; 2179 2180 return 0xFFFF; 2181 } 2182 2183 static void ms_set_l2p_tbl(struct rtsx_chip *chip, 2184 int seg_no, u16 log_off, u16 phy_blk) 2185 { 2186 struct ms_info *ms_card = &chip->ms_card; 2187 struct zone_entry *segment; 2188 2189 if (!ms_card->segment) 2190 return; 2191 2192 segment = &ms_card->segment[seg_no]; 2193 if (segment->l2p_table) 2194 segment->l2p_table[log_off] = phy_blk; 2195 } 2196 2197 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk) 2198 { 2199 struct ms_info *ms_card = &chip->ms_card; 2200 struct zone_entry *segment; 2201 int seg_no; 2202 2203 seg_no = (int)phy_blk >> 9; 2204 segment = &ms_card->segment[seg_no]; 2205 2206 segment->free_table[segment->set_index++] = phy_blk; 2207 if (segment->set_index >= MS_FREE_TABLE_CNT) 2208 segment->set_index = 0; 2209 2210 segment->unused_blk_cnt++; 2211 } 2212 2213 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no) 2214 { 2215 struct ms_info *ms_card = &chip->ms_card; 2216 struct zone_entry *segment; 2217 u16 phy_blk; 2218 2219 segment = &ms_card->segment[seg_no]; 2220 2221 if (segment->unused_blk_cnt <= 0) 2222 return 0xFFFF; 2223 2224 phy_blk = segment->free_table[segment->get_index]; 2225 segment->free_table[segment->get_index++] = 0xFFFF; 2226 if (segment->get_index >= MS_FREE_TABLE_CNT) 2227 segment->get_index = 0; 2228 2229 segment->unused_blk_cnt--; 2230 2231 return phy_blk; 2232 } 2233 2234 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478, 2235 2974, 3470, 3966, 4462, 4958, 2236 5454, 5950, 6446, 6942, 7438, 2237 7934}; 2238 2239 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk, 2240 u16 log_off, u8 us1, u8 us2) 2241 { 2242 struct ms_info *ms_card = &chip->ms_card; 2243 struct zone_entry *segment; 2244 int seg_no; 2245 u16 tmp_blk; 2246 2247 seg_no = (int)phy_blk >> 9; 2248 segment = &ms_card->segment[seg_no]; 2249 tmp_blk = segment->l2p_table[log_off]; 2250 2251 if (us1 != us2) { 2252 if (us1 == 0) { 2253 if (!(chip->card_wp & MS_CARD)) 2254 ms_erase_block(chip, tmp_blk); 2255 2256 ms_set_unused_block(chip, tmp_blk); 2257 segment->l2p_table[log_off] = phy_blk; 2258 } else { 2259 if (!(chip->card_wp & MS_CARD)) 2260 ms_erase_block(chip, phy_blk); 2261 2262 ms_set_unused_block(chip, phy_blk); 2263 } 2264 } else { 2265 if (phy_blk < tmp_blk) { 2266 if (!(chip->card_wp & MS_CARD)) 2267 ms_erase_block(chip, phy_blk); 2268 2269 ms_set_unused_block(chip, phy_blk); 2270 } else { 2271 if (!(chip->card_wp & MS_CARD)) 2272 ms_erase_block(chip, tmp_blk); 2273 2274 ms_set_unused_block(chip, tmp_blk); 2275 segment->l2p_table[log_off] = phy_blk; 2276 } 2277 } 2278 2279 return STATUS_SUCCESS; 2280 } 2281 2282 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no) 2283 { 2284 struct ms_info *ms_card = &chip->ms_card; 2285 struct zone_entry *segment; 2286 bool defect_flag; 2287 int retval, table_size, disable_cnt, i; 2288 u16 start, end, phy_blk, log_blk, tmp_blk, idx; 2289 u8 extra[MS_EXTRA_SIZE], us1, us2; 2290 2291 dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, seg_no); 2292 2293 if (!ms_card->segment) { 2294 retval = ms_init_l2p_tbl(chip); 2295 if (retval != STATUS_SUCCESS) 2296 return retval; 2297 } 2298 2299 if (ms_card->segment[seg_no].build_flag) { 2300 dev_dbg(rtsx_dev(chip), "l2p table of segment %d has been built\n", 2301 seg_no); 2302 return STATUS_SUCCESS; 2303 } 2304 2305 if (seg_no == 0) 2306 table_size = 494; 2307 else 2308 table_size = 496; 2309 2310 segment = &ms_card->segment[seg_no]; 2311 2312 if (!segment->l2p_table) { 2313 segment->l2p_table = vmalloc(array_size(table_size, 2)); 2314 if (!segment->l2p_table) 2315 goto BUILD_FAIL; 2316 } 2317 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2); 2318 2319 if (!segment->free_table) { 2320 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2); 2321 if (!segment->free_table) 2322 goto BUILD_FAIL; 2323 } 2324 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2); 2325 2326 start = (u16)seg_no << 9; 2327 end = (u16)(seg_no + 1) << 9; 2328 2329 disable_cnt = segment->disable_count; 2330 2331 segment->get_index = 0; 2332 segment->set_index = 0; 2333 segment->unused_blk_cnt = 0; 2334 2335 for (phy_blk = start; phy_blk < end; phy_blk++) { 2336 if (disable_cnt) { 2337 defect_flag = false; 2338 for (i = 0; i < segment->disable_count; i++) { 2339 if (phy_blk == segment->defect_list[i]) { 2340 defect_flag = true; 2341 break; 2342 } 2343 } 2344 if (defect_flag) { 2345 disable_cnt--; 2346 continue; 2347 } 2348 } 2349 2350 retval = ms_read_extra_data(chip, phy_blk, 0, 2351 extra, MS_EXTRA_SIZE); 2352 if (retval != STATUS_SUCCESS) { 2353 dev_dbg(rtsx_dev(chip), "read extra data fail\n"); 2354 ms_set_bad_block(chip, phy_blk); 2355 continue; 2356 } 2357 2358 if (seg_no == ms_card->segment_cnt - 1) { 2359 if (!(extra[1] & NOT_TRANSLATION_TABLE)) { 2360 if (!(chip->card_wp & MS_CARD)) { 2361 retval = ms_erase_block(chip, phy_blk); 2362 if (retval != STATUS_SUCCESS) 2363 continue; 2364 extra[2] = 0xff; 2365 extra[3] = 0xff; 2366 } 2367 } 2368 } 2369 2370 if (!(extra[0] & BLOCK_OK)) 2371 continue; 2372 if (!(extra[1] & NOT_BOOT_BLOCK)) 2373 continue; 2374 if ((extra[0] & PAGE_OK) != PAGE_OK) 2375 continue; 2376 2377 log_blk = ((u16)extra[2] << 8) | extra[3]; 2378 2379 if (log_blk == 0xFFFF) { 2380 if (!(chip->card_wp & MS_CARD)) { 2381 retval = ms_erase_block(chip, phy_blk); 2382 if (retval != STATUS_SUCCESS) 2383 continue; 2384 } 2385 ms_set_unused_block(chip, phy_blk); 2386 continue; 2387 } 2388 2389 if ((log_blk < ms_start_idx[seg_no]) || 2390 (log_blk >= ms_start_idx[seg_no + 1])) { 2391 if (!(chip->card_wp & MS_CARD)) { 2392 retval = ms_erase_block(chip, phy_blk); 2393 if (retval != STATUS_SUCCESS) 2394 continue; 2395 } 2396 ms_set_unused_block(chip, phy_blk); 2397 continue; 2398 } 2399 2400 idx = log_blk - ms_start_idx[seg_no]; 2401 2402 if (segment->l2p_table[idx] == 0xFFFF) { 2403 segment->l2p_table[idx] = phy_blk; 2404 continue; 2405 } 2406 2407 us1 = extra[0] & 0x10; 2408 tmp_blk = segment->l2p_table[idx]; 2409 retval = ms_read_extra_data(chip, tmp_blk, 0, 2410 extra, MS_EXTRA_SIZE); 2411 if (retval != STATUS_SUCCESS) 2412 continue; 2413 us2 = extra[0] & 0x10; 2414 2415 (void)ms_arbitrate_l2p(chip, phy_blk, 2416 log_blk - ms_start_idx[seg_no], us1, us2); 2417 continue; 2418 } 2419 2420 segment->build_flag = 1; 2421 2422 dev_dbg(rtsx_dev(chip), "unused block count: %d\n", 2423 segment->unused_blk_cnt); 2424 2425 /* Logical Address Confirmation Process */ 2426 if (seg_no == ms_card->segment_cnt - 1) { 2427 if (segment->unused_blk_cnt < 2) 2428 chip->card_wp |= MS_CARD; 2429 } else { 2430 if (segment->unused_blk_cnt < 1) 2431 chip->card_wp |= MS_CARD; 2432 } 2433 2434 if (chip->card_wp & MS_CARD) 2435 return STATUS_SUCCESS; 2436 2437 for (log_blk = ms_start_idx[seg_no]; 2438 log_blk < ms_start_idx[seg_no + 1]; log_blk++) { 2439 idx = log_blk - ms_start_idx[seg_no]; 2440 if (segment->l2p_table[idx] == 0xFFFF) { 2441 phy_blk = ms_get_unused_block(chip, seg_no); 2442 if (phy_blk == 0xFFFF) { 2443 chip->card_wp |= MS_CARD; 2444 return STATUS_SUCCESS; 2445 } 2446 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1); 2447 if (retval != STATUS_SUCCESS) 2448 goto BUILD_FAIL; 2449 2450 segment->l2p_table[idx] = phy_blk; 2451 if (seg_no == ms_card->segment_cnt - 1) { 2452 if (segment->unused_blk_cnt < 2) { 2453 chip->card_wp |= MS_CARD; 2454 return STATUS_SUCCESS; 2455 } 2456 } else { 2457 if (segment->unused_blk_cnt < 1) { 2458 chip->card_wp |= MS_CARD; 2459 return STATUS_SUCCESS; 2460 } 2461 } 2462 } 2463 } 2464 2465 /* Make boot block be the first normal block */ 2466 if (seg_no == 0) { 2467 for (log_blk = 0; log_blk < 494; log_blk++) { 2468 tmp_blk = segment->l2p_table[log_blk]; 2469 if (tmp_blk < ms_card->boot_block) { 2470 dev_dbg(rtsx_dev(chip), "Boot block is not the first normal block.\n"); 2471 2472 if (chip->card_wp & MS_CARD) 2473 break; 2474 2475 phy_blk = ms_get_unused_block(chip, 0); 2476 retval = ms_copy_page(chip, tmp_blk, phy_blk, 2477 log_blk, 0, 2478 ms_card->page_off + 1); 2479 if (retval != STATUS_SUCCESS) 2480 return STATUS_FAIL; 2481 2482 segment->l2p_table[log_blk] = phy_blk; 2483 2484 retval = ms_set_bad_block(chip, tmp_blk); 2485 if (retval != STATUS_SUCCESS) 2486 return STATUS_FAIL; 2487 } 2488 } 2489 } 2490 2491 return STATUS_SUCCESS; 2492 2493 BUILD_FAIL: 2494 segment->build_flag = 0; 2495 vfree(segment->l2p_table); 2496 segment->l2p_table = NULL; 2497 vfree(segment->free_table); 2498 segment->free_table = NULL; 2499 2500 return STATUS_FAIL; 2501 } 2502 2503 int reset_ms_card(struct rtsx_chip *chip) 2504 { 2505 struct ms_info *ms_card = &chip->ms_card; 2506 int seg_no = ms_card->total_block / 512 - 1; 2507 int retval; 2508 2509 memset(ms_card, 0, sizeof(struct ms_info)); 2510 2511 retval = enable_card_clock(chip, MS_CARD); 2512 if (retval != STATUS_SUCCESS) 2513 return STATUS_FAIL; 2514 2515 retval = select_card(chip, MS_CARD); 2516 if (retval != STATUS_SUCCESS) 2517 return STATUS_FAIL; 2518 2519 ms_card->ms_type = 0; 2520 2521 retval = reset_ms_pro(chip); 2522 if (retval != STATUS_SUCCESS) { 2523 if (ms_card->check_ms_flow) { 2524 retval = reset_ms(chip); 2525 if (retval != STATUS_SUCCESS) 2526 return STATUS_FAIL; 2527 } else { 2528 return STATUS_FAIL; 2529 } 2530 } 2531 2532 retval = ms_set_init_para(chip); 2533 if (retval != STATUS_SUCCESS) 2534 return STATUS_FAIL; 2535 2536 if (!CHK_MSPRO(ms_card)) { 2537 /* Build table for the last segment, 2538 * to check if L2P table block exists, erasing it 2539 */ 2540 retval = ms_build_l2p_tbl(chip, seg_no); 2541 if (retval != STATUS_SUCCESS) 2542 return STATUS_FAIL; 2543 } 2544 2545 dev_dbg(rtsx_dev(chip), "ms_card->ms_type = 0x%x\n", ms_card->ms_type); 2546 2547 return STATUS_SUCCESS; 2548 } 2549 2550 static int mspro_set_rw_cmd(struct rtsx_chip *chip, 2551 u32 start_sec, u16 sec_cnt, u8 cmd) 2552 { 2553 int retval, i; 2554 u8 data[8]; 2555 2556 data[0] = cmd; 2557 data[1] = (u8)(sec_cnt >> 8); 2558 data[2] = (u8)sec_cnt; 2559 data[3] = (u8)(start_sec >> 24); 2560 data[4] = (u8)(start_sec >> 16); 2561 data[5] = (u8)(start_sec >> 8); 2562 data[6] = (u8)start_sec; 2563 data[7] = 0; 2564 2565 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2566 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, 2567 WAIT_INT, data, 8); 2568 if (retval == STATUS_SUCCESS) 2569 break; 2570 } 2571 if (i == MS_MAX_RETRY_COUNT) 2572 return STATUS_FAIL; 2573 2574 return STATUS_SUCCESS; 2575 } 2576 2577 void mspro_stop_seq_mode(struct rtsx_chip *chip) 2578 { 2579 struct ms_info *ms_card = &chip->ms_card; 2580 int retval; 2581 2582 if (ms_card->seq_mode) { 2583 retval = ms_switch_clock(chip); 2584 if (retval != STATUS_SUCCESS) 2585 return; 2586 2587 ms_card->seq_mode = 0; 2588 ms_card->total_sec_cnt = 0; 2589 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2590 2591 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH); 2592 } 2593 } 2594 2595 static inline int ms_auto_tune_clock(struct rtsx_chip *chip) 2596 { 2597 struct ms_info *ms_card = &chip->ms_card; 2598 int retval; 2599 2600 if (chip->asic_code) { 2601 if (ms_card->ms_clock > 30) 2602 ms_card->ms_clock -= 20; 2603 } else { 2604 if (ms_card->ms_clock == CLK_80) 2605 ms_card->ms_clock = CLK_60; 2606 else if (ms_card->ms_clock == CLK_60) 2607 ms_card->ms_clock = CLK_40; 2608 } 2609 2610 retval = ms_switch_clock(chip); 2611 if (retval != STATUS_SUCCESS) 2612 return STATUS_FAIL; 2613 2614 return STATUS_SUCCESS; 2615 } 2616 2617 static int mspro_rw_multi_sector(struct scsi_cmnd *srb, 2618 struct rtsx_chip *chip, u32 start_sector, 2619 u16 sector_cnt) 2620 { 2621 struct ms_info *ms_card = &chip->ms_card; 2622 bool mode_2k = false; 2623 int retval; 2624 u16 count; 2625 u8 val, trans_mode, rw_tpc, rw_cmd; 2626 2627 ms_set_err_code(chip, MS_NO_ERROR); 2628 2629 ms_card->cleanup_counter = 0; 2630 2631 if (CHK_MSHG(ms_card)) { 2632 if ((start_sector % 4) || (sector_cnt % 4)) { 2633 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2634 rw_tpc = PRO_READ_LONG_DATA; 2635 rw_cmd = PRO_READ_DATA; 2636 } else { 2637 rw_tpc = PRO_WRITE_LONG_DATA; 2638 rw_cmd = PRO_WRITE_DATA; 2639 } 2640 } else { 2641 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2642 rw_tpc = PRO_READ_QUAD_DATA; 2643 rw_cmd = PRO_READ_2K_DATA; 2644 } else { 2645 rw_tpc = PRO_WRITE_QUAD_DATA; 2646 rw_cmd = PRO_WRITE_2K_DATA; 2647 } 2648 mode_2k = true; 2649 } 2650 } else { 2651 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 2652 rw_tpc = PRO_READ_LONG_DATA; 2653 rw_cmd = PRO_READ_DATA; 2654 } else { 2655 rw_tpc = PRO_WRITE_LONG_DATA; 2656 rw_cmd = PRO_WRITE_DATA; 2657 } 2658 } 2659 2660 retval = ms_switch_clock(chip); 2661 if (retval != STATUS_SUCCESS) 2662 return STATUS_FAIL; 2663 2664 if (srb->sc_data_direction == DMA_FROM_DEVICE) 2665 trans_mode = MS_TM_AUTO_READ; 2666 else 2667 trans_mode = MS_TM_AUTO_WRITE; 2668 2669 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 2670 if (retval) 2671 return retval; 2672 2673 if (ms_card->seq_mode) { 2674 if ((ms_card->pre_dir != srb->sc_data_direction) || 2675 ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != 2676 start_sector) || 2677 (mode_2k && (ms_card->seq_mode & MODE_512_SEQ)) || 2678 (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ)) || 2679 !(val & MS_INT_BREQ) || 2680 ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) { 2681 ms_card->seq_mode = 0; 2682 ms_card->total_sec_cnt = 0; 2683 if (val & MS_INT_BREQ) { 2684 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2685 if (retval != STATUS_SUCCESS) 2686 return STATUS_FAIL; 2687 2688 rtsx_write_register(chip, RBCTL, RB_FLUSH, 2689 RB_FLUSH); 2690 } 2691 } 2692 } 2693 2694 if (!ms_card->seq_mode) { 2695 ms_card->total_sec_cnt = 0; 2696 if (sector_cnt >= SEQ_START_CRITERIA) { 2697 if ((ms_card->capacity - start_sector) > 0xFE00) 2698 count = 0xFE00; 2699 else 2700 count = (u16)(ms_card->capacity - start_sector); 2701 2702 if (count > sector_cnt) { 2703 if (mode_2k) 2704 ms_card->seq_mode = MODE_2K_SEQ; 2705 else 2706 ms_card->seq_mode = MODE_512_SEQ; 2707 } 2708 } else { 2709 count = sector_cnt; 2710 } 2711 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd); 2712 if (retval != STATUS_SUCCESS) { 2713 ms_card->seq_mode = 0; 2714 return STATUS_FAIL; 2715 } 2716 } 2717 2718 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt, 2719 WAIT_INT, mode_2k, scsi_sg_count(srb), 2720 scsi_sglist(srb), scsi_bufflen(srb)); 2721 if (retval != STATUS_SUCCESS) { 2722 ms_card->seq_mode = 0; 2723 rtsx_read_register(chip, MS_TRANS_CFG, &val); 2724 rtsx_clear_ms_error(chip); 2725 2726 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 2727 chip->rw_need_retry = 0; 2728 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", 2729 __func__); 2730 return STATUS_FAIL; 2731 } 2732 2733 if (val & MS_INT_BREQ) 2734 ms_send_cmd(chip, PRO_STOP, WAIT_INT); 2735 2736 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 2737 dev_dbg(rtsx_dev(chip), "MSPro CRC error, tune clock!\n"); 2738 chip->rw_need_retry = 1; 2739 ms_auto_tune_clock(chip); 2740 } 2741 2742 return retval; 2743 } 2744 2745 if (ms_card->seq_mode) { 2746 ms_card->pre_sec_addr = start_sector; 2747 ms_card->pre_sec_cnt = sector_cnt; 2748 ms_card->pre_dir = srb->sc_data_direction; 2749 ms_card->total_sec_cnt += sector_cnt; 2750 } 2751 2752 return STATUS_SUCCESS; 2753 } 2754 2755 static int mspro_read_format_progress(struct rtsx_chip *chip, 2756 const int short_data_len) 2757 { 2758 struct ms_info *ms_card = &chip->ms_card; 2759 int retval, i; 2760 u32 total_progress, cur_progress; 2761 u8 cnt, tmp; 2762 u8 data[8]; 2763 2764 dev_dbg(rtsx_dev(chip), "%s, short_data_len = %d\n", __func__, 2765 short_data_len); 2766 2767 retval = ms_switch_clock(chip); 2768 if (retval != STATUS_SUCCESS) { 2769 ms_card->format_status = FORMAT_FAIL; 2770 return STATUS_FAIL; 2771 } 2772 2773 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2774 if (retval != STATUS_SUCCESS) { 2775 ms_card->format_status = FORMAT_FAIL; 2776 return STATUS_FAIL; 2777 } 2778 2779 if (!(tmp & MS_INT_BREQ)) { 2780 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | 2781 MS_INT_ERR)) == MS_INT_CED) { 2782 ms_card->format_status = FORMAT_SUCCESS; 2783 return STATUS_SUCCESS; 2784 } 2785 ms_card->format_status = FORMAT_FAIL; 2786 return STATUS_FAIL; 2787 } 2788 2789 if (short_data_len >= 256) 2790 cnt = 0; 2791 else 2792 cnt = (u8)short_data_len; 2793 2794 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 2795 MS_NO_CHECK_INT); 2796 if (retval != STATUS_SUCCESS) { 2797 ms_card->format_status = FORMAT_FAIL; 2798 return STATUS_FAIL; 2799 } 2800 2801 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT, 2802 data, 8); 2803 if (retval != STATUS_SUCCESS) { 2804 ms_card->format_status = FORMAT_FAIL; 2805 return STATUS_FAIL; 2806 } 2807 2808 total_progress = (data[0] << 24) | (data[1] << 16) | 2809 (data[2] << 8) | data[3]; 2810 cur_progress = (data[4] << 24) | (data[5] << 16) | 2811 (data[6] << 8) | data[7]; 2812 2813 dev_dbg(rtsx_dev(chip), "total_progress = %d, cur_progress = %d\n", 2814 total_progress, cur_progress); 2815 2816 if (total_progress == 0) { 2817 ms_card->progress = 0; 2818 } else { 2819 u64 ulltmp = (u64)cur_progress * (u64)65535; 2820 2821 do_div(ulltmp, total_progress); 2822 ms_card->progress = (u16)ulltmp; 2823 } 2824 dev_dbg(rtsx_dev(chip), "progress = %d\n", ms_card->progress); 2825 2826 for (i = 0; i < 5000; i++) { 2827 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2828 if (retval != STATUS_SUCCESS) { 2829 ms_card->format_status = FORMAT_FAIL; 2830 return STATUS_FAIL; 2831 } 2832 if (tmp & (MS_INT_CED | MS_INT_CMDNK | 2833 MS_INT_BREQ | MS_INT_ERR)) 2834 break; 2835 2836 wait_timeout(1); 2837 } 2838 2839 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0); 2840 if (retval != STATUS_SUCCESS) { 2841 ms_card->format_status = FORMAT_FAIL; 2842 return STATUS_FAIL; 2843 } 2844 2845 if (i == 5000) { 2846 ms_card->format_status = FORMAT_FAIL; 2847 return STATUS_FAIL; 2848 } 2849 2850 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) { 2851 ms_card->format_status = FORMAT_FAIL; 2852 return STATUS_FAIL; 2853 } 2854 2855 if (tmp & MS_INT_CED) { 2856 ms_card->format_status = FORMAT_SUCCESS; 2857 ms_card->pro_under_formatting = 0; 2858 } else if (tmp & MS_INT_BREQ) { 2859 ms_card->format_status = FORMAT_IN_PROGRESS; 2860 } else { 2861 ms_card->format_status = FORMAT_FAIL; 2862 ms_card->pro_under_formatting = 0; 2863 return STATUS_FAIL; 2864 } 2865 2866 return STATUS_SUCCESS; 2867 } 2868 2869 void mspro_polling_format_status(struct rtsx_chip *chip) 2870 { 2871 struct ms_info *ms_card = &chip->ms_card; 2872 int i; 2873 2874 if (ms_card->pro_under_formatting && 2875 (rtsx_get_stat(chip) != RTSX_STAT_SS)) { 2876 rtsx_set_stat(chip, RTSX_STAT_RUN); 2877 2878 for (i = 0; i < 65535; i++) { 2879 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN); 2880 if (ms_card->format_status != FORMAT_IN_PROGRESS) 2881 break; 2882 } 2883 } 2884 } 2885 2886 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip, 2887 int short_data_len, bool quick_format) 2888 { 2889 struct ms_info *ms_card = &chip->ms_card; 2890 int retval, i; 2891 u8 buf[8], tmp; 2892 u16 para; 2893 2894 retval = ms_switch_clock(chip); 2895 if (retval != STATUS_SUCCESS) 2896 return STATUS_FAIL; 2897 2898 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01); 2899 if (retval != STATUS_SUCCESS) 2900 return STATUS_FAIL; 2901 2902 memset(buf, 0, 2); 2903 switch (short_data_len) { 2904 case 32: 2905 buf[0] = 0; 2906 break; 2907 case 64: 2908 buf[0] = 1; 2909 break; 2910 case 128: 2911 buf[0] = 2; 2912 break; 2913 case 256: 2914 default: 2915 buf[0] = 3; 2916 break; 2917 } 2918 2919 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2920 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1, 2921 NO_WAIT_INT, buf, 2); 2922 if (retval == STATUS_SUCCESS) 2923 break; 2924 } 2925 if (i == MS_MAX_RETRY_COUNT) 2926 return STATUS_FAIL; 2927 2928 if (quick_format) 2929 para = 0x0000; 2930 else 2931 para = 0x0001; 2932 2933 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT); 2934 if (retval != STATUS_SUCCESS) 2935 return STATUS_FAIL; 2936 2937 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp); 2938 if (retval) 2939 return retval; 2940 2941 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) 2942 return STATUS_FAIL; 2943 2944 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) { 2945 ms_card->pro_under_formatting = 1; 2946 ms_card->progress = 0; 2947 ms_card->format_status = FORMAT_IN_PROGRESS; 2948 return STATUS_SUCCESS; 2949 } 2950 2951 if (tmp & MS_INT_CED) { 2952 ms_card->pro_under_formatting = 0; 2953 ms_card->progress = 0; 2954 ms_card->format_status = FORMAT_SUCCESS; 2955 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE); 2956 return STATUS_SUCCESS; 2957 } 2958 2959 return STATUS_FAIL; 2960 } 2961 2962 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk, 2963 u16 log_blk, u8 start_page, u8 end_page, 2964 u8 *buf, unsigned int *index, 2965 unsigned int *offset) 2966 { 2967 struct ms_info *ms_card = &chip->ms_card; 2968 int retval, i; 2969 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6]; 2970 u8 *ptr; 2971 2972 retval = ms_read_extra_data(chip, phy_blk, start_page, 2973 extra, MS_EXTRA_SIZE); 2974 if (retval == STATUS_SUCCESS) { 2975 if ((extra[1] & 0x30) != 0x30) { 2976 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 2977 return STATUS_FAIL; 2978 } 2979 } 2980 2981 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 2982 SystemParm, 6); 2983 if (retval != STATUS_SUCCESS) 2984 return STATUS_FAIL; 2985 2986 if (CHK_MS4BIT(ms_card)) 2987 data[0] = 0x88; 2988 else 2989 data[0] = 0x80; 2990 2991 data[1] = 0; 2992 data[2] = (u8)(phy_blk >> 8); 2993 data[3] = (u8)phy_blk; 2994 data[4] = 0; 2995 data[5] = start_page; 2996 2997 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 2998 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, 2999 data, 6); 3000 if (retval == STATUS_SUCCESS) 3001 break; 3002 } 3003 if (i == MS_MAX_RETRY_COUNT) 3004 return STATUS_FAIL; 3005 3006 ms_set_err_code(chip, MS_NO_ERROR); 3007 3008 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT); 3009 if (retval != STATUS_SUCCESS) 3010 return STATUS_FAIL; 3011 3012 ptr = buf; 3013 3014 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3015 ms_set_err_code(chip, MS_NO_ERROR); 3016 3017 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3018 ms_set_err_code(chip, MS_NO_CARD); 3019 return STATUS_FAIL; 3020 } 3021 3022 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3023 if (retval != STATUS_SUCCESS) 3024 return STATUS_FAIL; 3025 3026 if (val & INT_REG_CMDNK) { 3027 ms_set_err_code(chip, MS_CMD_NK); 3028 return STATUS_FAIL; 3029 } 3030 if (val & INT_REG_ERR) { 3031 if (val & INT_REG_BREQ) { 3032 retval = ms_read_status_reg(chip); 3033 if (retval != STATUS_SUCCESS) { 3034 if (!(chip->card_wp & MS_CARD)) { 3035 reset_ms(chip); 3036 ms_set_page_status 3037 (log_blk, setPS_NG, 3038 extra, 3039 MS_EXTRA_SIZE); 3040 ms_write_extra_data 3041 (chip, phy_blk, 3042 page_addr, extra, 3043 MS_EXTRA_SIZE); 3044 } 3045 ms_set_err_code(chip, 3046 MS_FLASH_READ_ERROR); 3047 return STATUS_FAIL; 3048 } 3049 } else { 3050 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3051 return STATUS_FAIL; 3052 } 3053 } else { 3054 if (!(val & INT_REG_BREQ)) { 3055 ms_set_err_code(chip, MS_BREQ_ERROR); 3056 return STATUS_FAIL; 3057 } 3058 } 3059 3060 if (page_addr == (end_page - 1)) { 3061 if (!(val & INT_REG_CED)) { 3062 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT); 3063 if (retval != STATUS_SUCCESS) 3064 return STATUS_FAIL; 3065 } 3066 3067 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, 3068 &val, 1); 3069 if (retval != STATUS_SUCCESS) 3070 return STATUS_FAIL; 3071 3072 if (!(val & INT_REG_CED)) { 3073 ms_set_err_code(chip, MS_FLASH_READ_ERROR); 3074 return STATUS_FAIL; 3075 } 3076 3077 trans_cfg = NO_WAIT_INT; 3078 } else { 3079 trans_cfg = WAIT_INT; 3080 } 3081 3082 rtsx_init_cmd(chip); 3083 3084 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA); 3085 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3086 0xFF, trans_cfg); 3087 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3088 0x01, RING_BUFFER); 3089 3090 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512); 3091 3092 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3093 MS_TRANSFER_START | MS_TM_NORMAL_READ); 3094 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3095 MS_TRANSFER_END, MS_TRANSFER_END); 3096 3097 rtsx_send_cmd_no_wait(chip); 3098 3099 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3100 scsi_sg_count(chip->srb), 3101 index, offset, 3102 DMA_FROM_DEVICE, 3103 chip->ms_timeout); 3104 if (retval < 0) { 3105 if (retval == -ETIMEDOUT) { 3106 ms_set_err_code(chip, MS_TO_ERROR); 3107 rtsx_clear_ms_error(chip); 3108 return STATUS_TIMEDOUT; 3109 } 3110 3111 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3112 if (retval != STATUS_SUCCESS) { 3113 ms_set_err_code(chip, MS_TO_ERROR); 3114 rtsx_clear_ms_error(chip); 3115 return STATUS_TIMEDOUT; 3116 } 3117 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) { 3118 ms_set_err_code(chip, MS_CRC16_ERROR); 3119 rtsx_clear_ms_error(chip); 3120 return STATUS_FAIL; 3121 } 3122 } 3123 3124 if (scsi_sg_count(chip->srb) == 0) 3125 ptr += 512; 3126 } 3127 3128 return STATUS_SUCCESS; 3129 } 3130 3131 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk, 3132 u16 new_blk, u16 log_blk, u8 start_page, 3133 u8 end_page, u8 *buf, unsigned int *index, 3134 unsigned int *offset) 3135 { 3136 struct ms_info *ms_card = &chip->ms_card; 3137 int retval, i; 3138 u8 page_addr, val, data[16]; 3139 u8 *ptr; 3140 3141 if (!start_page) { 3142 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3143 SystemParm, 7); 3144 if (retval != STATUS_SUCCESS) 3145 return STATUS_FAIL; 3146 3147 if (CHK_MS4BIT(ms_card)) 3148 data[0] = 0x88; 3149 else 3150 data[0] = 0x80; 3151 3152 data[1] = 0; 3153 data[2] = (u8)(old_blk >> 8); 3154 data[3] = (u8)old_blk; 3155 data[4] = 0x80; 3156 data[5] = 0; 3157 data[6] = 0xEF; 3158 data[7] = 0xFF; 3159 3160 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, 3161 data, 8); 3162 if (retval != STATUS_SUCCESS) 3163 return STATUS_FAIL; 3164 3165 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3166 if (retval != STATUS_SUCCESS) 3167 return STATUS_FAIL; 3168 3169 ms_set_err_code(chip, MS_NO_ERROR); 3170 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1, 3171 NO_WAIT_INT); 3172 if (retval != STATUS_SUCCESS) 3173 return STATUS_FAIL; 3174 } 3175 3176 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE, 3177 SystemParm, (6 + MS_EXTRA_SIZE)); 3178 if (retval != STATUS_SUCCESS) 3179 return STATUS_FAIL; 3180 3181 ms_set_err_code(chip, MS_NO_ERROR); 3182 3183 if (CHK_MS4BIT(ms_card)) 3184 data[0] = 0x88; 3185 else 3186 data[0] = 0x80; 3187 3188 data[1] = 0; 3189 data[2] = (u8)(new_blk >> 8); 3190 data[3] = (u8)new_blk; 3191 if ((end_page - start_page) == 1) 3192 data[4] = 0x20; 3193 else 3194 data[4] = 0; 3195 3196 data[5] = start_page; 3197 data[6] = 0xF8; 3198 data[7] = 0xFF; 3199 data[8] = (u8)(log_blk >> 8); 3200 data[9] = (u8)log_blk; 3201 3202 for (i = 0x0A; i < 0x10; i++) 3203 data[i] = 0xFF; 3204 3205 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3206 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE, 3207 NO_WAIT_INT, data, 16); 3208 if (retval == STATUS_SUCCESS) 3209 break; 3210 } 3211 if (i == MS_MAX_RETRY_COUNT) 3212 return STATUS_FAIL; 3213 3214 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3215 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT); 3216 if (retval == STATUS_SUCCESS) 3217 break; 3218 } 3219 if (i == MS_MAX_RETRY_COUNT) 3220 return STATUS_FAIL; 3221 3222 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3223 if (retval != STATUS_SUCCESS) 3224 return STATUS_FAIL; 3225 3226 ptr = buf; 3227 for (page_addr = start_page; page_addr < end_page; page_addr++) { 3228 ms_set_err_code(chip, MS_NO_ERROR); 3229 3230 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3231 ms_set_err_code(chip, MS_NO_CARD); 3232 return STATUS_FAIL; 3233 } 3234 3235 if (val & INT_REG_CMDNK) { 3236 ms_set_err_code(chip, MS_CMD_NK); 3237 return STATUS_FAIL; 3238 } 3239 if (val & INT_REG_ERR) { 3240 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3241 return STATUS_FAIL; 3242 } 3243 if (!(val & INT_REG_BREQ)) { 3244 ms_set_err_code(chip, MS_BREQ_ERROR); 3245 return STATUS_FAIL; 3246 } 3247 3248 udelay(30); 3249 3250 rtsx_init_cmd(chip); 3251 3252 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 3253 0xFF, WRITE_PAGE_DATA); 3254 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 3255 0xFF, WAIT_INT); 3256 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 3257 0x01, RING_BUFFER); 3258 3259 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 3260 3261 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 3262 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 3263 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 3264 MS_TRANSFER_END, MS_TRANSFER_END); 3265 3266 rtsx_send_cmd_no_wait(chip); 3267 3268 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr, 512, 3269 scsi_sg_count(chip->srb), 3270 index, offset, 3271 DMA_TO_DEVICE, 3272 chip->ms_timeout); 3273 if (retval < 0) { 3274 ms_set_err_code(chip, MS_TO_ERROR); 3275 rtsx_clear_ms_error(chip); 3276 3277 if (retval == -ETIMEDOUT) 3278 return STATUS_TIMEDOUT; 3279 return STATUS_FAIL; 3280 } 3281 3282 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1); 3283 if (retval != STATUS_SUCCESS) 3284 return STATUS_FAIL; 3285 3286 if ((end_page - start_page) == 1) { 3287 if (!(val & INT_REG_CED)) { 3288 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR); 3289 return STATUS_FAIL; 3290 } 3291 } else { 3292 if (page_addr == (end_page - 1)) { 3293 if (!(val & INT_REG_CED)) { 3294 retval = ms_send_cmd(chip, BLOCK_END, 3295 WAIT_INT); 3296 if (retval != STATUS_SUCCESS) 3297 return STATUS_FAIL; 3298 } 3299 3300 retval = ms_read_bytes(chip, GET_INT, 1, 3301 NO_WAIT_INT, &val, 1); 3302 if (retval != STATUS_SUCCESS) 3303 return STATUS_FAIL; 3304 } 3305 3306 if ((page_addr == (end_page - 1)) || 3307 (page_addr == ms_card->page_off)) { 3308 if (!(val & INT_REG_CED)) { 3309 ms_set_err_code(chip, 3310 MS_FLASH_WRITE_ERROR); 3311 return STATUS_FAIL; 3312 } 3313 } 3314 } 3315 3316 if (scsi_sg_count(chip->srb) == 0) 3317 ptr += 512; 3318 } 3319 3320 return STATUS_SUCCESS; 3321 } 3322 3323 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3324 u16 log_blk, u8 page_off) 3325 { 3326 struct ms_info *ms_card = &chip->ms_card; 3327 int retval, seg_no; 3328 3329 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3330 page_off, ms_card->page_off + 1); 3331 if (retval != STATUS_SUCCESS) 3332 return STATUS_FAIL; 3333 3334 seg_no = old_blk >> 9; 3335 3336 if (MS_TST_BAD_BLOCK_FLG(ms_card)) { 3337 MS_CLR_BAD_BLOCK_FLG(ms_card); 3338 ms_set_bad_block(chip, old_blk); 3339 } else { 3340 retval = ms_erase_block(chip, old_blk); 3341 if (retval == STATUS_SUCCESS) 3342 ms_set_unused_block(chip, old_blk); 3343 } 3344 3345 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk); 3346 3347 return STATUS_SUCCESS; 3348 } 3349 3350 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk, 3351 u16 log_blk, u8 start_page) 3352 { 3353 int retval; 3354 3355 if (start_page) { 3356 retval = ms_copy_page(chip, old_blk, new_blk, log_blk, 3357 0, start_page); 3358 if (retval != STATUS_SUCCESS) 3359 return STATUS_FAIL; 3360 } 3361 3362 return STATUS_SUCCESS; 3363 } 3364 3365 #ifdef MS_DELAY_WRITE 3366 int ms_delay_write(struct rtsx_chip *chip) 3367 { 3368 struct ms_info *ms_card = &chip->ms_card; 3369 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3370 int retval; 3371 3372 if (delay_write->delay_write_flag) { 3373 retval = ms_set_init_para(chip); 3374 if (retval != STATUS_SUCCESS) 3375 return STATUS_FAIL; 3376 3377 delay_write->delay_write_flag = 0; 3378 retval = ms_finish_write(chip, 3379 delay_write->old_phyblock, 3380 delay_write->new_phyblock, 3381 delay_write->logblock, 3382 delay_write->pageoff); 3383 if (retval != STATUS_SUCCESS) 3384 return STATUS_FAIL; 3385 } 3386 3387 return STATUS_SUCCESS; 3388 } 3389 #endif 3390 3391 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3392 { 3393 if (srb->sc_data_direction == DMA_FROM_DEVICE) 3394 set_sense_type(chip, SCSI_LUN(srb), 3395 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3396 else 3397 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR); 3398 } 3399 3400 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3401 u32 start_sector, u16 sector_cnt) 3402 { 3403 struct ms_info *ms_card = &chip->ms_card; 3404 unsigned int lun = SCSI_LUN(srb); 3405 int retval, seg_no; 3406 unsigned int index = 0, offset = 0; 3407 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt; 3408 u8 start_page, end_page = 0, page_cnt; 3409 u8 *ptr; 3410 #ifdef MS_DELAY_WRITE 3411 struct ms_delay_write_tag *delay_write = &ms_card->delay_write; 3412 #endif 3413 3414 ms_set_err_code(chip, MS_NO_ERROR); 3415 3416 ms_card->cleanup_counter = 0; 3417 3418 ptr = (u8 *)scsi_sglist(srb); 3419 3420 retval = ms_switch_clock(chip); 3421 if (retval != STATUS_SUCCESS) { 3422 ms_rw_fail(srb, chip); 3423 return STATUS_FAIL; 3424 } 3425 3426 log_blk = (u16)(start_sector >> ms_card->block_shift); 3427 start_page = (u8)(start_sector & ms_card->page_off); 3428 3429 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) { 3430 if (log_blk < ms_start_idx[seg_no + 1]) 3431 break; 3432 } 3433 3434 if (ms_card->segment[seg_no].build_flag == 0) { 3435 retval = ms_build_l2p_tbl(chip, seg_no); 3436 if (retval != STATUS_SUCCESS) { 3437 chip->card_fail |= MS_CARD; 3438 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT); 3439 return STATUS_FAIL; 3440 } 3441 } 3442 3443 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3444 #ifdef MS_DELAY_WRITE 3445 if (delay_write->delay_write_flag && 3446 (delay_write->logblock == log_blk) && 3447 (start_page > delay_write->pageoff)) { 3448 delay_write->delay_write_flag = 0; 3449 retval = ms_copy_page(chip, 3450 delay_write->old_phyblock, 3451 delay_write->new_phyblock, 3452 log_blk, 3453 delay_write->pageoff, start_page); 3454 if (retval != STATUS_SUCCESS) { 3455 set_sense_type(chip, lun, 3456 SENSE_TYPE_MEDIA_WRITE_ERR); 3457 return STATUS_FAIL; 3458 } 3459 old_blk = delay_write->old_phyblock; 3460 new_blk = delay_write->new_phyblock; 3461 } else if (delay_write->delay_write_flag && 3462 (delay_write->logblock == log_blk) && 3463 (start_page == delay_write->pageoff)) { 3464 delay_write->delay_write_flag = 0; 3465 old_blk = delay_write->old_phyblock; 3466 new_blk = delay_write->new_phyblock; 3467 } else { 3468 retval = ms_delay_write(chip); 3469 if (retval != STATUS_SUCCESS) { 3470 set_sense_type(chip, lun, 3471 SENSE_TYPE_MEDIA_WRITE_ERR); 3472 return STATUS_FAIL; 3473 } 3474 #endif 3475 old_blk = ms_get_l2p_tbl 3476 (chip, seg_no, 3477 log_blk - ms_start_idx[seg_no]); 3478 new_blk = ms_get_unused_block(chip, seg_no); 3479 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) { 3480 set_sense_type(chip, lun, 3481 SENSE_TYPE_MEDIA_WRITE_ERR); 3482 return STATUS_FAIL; 3483 } 3484 3485 retval = ms_prepare_write(chip, old_blk, new_blk, 3486 log_blk, start_page); 3487 if (retval != STATUS_SUCCESS) { 3488 if (detect_card_cd(chip, MS_CARD) != 3489 STATUS_SUCCESS) { 3490 set_sense_type 3491 (chip, lun, 3492 SENSE_TYPE_MEDIA_NOT_PRESENT); 3493 return STATUS_FAIL; 3494 } 3495 set_sense_type(chip, lun, 3496 SENSE_TYPE_MEDIA_WRITE_ERR); 3497 return STATUS_FAIL; 3498 } 3499 #ifdef MS_DELAY_WRITE 3500 } 3501 #endif 3502 } else { 3503 #ifdef MS_DELAY_WRITE 3504 retval = ms_delay_write(chip); 3505 if (retval != STATUS_SUCCESS) { 3506 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3507 set_sense_type(chip, lun, 3508 SENSE_TYPE_MEDIA_NOT_PRESENT); 3509 return STATUS_FAIL; 3510 } 3511 set_sense_type(chip, lun, 3512 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3513 return STATUS_FAIL; 3514 } 3515 #endif 3516 old_blk = ms_get_l2p_tbl(chip, seg_no, 3517 log_blk - ms_start_idx[seg_no]); 3518 if (old_blk == 0xFFFF) { 3519 set_sense_type(chip, lun, 3520 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 3521 return STATUS_FAIL; 3522 } 3523 } 3524 3525 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3526 seg_no, old_blk, new_blk); 3527 3528 while (total_sec_cnt) { 3529 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1)) 3530 end_page = ms_card->page_off + 1; 3531 else 3532 end_page = start_page + (u8)total_sec_cnt; 3533 3534 page_cnt = end_page - start_page; 3535 3536 dev_dbg(rtsx_dev(chip), "start_page = %d, end_page = %d, page_cnt = %d\n", 3537 start_page, end_page, page_cnt); 3538 3539 if (srb->sc_data_direction == DMA_FROM_DEVICE) { 3540 retval = ms_read_multiple_pages(chip, 3541 old_blk, log_blk, 3542 start_page, end_page, 3543 ptr, &index, &offset); 3544 } else { 3545 retval = ms_write_multiple_pages(chip, old_blk, new_blk, 3546 log_blk, start_page, 3547 end_page, ptr, &index, 3548 &offset); 3549 } 3550 3551 if (retval != STATUS_SUCCESS) { 3552 toggle_gpio(chip, 1); 3553 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) { 3554 set_sense_type(chip, lun, 3555 SENSE_TYPE_MEDIA_NOT_PRESENT); 3556 return STATUS_FAIL; 3557 } 3558 ms_rw_fail(srb, chip); 3559 return STATUS_FAIL; 3560 } 3561 3562 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3563 if (end_page == (ms_card->page_off + 1)) { 3564 retval = ms_erase_block(chip, old_blk); 3565 if (retval == STATUS_SUCCESS) 3566 ms_set_unused_block(chip, old_blk); 3567 3568 ms_set_l2p_tbl(chip, seg_no, 3569 log_blk - ms_start_idx[seg_no], 3570 new_blk); 3571 } 3572 } 3573 3574 total_sec_cnt -= page_cnt; 3575 if (scsi_sg_count(srb) == 0) 3576 ptr += page_cnt * 512; 3577 3578 if (total_sec_cnt == 0) 3579 break; 3580 3581 log_blk++; 3582 3583 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; 3584 seg_no++) { 3585 if (log_blk < ms_start_idx[seg_no + 1]) 3586 break; 3587 } 3588 3589 if (ms_card->segment[seg_no].build_flag == 0) { 3590 retval = ms_build_l2p_tbl(chip, seg_no); 3591 if (retval != STATUS_SUCCESS) { 3592 chip->card_fail |= MS_CARD; 3593 set_sense_type(chip, lun, 3594 SENSE_TYPE_MEDIA_NOT_PRESENT); 3595 return STATUS_FAIL; 3596 } 3597 } 3598 3599 old_blk = ms_get_l2p_tbl(chip, seg_no, 3600 log_blk - ms_start_idx[seg_no]); 3601 if (old_blk == 0xFFFF) { 3602 ms_rw_fail(srb, chip); 3603 return STATUS_FAIL; 3604 } 3605 3606 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3607 new_blk = ms_get_unused_block(chip, seg_no); 3608 if (new_blk == 0xFFFF) { 3609 ms_rw_fail(srb, chip); 3610 return STATUS_FAIL; 3611 } 3612 } 3613 3614 dev_dbg(rtsx_dev(chip), "seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n", 3615 seg_no, old_blk, new_blk); 3616 3617 start_page = 0; 3618 } 3619 3620 if (srb->sc_data_direction == DMA_TO_DEVICE) { 3621 if (end_page < (ms_card->page_off + 1)) { 3622 #ifdef MS_DELAY_WRITE 3623 delay_write->delay_write_flag = 1; 3624 delay_write->old_phyblock = old_blk; 3625 delay_write->new_phyblock = new_blk; 3626 delay_write->logblock = log_blk; 3627 delay_write->pageoff = end_page; 3628 #else 3629 retval = ms_finish_write(chip, old_blk, new_blk, 3630 log_blk, end_page); 3631 if (retval != STATUS_SUCCESS) { 3632 if (detect_card_cd(chip, MS_CARD) != 3633 STATUS_SUCCESS) { 3634 set_sense_type 3635 (chip, lun, 3636 SENSE_TYPE_MEDIA_NOT_PRESENT); 3637 return STATUS_FAIL; 3638 } 3639 3640 ms_rw_fail(srb, chip); 3641 return STATUS_FAIL; 3642 } 3643 #endif 3644 } 3645 } 3646 3647 scsi_set_resid(srb, 0); 3648 3649 return STATUS_SUCCESS; 3650 } 3651 3652 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, 3653 u32 start_sector, u16 sector_cnt) 3654 { 3655 struct ms_info *ms_card = &chip->ms_card; 3656 int retval; 3657 3658 if (CHK_MSPRO(ms_card)) 3659 retval = mspro_rw_multi_sector(srb, chip, start_sector, 3660 sector_cnt); 3661 else 3662 retval = ms_rw_multi_sector(srb, chip, start_sector, 3663 sector_cnt); 3664 3665 return retval; 3666 } 3667 3668 void ms_free_l2p_tbl(struct rtsx_chip *chip) 3669 { 3670 struct ms_info *ms_card = &chip->ms_card; 3671 int i = 0; 3672 3673 if (ms_card->segment) { 3674 for (i = 0; i < ms_card->segment_cnt; i++) { 3675 vfree(ms_card->segment[i].l2p_table); 3676 ms_card->segment[i].l2p_table = NULL; 3677 vfree(ms_card->segment[i].free_table); 3678 ms_card->segment[i].free_table = NULL; 3679 } 3680 vfree(ms_card->segment); 3681 ms_card->segment = NULL; 3682 } 3683 } 3684 3685 #ifdef SUPPORT_MAGIC_GATE 3686 3687 #ifdef READ_BYTES_WAIT_INT 3688 static int ms_poll_int(struct rtsx_chip *chip) 3689 { 3690 int retval; 3691 u8 val; 3692 3693 rtsx_init_cmd(chip); 3694 3695 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED); 3696 3697 retval = rtsx_send_cmd(chip, MS_CARD, 5000); 3698 if (retval != STATUS_SUCCESS) 3699 return STATUS_FAIL; 3700 3701 val = *rtsx_get_cmd_data(chip); 3702 if (val & MS_INT_ERR) 3703 return STATUS_FAIL; 3704 3705 return STATUS_SUCCESS; 3706 } 3707 #endif 3708 3709 #ifdef MS_SAMPLE_INT_ERR 3710 static int check_ms_err(struct rtsx_chip *chip) 3711 { 3712 int retval; 3713 u8 val; 3714 3715 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 3716 if (retval != STATUS_SUCCESS) 3717 return 1; 3718 if (val & MS_TRANSFER_ERR) 3719 return 1; 3720 3721 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val); 3722 if (retval != STATUS_SUCCESS) 3723 return 1; 3724 3725 if (val & (MS_INT_ERR | MS_INT_CMDNK)) 3726 return 1; 3727 3728 return 0; 3729 } 3730 #else 3731 static int check_ms_err(struct rtsx_chip *chip) 3732 { 3733 int retval; 3734 u8 val; 3735 3736 retval = rtsx_read_register(chip, MS_TRANSFER, &val); 3737 if (retval != STATUS_SUCCESS) 3738 return 1; 3739 if (val & MS_TRANSFER_ERR) 3740 return 1; 3741 3742 return 0; 3743 } 3744 #endif 3745 3746 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num) 3747 { 3748 int retval, i; 3749 u8 data[8]; 3750 3751 data[0] = cmd; 3752 data[1] = 0; 3753 data[2] = 0; 3754 data[3] = 0; 3755 data[4] = 0; 3756 data[5] = 0; 3757 data[6] = entry_num; 3758 data[7] = 0; 3759 3760 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) { 3761 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT, 3762 data, 8); 3763 if (retval == STATUS_SUCCESS) 3764 break; 3765 } 3766 if (i == MS_MAX_RETRY_COUNT) 3767 return STATUS_FAIL; 3768 3769 if (check_ms_err(chip)) { 3770 rtsx_clear_ms_error(chip); 3771 return STATUS_FAIL; 3772 } 3773 3774 return STATUS_SUCCESS; 3775 } 3776 3777 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type, 3778 u8 mg_entry_num) 3779 { 3780 int retval; 3781 u8 buf[6]; 3782 3783 if (type == 0) 3784 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1); 3785 else 3786 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6); 3787 3788 if (retval != STATUS_SUCCESS) 3789 return STATUS_FAIL; 3790 3791 buf[0] = 0; 3792 buf[1] = 0; 3793 if (type == 1) { 3794 buf[2] = 0; 3795 buf[3] = 0; 3796 buf[4] = 0; 3797 buf[5] = mg_entry_num; 3798 } 3799 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6, 3800 NO_WAIT_INT, buf, 6); 3801 if (retval != STATUS_SUCCESS) 3802 return STATUS_FAIL; 3803 3804 return STATUS_SUCCESS; 3805 } 3806 3807 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3808 { 3809 int retval; 3810 int i; 3811 unsigned int lun = SCSI_LUN(srb); 3812 u8 buf1[32], buf2[12]; 3813 3814 if (scsi_bufflen(srb) < 12) { 3815 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD); 3816 return STATUS_FAIL; 3817 } 3818 3819 ms_cleanup_work(chip); 3820 3821 retval = ms_switch_clock(chip); 3822 if (retval != STATUS_SUCCESS) 3823 return STATUS_FAIL; 3824 3825 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0); 3826 if (retval != STATUS_SUCCESS) { 3827 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3828 return STATUS_FAIL; 3829 } 3830 3831 memset(buf1, 0, 32); 3832 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb); 3833 for (i = 0; i < 8; i++) 3834 buf1[8 + i] = buf2[4 + i]; 3835 3836 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 3837 buf1, 32); 3838 if (retval != STATUS_SUCCESS) { 3839 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3840 return STATUS_FAIL; 3841 } 3842 if (check_ms_err(chip)) { 3843 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 3844 rtsx_clear_ms_error(chip); 3845 return STATUS_FAIL; 3846 } 3847 3848 return STATUS_SUCCESS; 3849 } 3850 3851 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3852 { 3853 int retval = STATUS_FAIL; 3854 int bufflen; 3855 unsigned int lun = SCSI_LUN(srb); 3856 u8 *buf = NULL; 3857 3858 ms_cleanup_work(chip); 3859 3860 retval = ms_switch_clock(chip); 3861 if (retval != STATUS_SUCCESS) 3862 return STATUS_FAIL; 3863 3864 buf = kmalloc(1540, GFP_KERNEL); 3865 if (!buf) 3866 return STATUS_ERROR; 3867 3868 buf[0] = 0x04; 3869 buf[1] = 0x1A; 3870 buf[2] = 0x00; 3871 buf[3] = 0x00; 3872 3873 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0); 3874 if (retval != STATUS_SUCCESS) { 3875 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3876 goto free_buffer; 3877 } 3878 3879 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 3880 3, WAIT_INT, 0, 0, buf + 4, 1536); 3881 if (retval != STATUS_SUCCESS) { 3882 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3883 rtsx_clear_ms_error(chip); 3884 goto free_buffer; 3885 } 3886 if (check_ms_err(chip)) { 3887 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3888 rtsx_clear_ms_error(chip); 3889 retval = STATUS_FAIL; 3890 goto free_buffer; 3891 } 3892 3893 bufflen = min_t(int, 1052, scsi_bufflen(srb)); 3894 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 3895 3896 free_buffer: 3897 kfree(buf); 3898 return retval; 3899 } 3900 3901 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3902 { 3903 struct ms_info *ms_card = &chip->ms_card; 3904 int retval; 3905 int bufflen; 3906 int i; 3907 unsigned int lun = SCSI_LUN(srb); 3908 u8 buf[32]; 3909 3910 ms_cleanup_work(chip); 3911 3912 retval = ms_switch_clock(chip); 3913 if (retval != STATUS_SUCCESS) 3914 return STATUS_FAIL; 3915 3916 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0); 3917 if (retval != STATUS_SUCCESS) { 3918 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3919 return STATUS_FAIL; 3920 } 3921 3922 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 3923 buf, 32); 3924 if (retval != STATUS_SUCCESS) { 3925 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3926 return STATUS_FAIL; 3927 } 3928 if (check_ms_err(chip)) { 3929 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3930 rtsx_clear_ms_error(chip); 3931 return STATUS_FAIL; 3932 } 3933 3934 memcpy(ms_card->magic_gate_id, buf, 16); 3935 3936 #ifdef READ_BYTES_WAIT_INT 3937 retval = ms_poll_int(chip); 3938 if (retval != STATUS_SUCCESS) { 3939 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3940 return STATUS_FAIL; 3941 } 3942 #endif 3943 3944 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0); 3945 if (retval != STATUS_SUCCESS) { 3946 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3947 return STATUS_FAIL; 3948 } 3949 3950 bufflen = min_t(int, 12, scsi_bufflen(srb)); 3951 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 3952 3953 for (i = 0; i < 8; i++) 3954 buf[i] = buf[4 + i]; 3955 3956 for (i = 0; i < 24; i++) 3957 buf[8 + i] = 0; 3958 3959 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 3960 32, WAIT_INT, buf, 32); 3961 if (retval != STATUS_SUCCESS) { 3962 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3963 return STATUS_FAIL; 3964 } 3965 if (check_ms_err(chip)) { 3966 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM); 3967 rtsx_clear_ms_error(chip); 3968 return STATUS_FAIL; 3969 } 3970 3971 ms_card->mg_auth = 0; 3972 3973 return STATUS_SUCCESS; 3974 } 3975 3976 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip) 3977 { 3978 struct ms_info *ms_card = &chip->ms_card; 3979 int retval; 3980 int bufflen; 3981 unsigned int lun = SCSI_LUN(srb); 3982 u8 buf1[32], buf2[36]; 3983 3984 ms_cleanup_work(chip); 3985 3986 retval = ms_switch_clock(chip); 3987 if (retval != STATUS_SUCCESS) 3988 return STATUS_FAIL; 3989 3990 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0); 3991 if (retval != STATUS_SUCCESS) { 3992 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 3993 return STATUS_FAIL; 3994 } 3995 3996 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT, 3997 buf1, 32); 3998 if (retval != STATUS_SUCCESS) { 3999 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4000 return STATUS_FAIL; 4001 } 4002 if (check_ms_err(chip)) { 4003 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4004 rtsx_clear_ms_error(chip); 4005 return STATUS_FAIL; 4006 } 4007 4008 buf2[0] = 0x00; 4009 buf2[1] = 0x22; 4010 buf2[2] = 0x00; 4011 buf2[3] = 0x00; 4012 4013 memcpy(buf2 + 4, ms_card->magic_gate_id, 16); 4014 memcpy(buf2 + 20, buf1, 16); 4015 4016 bufflen = min_t(int, 36, scsi_bufflen(srb)); 4017 rtsx_stor_set_xfer_buf(buf2, bufflen, srb); 4018 4019 #ifdef READ_BYTES_WAIT_INT 4020 retval = ms_poll_int(chip); 4021 if (retval != STATUS_SUCCESS) { 4022 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4023 return STATUS_FAIL; 4024 } 4025 #endif 4026 4027 return STATUS_SUCCESS; 4028 } 4029 4030 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4031 { 4032 struct ms_info *ms_card = &chip->ms_card; 4033 int retval; 4034 int i; 4035 int bufflen; 4036 unsigned int lun = SCSI_LUN(srb); 4037 u8 buf[32]; 4038 4039 ms_cleanup_work(chip); 4040 4041 retval = ms_switch_clock(chip); 4042 if (retval != STATUS_SUCCESS) 4043 return STATUS_FAIL; 4044 4045 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0); 4046 if (retval != STATUS_SUCCESS) { 4047 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4048 return STATUS_FAIL; 4049 } 4050 4051 bufflen = min_t(int, 12, scsi_bufflen(srb)); 4052 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4053 4054 for (i = 0; i < 8; i++) 4055 buf[i] = buf[4 + i]; 4056 4057 for (i = 0; i < 24; i++) 4058 buf[8 + i] = 0; 4059 4060 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT, 4061 buf, 32); 4062 if (retval != STATUS_SUCCESS) { 4063 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4064 return STATUS_FAIL; 4065 } 4066 if (check_ms_err(chip)) { 4067 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN); 4068 rtsx_clear_ms_error(chip); 4069 return STATUS_FAIL; 4070 } 4071 4072 ms_card->mg_auth = 1; 4073 4074 return STATUS_SUCCESS; 4075 } 4076 4077 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4078 { 4079 struct ms_info *ms_card = &chip->ms_card; 4080 int retval; 4081 int bufflen; 4082 unsigned int lun = SCSI_LUN(srb); 4083 u8 *buf = NULL; 4084 4085 ms_cleanup_work(chip); 4086 4087 retval = ms_switch_clock(chip); 4088 if (retval != STATUS_SUCCESS) 4089 return STATUS_FAIL; 4090 4091 buf = kmalloc(1028, GFP_KERNEL); 4092 if (!buf) 4093 return STATUS_ERROR; 4094 4095 buf[0] = 0x04; 4096 buf[1] = 0x02; 4097 buf[2] = 0x00; 4098 buf[3] = 0x00; 4099 4100 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num); 4101 if (retval != STATUS_SUCCESS) { 4102 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4103 goto free_buffer; 4104 } 4105 4106 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA, 4107 2, WAIT_INT, 0, 0, buf + 4, 1024); 4108 if (retval != STATUS_SUCCESS) { 4109 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4110 rtsx_clear_ms_error(chip); 4111 goto free_buffer; 4112 } 4113 if (check_ms_err(chip)) { 4114 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR); 4115 rtsx_clear_ms_error(chip); 4116 retval = STATUS_FAIL; 4117 goto free_buffer; 4118 } 4119 4120 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4121 rtsx_stor_set_xfer_buf(buf, bufflen, srb); 4122 4123 free_buffer: 4124 kfree(buf); 4125 return retval; 4126 } 4127 4128 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip) 4129 { 4130 struct ms_info *ms_card = &chip->ms_card; 4131 int retval; 4132 int bufflen; 4133 #ifdef MG_SET_ICV_SLOW 4134 int i; 4135 #endif 4136 unsigned int lun = SCSI_LUN(srb); 4137 u8 *buf = NULL; 4138 4139 ms_cleanup_work(chip); 4140 4141 retval = ms_switch_clock(chip); 4142 if (retval != STATUS_SUCCESS) 4143 return STATUS_FAIL; 4144 4145 buf = kmalloc(1028, GFP_KERNEL); 4146 if (!buf) 4147 return STATUS_ERROR; 4148 4149 bufflen = min_t(int, 1028, scsi_bufflen(srb)); 4150 rtsx_stor_get_xfer_buf(buf, bufflen, srb); 4151 4152 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num); 4153 if (retval != STATUS_SUCCESS) { 4154 if (ms_card->mg_auth == 0) { 4155 if ((buf[5] & 0xC0) != 0) 4156 set_sense_type 4157 (chip, lun, 4158 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4159 else 4160 set_sense_type(chip, lun, 4161 SENSE_TYPE_MG_WRITE_ERR); 4162 } else { 4163 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4164 } 4165 goto SetICVFinish; 4166 } 4167 4168 #ifdef MG_SET_ICV_SLOW 4169 for (i = 0; i < 2; i++) { 4170 udelay(50); 4171 4172 rtsx_init_cmd(chip); 4173 4174 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 4175 0xFF, PRO_WRITE_LONG_DATA); 4176 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT); 4177 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 4178 0x01, RING_BUFFER); 4179 4180 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512); 4181 4182 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF, 4183 MS_TRANSFER_START | MS_TM_NORMAL_WRITE); 4184 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER, 4185 MS_TRANSFER_END, MS_TRANSFER_END); 4186 4187 rtsx_send_cmd_no_wait(chip); 4188 4189 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i * 512, 4190 512, 0, DMA_TO_DEVICE, 3000); 4191 if ((retval < 0) || check_ms_err(chip)) { 4192 rtsx_clear_ms_error(chip); 4193 if (ms_card->mg_auth == 0) { 4194 if ((buf[5] & 0xC0) != 0) 4195 set_sense_type 4196 (chip, lun, 4197 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4198 else 4199 set_sense_type(chip, lun, 4200 SENSE_TYPE_MG_WRITE_ERR); 4201 } else { 4202 set_sense_type(chip, lun, 4203 SENSE_TYPE_MG_WRITE_ERR); 4204 } 4205 retval = STATUS_FAIL; 4206 goto SetICVFinish; 4207 } 4208 } 4209 #else 4210 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA, 4211 2, WAIT_INT, 0, 0, buf + 4, 1024); 4212 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) { 4213 rtsx_clear_ms_error(chip); 4214 if (ms_card->mg_auth == 0) { 4215 if ((buf[5] & 0xC0) != 0) 4216 set_sense_type 4217 (chip, lun, 4218 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB); 4219 else 4220 set_sense_type(chip, lun, 4221 SENSE_TYPE_MG_WRITE_ERR); 4222 } else { 4223 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR); 4224 } 4225 goto SetICVFinish; 4226 } 4227 #endif 4228 4229 SetICVFinish: 4230 kfree(buf); 4231 return retval; 4232 } 4233 4234 #endif /* SUPPORT_MAGIC_GATE */ 4235 4236 void ms_cleanup_work(struct rtsx_chip *chip) 4237 { 4238 struct ms_info *ms_card = &chip->ms_card; 4239 4240 if (CHK_MSPRO(ms_card)) { 4241 if (ms_card->seq_mode) { 4242 dev_dbg(rtsx_dev(chip), "MS Pro: stop transmission\n"); 4243 mspro_stop_seq_mode(chip); 4244 ms_card->cleanup_counter = 0; 4245 } 4246 if (CHK_MSHG(ms_card)) { 4247 rtsx_write_register(chip, MS_CFG, 4248 MS_2K_SECTOR_MODE, 0x00); 4249 } 4250 } 4251 #ifdef MS_DELAY_WRITE 4252 else if ((!CHK_MSPRO(ms_card)) && 4253 ms_card->delay_write.delay_write_flag) { 4254 dev_dbg(rtsx_dev(chip), "MS: delay write\n"); 4255 ms_delay_write(chip); 4256 ms_card->cleanup_counter = 0; 4257 } 4258 #endif 4259 } 4260 4261 int ms_power_off_card3v3(struct rtsx_chip *chip) 4262 { 4263 int retval; 4264 4265 retval = disable_card_clock(chip, MS_CARD); 4266 if (retval != STATUS_SUCCESS) 4267 return STATUS_FAIL; 4268 4269 if (chip->asic_code) { 4270 retval = ms_pull_ctl_disable(chip); 4271 if (retval != STATUS_SUCCESS) 4272 return STATUS_FAIL; 4273 } else { 4274 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 4275 FPGA_MS_PULL_CTL_BIT | 0x20, 4276 FPGA_MS_PULL_CTL_BIT); 4277 if (retval) 4278 return retval; 4279 } 4280 retval = rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0); 4281 if (retval) 4282 return retval; 4283 4284 if (!chip->ft2_fast_mode) { 4285 retval = card_power_off(chip, MS_CARD); 4286 if (retval != STATUS_SUCCESS) 4287 return STATUS_FAIL; 4288 } 4289 4290 return STATUS_SUCCESS; 4291 } 4292 4293 int release_ms_card(struct rtsx_chip *chip) 4294 { 4295 struct ms_info *ms_card = &chip->ms_card; 4296 int retval; 4297 4298 #ifdef MS_DELAY_WRITE 4299 ms_card->delay_write.delay_write_flag = 0; 4300 #endif 4301 ms_card->pro_under_formatting = 0; 4302 4303 chip->card_ready &= ~MS_CARD; 4304 chip->card_fail &= ~MS_CARD; 4305 chip->card_wp &= ~MS_CARD; 4306 4307 ms_free_l2p_tbl(chip); 4308 4309 memset(ms_card->raw_sys_info, 0, 96); 4310 #ifdef SUPPORT_PCGL_1P18 4311 memset(ms_card->raw_model_name, 0, 48); 4312 #endif 4313 4314 retval = ms_power_off_card3v3(chip); 4315 if (retval != STATUS_SUCCESS) 4316 return STATUS_FAIL; 4317 4318 return STATUS_SUCCESS; 4319 } 4320