192096dc0SQuytelda Kahja /* SPDX-License-Identifier: GPL-2.0 */ 292096dc0SQuytelda Kahja /****************************************************************************** 392096dc0SQuytelda Kahja * 492096dc0SQuytelda Kahja * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 592096dc0SQuytelda Kahja * 692096dc0SQuytelda Kahja ******************************************************************************/ 792096dc0SQuytelda Kahja #ifndef __INC_HAL8723BPHYCFG_H__ 892096dc0SQuytelda Kahja #define __INC_HAL8723BPHYCFG_H__ 992096dc0SQuytelda Kahja 1092096dc0SQuytelda Kahja /*--------------------------Define Parameters-------------------------------*/ 1192096dc0SQuytelda Kahja #define LOOP_LIMIT 5 1292096dc0SQuytelda Kahja #define MAX_STALL_TIME 50 /* us */ 1392096dc0SQuytelda Kahja #define AntennaDiversityValue 0x80 /* Adapter->bSoftwareAntennaDiversity ? 0x00:0x80) */ 1492096dc0SQuytelda Kahja #define MAX_TXPWR_IDX_NMODE_92S 63 1592096dc0SQuytelda Kahja #define Reset_Cnt_Limit 3 1692096dc0SQuytelda Kahja 1792096dc0SQuytelda Kahja #define MAX_AGGR_NUM 0x07 1892096dc0SQuytelda Kahja 1992096dc0SQuytelda Kahja 2092096dc0SQuytelda Kahja /*--------------------------Define Parameters End-------------------------------*/ 2192096dc0SQuytelda Kahja 2292096dc0SQuytelda Kahja 2392096dc0SQuytelda Kahja /*------------------------------Define structure----------------------------*/ 2492096dc0SQuytelda Kahja 2592096dc0SQuytelda Kahja /*------------------------------Define structure End----------------------------*/ 2692096dc0SQuytelda Kahja 2792096dc0SQuytelda Kahja /*--------------------------Exported Function prototype---------------------*/ 280b64587aSAditya Jain u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask); 2992096dc0SQuytelda Kahja 300b64587aSAditya Jain void PHY_SetBBReg_8723B(struct adapter *Adapter, u32 RegAddr, 310b64587aSAditya Jain u32 BitMask, u32 Data); 3292096dc0SQuytelda Kahja 330b64587aSAditya Jain u32 PHY_QueryRFReg_8723B(struct adapter *Adapter, u8 eRFPath, 340b64587aSAditya Jain u32 RegAddr, u32 BitMask); 3592096dc0SQuytelda Kahja 360b64587aSAditya Jain void PHY_SetRFReg_8723B(struct adapter *Adapter, u8 eRFPath, 370b64587aSAditya Jain u32 RegAddr, u32 BitMask, u32 Data); 3892096dc0SQuytelda Kahja 3992096dc0SQuytelda Kahja /* MAC/BB/RF HAL config */ 4092096dc0SQuytelda Kahja int PHY_BBConfig8723B(struct adapter *Adapter); 4192096dc0SQuytelda Kahja 4292096dc0SQuytelda Kahja int PHY_RFConfig8723B(struct adapter *Adapter); 4392096dc0SQuytelda Kahja 4492096dc0SQuytelda Kahja s32 PHY_MACConfig8723B(struct adapter *padapter); 4592096dc0SQuytelda Kahja 460b64587aSAditya Jain void PHY_SetTxPowerIndex(struct adapter *Adapter, u32 PowerIndex, 470b64587aSAditya Jain u8 RFPath, u8 Rate); 4892096dc0SQuytelda Kahja 490b64587aSAditya Jain u8 PHY_GetTxPowerIndex(struct adapter *padapter, u8 RFPath, u8 Rate, 50*80e3e599SMarco Cesati enum channel_width BandWidth, u8 Channel); 5192096dc0SQuytelda Kahja 520b64587aSAditya Jain void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel); 5392096dc0SQuytelda Kahja 540b64587aSAditya Jain void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 channel); 5592096dc0SQuytelda Kahja 56*80e3e599SMarco Cesati void PHY_SetBWMode8723B(struct adapter *Adapter, enum channel_width Bandwidth, 570b64587aSAditya Jain unsigned char Offset); 5892096dc0SQuytelda Kahja 590b64587aSAditya Jain /* Call after initialization */ 600b64587aSAditya Jain void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel); 6192096dc0SQuytelda Kahja 620b64587aSAditya Jain void PHY_SetSwChnlBWMode8723B(struct adapter *Adapter, u8 channel, 63*80e3e599SMarco Cesati enum channel_width Bandwidth, 640b64587aSAditya Jain u8 Offset40, u8 Offset80); 6592096dc0SQuytelda Kahja 6692096dc0SQuytelda Kahja /*--------------------------Exported Function prototype End---------------------*/ 6792096dc0SQuytelda Kahja 6892096dc0SQuytelda Kahja #endif 69