1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __HAL_INTF_H__ 8 #define __HAL_INTF_H__ 9 10 11 enum rtl871x_hci_type { 12 RTW_PCIE = BIT0, 13 RTW_USB = BIT1, 14 RTW_SDIO = BIT2, 15 RTW_GSPI = BIT3, 16 }; 17 18 enum hw_variables { 19 HW_VAR_MEDIA_STATUS, 20 HW_VAR_MEDIA_STATUS1, 21 HW_VAR_SET_OPMODE, 22 HW_VAR_MAC_ADDR, 23 HW_VAR_BSSID, 24 HW_VAR_INIT_RTS_RATE, 25 HW_VAR_BASIC_RATE, 26 HW_VAR_TXPAUSE, 27 HW_VAR_BCN_FUNC, 28 HW_VAR_CORRECT_TSF, 29 HW_VAR_CHECK_BSSID, 30 HW_VAR_MLME_DISCONNECT, 31 HW_VAR_MLME_SITESURVEY, 32 HW_VAR_MLME_JOIN, 33 HW_VAR_ON_RCR_AM, 34 HW_VAR_OFF_RCR_AM, 35 HW_VAR_BEACON_INTERVAL, 36 HW_VAR_SLOT_TIME, 37 HW_VAR_RESP_SIFS, 38 HW_VAR_ACK_PREAMBLE, 39 HW_VAR_SEC_CFG, 40 HW_VAR_SEC_DK_CFG, 41 HW_VAR_BCN_VALID, 42 HW_VAR_RF_TYPE, 43 HW_VAR_DM_FLAG, 44 HW_VAR_DM_FUNC_OP, 45 HW_VAR_DM_FUNC_SET, 46 HW_VAR_DM_FUNC_CLR, 47 HW_VAR_CAM_EMPTY_ENTRY, 48 HW_VAR_CAM_INVALID_ALL, 49 HW_VAR_CAM_WRITE, 50 HW_VAR_CAM_READ, 51 HW_VAR_AC_PARAM_VO, 52 HW_VAR_AC_PARAM_VI, 53 HW_VAR_AC_PARAM_BE, 54 HW_VAR_AC_PARAM_BK, 55 HW_VAR_ACM_CTRL, 56 HW_VAR_AMPDU_MIN_SPACE, 57 HW_VAR_AMPDU_FACTOR, 58 HW_VAR_RXDMA_AGG_PG_TH, 59 HW_VAR_SET_RPWM, 60 HW_VAR_CPWM, 61 HW_VAR_H2C_FW_PWRMODE, 62 HW_VAR_H2C_PS_TUNE_PARAM, 63 HW_VAR_H2C_FW_JOINBSSRPT, 64 HW_VAR_FWLPS_RF_ON, 65 HW_VAR_H2C_FW_P2P_PS_OFFLOAD, 66 HW_VAR_TDLS_WRCR, 67 HW_VAR_TDLS_INIT_CH_SEN, 68 HW_VAR_TDLS_RS_RCR, 69 HW_VAR_TDLS_DONE_CH_SEN, 70 HW_VAR_INITIAL_GAIN, 71 HW_VAR_TRIGGER_GPIO_0, 72 HW_VAR_BT_SET_COEXIST, 73 HW_VAR_BT_ISSUE_DELBA, 74 HW_VAR_CURRENT_ANTENNA, 75 HW_VAR_ANTENNA_DIVERSITY_LINK, 76 HW_VAR_ANTENNA_DIVERSITY_SELECT, 77 HW_VAR_SWITCH_EPHY_WoWLAN, 78 HW_VAR_EFUSE_USAGE, 79 HW_VAR_EFUSE_BYTES, 80 HW_VAR_EFUSE_BT_USAGE, 81 HW_VAR_EFUSE_BT_BYTES, 82 HW_VAR_FIFO_CLEARN_UP, 83 HW_VAR_CHECK_TXBUF, 84 HW_VAR_PCIE_STOP_TX_DMA, 85 HW_VAR_APFM_ON_MAC, /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 86 /* The valid upper nav range for the HW updating, if the true value is larger than the upper range, the HW won't update it. */ 87 /* Unit in microsecond. 0 means disable this function. */ 88 #ifdef CONFIG_AP_WOWLAN 89 HW_VAR_AP_WOWLAN, 90 #endif 91 HW_VAR_SYS_CLKR, 92 HW_VAR_NAV_UPPER, 93 HW_VAR_C2H_HANDLE, 94 HW_VAR_RPT_TIMER_SETTING, 95 HW_VAR_TX_RPT_MAX_MACID, 96 HW_VAR_H2C_MEDIA_STATUS_RPT, 97 HW_VAR_CHK_HI_QUEUE_EMPTY, 98 HW_VAR_DL_BCN_SEL, 99 HW_VAR_AMPDU_MAX_TIME, 100 HW_VAR_WIRELESS_MODE, 101 HW_VAR_USB_MODE, 102 HW_VAR_PORT_SWITCH, 103 HW_VAR_DO_IQK, 104 HW_VAR_DM_IN_LPS, 105 HW_VAR_SET_REQ_FW_PS, 106 HW_VAR_FW_PS_STATE, 107 HW_VAR_SOUNDING_ENTER, 108 HW_VAR_SOUNDING_LEAVE, 109 HW_VAR_SOUNDING_RATE, 110 HW_VAR_SOUNDING_STATUS, 111 HW_VAR_SOUNDING_FW_NDPA, 112 HW_VAR_SOUNDING_CLK, 113 HW_VAR_DL_RSVD_PAGE, 114 HW_VAR_MACID_SLEEP, 115 HW_VAR_MACID_WAKEUP, 116 }; 117 118 enum hal_def_variable { 119 HAL_DEF_UNDERCORATEDSMOOTHEDPWDB, 120 HAL_DEF_IS_SUPPORT_ANT_DIV, 121 HAL_DEF_CURRENT_ANTENNA, 122 HAL_DEF_DRVINFO_SZ, 123 HAL_DEF_MAX_RECVBUF_SZ, 124 HAL_DEF_RX_PACKET_OFFSET, 125 HAL_DEF_DBG_DUMP_RXPKT,/* for dbg */ 126 HAL_DEF_DBG_DM_FUNC,/* for dbg */ 127 HAL_DEF_RA_DECISION_RATE, 128 HAL_DEF_RA_SGI, 129 HAL_DEF_PT_PWR_STATUS, 130 HAL_DEF_TX_LDPC, /* LDPC support */ 131 HAL_DEF_RX_LDPC, /* LDPC support */ 132 HAL_DEF_TX_STBC, /* TX STBC support */ 133 HAL_DEF_RX_STBC, /* RX STBC support */ 134 HAL_DEF_EXPLICIT_BEAMFORMER,/* Explicit Compressed Steering Capable */ 135 HAL_DEF_EXPLICIT_BEAMFORMEE,/* Explicit Compressed Beamforming Feedback Capable */ 136 HW_VAR_MAX_RX_AMPDU_FACTOR, 137 HW_DEF_RA_INFO_DUMP, 138 HAL_DEF_DBG_DUMP_TXPKT, 139 HW_DEF_FA_CNT_DUMP, 140 HW_DEF_ODM_DBG_FLAG, 141 HW_DEF_ODM_DBG_LEVEL, 142 HAL_DEF_TX_PAGE_SIZE, 143 HAL_DEF_TX_PAGE_BOUNDARY, 144 HAL_DEF_TX_PAGE_BOUNDARY_WOWLAN, 145 HAL_DEF_ANT_DETECT,/* to do for 8723a */ 146 HAL_DEF_PCI_SUUPORT_L1_BACKDOOR, /* Determine if the L1 Backdoor setting is turned on. */ 147 HAL_DEF_PCI_AMD_L1_SUPPORT, 148 HAL_DEF_PCI_ASPM_OSC, /* Support for ASPM OSC, added by Roger, 2013.03.27. */ 149 HAL_DEF_MACID_SLEEP, /* Support for MACID sleep */ 150 HAL_DEF_DBG_RX_INFO_DUMP, 151 }; 152 153 enum hal_odm_variable { 154 HAL_ODM_STA_INFO, 155 HAL_ODM_P2P_STATE, 156 HAL_ODM_WIFI_DISPLAY_STATE, 157 HAL_ODM_NOISE_MONITOR, 158 }; 159 160 enum hal_intf_ps_func { 161 HAL_USB_SELECT_SUSPEND, 162 HAL_MAX_ID, 163 }; 164 165 typedef s32 (*c2h_id_filter)(u8 *c2h_evt); 166 167 struct hal_ops { 168 u32 (*hal_power_on)(struct adapter *padapter); 169 void (*hal_power_off)(struct adapter *padapter); 170 u32 (*hal_init)(struct adapter *padapter); 171 u32 (*hal_deinit)(struct adapter *padapter); 172 173 void (*free_hal_data)(struct adapter *padapter); 174 175 u32 (*inirp_init)(struct adapter *padapter); 176 u32 (*inirp_deinit)(struct adapter *padapter); 177 void (*irp_reset)(struct adapter *padapter); 178 179 s32 (*init_xmit_priv)(struct adapter *padapter); 180 void (*free_xmit_priv)(struct adapter *padapter); 181 182 s32 (*init_recv_priv)(struct adapter *padapter); 183 void (*free_recv_priv)(struct adapter *padapter); 184 185 void (*dm_init)(struct adapter *padapter); 186 void (*dm_deinit)(struct adapter *padapter); 187 void (*read_chip_version)(struct adapter *padapter); 188 189 void (*init_default_value)(struct adapter *padapter); 190 191 void (*intf_chip_configure)(struct adapter *padapter); 192 193 void (*read_adapter_info)(struct adapter *padapter); 194 195 void (*enable_interrupt)(struct adapter *padapter); 196 void (*disable_interrupt)(struct adapter *padapter); 197 u8 (*check_ips_status)(struct adapter *padapter); 198 s32 (*interrupt_handler)(struct adapter *padapter); 199 void (*clear_interrupt)(struct adapter *padapter); 200 void (*set_bwmode_handler)(struct adapter *padapter, enum CHANNEL_WIDTH Bandwidth, u8 Offset); 201 void (*set_channel_handler)(struct adapter *padapter, u8 channel); 202 void (*set_chnl_bw_handler)(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); 203 204 void (*set_tx_power_level_handler)(struct adapter *padapter, u8 channel); 205 void (*get_tx_power_level_handler)(struct adapter *padapter, s32 *powerlevel); 206 207 void (*hal_dm_watchdog)(struct adapter *padapter); 208 void (*hal_dm_watchdog_in_lps)(struct adapter *padapter); 209 210 211 void (*SetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val); 212 void (*GetHwRegHandler)(struct adapter *padapter, u8 variable, u8 *val); 213 214 void (*SetHwRegHandlerWithBuf)(struct adapter *padapter, u8 variable, u8 *pbuf, int len); 215 216 u8 (*GetHalDefVarHandler)(struct adapter *padapter, enum hal_def_variable eVariable, void *pValue); 217 u8 (*SetHalDefVarHandler)(struct adapter *padapter, enum hal_def_variable eVariable, void *pValue); 218 219 void (*GetHalODMVarHandler)(struct adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, void *pValue2); 220 void (*SetHalODMVarHandler)(struct adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet); 221 222 void (*UpdateRAMaskHandler)(struct adapter *padapter, u32 mac_id, u8 rssi_level); 223 void (*SetBeaconRelatedRegistersHandler)(struct adapter *padapter); 224 225 void (*Add_RateATid)(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level); 226 227 void (*run_thread)(struct adapter *padapter); 228 void (*cancel_thread)(struct adapter *padapter); 229 230 u8 (*interface_ps_func)(struct adapter *padapter, enum hal_intf_ps_func efunc_id, u8 *val); 231 232 s32 (*hal_xmit)(struct adapter *padapter, struct xmit_frame *pxmitframe); 233 /* 234 * mgnt_xmit should be implemented to run in interrupt context 235 */ 236 s32 (*mgnt_xmit)(struct adapter *padapter, struct xmit_frame *pmgntframe); 237 s32 (*hal_xmitframe_enqueue)(struct adapter *padapter, struct xmit_frame *pxmitframe); 238 239 u32 (*read_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask); 240 void (*write_bbreg)(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 241 u32 (*read_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask); 242 void (*write_rfreg)(struct adapter *padapter, u8 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); 243 244 void (*EfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState); 245 void (*BTEfusePowerSwitch)(struct adapter *padapter, u8 bWrite, u8 PwrState); 246 void (*ReadEFuse)(struct adapter *padapter, u8 efuseType, u16 _offset, u16 _size_byte, u8 *pbuf, bool bPseudoTest); 247 void (*EFUSEGetEfuseDefinition)(struct adapter *padapter, u8 efuseType, u8 type, void *pOut, bool bPseudoTest); 248 u16 (*EfuseGetCurrentSize)(struct adapter *padapter, u8 efuseType, bool bPseudoTest); 249 int (*Efuse_PgPacketRead)(struct adapter *padapter, u8 offset, u8 *data, bool bPseudoTest); 250 int (*Efuse_PgPacketWrite)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest); 251 u8 (*Efuse_WordEnableDataWrite)(struct adapter *padapter, u16 efuse_addr, u8 word_en, u8 *data, bool bPseudoTest); 252 bool (*Efuse_PgPacketWrite_BT)(struct adapter *padapter, u8 offset, u8 word_en, u8 *data, bool bPseudoTest); 253 254 s32 (*xmit_thread_handler)(struct adapter *padapter); 255 void (*hal_notch_filter)(struct adapter *adapter, bool enable); 256 void (*hal_reset_security_engine)(struct adapter *adapter); 257 s32 (*c2h_handler)(struct adapter *padapter, u8 *c2h_evt); 258 c2h_id_filter c2h_id_filter_ccx; 259 260 s32 (*fill_h2c_cmd)(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); 261 }; 262 263 enum rt_eeprom_type { 264 EEPROM_93C46, 265 EEPROM_93C56, 266 EEPROM_BOOT_EFUSE, 267 }; 268 269 #define RF_CHANGE_BY_INIT 0 270 #define RF_CHANGE_BY_IPS BIT28 271 #define RF_CHANGE_BY_PS BIT29 272 #define RF_CHANGE_BY_HW BIT30 273 #define RF_CHANGE_BY_SW BIT31 274 275 #define GET_EEPROM_EFUSE_PRIV(adapter) (&adapter->eeprompriv) 276 #define is_boot_from_eeprom(adapter) (adapter->eeprompriv.EepromOrEfuse) 277 278 enum wowlan_subcode { 279 WOWLAN_PATTERN_MATCH = 1, 280 WOWLAN_MAGIC_PACKET = 2, 281 WOWLAN_UNICAST = 3, 282 WOWLAN_SET_PATTERN = 4, 283 WOWLAN_DUMP_REG = 5, 284 WOWLAN_ENABLE = 6, 285 WOWLAN_DISABLE = 7, 286 WOWLAN_STATUS = 8, 287 WOWLAN_DEBUG_RELOAD_FW = 9, 288 WOWLAN_DEBUG_1 = 10, 289 WOWLAN_DEBUG_2 = 11, 290 WOWLAN_AP_ENABLE = 12, 291 WOWLAN_AP_DISABLE = 13 292 }; 293 294 struct wowlan_ioctl_param { 295 unsigned int subcode; 296 unsigned int subcode_value; 297 unsigned int wakeup_reason; 298 unsigned int len; 299 unsigned char pattern[0]; 300 }; 301 302 #define Rx_Pairwisekey 0x01 303 #define Rx_GTK 0x02 304 #define Rx_DisAssoc 0x04 305 #define Rx_DeAuth 0x08 306 #define Rx_ARPReq 0x09 307 #define FWDecisionDisconnect 0x10 308 #define Rx_MagicPkt 0x21 309 #define Rx_UnicastPkt 0x22 310 #define Rx_PatternPkt 0x23 311 #define RX_PNOWakeUp 0x55 312 #define AP_WakeUp 0x66 313 314 void rtw_hal_def_value_init(struct adapter *padapter); 315 316 void rtw_hal_free_data(struct adapter *padapter); 317 318 void rtw_hal_dm_init(struct adapter *padapter); 319 void rtw_hal_dm_deinit(struct adapter *padapter); 320 321 uint rtw_hal_init(struct adapter *padapter); 322 uint rtw_hal_deinit(struct adapter *padapter); 323 void rtw_hal_stop(struct adapter *padapter); 324 void rtw_hal_set_hwreg(struct adapter *padapter, u8 variable, u8 *val); 325 void rtw_hal_get_hwreg(struct adapter *padapter, u8 variable, u8 *val); 326 327 void rtw_hal_set_hwreg_with_buf(struct adapter *padapter, u8 variable, u8 *pbuf, int len); 328 329 void rtw_hal_chip_configure(struct adapter *padapter); 330 void rtw_hal_read_chip_info(struct adapter *padapter); 331 void rtw_hal_read_chip_version(struct adapter *padapter); 332 333 u8 rtw_hal_set_def_var(struct adapter *padapter, enum hal_def_variable eVariable, void *pValue); 334 u8 rtw_hal_get_def_var(struct adapter *padapter, enum hal_def_variable eVariable, void *pValue); 335 336 void rtw_hal_set_odm_var(struct adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, bool bSet); 337 void rtw_hal_get_odm_var(struct adapter *padapter, enum hal_odm_variable eVariable, void *pValue1, void *pValue2); 338 339 void rtw_hal_enable_interrupt(struct adapter *padapter); 340 void rtw_hal_disable_interrupt(struct adapter *padapter); 341 342 u8 rtw_hal_check_ips_status(struct adapter *padapter); 343 344 s32 rtw_hal_xmitframe_enqueue(struct adapter *padapter, struct xmit_frame *pxmitframe); 345 s32 rtw_hal_xmit(struct adapter *padapter, struct xmit_frame *pxmitframe); 346 s32 rtw_hal_mgnt_xmit(struct adapter *padapter, struct xmit_frame *pmgntframe); 347 348 s32 rtw_hal_init_xmit_priv(struct adapter *padapter); 349 void rtw_hal_free_xmit_priv(struct adapter *padapter); 350 351 s32 rtw_hal_init_recv_priv(struct adapter *padapter); 352 void rtw_hal_free_recv_priv(struct adapter *padapter); 353 354 void rtw_hal_update_ra_mask(struct sta_info *psta, u8 rssi_level); 355 void rtw_hal_add_ra_tid(struct adapter *padapter, u32 bitmap, u8 *arg, u8 rssi_level); 356 357 void rtw_hal_start_thread(struct adapter *padapter); 358 void rtw_hal_stop_thread(struct adapter *padapter); 359 360 void beacon_timing_control(struct adapter *padapter); 361 362 u32 rtw_hal_read_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask); 363 void rtw_hal_write_bbreg(struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data); 364 u32 rtw_hal_read_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask); 365 void rtw_hal_write_rfreg(struct adapter *padapter, u32 eRFPath, u32 RegAddr, u32 BitMask, u32 Data); 366 367 #define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtw_hal_read_bbreg((Adapter), (RegAddr), (BitMask)) 368 #define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtw_hal_write_bbreg((Adapter), (RegAddr), (BitMask), (Data)) 369 #define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtw_hal_read_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask)) 370 #define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtw_hal_write_rfreg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data)) 371 372 #define PHY_SetMacReg PHY_SetBBReg 373 #define PHY_QueryMacReg PHY_QueryBBReg 374 375 void rtw_hal_set_chan(struct adapter *padapter, u8 channel); 376 void rtw_hal_set_chnl_bw(struct adapter *padapter, u8 channel, enum CHANNEL_WIDTH Bandwidth, u8 Offset40, u8 Offset80); 377 void rtw_hal_dm_watchdog(struct adapter *padapter); 378 void rtw_hal_dm_watchdog_in_lps(struct adapter *padapter); 379 380 s32 rtw_hal_xmit_thread_handler(struct adapter *padapter); 381 382 void rtw_hal_notch_filter(struct adapter *adapter, bool enable); 383 void rtw_hal_reset_security_engine(struct adapter *adapter); 384 385 bool rtw_hal_c2h_valid(struct adapter *adapter, u8 *buf); 386 s32 rtw_hal_c2h_handler(struct adapter *adapter, u8 *c2h_evt); 387 c2h_id_filter rtw_hal_c2h_id_filter_ccx(struct adapter *adapter); 388 389 s32 rtw_hal_is_disable_sw_channel_plan(struct adapter *padapter); 390 391 s32 rtw_hal_macid_sleep(struct adapter *padapter, u32 macid); 392 s32 rtw_hal_macid_wakeup(struct adapter *padapter, u32 macid); 393 394 s32 rtw_hal_fill_h2c_cmd(struct adapter *, u8 ElementID, u32 CmdLen, u8 *pCmdBuffer); 395 396 #endif /* __HAL_INTF_H__ */ 397