1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __HAL_DATA_H__ 8 #define __HAL_DATA_H__ 9 10 #include "odm_precomp.h" 11 #include <hal_btcoex.h> 12 13 #include <hal_sdio.h> 14 15 /* */ 16 /* <Roger_Notes> For RTL8723 WiFi/BT/GPS multi-function configuration. 2010.10.06. */ 17 /* */ 18 enum rt_multi_func { 19 RT_MULTI_FUNC_NONE = 0x00, 20 RT_MULTI_FUNC_WIFI = 0x01, 21 RT_MULTI_FUNC_BT = 0x02, 22 RT_MULTI_FUNC_GPS = 0x04, 23 }; 24 /* */ 25 /* <Roger_Notes> For RTL8723 WiFi PDn/GPIO polarity control configuration. 2010.10.08. */ 26 /* */ 27 enum rt_polarity_ctl { 28 RT_POLARITY_LOW_ACT = 0, 29 RT_POLARITY_HIGH_ACT = 1, 30 }; 31 32 /* For RTL8723 regulator mode. by tynli. 2011.01.14. */ 33 enum rt_regulator_mode { 34 RT_SWITCHING_REGULATOR = 0, 35 RT_LDO_REGULATOR = 1, 36 }; 37 38 enum rt_ampdu_burst { 39 RT_AMPDU_BURST_NONE = 0, 40 RT_AMPDU_BURST_92D = 1, 41 RT_AMPDU_BURST_88E = 2, 42 RT_AMPDU_BURST_8812_4 = 3, 43 RT_AMPDU_BURST_8812_8 = 4, 44 RT_AMPDU_BURST_8812_12 = 5, 45 RT_AMPDU_BURST_8812_15 = 6, 46 RT_AMPDU_BURST_8723B = 7, 47 }; 48 49 #define CHANNEL_MAX_NUMBER (14) /* 14 is the max channel number */ 50 #define CHANNEL_MAX_NUMBER_2G 14 51 #define MAX_PG_GROUP 13 52 53 /* Tx Power Limit Table Size */ 54 #define MAX_REGULATION_NUM 4 55 #define MAX_2_4G_BANDWIDTH_NUM 4 56 #define MAX_RATE_SECTION_NUM 10 57 58 #define MAX_BASE_NUM_IN_PHY_REG_PG_2_4G 10 /* CCK:1, OFDM:1, HT:4, VHT:4 */ 59 60 /* duplicate code, will move to ODM ######### */ 61 /* define IQK_MAC_REG_NUM 4 */ 62 /* define IQK_ADDA_REG_NUM 16 */ 63 64 /* define IQK_BB_REG_NUM 10 */ 65 66 /* define HP_THERMAL_NUM 8 */ 67 /* duplicate code, will move to ODM ######### */ 68 69 enum { 70 SINGLEMAC_SINGLEPHY, /* SMSP */ 71 DUALMAC_DUALPHY, /* DMDP */ 72 DUALMAC_SINGLEPHY, /* DMSP */ 73 }; 74 75 #define PAGE_SIZE_128 128 76 #define PAGE_SIZE_256 256 77 #define PAGE_SIZE_512 512 78 79 struct dm_priv { 80 u8 DM_Type; 81 82 #define DYNAMIC_FUNC_BT BIT0 83 84 u8 DMFlag; 85 u8 InitDMFlag; 86 /* u8 RSVD_1; */ 87 88 u32 InitODMFlag; 89 /* Upper and Lower Signal threshold for Rate Adaptive */ 90 int UndecoratedSmoothedPWDB; 91 int UndecoratedSmoothedCCK; 92 int EntryMinUndecoratedSmoothedPWDB; 93 int EntryMaxUndecoratedSmoothedPWDB; 94 int MinUndecoratedPWDBForDM; 95 int LastMinUndecoratedPWDBForDM; 96 97 s32 UndecoratedSmoothedBeacon; 98 99 /* duplicate code, will move to ODM ######### */ 100 /* for High Power */ 101 u8 bDynamicTxPowerEnable; 102 u8 LastDTPLvl; 103 u8 DynamicTxHighPowerLvl;/* Add by Jacken Tx Power Control for Near/Far Range 2008/03/06 */ 104 105 /* for tx power tracking */ 106 u8 bTXPowerTracking; 107 u8 TXPowercount; 108 u8 bTXPowerTrackingInit; 109 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 110 u8 TM_Trigger; 111 112 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 113 u8 ThermalValue; 114 u8 ThermalValue_LCK; 115 u8 ThermalValue_IQK; 116 u8 ThermalValue_DPK; 117 u8 bRfPiEnable; 118 /* u8 RSVD_2; */ 119 120 /* for APK */ 121 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 122 u8 bAPKdone; 123 u8 bAPKThermalMeterIgnore; 124 u8 bDPdone; 125 u8 bDPPathAOK; 126 u8 bDPPathBOK; 127 /* u8 RSVD_3; */ 128 /* u8 RSVD_4; */ 129 /* u8 RSVD_5; */ 130 131 /* for IQK */ 132 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 133 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 134 u32 IQK_BB_backup_recover[9]; 135 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 136 137 u8 PowerIndex_backup[6]; 138 u8 OFDM_index[2]; 139 140 u8 bCCKinCH14; 141 u8 CCK_index; 142 u8 bDoneTxpower; 143 u8 CCK_index_HP; 144 145 u8 OFDM_index_HP[2]; 146 u8 ThermalValue_HP[HP_THERMAL_NUM]; 147 u8 ThermalValue_HP_index; 148 /* u8 RSVD_6; */ 149 150 /* for TxPwrTracking2 */ 151 s32 RegE94; 152 s32 RegE9C; 153 s32 RegEB4; 154 s32 RegEBC; 155 156 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 157 158 u32 prv_traffic_idx; /* edca turbo */ 159 /* duplicate code, will move to ODM ######### */ 160 161 /* Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas */ 162 u8 INIDATA_RATE[32]; 163 }; 164 165 166 struct hal_com_data { 167 struct hal_version VersionID; 168 enum rt_multi_func MultiFunc; /* For multi-function consideration. */ 169 enum rt_polarity_ctl PolarityCtl; /* For Wifi PDn Polarity control. */ 170 enum rt_regulator_mode RegulatorMode; /* switching regulator or LDO */ 171 172 u16 FirmwareVersion; 173 u16 FirmwareVersionRev; 174 u16 FirmwareSubVersion; 175 u16 FirmwareSignature; 176 177 /* current WIFI_PHY values */ 178 enum wireless_mode CurrentWirelessMode; 179 enum channel_width CurrentChannelBW; 180 u8 CurrentChannel; 181 u8 CurrentCenterFrequencyIndex1; 182 u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */ 183 u8 nCur80MhzPrimeSC; /* used for primary 40MHz of 80MHz mode */ 184 185 u16 CustomerID; 186 u16 BasicRateSet; 187 u16 ForcedDataRate;/* Force Data Rate. 0: Auto, 0x02: 1M ~ 0x6C: 54M. */ 188 u32 ReceiveConfig; 189 190 /* rf_ctrl */ 191 u8 rf_chip; 192 u8 rf_type; 193 u8 PackageType; 194 u8 NumTotalRFPath; 195 196 u8 InterfaceSel; 197 u8 framesync; 198 u32 framesyncC34; 199 u8 framesyncMonitor; 200 u8 DefaultInitialGain[4]; 201 /* EEPROM setting. */ 202 u16 EEPROMVID; 203 u16 EEPROMSVID; 204 205 u8 EEPROMCustomerID; 206 u8 EEPROMSubCustomerID; 207 u8 EEPROMVersion; 208 u8 EEPROMRegulatory; 209 u8 EEPROMThermalMeter; 210 u8 EEPROMBluetoothCoexist; 211 u8 EEPROMBluetoothType; 212 u8 EEPROMBluetoothAntNum; 213 u8 EEPROMBluetoothAntIsolation; 214 u8 EEPROMBluetoothRadioShared; 215 u8 bTXPowerDataReadFromEEPORM; 216 u8 bAPKThermalMeterIgnore; 217 u8 bDisableSWChannelPlan; /* flag of disable software change channel plan */ 218 219 bool EepromOrEfuse; 220 u8 EfuseUsedPercentage; 221 u16 EfuseUsedBytes; 222 struct efuse_hal EfuseHal; 223 224 /* 3 [2.4G] */ 225 u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 226 u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER]; 227 /* If only one tx, only BW20 and OFDM are used. */ 228 s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 229 s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 230 s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 231 s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT]; 232 233 u8 Regulation2_4G; 234 235 u8 TxPwrInPercentage; 236 237 u8 TxPwrCalibrateRate; 238 /* TX power by rate table at most 4RF path. */ 239 /* The register is */ 240 /* VHT TX power by rate off setArray = */ 241 /* RF: at most 4*4 = ABCD = 0/1/2/3 */ 242 /* CCK = 0 OFDM = 1/2 HT-MCS 0-15 =3/4/56 VHT =7/8/9/10/11 */ 243 u8 TxPwrByRateTable; 244 u8 TxPwrByRateBand; 245 s8 TxPwrByRateOffset[TX_PWR_BY_RATE_NUM_RF] 246 [TX_PWR_BY_RATE_NUM_RF] 247 [TX_PWR_BY_RATE_NUM_RATE]; 248 /* */ 249 250 /* 2 Power Limit Table */ 251 u8 TxPwrLevelCck[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 252 u8 TxPwrLevelHT40_1S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 253 u8 TxPwrLevelHT40_2S[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; /* For HT 40MHZ pwr */ 254 s8 TxPwrHt20Diff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* HT 20<->40 Pwr diff */ 255 u8 TxPwrLegacyHtDiff[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER];/* For HT<->legacy pwr diff */ 256 257 /* Power Limit Table for 2.4G */ 258 s8 TxPwrLimit_2_4G[MAX_REGULATION_NUM] 259 [MAX_2_4G_BANDWIDTH_NUM] 260 [MAX_RATE_SECTION_NUM] 261 [CHANNEL_MAX_NUMBER_2G] 262 [MAX_RF_PATH_NUM]; 263 264 /* Store the original power by rate value of the base of each rate section of rf path A & B */ 265 u8 TxPwrByRateBase2_4G[TX_PWR_BY_RATE_NUM_RF] 266 [TX_PWR_BY_RATE_NUM_RF] 267 [MAX_BASE_NUM_IN_PHY_REG_PG_2_4G]; 268 269 /* For power group */ 270 u8 PwrGroupHT20[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 271 u8 PwrGroupHT40[RF_PATH_MAX_92C_88E][CHANNEL_MAX_NUMBER]; 272 273 274 275 276 u8 PGMaxGroup; 277 u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */ 278 /* The current Tx Power Level */ 279 u8 CurrentCckTxPwrIdx; 280 u8 CurrentOfdm24GTxPwrIdx; 281 u8 CurrentBW2024GTxPwrIdx; 282 u8 CurrentBW4024GTxPwrIdx; 283 284 /* Read/write are allow for following hardware information variables */ 285 u8 pwrGroupCnt; 286 u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16]; 287 u32 CCKTxPowerLevelOriginalOffset; 288 289 u8 CrystalCap; 290 u32 AntennaTxPath; /* Antenna path Tx */ 291 u32 AntennaRxPath; /* Antenna path Rx */ 292 293 u8 PAType_2G; 294 u8 LNAType_2G; 295 u8 ExternalPA_2G; 296 u8 ExternalLNA_2G; 297 u8 TypeGLNA; 298 u8 TypeGPA; 299 u8 TypeALNA; 300 u8 TypeAPA; 301 u8 RFEType; 302 u8 BoardType; 303 u8 ExternalPA; 304 u8 bIQKInitialized; 305 bool bLCKInProgress; 306 307 bool bSwChnl; 308 bool bSetChnlBW; 309 bool bChnlBWInitialized; 310 bool bNeedIQK; 311 312 u8 bLedOpenDrain; /* Support Open-drain arrangement for controlling the LED. Added by Roger, 2009.10.16. */ 313 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 314 u8 b1x1RecvCombine; /* for 1T1R receive combining */ 315 316 u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */ 317 318 struct bb_register_def PHYRegDef[4]; /* Radio A/B/C/D */ 319 320 u32 RfRegChnlVal[2]; 321 322 /* RDG enable */ 323 bool bRDGEnable; 324 325 /* for host message to fw */ 326 u8 LastHMEBoxNum; 327 328 u8 fw_ractrl; 329 u8 RegTxPause; 330 /* Beacon function related global variable. */ 331 u8 RegBcnCtrlVal; 332 u8 RegFwHwTxQCtrl; 333 u8 RegReg542; 334 u8 RegCR_1; 335 u8 Reg837; 336 u8 RegRFPathS1; 337 u16 RegRRSR; 338 339 u8 CurAntenna; 340 u8 AntDivCfg; 341 u8 AntDetection; 342 u8 TRxAntDivType; 343 u8 ant_path; /* for 8723B s0/s1 selection */ 344 345 u8 u1ForcedIgiLb; /* forced IGI lower bound */ 346 347 u8 bDumpRxPkt;/* for debug */ 348 u8 bDumpTxPkt;/* for debug */ 349 u8 FwRsvdPageStartOffset; /* 2010.06.23. Added by tynli. Reserve page start offset except beacon in TxQ. */ 350 351 /* 2010/08/09 MH Add CU power down mode. */ 352 bool pwrdown; 353 354 /* Add for dual MAC 0--Mac0 1--Mac1 */ 355 u32 interfaceIndex; 356 357 u8 OutEpQueueSel; 358 u8 OutEpNumber; 359 360 /* 2010/12/10 MH Add for USB aggregation mode dynamic scheme. */ 361 bool UsbRxHighSpeedMode; 362 363 /* 2010/11/22 MH Add for slim combo debug mode selective. */ 364 /* This is used for fix the drawback of CU TSMC-A/UMC-A cut. HW auto suspend ability. Close BT clock. */ 365 bool SlimComboDbg; 366 367 /* u8 AMPDUDensity; */ 368 369 /* Auto FSM to Turn On, include clock, isolation, power control for MAC only */ 370 u8 bMacPwrCtrlOn; 371 372 u8 RegIQKFWOffload; 373 struct submit_ctx iqk_sctx; 374 375 enum rt_ampdu_burst AMPDUBurstMode; /* 92C maybe not use, but for compile successfully */ 376 377 u32 sdio_himr; 378 u32 sdio_hisr; 379 380 /* SDIO Tx FIFO related. */ 381 /* HIQ, MID, LOW, PUB free pages; padapter->xmitpriv.free_txpg */ 382 u8 SdioTxFIFOFreePage[SDIO_TX_FREE_PG_QUEUE]; 383 spinlock_t SdioTxFIFOFreePageLock; 384 u8 SdioTxOQTMaxFreeSpace; 385 u8 SdioTxOQTFreeSpace; 386 387 388 /* SDIO Rx FIFO related. */ 389 u8 SdioRxFIFOCnt; 390 u16 SdioRxFIFOSize; 391 392 u32 sdio_tx_max_len[SDIO_MAX_TX_QUEUE];/* H, N, L, used for sdio tx aggregation max length per queue */ 393 394 struct dm_priv dmpriv; 395 struct dm_odm_t odmpriv; 396 397 /* For bluetooth co-existance */ 398 struct bt_coexist bt_coexist; 399 400 /* Interrupt related register information. */ 401 u32 SysIntrStatus; 402 u32 SysIntrMask; 403 }; 404 405 #define GET_HAL_DATA(__padapter) ((struct hal_com_data *)((__padapter)->HalData)) 406 #define GET_HAL_RFPATH_NUM(__padapter) (((struct hal_com_data *)((__padapter)->HalData))->NumTotalRFPath) 407 #define RT_GetInterfaceSelection(_Adapter) (GET_HAL_DATA(_Adapter)->InterfaceSel) 408 #define GET_RF_TYPE(__padapter) (GET_HAL_DATA(__padapter)->rf_type) 409 410 #endif /* __HAL_DATA_H__ */ 411