1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 #ifndef __HAL_COMMON_REG_H__ 16 #define __HAL_COMMON_REG_H__ 17 18 19 #define MAC_ADDR_LEN 6 20 21 #define HAL_NAV_UPPER_UNIT 128 /* micro-second */ 22 23 /* 8188E PKT_BUFF_ACCESS_CTRL value */ 24 #define TXPKT_BUF_SELECT 0x69 25 #define RXPKT_BUF_SELECT 0xA5 26 #define DISABLE_TRXPKT_BUF_ACCESS 0x0 27 28 /* */ 29 /* */ 30 /* */ 31 32 /* */ 33 /* */ 34 /* 0x0000h ~ 0x00FFh System Configuration */ 35 /* */ 36 /* */ 37 #define REG_SYS_ISO_CTRL 0x0000 38 #define REG_SYS_FUNC_EN 0x0002 39 #define REG_APS_FSMCO 0x0004 40 #define REG_SYS_CLKR 0x0008 41 #define REG_9346CR 0x000A 42 #define REG_SYS_EEPROM_CTRL 0x000A 43 #define REG_EE_VPD 0x000C 44 #define REG_AFE_MISC 0x0010 45 #define REG_SPS0_CTRL 0x0011 46 #define REG_SPS0_CTRL_6 0x0016 47 #define REG_POWER_OFF_IN_PROCESS 0x0017 48 #define REG_SPS_OCP_CFG 0x0018 49 #define REG_RSV_CTRL 0x001C 50 #define REG_RF_CTRL 0x001F 51 #define REG_LDOA15_CTRL 0x0020 52 #define REG_LDOV12D_CTRL 0x0021 53 #define REG_LDOHCI12_CTRL 0x0022 54 #define REG_LPLDO_CTRL 0x0023 55 #define REG_AFE_XTAL_CTRL 0x0024 56 #define REG_AFE_LDO_CTRL 0x0027 /* 1.5v for 8188EE test chip, 1.4v for MP chip */ 57 #define REG_AFE_PLL_CTRL 0x0028 58 #define REG_MAC_PHY_CTRL 0x002c /* for 92d, DMDP, SMSP, DMSP contrl */ 59 #define REG_APE_PLL_CTRL_EXT 0x002c 60 #define REG_EFUSE_CTRL 0x0030 61 #define REG_EFUSE_TEST 0x0034 62 #define REG_PWR_DATA 0x0038 63 #define REG_CAL_TIMER 0x003C 64 #define REG_ACLK_MON 0x003E 65 #define REG_GPIO_MUXCFG 0x0040 66 #define REG_GPIO_IO_SEL 0x0042 67 #define REG_MAC_PINMUX_CFG 0x0043 68 #define REG_GPIO_PIN_CTRL 0x0044 69 #define REG_GPIO_INTM 0x0048 70 #define REG_LEDCFG0 0x004C 71 #define REG_LEDCFG1 0x004D 72 #define REG_LEDCFG2 0x004E 73 #define REG_LEDCFG3 0x004F 74 #define REG_FSIMR 0x0050 75 #define REG_FSISR 0x0054 76 #define REG_HSIMR 0x0058 77 #define REG_HSISR 0x005c 78 #define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 79 #define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 80 #define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 81 #define REG_GSSR 0x006c 82 #define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */ 83 #define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */ 84 #define REG_MCUFWDL 0x0080 85 #define REG_WOL_EVENT 0x0081 /* RTL8188E */ 86 #define REG_MCUTSTCFG 0x0084 87 #define REG_FDHM0 0x0088 88 #define REG_HOST_SUSP_CNT 0x00BC /* RTL8192C Host suspend counter on FPGA platform */ 89 #define REG_SYSTEM_ON_CTRL 0x00CC /* For 8723AE Reset after S3 */ 90 #define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection for RTL8723 */ 91 #define REG_BIST_SCAN 0x00D0 92 #define REG_BIST_RPT 0x00D4 93 #define REG_BIST_ROM_RPT 0x00D8 94 #define REG_USB_SIE_INTF 0x00E0 95 #define REG_PCIE_MIO_INTF 0x00E4 96 #define REG_PCIE_MIO_INTD 0x00E8 97 #define REG_HPON_FSM 0x00EC 98 #define REG_SYS_CFG 0x00F0 99 #define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */ 100 #define REG_TYPE_ID 0x00FC 101 102 /* */ 103 /* 2010/12/29 MH Add for 92D */ 104 /* */ 105 #define REG_MAC_PHY_CTRL_NORMAL 0x00f8 106 107 108 /* */ 109 /* */ 110 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 111 /* */ 112 /* */ 113 #define REG_CR 0x0100 114 #define REG_PBP 0x0104 115 #define REG_PKT_BUFF_ACCESS_CTRL 0x0106 116 #define REG_TRXDMA_CTRL 0x010C 117 #define REG_TRXFF_BNDY 0x0114 118 #define REG_TRXFF_STATUS 0x0118 119 #define REG_RXFF_PTR 0x011C 120 #define REG_HIMR 0x0120 121 #define REG_HISR 0x0124 122 #define REG_HIMRE 0x0128 123 #define REG_HISRE 0x012C 124 #define REG_CPWM 0x012F 125 #define REG_FWIMR 0x0130 126 #define REG_FWISR 0x0134 127 #define REG_FTIMR 0x0138 128 #define REG_FTISR 0x013C /* RTL8192C */ 129 #define REG_PKTBUF_DBG_CTRL 0x0140 130 #define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL+2) 131 #define REG_PKTBUF_DBG_DATA_L 0x0144 132 #define REG_PKTBUF_DBG_DATA_H 0x0148 133 134 #define REG_TC0_CTRL 0x0150 135 #define REG_TC1_CTRL 0x0154 136 #define REG_TC2_CTRL 0x0158 137 #define REG_TC3_CTRL 0x015C 138 #define REG_TC4_CTRL 0x0160 139 #define REG_TCUNIT_BASE 0x0164 140 #define REG_MBIST_START 0x0174 141 #define REG_MBIST_DONE 0x0178 142 #define REG_MBIST_FAIL 0x017C 143 #define REG_32K_CTRL 0x0194 /* RTL8188E */ 144 #define REG_C2HEVT_MSG_NORMAL 0x01A0 145 #define REG_C2HEVT_CLEAR 0x01AF 146 #define REG_MCUTST_1 0x01c0 147 #define REG_MCUTST_WOWLAN 0x01C7 /* Defined after 8188E series. */ 148 #define REG_FMETHR 0x01C8 149 #define REG_HMETFR 0x01CC 150 #define REG_HMEBOX_0 0x01D0 151 #define REG_HMEBOX_1 0x01D4 152 #define REG_HMEBOX_2 0x01D8 153 #define REG_HMEBOX_3 0x01DC 154 #define REG_LLT_INIT 0x01E0 155 156 157 /* */ 158 /* */ 159 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 160 /* */ 161 /* */ 162 #define REG_RQPN 0x0200 163 #define REG_FIFOPAGE 0x0204 164 #define REG_TDECTRL 0x0208 165 #define REG_TXDMA_OFFSET_CHK 0x020C 166 #define REG_TXDMA_STATUS 0x0210 167 #define REG_RQPN_NPQ 0x0214 168 #define REG_AUTO_LLT 0x0224 169 170 171 /* */ 172 /* */ 173 /* 0x0280h ~ 0x02FFh RXDMA Configuration */ 174 /* */ 175 /* */ 176 #define REG_RXDMA_AGG_PG_TH 0x0280 177 #define REG_RXPKT_NUM 0x0284 178 #define REG_RXDMA_STATUS 0x0288 179 180 /* */ 181 /* */ 182 /* 0x0300h ~ 0x03FFh PCIe */ 183 /* */ 184 /* */ 185 #define REG_PCIE_CTRL_REG 0x0300 186 #define REG_INT_MIG 0x0304 /* Interrupt Migration */ 187 #define REG_BCNQ_DESA 0x0308 /* TX Beacon Descriptor Address */ 188 #define REG_HQ_DESA 0x0310 /* TX High Queue Descriptor Address */ 189 #define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descriptor Address */ 190 #define REG_VOQ_DESA 0x0320 /* TX VO Queue Descriptor Address */ 191 #define REG_VIQ_DESA 0x0328 /* TX VI Queue Descriptor Address */ 192 #define REG_BEQ_DESA 0x0330 /* TX BE Queue Descriptor Address */ 193 #define REG_BKQ_DESA 0x0338 /* TX BK Queue Descriptor Address */ 194 #define REG_RX_DESA 0x0340 /* RX Queue Descriptor Address */ 195 /* sherry added for DBI Read/Write 20091126 */ 196 #define REG_DBI_WDATA 0x0348 /* Backdoor REG for Access Configuration */ 197 #define REG_DBI_RDATA 0x034C /* Backdoor REG for Access Configuration */ 198 #define REG_DBI_CTRL 0x0350 /* Backdoor REG for Access Configuration */ 199 #define REG_DBI_FLAG 0x0352 /* Backdoor REG for Access Configuration */ 200 #define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */ 201 #define REG_DBG_SEL 0x0360 /* Debug Selection Register */ 202 #define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */ 203 #define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */ 204 #define REG_WATCH_DOG 0x0368 205 206 /* RTL8723 series ------------------------------- */ 207 #define REG_PCIE_HISR_EN 0x0394 /* PCIE Local Interrupt Enable Register */ 208 #define REG_PCIE_HISR 0x03A0 209 #define REG_PCIE_HISRE 0x03A4 210 #define REG_PCIE_HIMR 0x03A8 211 #define REG_PCIE_HIMRE 0x03AC 212 213 #define REG_USB_HIMR 0xFE38 214 #define REG_USB_HIMRE 0xFE3C 215 #define REG_USB_HISR 0xFE78 216 #define REG_USB_HISRE 0xFE7C 217 218 219 /* */ 220 /* */ 221 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 222 /* */ 223 /* */ 224 #define REG_VOQ_INFORMATION 0x0400 225 #define REG_VIQ_INFORMATION 0x0404 226 #define REG_BEQ_INFORMATION 0x0408 227 #define REG_BKQ_INFORMATION 0x040C 228 #define REG_MGQ_INFORMATION 0x0410 229 #define REG_HGQ_INFORMATION 0x0414 230 #define REG_BCNQ_INFORMATION 0x0418 231 #define REG_TXPKT_EMPTY 0x041A 232 #define REG_CPU_MGQ_INFORMATION 0x041C 233 #define REG_FWHW_TXQ_CTRL 0x0420 234 #define REG_HWSEQ_CTRL 0x0423 235 #define REG_BCNQ_BDNY 0x0424 236 #define REG_MGQ_BDNY 0x0425 237 #define REG_LIFETIME_CTRL 0x0426 238 #define REG_MULTI_BCNQ_OFFSET 0x0427 239 #define REG_SPEC_SIFS 0x0428 240 #define REG_RL 0x042A 241 #define REG_DARFRC 0x0430 242 #define REG_RARFRC 0x0438 243 #define REG_RRSR 0x0440 244 #define REG_ARFR0 0x0444 245 #define REG_ARFR1 0x0448 246 #define REG_ARFR2 0x044C 247 #define REG_ARFR3 0x0450 248 #define REG_BCNQ1_BDNY 0x0457 249 250 #define REG_AGGLEN_LMT 0x0458 251 #define REG_AMPDU_MIN_SPACE 0x045C 252 #define REG_WMAC_LBK_BF_HD 0x045D 253 #define REG_FAST_EDCA_CTRL 0x0460 254 #define REG_RD_RESP_PKT_TH 0x0463 255 256 #define REG_INIRTS_RATE_SEL 0x0480 257 #define REG_INIDATA_RATE_SEL 0x0484 258 259 #define REG_POWER_STAGE1 0x04B4 260 #define REG_POWER_STAGE2 0x04B8 261 #define REG_PKT_VO_VI_LIFE_TIME 0x04C0 262 #define REG_PKT_BE_BK_LIFE_TIME 0x04C2 263 #define REG_STBC_SETTING 0x04C4 264 #define REG_QUEUE_CTRL 0x04C6 265 #define REG_SINGLE_AMPDU_CTRL 0x04c7 266 #define REG_PROT_MODE_CTRL 0x04C8 267 #define REG_MAX_AGGR_NUM 0x04CA 268 #define REG_RTS_MAX_AGGR_NUM 0x04CB 269 #define REG_BAR_MODE_CTRL 0x04CC 270 #define REG_RA_TRY_RATE_AGG_LMT 0x04CF 271 #define REG_EARLY_MODE_CONTROL 0x04D0 272 #define REG_MACID_SLEEP 0x04D4 273 #define REG_NQOS_SEQ 0x04DC 274 #define REG_QOS_SEQ 0x04DE 275 #define REG_NEED_CPU_HANDLE 0x04E0 276 #define REG_PKT_LOSE_RPT 0x04E1 277 #define REG_PTCL_ERR_STATUS 0x04E2 278 #define REG_TX_RPT_CTRL 0x04EC 279 #define REG_TX_RPT_TIME 0x04F0 /* 2 byte */ 280 #define REG_DUMMY 0x04FC 281 282 /* */ 283 /* */ 284 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 285 /* */ 286 /* */ 287 #define REG_EDCA_VO_PARAM 0x0500 288 #define REG_EDCA_VI_PARAM 0x0504 289 #define REG_EDCA_BE_PARAM 0x0508 290 #define REG_EDCA_BK_PARAM 0x050C 291 #define REG_BCNTCFG 0x0510 292 #define REG_PIFS 0x0512 293 #define REG_RDG_PIFS 0x0513 294 #define REG_SIFS_CTX 0x0514 295 #define REG_SIFS_TRX 0x0516 296 #define REG_TSFTR_SYN_OFFSET 0x0518 297 #define REG_AGGR_BREAK_TIME 0x051A 298 #define REG_SLOT 0x051B 299 #define REG_TX_PTCL_CTRL 0x0520 300 #define REG_TXPAUSE 0x0522 301 #define REG_DIS_TXREQ_CLR 0x0523 302 #define REG_RD_CTRL 0x0524 303 /* */ 304 /* Format for offset 540h-542h: */ 305 /* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting beacon content before TBTT. */ 306 /* [7:4]: Reserved. */ 307 /* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding to send the beacon packet. */ 308 /* [23:20]: Reserved */ 309 /* Description: */ 310 /* | */ 311 /* |<--Setup--|--Hold------------>| */ 312 /* --------------|---------------------- */ 313 /* | */ 314 /* TBTT */ 315 /* Note: We cannot update beacon content to HW or send any AC packets during the time between Setup and Hold. */ 316 /* Described by Designer Tim and Bruce, 2011-01-14. */ 317 /* */ 318 #define REG_TBTT_PROHIBIT 0x0540 319 #define REG_RD_NAV_NXT 0x0544 320 #define REG_NAV_PROT_LEN 0x0546 321 #define REG_BCN_CTRL 0x0550 322 #define REG_BCN_CTRL_1 0x0551 323 #define REG_MBID_NUM 0x0552 324 #define REG_DUAL_TSF_RST 0x0553 325 #define REG_BCN_INTERVAL 0x0554 /* The same as REG_MBSSID_BCN_SPACE */ 326 #define REG_DRVERLYINT 0x0558 327 #define REG_BCNDMATIM 0x0559 328 #define REG_ATIMWND 0x055A 329 #define REG_USTIME_TSF 0x055C 330 #define REG_BCN_MAX_ERR 0x055D 331 #define REG_RXTSF_OFFSET_CCK 0x055E 332 #define REG_RXTSF_OFFSET_OFDM 0x055F 333 #define REG_TSFTR 0x0560 334 #define REG_TSFTR1 0x0568 /* HW Port 1 TSF Register */ 335 #define REG_ATIMWND_1 0x0570 336 #define REG_P2P_CTWIN 0x0572 /* 1 Byte long (in unit of TU) */ 337 #define REG_PSTIMER 0x0580 338 #define REG_TIMER0 0x0584 339 #define REG_TIMER1 0x0588 340 #define REG_ACMHWCTRL 0x05C0 341 #define REG_NOA_DESC_SEL 0x05CF 342 #define REG_NOA_DESC_DURATION 0x05E0 343 #define REG_NOA_DESC_INTERVAL 0x05E4 344 #define REG_NOA_DESC_START 0x05E8 345 #define REG_NOA_DESC_COUNT 0x05EC 346 347 #define REG_DMC 0x05F0 /* Dual MAC Co-Existence Register */ 348 #define REG_SCH_TX_CMD 0x05F8 349 350 #define REG_FW_RESET_TSF_CNT_1 0x05FC 351 #define REG_FW_RESET_TSF_CNT_0 0x05FD 352 #define REG_FW_BCN_DIS_CNT 0x05FE 353 354 /* */ 355 /* */ 356 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 357 /* */ 358 /* */ 359 #define REG_APSD_CTRL 0x0600 360 #define REG_BWOPMODE 0x0603 361 #define REG_TCR 0x0604 362 #define REG_RCR 0x0608 363 #define REG_RX_PKT_LIMIT 0x060C 364 #define REG_RX_DLK_TIME 0x060D 365 #define REG_RX_DRVINFO_SZ 0x060F 366 367 #define REG_MACID 0x0610 368 #define REG_BSSID 0x0618 369 #define REG_MAR 0x0620 370 #define REG_MBIDCAMCFG 0x0628 371 372 #define REG_PNO_STATUS 0x0631 373 #define REG_USTIME_EDCA 0x0638 374 #define REG_MAC_SPEC_SIFS 0x063A 375 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */ 376 #define REG_RESP_SIFS_CCK 0x063C /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 377 #define REG_RESP_SIFS_OFDM 0x063E /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 378 379 #define REG_ACKTO 0x0640 380 #define REG_CTS2TO 0x0641 381 #define REG_EIFS 0x0642 382 383 384 /* RXERR_RPT */ 385 #define RXERR_TYPE_OFDM_PPDU 0 386 #define RXERR_TYPE_OFDMfalse_ALARM 1 387 #define RXERR_TYPE_OFDM_MPDU_OK 2 388 #define RXERR_TYPE_OFDM_MPDU_FAIL 3 389 #define RXERR_TYPE_CCK_PPDU 4 390 #define RXERR_TYPE_CCKfalse_ALARM 5 391 #define RXERR_TYPE_CCK_MPDU_OK 6 392 #define RXERR_TYPE_CCK_MPDU_FAIL 7 393 #define RXERR_TYPE_HT_PPDU 8 394 #define RXERR_TYPE_HTfalse_ALARM 9 395 #define RXERR_TYPE_HT_MPDU_TOTAL 10 396 #define RXERR_TYPE_HT_MPDU_OK 11 397 #define RXERR_TYPE_HT_MPDU_FAIL 12 398 #define RXERR_TYPE_RX_FULL_DROP 15 399 400 #define RXERR_COUNTER_MASK 0xFFFFF 401 #define RXERR_RPT_RST BIT(27) 402 #define _RXERR_RPT_SEL(type) ((type) << 28) 403 404 /* */ 405 /* Note: */ 406 /* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is */ 407 /* always too small, but the WiFi TestPlan test by 25, 000 microseconds of NAV through sending */ 408 /* CTS in the air. We must update this value greater than 25, 000 microseconds to pass the item. */ 409 /* The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented */ 410 /* by SD1 Scott. */ 411 /* By Bruce, 2011-07-18. */ 412 /* */ 413 #define REG_NAV_UPPER 0x0652 /* unit of 128 */ 414 415 /* WMA, BA, CCX */ 416 #define REG_NAV_CTRL 0x0650 417 #define REG_BACAMCMD 0x0654 418 #define REG_BACAMCONTENT 0x0658 419 #define REG_LBDLY 0x0660 420 #define REG_FWDLY 0x0661 421 #define REG_RXERR_RPT 0x0664 422 #define REG_WMAC_TRXPTCL_CTL 0x0668 423 424 /* Security */ 425 #define REG_CAMCMD 0x0670 426 #define REG_CAMWRITE 0x0674 427 #define REG_CAMREAD 0x0678 428 #define REG_CAMDBG 0x067C 429 #define REG_SECCFG 0x0680 430 431 /* Power */ 432 #define REG_WOW_CTRL 0x0690 433 #define REG_PS_RX_INFO 0x0692 434 #define REG_UAPSD_TID 0x0693 435 #define REG_WKFMCAM_CMD 0x0698 436 #define REG_WKFMCAM_NUM REG_WKFMCAM_CMD 437 #define REG_WKFMCAM_RWD 0x069C 438 #define REG_RXFLTMAP0 0x06A0 439 #define REG_RXFLTMAP1 0x06A2 440 #define REG_RXFLTMAP2 0x06A4 441 #define REG_BCN_PSR_RPT 0x06A8 442 #define REG_BT_COEX_TABLE 0x06C0 443 444 /* Hardware Port 2 */ 445 #define REG_MACID1 0x0700 446 #define REG_BSSID1 0x0708 447 448 449 /* */ 450 /* */ 451 /* 0xFE00h ~ 0xFE55h USB Configuration */ 452 /* */ 453 /* */ 454 #define REG_USB_INFO 0xFE17 455 #define REG_USB_SPECIAL_OPTION 0xFE55 456 #define REG_USB_DMA_AGG_TO 0xFE5B 457 #define REG_USB_AGG_TO 0xFE5C 458 #define REG_USB_AGG_TH 0xFE5D 459 460 #define REG_USB_HRPWM 0xFE58 461 #define REG_USB_HCPWM 0xFE57 462 463 /* for 92DU high_Queue low_Queue Normal_Queue select */ 464 #define REG_USB_High_NORMAL_Queue_Select_MAC0 0xFE44 465 /* define REG_USB_LOW_Queue_Select_MAC0 0xFE45 */ 466 #define REG_USB_High_NORMAL_Queue_Select_MAC1 0xFE47 467 /* define REG_USB_LOW_Queue_Select_MAC1 0xFE48 */ 468 469 /* For test chip */ 470 #define REG_TEST_USB_TXQS 0xFE48 471 #define REG_TEST_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 472 #define REG_TEST_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 473 #define REG_TEST_SIE_OPTIONAL 0xFE64 474 #define REG_TEST_SIE_CHIRP_K 0xFE65 475 #define REG_TEST_SIE_PHY 0xFE66 /* 0xFE66~0xFE6B */ 476 #define REG_TEST_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 477 #define REG_TEST_SIE_STRING 0xFE80 /* 0xFE80~0xFEB9 */ 478 479 480 /* For normal chip */ 481 #define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */ 482 #define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */ 483 #define REG_NORMAL_SIE_OPTIONAL 0xFE64 484 #define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */ 485 #define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */ 486 #define REG_NORMAL_SIE_OPTIONAL2 0xFE6C 487 #define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */ 488 #define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */ 489 #define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */ 490 491 492 /* */ 493 /* */ 494 /* Redifine 8192C register definition for compatibility */ 495 /* */ 496 /* */ 497 498 /* TODO: use these definition when using REG_xxx naming rule. */ 499 /* NOTE: DO NOT Remove these definition. Use later. */ 500 501 #define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */ 502 #define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */ 503 #define MSR (REG_CR + 2) /* Media Status register */ 504 /* define ISR REG_HISR */ 505 506 #define TSFR REG_TSFTR /* Timing Sync Function Timer Register. */ 507 #define TSFR1 REG_TSFTR1 /* HW Port 1 TSF Register */ 508 509 #define PBP REG_PBP 510 511 /* Redifine MACID register, to compatible prior ICs. */ 512 #define IDR0 REG_MACID /* MAC ID Register, Offset 0x0050-0x0053 */ 513 #define IDR4 (REG_MACID + 4) /* MAC ID Register, Offset 0x0054-0x0055 */ 514 515 516 /* */ 517 /* 9. Security Control Registers (Offset:) */ 518 /* */ 519 #define RWCAM REG_CAMCMD /* IN 8190 Data Sheet is called CAMcmd */ 520 #define WCAMI REG_CAMWRITE /* Software write CAM input content */ 521 #define RCAMO REG_CAMREAD /* Software read/write CAM config */ 522 #define CAMDBG REG_CAMDBG 523 #define SECR REG_SECCFG /* Security Configuration Register */ 524 525 /* Unused register */ 526 #define UnusedRegister 0x1BF 527 #define DCAM UnusedRegister 528 #define PSR UnusedRegister 529 #define BBAddr UnusedRegister 530 #define PhyDataR UnusedRegister 531 532 /* Min Spacing related settings. */ 533 #define MAX_MSS_DENSITY_2T 0x13 534 #define MAX_MSS_DENSITY_1T 0x0A 535 536 /* */ 537 /* 8192C Cmd9346CR bits (Offset 0xA, 16bit) */ 538 /* */ 539 #define CmdEEPROM_En BIT5 /* EEPROM enable when set 1 */ 540 #define CmdEERPOMSEL BIT4 /* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */ 541 #define Cmd9346CR_9356SEL BIT4 542 543 /* */ 544 /* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */ 545 /* */ 546 #define GPIOSEL_GPIO 0 547 #define GPIOSEL_ENBT BIT5 548 549 /* */ 550 /* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */ 551 /* */ 552 #define GPIO_IN REG_GPIO_PIN_CTRL /* GPIO pins input value */ 553 #define GPIO_OUT (REG_GPIO_PIN_CTRL+1) /* GPIO pins output value */ 554 #define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ 555 #define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 556 557 /* */ 558 /* 8811A GPIO PIN Control Register (offset 0x60, 4 byte) */ 559 /* */ 560 #define GPIO_IN_8811A REG_GPIO_PIN_CTRL_2 /* GPIO pins input value */ 561 #define GPIO_OUT_8811A (REG_GPIO_PIN_CTRL_2+1) /* GPIO pins output value */ 562 #define GPIO_IO_SEL_8811A (REG_GPIO_PIN_CTRL_2+2) /* GPIO pins output enable when a bit is set to "1"; otherwise, input is configured. */ 563 #define GPIO_MOD_8811A (REG_GPIO_PIN_CTRL_2+3) 564 565 /* */ 566 /* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */ 567 /* */ 568 #define HSIMR_GPIO12_0_INT_EN BIT0 569 #define HSIMR_SPS_OCP_INT_EN BIT5 570 #define HSIMR_RON_INT_EN BIT6 571 #define HSIMR_PDN_INT_EN BIT7 572 #define HSIMR_GPIO9_INT_EN BIT25 573 574 /* */ 575 /* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */ 576 /* */ 577 #define HSISR_GPIO12_0_INT BIT0 578 #define HSISR_SPS_OCP_INT BIT5 579 #define HSISR_RON_INT BIT6 580 #define HSISR_PDNINT BIT7 581 #define HSISR_GPIO9_INT BIT25 582 583 /* */ 584 /* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */ 585 /* */ 586 /* 587 Network Type 588 00: No link 589 01: Link in ad hoc network 590 10: Link in infrastructure network 591 11: AP mode 592 Default: 00b. 593 */ 594 #define MSR_NOLINK 0x00 595 #define MSR_ADHOC 0x01 596 #define MSR_INFRA 0x02 597 #define MSR_AP 0x03 598 599 /* */ 600 /* USB INTR CONTENT */ 601 /* */ 602 #define USB_C2H_CMDID_OFFSET 0 603 #define USB_C2H_SEQ_OFFSET 1 604 #define USB_C2H_EVENT_OFFSET 2 605 #define USB_INTR_CPWM_OFFSET 16 606 #define USB_INTR_CONTENT_C2H_OFFSET 0 607 #define USB_INTR_CONTENT_CPWM1_OFFSET 16 608 #define USB_INTR_CONTENT_CPWM2_OFFSET 20 609 #define USB_INTR_CONTENT_HISR_OFFSET 48 610 #define USB_INTR_CONTENT_HISRE_OFFSET 52 611 #define USB_INTR_CONTENT_LENGTH 56 612 613 /* */ 614 /* Response Rate Set Register (offset 0x440, 24bits) */ 615 /* */ 616 #define RRSR_1M BIT0 617 #define RRSR_2M BIT1 618 #define RRSR_5_5M BIT2 619 #define RRSR_11M BIT3 620 #define RRSR_6M BIT4 621 #define RRSR_9M BIT5 622 #define RRSR_12M BIT6 623 #define RRSR_18M BIT7 624 #define RRSR_24M BIT8 625 #define RRSR_36M BIT9 626 #define RRSR_48M BIT10 627 #define RRSR_54M BIT11 628 #define RRSR_MCS0 BIT12 629 #define RRSR_MCS1 BIT13 630 #define RRSR_MCS2 BIT14 631 #define RRSR_MCS3 BIT15 632 #define RRSR_MCS4 BIT16 633 #define RRSR_MCS5 BIT17 634 #define RRSR_MCS6 BIT18 635 #define RRSR_MCS7 BIT19 636 637 #define RRSR_CCK_RATES (RRSR_11M|RRSR_5_5M|RRSR_2M|RRSR_1M) 638 #define RRSR_OFDM_RATES (RRSR_54M|RRSR_48M|RRSR_36M|RRSR_24M|RRSR_18M|RRSR_12M|RRSR_9M|RRSR_6M) 639 640 /* WOL bit information */ 641 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0 642 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 643 #define HAL92C_WOL_DISASSOC_EVENT BIT2 644 #define HAL92C_WOL_DEAUTH_EVENT BIT3 645 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4 646 647 /* */ 648 /* Rate Definition */ 649 /* */ 650 /* CCK */ 651 #define RATR_1M 0x00000001 652 #define RATR_2M 0x00000002 653 #define RATR_55M 0x00000004 654 #define RATR_11M 0x00000008 655 /* OFDM */ 656 #define RATR_6M 0x00000010 657 #define RATR_9M 0x00000020 658 #define RATR_12M 0x00000040 659 #define RATR_18M 0x00000080 660 #define RATR_24M 0x00000100 661 #define RATR_36M 0x00000200 662 #define RATR_48M 0x00000400 663 #define RATR_54M 0x00000800 664 /* MCS 1 Spatial Stream */ 665 #define RATR_MCS0 0x00001000 666 #define RATR_MCS1 0x00002000 667 #define RATR_MCS2 0x00004000 668 #define RATR_MCS3 0x00008000 669 #define RATR_MCS4 0x00010000 670 #define RATR_MCS5 0x00020000 671 #define RATR_MCS6 0x00040000 672 #define RATR_MCS7 0x00080000 673 /* MCS 2 Spatial Stream */ 674 #define RATR_MCS8 0x00100000 675 #define RATR_MCS9 0x00200000 676 #define RATR_MCS10 0x00400000 677 #define RATR_MCS11 0x00800000 678 #define RATR_MCS12 0x01000000 679 #define RATR_MCS13 0x02000000 680 #define RATR_MCS14 0x04000000 681 #define RATR_MCS15 0x08000000 682 683 /* CCK */ 684 #define RATE_1M BIT(0) 685 #define RATE_2M BIT(1) 686 #define RATE_5_5M BIT(2) 687 #define RATE_11M BIT(3) 688 /* OFDM */ 689 #define RATE_6M BIT(4) 690 #define RATE_9M BIT(5) 691 #define RATE_12M BIT(6) 692 #define RATE_18M BIT(7) 693 #define RATE_24M BIT(8) 694 #define RATE_36M BIT(9) 695 #define RATE_48M BIT(10) 696 #define RATE_54M BIT(11) 697 /* MCS 1 Spatial Stream */ 698 #define RATE_MCS0 BIT(12) 699 #define RATE_MCS1 BIT(13) 700 #define RATE_MCS2 BIT(14) 701 #define RATE_MCS3 BIT(15) 702 #define RATE_MCS4 BIT(16) 703 #define RATE_MCS5 BIT(17) 704 #define RATE_MCS6 BIT(18) 705 #define RATE_MCS7 BIT(19) 706 /* MCS 2 Spatial Stream */ 707 #define RATE_MCS8 BIT(20) 708 #define RATE_MCS9 BIT(21) 709 #define RATE_MCS10 BIT(22) 710 #define RATE_MCS11 BIT(23) 711 #define RATE_MCS12 BIT(24) 712 #define RATE_MCS13 BIT(25) 713 #define RATE_MCS14 BIT(26) 714 #define RATE_MCS15 BIT(27) 715 716 717 /* ALL CCK Rate */ 718 #define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M 719 #define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|\ 720 RATR_36M|RATR_48M|RATR_54M 721 #define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 |\ 722 RATR_MCS4|RATR_MCS5|RATR_MCS6 |RATR_MCS7 723 #define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11|\ 724 RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15 725 726 #define RATE_BITMAP_ALL 0xFFFFF 727 728 /* Only use CCK 1M rate for ACK */ 729 #define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 730 #define RATE_RRSR_WITHOUT_CCK 0xFFFF0 731 732 /* */ 733 /* BW_OPMODE bits (Offset 0x603, 8bit) */ 734 /* */ 735 #define BW_OPMODE_20MHZ BIT2 736 #define BW_OPMODE_5G BIT1 737 738 /* */ 739 /* CAM Config Setting (offset 0x680, 1 byte) */ 740 /* */ 741 #define CAM_VALID BIT15 742 #define CAM_NOTVALID 0x0000 743 #define CAM_USEDK BIT5 744 745 #define CAM_CONTENT_COUNT 8 746 747 #define CAM_NONE 0x0 748 #define CAM_WEP40 0x01 749 #define CAM_TKIP 0x02 750 #define CAM_AES 0x04 751 #define CAM_WEP104 0x05 752 #define CAM_SMS4 0x6 753 754 #define TOTAL_CAM_ENTRY 32 755 #define HALF_CAM_ENTRY 16 756 757 #define CAM_CONFIG_USEDK true 758 #define CAM_CONFIG_NO_USEDK false 759 760 #define CAM_WRITE BIT16 761 #define CAM_READ 0x00000000 762 #define CAM_POLLINIG BIT31 763 764 /* */ 765 /* 10. Power Save Control Registers */ 766 /* */ 767 #define WOW_PMEN BIT0 /* Power management Enable. */ 768 #define WOW_WOMEN BIT1 /* WoW function on or off. */ 769 #define WOW_MAGIC BIT2 /* Magic packet */ 770 #define WOW_UWF BIT3 /* Unicast Wakeup frame. */ 771 772 /* */ 773 /* 12. Host Interrupt Status Registers */ 774 /* */ 775 /* */ 776 /* 8190 IMR/ISR bits */ 777 /* */ 778 #define IMR8190_DISABLED 0x0 779 #define IMR_DISABLED 0x0 780 /* IMR DW0 Bit 0-31 */ 781 #define IMR_BCNDMAINT6 BIT31 /* Beacon DMA Interrupt 6 */ 782 #define IMR_BCNDMAINT5 BIT30 /* Beacon DMA Interrupt 5 */ 783 #define IMR_BCNDMAINT4 BIT29 /* Beacon DMA Interrupt 4 */ 784 #define IMR_BCNDMAINT3 BIT28 /* Beacon DMA Interrupt 3 */ 785 #define IMR_BCNDMAINT2 BIT27 /* Beacon DMA Interrupt 2 */ 786 #define IMR_BCNDMAINT1 BIT26 /* Beacon DMA Interrupt 1 */ 787 #define IMR_BCNDOK8 BIT25 /* Beacon Queue DMA OK Interrup 8 */ 788 #define IMR_BCNDOK7 BIT24 /* Beacon Queue DMA OK Interrup 7 */ 789 #define IMR_BCNDOK6 BIT23 /* Beacon Queue DMA OK Interrup 6 */ 790 #define IMR_BCNDOK5 BIT22 /* Beacon Queue DMA OK Interrup 5 */ 791 #define IMR_BCNDOK4 BIT21 /* Beacon Queue DMA OK Interrup 4 */ 792 #define IMR_BCNDOK3 BIT20 /* Beacon Queue DMA OK Interrup 3 */ 793 #define IMR_BCNDOK2 BIT19 /* Beacon Queue DMA OK Interrup 2 */ 794 #define IMR_BCNDOK1 BIT18 /* Beacon Queue DMA OK Interrup 1 */ 795 #define IMR_TIMEOUT2 BIT17 /* Timeout interrupt 2 */ 796 #define IMR_TIMEOUT1 BIT16 /* Timeout interrupt 1 */ 797 #define IMR_TXFOVW BIT15 /* Transmit FIFO Overflow */ 798 #define IMR_PSTIMEOUT BIT14 /* Power save time out interrupt */ 799 #define IMR_BcnInt BIT13 /* Beacon DMA Interrupt 0 */ 800 #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */ 801 #define IMR_RDU BIT11 /* Receive Descriptor Unavailable */ 802 #define IMR_ATIMEND BIT10 /* For 92C, ATIM Window End Interrupt. For 8723 and later ICs, it also means P2P CTWin End interrupt. */ 803 #define IMR_BDOK BIT9 /* Beacon Queue DMA OK Interrup */ 804 #define IMR_HIGHDOK BIT8 /* High Queue DMA OK Interrupt */ 805 #define IMR_TBDOK BIT7 /* Transmit Beacon OK interrup */ 806 #define IMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ 807 #define IMR_TBDER BIT5 /* For 92C, Transmit Beacon Error Interrupt */ 808 #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */ 809 #define IMR_BEDOK BIT3 /* AC_BE DMA OK Interrupt */ 810 #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ 811 #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ 812 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */ 813 814 /* 13. Host Interrupt Status Extension Register (Offset: 0x012C-012Eh) */ 815 #define IMR_TSF_BIT32_TOGGLE BIT15 816 #define IMR_BcnInt_E BIT12 817 #define IMR_TXERR BIT11 818 #define IMR_RXERR BIT10 819 #define IMR_C2HCMD BIT9 820 #define IMR_CPWM BIT8 821 /* RSVD [2-7] */ 822 #define IMR_OCPINT BIT1 823 #define IMR_WLANOFF BIT0 824 825 /* */ 826 /* 8723E series PCIE Host IMR/ISR bit */ 827 /* */ 828 /* IMR DW0 Bit 0-31 */ 829 #define PHIMR_TIMEOUT2 BIT31 830 #define PHIMR_TIMEOUT1 BIT30 831 #define PHIMR_PSTIMEOUT BIT29 832 #define PHIMR_GTINT4 BIT28 833 #define PHIMR_GTINT3 BIT27 834 #define PHIMR_TXBCNERR BIT26 835 #define PHIMR_TXBCNOK BIT25 836 #define PHIMR_TSF_BIT32_TOGGLE BIT24 837 #define PHIMR_BCNDMAINT3 BIT23 838 #define PHIMR_BCNDMAINT2 BIT22 839 #define PHIMR_BCNDMAINT1 BIT21 840 #define PHIMR_BCNDMAINT0 BIT20 841 #define PHIMR_BCNDOK3 BIT19 842 #define PHIMR_BCNDOK2 BIT18 843 #define PHIMR_BCNDOK1 BIT17 844 #define PHIMR_BCNDOK0 BIT16 845 #define PHIMR_HSISR_IND_ON BIT15 846 #define PHIMR_BCNDMAINT_E BIT14 847 #define PHIMR_ATIMEND_E BIT13 848 #define PHIMR_ATIM_CTW_END BIT12 849 #define PHIMR_HISRE_IND BIT11 /* RO. HISRE Indicator (HISRE & HIMRE is true, this bit is set to 1) */ 850 #define PHIMR_C2HCMD BIT10 851 #define PHIMR_CPWM2 BIT9 852 #define PHIMR_CPWM BIT8 853 #define PHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ 854 #define PHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ 855 #define PHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ 856 #define PHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ 857 #define PHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ 858 #define PHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ 859 #define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ 860 #define PHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ 861 862 /* PCIE Host Interrupt Status Extension bit */ 863 #define PHIMR_BCNDMAINT7 BIT23 864 #define PHIMR_BCNDMAINT6 BIT22 865 #define PHIMR_BCNDMAINT5 BIT21 866 #define PHIMR_BCNDMAINT4 BIT20 867 #define PHIMR_BCNDOK7 BIT19 868 #define PHIMR_BCNDOK6 BIT18 869 #define PHIMR_BCNDOK5 BIT17 870 #define PHIMR_BCNDOK4 BIT16 871 /* bit12 15: RSVD */ 872 #define PHIMR_TXERR BIT11 873 #define PHIMR_RXERR BIT10 874 #define PHIMR_TXFOVW BIT9 875 #define PHIMR_RXFOVW BIT8 876 /* bit2-7: RSVD */ 877 #define PHIMR_OCPINT BIT1 878 /* bit0: RSVD */ 879 880 #define UHIMR_TIMEOUT2 BIT31 881 #define UHIMR_TIMEOUT1 BIT30 882 #define UHIMR_PSTIMEOUT BIT29 883 #define UHIMR_GTINT4 BIT28 884 #define UHIMR_GTINT3 BIT27 885 #define UHIMR_TXBCNERR BIT26 886 #define UHIMR_TXBCNOK BIT25 887 #define UHIMR_TSF_BIT32_TOGGLE BIT24 888 #define UHIMR_BCNDMAINT3 BIT23 889 #define UHIMR_BCNDMAINT2 BIT22 890 #define UHIMR_BCNDMAINT1 BIT21 891 #define UHIMR_BCNDMAINT0 BIT20 892 #define UHIMR_BCNDOK3 BIT19 893 #define UHIMR_BCNDOK2 BIT18 894 #define UHIMR_BCNDOK1 BIT17 895 #define UHIMR_BCNDOK0 BIT16 896 #define UHIMR_HSISR_IND BIT15 897 #define UHIMR_BCNDMAINT_E BIT14 898 /* RSVD BIT13 */ 899 #define UHIMR_CTW_END BIT12 900 /* RSVD BIT11 */ 901 #define UHIMR_C2HCMD BIT10 902 #define UHIMR_CPWM2 BIT9 903 #define UHIMR_CPWM BIT8 904 #define UHIMR_HIGHDOK BIT7 /* High Queue DMA OK Interrupt */ 905 #define UHIMR_MGNTDOK BIT6 /* Management Queue DMA OK Interrupt */ 906 #define UHIMR_BKDOK BIT5 /* AC_BK DMA OK Interrupt */ 907 #define UHIMR_BEDOK BIT4 /* AC_BE DMA OK Interrupt */ 908 #define UHIMR_VIDOK BIT3 /* AC_VI DMA OK Interrupt */ 909 #define UHIMR_VODOK BIT2 /* AC_VO DMA Interrupt */ 910 #define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ 911 #define UHIMR_ROK BIT0 /* Receive DMA OK Interrupt */ 912 913 /* USB Host Interrupt Status Extension bit */ 914 #define UHIMR_BCNDMAINT7 BIT23 915 #define UHIMR_BCNDMAINT6 BIT22 916 #define UHIMR_BCNDMAINT5 BIT21 917 #define UHIMR_BCNDMAINT4 BIT20 918 #define UHIMR_BCNDOK7 BIT19 919 #define UHIMR_BCNDOK6 BIT18 920 #define UHIMR_BCNDOK5 BIT17 921 #define UHIMR_BCNDOK4 BIT16 922 /* bit14-15: RSVD */ 923 #define UHIMR_ATIMEND_E BIT13 924 #define UHIMR_ATIMEND BIT12 925 #define UHIMR_TXERR BIT11 926 #define UHIMR_RXERR BIT10 927 #define UHIMR_TXFOVW BIT9 928 #define UHIMR_RXFOVW BIT8 929 /* bit2-7: RSVD */ 930 #define UHIMR_OCPINT BIT1 931 /* bit0: RSVD */ 932 933 934 #define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */ 935 #define HAL_NIC_UNPLUG_PCI_ISR 0xEAEAEAEA /* The value when the NIC is unplugged for PCI in PCI interrupt (page 3). */ 936 937 /* */ 938 /* 8188 IMR/ISR bits */ 939 /* */ 940 #define IMR_DISABLED_88E 0x0 941 /* IMR DW0(0x0060-0063) Bit 0-31 */ 942 #define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */ 943 #define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */ 944 #define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */ 945 #define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */ 946 #define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */ 947 #define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */ 948 #define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */ 949 #define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */ 950 #define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */ 951 #define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */ 952 #define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */ 953 #define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */ 954 #define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */ 955 #define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */ 956 #define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */ 957 #define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */ 958 #define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */ 959 #define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */ 960 #define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */ 961 #define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */ 962 #define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */ 963 #define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */ 964 #define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */ 965 #define IMR_ROK_88E BIT0 /* Receive DMA OK */ 966 967 /* IMR DW1(0x00B4-00B7) Bit 0-31 */ 968 #define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */ 969 #define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */ 970 #define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */ 971 #define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */ 972 #define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */ 973 #define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */ 974 #define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */ 975 #define IMR_BCNDOK7_88E BIT20 /* Beacon Queue DMA OK Interrup 7 */ 976 #define IMR_BCNDOK6_88E BIT19 /* Beacon Queue DMA OK Interrup 6 */ 977 #define IMR_BCNDOK5_88E BIT18 /* Beacon Queue DMA OK Interrup 5 */ 978 #define IMR_BCNDOK4_88E BIT17 /* Beacon Queue DMA OK Interrup 4 */ 979 #define IMR_BCNDOK3_88E BIT16 /* Beacon Queue DMA OK Interrup 3 */ 980 #define IMR_BCNDOK2_88E BIT15 /* Beacon Queue DMA OK Interrup 2 */ 981 #define IMR_BCNDOK1_88E BIT14 /* Beacon Queue DMA OK Interrup 1 */ 982 #define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Extension for Win7 */ 983 #define IMR_TXERR_88E BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */ 984 #define IMR_RXERR_88E BIT10 /* Rx Error Flag INT Status, Write 1 clear */ 985 #define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */ 986 #define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */ 987 988 /*=================================================================== 989 ===================================================================== 990 Here the register defines are for 92C. When the define is as same with 92C, 991 we will use the 92C's define for the consistency 992 So the following defines for 92C is not entire!!!!!! 993 ===================================================================== 994 =====================================================================*/ 995 /* 996 Based on Datasheet V33---090401 997 Register Summary 998 Current IOREG MAP 999 0x0000h ~ 0x00FFh System Configuration (256 Bytes) 1000 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes) 1001 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes) 1002 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes) 1003 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes) 1004 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes) 1005 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes) 1006 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes) 1007 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes) 1008 */ 1009 /* */ 1010 /* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */ 1011 /* */ 1012 /* Note: */ 1013 /* The the bits of stoping AC(VO/VI/BE/BK) queue in datasheet RTL8192S/RTL8192C are wrong, */ 1014 /* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2, and BK - Bit3. */ 1015 /* 8723 and 88E may be not correct either in the eralier version. Confirmed with DD Tim. */ 1016 /* By Bruce, 2011-09-22. */ 1017 #define StopBecon BIT6 1018 #define StopHigh BIT5 1019 #define StopMgt BIT4 1020 #define StopBK BIT3 1021 #define StopBE BIT2 1022 #define StopVI BIT1 1023 #define StopVO BIT0 1024 1025 /* */ 1026 /* 8192C (RCR) Receive Configuration Register (Offset 0x608, 32 bits) */ 1027 /* */ 1028 #define RCR_APPFCS BIT31 /* WMAC append FCS after pauload */ 1029 #define RCR_APP_MIC BIT30 /* MACRX will retain the MIC at the bottom of the packet. */ 1030 #define RCR_APP_ICV BIT29 /* MACRX will retain the ICV at the bottom of the packet. */ 1031 #define RCR_APP_PHYST_RXFF BIT28 /* PHY Status is appended before RX packet in RXFF */ 1032 #define RCR_APP_BA_SSN BIT27 /* SSN of previous TXBA is appended as after original RXDESC as the 4-th DW of RXDESC. */ 1033 #define RCR_NONQOS_VHT BIT26 /* Reserved */ 1034 #define RCR_RSVD_BIT25 BIT25 /* Reserved */ 1035 #define RCR_ENMBID BIT24 /* Enable Multiple BssId. Only response ACK to the packets whose DID(A1) matching to the addresses in the MBSSID CAM Entries. */ 1036 #define RCR_LSIGEN BIT23 /* Enable LSIG TXOP Protection function. Search KEYCAM for each rx packet to check if LSIGEN bit is set. */ 1037 #define RCR_MFBEN BIT22 /* Enable immediate MCS Feedback function. When Rx packet with MRQ = 1'b1, then search KEYCAM to find sender's MCS Feedback function and send response. */ 1038 #define RCR_RSVD_BIT21 BIT21 /* Reserved */ 1039 #define RCR_RSVD_BIT20 BIT20 /* Reserved */ 1040 #define RCR_RSVD_BIT19 BIT19 /* Reserved */ 1041 #define RCR_TIM_PARSER_EN BIT18 /* RX Beacon TIM Parser. */ 1042 #define RCR_BM_DATA_EN BIT17 /* Broadcast data packet interrupt enable. */ 1043 #define RCR_UC_DATA_EN BIT16 /* Unicast data packet interrupt enable. */ 1044 #define RCR_RSVD_BIT15 BIT15 /* Reserved */ 1045 #define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC = 1 MFC-->HTC = 0 */ 1046 #define RCR_AMF BIT13 /* Accept management type frame */ 1047 #define RCR_ACF BIT12 /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */ 1048 #define RCR_ADF BIT11 /* Accept data type frame. This bit also regulates BA, BAR, and PS-Poll (AP mode only). */ 1049 #define RCR_RSVD_BIT10 BIT10 /* Reserved */ 1050 #define RCR_AICV BIT9 /* Accept ICV error packet */ 1051 #define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */ 1052 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */ 1053 #define RCR_CBSSID_DATA BIT6 /* Accept BSSID match packet (Data) */ 1054 #define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match packet */ 1055 #define RCR_APWRMGT BIT5 /* Accept power management packet */ 1056 #define RCR_ADD3 BIT4 /* Accept address 3 match packet */ 1057 #define RCR_AB BIT3 /* Accept broadcast packet */ 1058 #define RCR_AM BIT2 /* Accept multicast packet */ 1059 #define RCR_APM BIT1 /* Accept physical match packet */ 1060 #define RCR_AAP BIT0 /* Accept all unicast packet */ 1061 1062 1063 /* */ 1064 /* */ 1065 /* 0x0000h ~ 0x00FFh System Configuration */ 1066 /* */ 1067 /* */ 1068 1069 /* 2 SYS_ISO_CTRL */ 1070 #define ISO_MD2PP BIT(0) 1071 #define ISO_UA2USB BIT(1) 1072 #define ISO_UD2CORE BIT(2) 1073 #define ISO_PA2PCIE BIT(3) 1074 #define ISO_PD2CORE BIT(4) 1075 #define ISO_IP2MAC BIT(5) 1076 #define ISO_DIOP BIT(6) 1077 #define ISO_DIOE BIT(7) 1078 #define ISO_EB2CORE BIT(8) 1079 #define ISO_DIOR BIT(9) 1080 #define PWC_EV12V BIT(15) 1081 1082 1083 /* 2 SYS_FUNC_EN */ 1084 #define FEN_BBRSTB BIT(0) 1085 #define FEN_BB_GLB_RSTn BIT(1) 1086 #define FEN_USBA BIT(2) 1087 #define FEN_UPLL BIT(3) 1088 #define FEN_USBD BIT(4) 1089 #define FEN_DIO_PCIE BIT(5) 1090 #define FEN_PCIEA BIT(6) 1091 #define FEN_PPLL BIT(7) 1092 #define FEN_PCIED BIT(8) 1093 #define FEN_DIOE BIT(9) 1094 #define FEN_CPUEN BIT(10) 1095 #define FEN_DCORE BIT(11) 1096 #define FEN_ELDR BIT(12) 1097 #define FEN_EN_25_1 BIT(13) 1098 #define FEN_HWPDN BIT(14) 1099 #define FEN_MREGEN BIT(15) 1100 1101 /* 2 APS_FSMCO */ 1102 #define PFM_LDALL BIT(0) 1103 #define PFM_ALDN BIT(1) 1104 #define PFM_LDKP BIT(2) 1105 #define PFM_WOWL BIT(3) 1106 #define EnPDN BIT(4) 1107 #define PDN_PL BIT(5) 1108 #define APFM_ONMAC BIT(8) 1109 #define APFM_OFF BIT(9) 1110 #define APFM_RSM BIT(10) 1111 #define AFSM_HSUS BIT(11) 1112 #define AFSM_PCIE BIT(12) 1113 #define APDM_MAC BIT(13) 1114 #define APDM_HOST BIT(14) 1115 #define APDM_HPDN BIT(15) 1116 #define RDY_MACON BIT(16) 1117 #define SUS_HOST BIT(17) 1118 #define ROP_ALD BIT(20) 1119 #define ROP_PWR BIT(21) 1120 #define ROP_SPS BIT(22) 1121 #define SOP_MRST BIT(25) 1122 #define SOP_FUSE BIT(26) 1123 #define SOP_ABG BIT(27) 1124 #define SOP_AMB BIT(28) 1125 #define SOP_RCK BIT(29) 1126 #define SOP_A8M BIT(30) 1127 #define XOP_BTCK BIT(31) 1128 1129 /* 2 SYS_CLKR */ 1130 #define ANAD16V_EN BIT(0) 1131 #define ANA8M BIT(1) 1132 #define MACSLP BIT(4) 1133 #define LOADER_CLK_EN BIT(5) 1134 1135 1136 /* 2 9346CR /REG_SYS_EEPROM_CTRL */ 1137 #define BOOT_FROM_EEPROM BIT(4) 1138 #define EEPROMSEL BIT(4) 1139 #define EEPROM_EN BIT(5) 1140 1141 1142 /* 2 RF_CTRL */ 1143 #define RF_EN BIT(0) 1144 #define RF_RSTB BIT(1) 1145 #define RF_SDMRSTB BIT(2) 1146 1147 1148 /* 2 LDOV12D_CTRL */ 1149 #define LDV12_EN BIT(0) 1150 #define LDV12_SDBY BIT(1) 1151 #define LPLDO_HSM BIT(2) 1152 #define LPLDO_LSM_DIS BIT(3) 1153 #define _LDV12_VADJ(x) (((x) & 0xF) << 4) 1154 1155 1156 1157 /* 2 EFUSE_TEST (For RTL8723 partially) */ 1158 #define EF_TRPT BIT(7) 1159 #define EF_CELL_SEL (BIT(8)|BIT(9)) /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */ 1160 #define LDOE25_EN BIT(31) 1161 #define EFUSE_SEL(x) (((x) & 0x3) << 8) 1162 #define EFUSE_SEL_MASK 0x300 1163 #define EFUSE_WIFI_SEL_0 0x0 1164 #define EFUSE_BT_SEL_0 0x1 1165 #define EFUSE_BT_SEL_1 0x2 1166 #define EFUSE_BT_SEL_2 0x3 1167 1168 1169 /* 2 8051FWDL */ 1170 /* 2 MCUFWDL */ 1171 #define MCUFWDL_EN BIT(0) 1172 #define MCUFWDL_RDY BIT(1) 1173 #define FWDL_ChkSum_rpt BIT(2) 1174 #define MACINI_RDY BIT(3) 1175 #define BBINI_RDY BIT(4) 1176 #define RFINI_RDY BIT(5) 1177 #define WINTINI_RDY BIT(6) 1178 #define RAM_DL_SEL BIT(7) 1179 #define ROM_DLEN BIT(19) 1180 #define CPRST BIT(23) 1181 1182 1183 /* 2 REG_SYS_CFG */ 1184 #define XCLK_VLD BIT(0) 1185 #define ACLK_VLD BIT(1) 1186 #define UCLK_VLD BIT(2) 1187 #define PCLK_VLD BIT(3) 1188 #define PCIRSTB BIT(4) 1189 #define V15_VLD BIT(5) 1190 #define SW_OFFLOAD_EN BIT(7) 1191 #define SIC_IDLE BIT(8) 1192 #define BD_MAC2 BIT(9) 1193 #define BD_MAC1 BIT(10) 1194 #define IC_MACPHY_MODE BIT(11) 1195 #define CHIP_VER (BIT(12)|BIT(13)|BIT(14)|BIT(15)) 1196 #define BT_FUNC BIT(16) 1197 #define VENDOR_ID BIT(19) 1198 #define EXT_VENDOR_ID (BIT(18)|BIT(19)) /* Currently only for RTL8723B */ 1199 #define PAD_HWPD_IDN BIT(22) 1200 #define TRP_VAUX_EN BIT(23) /* RTL ID */ 1201 #define TRP_BT_EN BIT(24) 1202 #define BD_PKG_SEL BIT(25) 1203 #define BD_HCI_SEL BIT(26) 1204 #define TYPE_ID BIT(27) 1205 #define RF_TYPE_ID BIT(27) 1206 1207 #define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */ 1208 #define SPS_SEL BIT(24) /* 1:LDO regulator mode; 0:Switching regulator mode */ 1209 1210 1211 #define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */ 1212 #define CHIP_VER_RTL_SHIFT 12 1213 #define EXT_VENDOR_ID_SHIFT 18 1214 1215 /* 2 REG_GPIO_OUTSTS (For RTL8723 only) */ 1216 #define EFS_HCI_SEL (BIT(0)|BIT(1)) 1217 #define PAD_HCI_SEL (BIT(2)|BIT(3)) 1218 #define HCI_SEL (BIT(4)|BIT(5)) 1219 #define PKG_SEL_HCI BIT(6) 1220 #define FEN_GPS BIT(7) 1221 #define FEN_BT BIT(8) 1222 #define FEN_WL BIT(9) 1223 #define FEN_PCI BIT(10) 1224 #define FEN_USB BIT(11) 1225 #define BTRF_HWPDN_N BIT(12) 1226 #define WLRF_HWPDN_N BIT(13) 1227 #define PDN_BT_N BIT(14) 1228 #define PDN_GPS_N BIT(15) 1229 #define BT_CTL_HWPDN BIT(16) 1230 #define GPS_CTL_HWPDN BIT(17) 1231 #define PPHY_SUSB BIT(20) 1232 #define UPHY_SUSB BIT(21) 1233 #define PCI_SUSEN BIT(22) 1234 #define USB_SUSEN BIT(23) 1235 #define RF_RL_ID (BIT(31)|BIT(30)|BIT(29)|BIT(28)) 1236 1237 1238 /* */ 1239 /* */ 1240 /* 0x0100h ~ 0x01FFh MACTOP General Configuration */ 1241 /* */ 1242 /* */ 1243 1244 /* 2 Function Enable Registers */ 1245 /* 2 CR */ 1246 #define HCI_TXDMA_EN BIT(0) 1247 #define HCI_RXDMA_EN BIT(1) 1248 #define TXDMA_EN BIT(2) 1249 #define RXDMA_EN BIT(3) 1250 #define PROTOCOL_EN BIT(4) 1251 #define SCHEDULE_EN BIT(5) 1252 #define MACTXEN BIT(6) 1253 #define MACRXEN BIT(7) 1254 #define ENSWBCN BIT(8) 1255 #define ENSEC BIT(9) 1256 #define CALTMR_EN BIT(10) /* 32k CAL TMR enable */ 1257 1258 /* Network type */ 1259 #define _NETTYPE(x) (((x) & 0x3) << 16) 1260 #define MASK_NETTYPE 0x30000 1261 #define NT_NO_LINK 0x0 1262 #define NT_LINK_AD_HOC 0x1 1263 #define NT_LINK_AP 0x2 1264 #define NT_AS_AP 0x3 1265 1266 /* 2 PBP - Page Size Register */ 1267 #define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 1268 #define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 1269 #define _PSRX_MASK 0xF 1270 #define _PSTX_MASK 0xF0 1271 #define _PSRX(x) (x) 1272 #define _PSTX(x) ((x) << 4) 1273 1274 #define PBP_64 0x0 1275 #define PBP_128 0x1 1276 #define PBP_256 0x2 1277 #define PBP_512 0x3 1278 #define PBP_1024 0x4 1279 1280 1281 /* 2 TX/RXDMA */ 1282 #define RXDMA_ARBBW_EN BIT(0) 1283 #define RXSHFT_EN BIT(1) 1284 #define RXDMA_AGG_EN BIT(2) 1285 #define QS_VO_QUEUE BIT(8) 1286 #define QS_VI_QUEUE BIT(9) 1287 #define QS_BE_QUEUE BIT(10) 1288 #define QS_BK_QUEUE BIT(11) 1289 #define QS_MANAGER_QUEUE BIT(12) 1290 #define QS_HIGH_QUEUE BIT(13) 1291 1292 #define HQSEL_VOQ BIT(0) 1293 #define HQSEL_VIQ BIT(1) 1294 #define HQSEL_BEQ BIT(2) 1295 #define HQSEL_BKQ BIT(3) 1296 #define HQSEL_MGTQ BIT(4) 1297 #define HQSEL_HIQ BIT(5) 1298 1299 /* For normal driver, 0x10C */ 1300 #define _TXDMA_CMQ_MAP(x) (((x)&0x3) << 16) 1301 #define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 1302 #define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 1303 #define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 1304 #define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 1305 #define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 1306 #define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 1307 1308 #define QUEUE_EXTRA 0 1309 #define QUEUE_LOW 1 1310 #define QUEUE_NORMAL 2 1311 #define QUEUE_HIGH 3 1312 1313 1314 /* 2 TRXFF_BNDY */ 1315 1316 1317 /* 2 LLT_INIT */ 1318 #define _LLT_NO_ACTIVE 0x0 1319 #define _LLT_WRITE_ACCESS 0x1 1320 #define _LLT_READ_ACCESS 0x2 1321 1322 #define _LLT_INIT_DATA(x) ((x) & 0xFF) 1323 #define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 1324 #define _LLT_OP(x) (((x) & 0x3) << 30) 1325 #define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 1326 1327 1328 /* */ 1329 /* */ 1330 /* 0x0200h ~ 0x027Fh TXDMA Configuration */ 1331 /* */ 1332 /* */ 1333 /* 2 RQPN */ 1334 #define _HPQ(x) ((x) & 0xFF) 1335 #define _LPQ(x) (((x) & 0xFF) << 8) 1336 #define _PUBQ(x) (((x) & 0xFF) << 16) 1337 #define _NPQ(x) ((x) & 0xFF) /* NOTE: in RQPN_NPQ register */ 1338 #define _EPQ(x) (((x) & 0xFF) << 16) /* NOTE: in RQPN_EPQ register */ 1339 1340 1341 #define HPQ_PUBLIC_DIS BIT(24) 1342 #define LPQ_PUBLIC_DIS BIT(25) 1343 #define LD_RQPN BIT(31) 1344 1345 1346 /* 2 TDECTL */ 1347 #define BLK_DESC_NUM_SHIFT 4 1348 #define BLK_DESC_NUM_MASK 0xF 1349 1350 1351 /* 2 TXDMA_OFFSET_CHK */ 1352 #define DROP_DATA_EN BIT(9) 1353 1354 /* 2 AUTO_LLT */ 1355 #define BIT_SHIFT_TXPKTNUM 24 1356 #define BIT_MASK_TXPKTNUM 0xff 1357 #define BIT_TXPKTNUM(x) (((x) & BIT_MASK_TXPKTNUM) << BIT_SHIFT_TXPKTNUM) 1358 1359 #define BIT_TDE_DBG_SEL BIT(23) 1360 #define BIT_AUTO_INIT_LLT BIT(16) 1361 1362 #define BIT_SHIFT_Tx_OQT_free_space 8 1363 #define BIT_MASK_Tx_OQT_free_space 0xff 1364 #define BIT_Tx_OQT_free_space(x) (((x) & BIT_MASK_Tx_OQT_free_space) << BIT_SHIFT_Tx_OQT_free_space) 1365 1366 1367 /* */ 1368 /* */ 1369 /* 0x0280h ~ 0x028Bh RX DMA Configuration */ 1370 /* */ 1371 /* */ 1372 1373 /* 2 REG_RXDMA_CONTROL, 0x0286h */ 1374 /* Write only. When this bit is set, RXDMA will decrease RX PKT counter by one. Before */ 1375 /* this bit is polled, FW shall update RXFF_RD_PTR first. This register is write pulse and auto clear. */ 1376 /* define RXPKT_RELEASE_POLL BIT(0) */ 1377 /* Read only. When RXMA finishes on-going DMA operation, RXMDA will report idle state in */ 1378 /* this bit. FW can start releasing packets after RXDMA entering idle mode. */ 1379 /* define RXDMA_IDLE BIT(1) */ 1380 /* When this bit is set, RXDMA will enter this mode after on-going RXDMA packet to host */ 1381 /* completed, and stop DMA packet to host. RXDMA will then report Default: 0; */ 1382 /* define RW_RELEASE_EN BIT(2) */ 1383 1384 /* 2 REG_RXPKT_NUM, 0x0284 */ 1385 #define RXPKT_RELEASE_POLL BIT(16) 1386 #define RXDMA_IDLE BIT(17) 1387 #define RW_RELEASE_EN BIT(18) 1388 1389 /* */ 1390 /* */ 1391 /* 0x0400h ~ 0x047Fh Protocol Configuration */ 1392 /* */ 1393 /* */ 1394 /* 2 FWHW_TXQ_CTRL */ 1395 #define EN_AMPDU_RTY_NEW BIT(7) 1396 1397 1398 /* 2 SPEC SIFS */ 1399 #define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 1400 #define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 1401 1402 /* 2 RL */ 1403 #define RETRY_LIMIT_SHORT_SHIFT 8 1404 #define RETRY_LIMIT_LONG_SHIFT 0 1405 1406 /* */ 1407 /* */ 1408 /* 0x0500h ~ 0x05FFh EDCA Configuration */ 1409 /* */ 1410 /* */ 1411 1412 /* 2 EDCA setting */ 1413 #define AC_PARAM_TXOP_LIMIT_OFFSET 16 1414 #define AC_PARAM_ECW_MAX_OFFSET 12 1415 #define AC_PARAM_ECW_MIN_OFFSET 8 1416 #define AC_PARAM_AIFS_OFFSET 0 1417 1418 1419 #define _LRL(x) ((x) & 0x3F) 1420 #define _SRL(x) (((x) & 0x3F) << 8) 1421 1422 1423 /* 2 BCN_CTRL */ 1424 #define EN_TXBCN_RPT BIT(2) 1425 #define EN_BCN_FUNCTION BIT(3) 1426 #define STOP_BCNQ BIT(6) 1427 #define DIS_RX_BSSID_FIT BIT(6) 1428 1429 #define DIS_ATIM BIT(0) 1430 #define DIS_BCNQ_SUB BIT(1) 1431 #define DIS_TSF_UDT BIT(4) 1432 1433 /* The same function but different bit field. */ 1434 #define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1435 #define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1436 1437 1438 /* 2 ACMHWCTRL */ 1439 #define AcmHw_HwEn BIT(0) 1440 #define AcmHw_BeqEn BIT(1) 1441 #define AcmHw_ViqEn BIT(2) 1442 #define AcmHw_VoqEn BIT(3) 1443 #define AcmHw_BeqStatus BIT(4) 1444 #define AcmHw_ViqStatus BIT(5) 1445 #define AcmHw_VoqStatus BIT(6) 1446 1447 /* 2 REG_DUAL_TSF_RST (0x553) */ 1448 #define DUAL_TSF_RST_P2P BIT(4) 1449 1450 /* 2 REG_NOA_DESC_SEL (0x5CF) */ 1451 #define NOA_DESC_SEL_0 0 1452 #define NOA_DESC_SEL_1 BIT(4) 1453 1454 /* */ 1455 /* */ 1456 /* 0x0600h ~ 0x07FFh WMAC Configuration */ 1457 /* */ 1458 /* */ 1459 1460 /* 2 APSD_CTRL */ 1461 #define APSDOFF BIT(6) 1462 1463 /* 2 TCR */ 1464 #define TSFRST BIT(0) 1465 #define DIS_GCLK BIT(1) 1466 #define PAD_SEL BIT(2) 1467 #define PWR_ST BIT(6) 1468 #define PWRBIT_OW_EN BIT(7) 1469 #define ACRC BIT(8) 1470 #define CFENDFORM BIT(9) 1471 #define ICV BIT(10) 1472 1473 1474 /* 2 RCR */ 1475 #define AAP BIT(0) 1476 #define APM BIT(1) 1477 #define AM BIT(2) 1478 #define AB BIT(3) 1479 #define ADD3 BIT(4) 1480 #define APWRMGT BIT(5) 1481 #define CBSSID BIT(6) 1482 #define CBSSID_DATA BIT(6) 1483 #define CBSSID_BCN BIT(7) 1484 #define ACRC32 BIT(8) 1485 #define AICV BIT(9) 1486 #define ADF BIT(11) 1487 #define ACF BIT(12) 1488 #define AMF BIT(13) 1489 #define HTC_LOC_CTRL BIT(14) 1490 #define UC_DATA_EN BIT(16) 1491 #define BM_DATA_EN BIT(17) 1492 #define MFBEN BIT(22) 1493 #define LSIGEN BIT(23) 1494 #define EnMBID BIT(24) 1495 #define FORCEACK BIT(26) 1496 #define APP_BASSN BIT(27) 1497 #define APP_PHYSTS BIT(28) 1498 #define APP_ICV BIT(29) 1499 #define APP_MIC BIT(30) 1500 #define APP_FCS BIT(31) 1501 1502 1503 /* 2 SECCFG */ 1504 #define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */ 1505 #define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */ 1506 #define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */ 1507 #define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */ 1508 #define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */ 1509 #define SCR_NoSKMC BIT(5) /* No Key Search Multicast */ 1510 #define SCR_TXBCUSEDK BIT(6) /* Force Tx Broadcast packets Use Default Key */ 1511 #define SCR_RXBCUSEDK BIT(7) /* Force Rx Broadcast packets Use Default Key */ 1512 #define SCR_CHK_KEYID BIT(8) 1513 1514 /* */ 1515 /* */ 1516 /* SDIO Bus Specification */ 1517 /* */ 1518 /* */ 1519 1520 /* I/O bus domain address mapping */ 1521 #define SDIO_LOCAL_BASE 0x10250000 1522 #define WLAN_IOREG_BASE 0x10260000 1523 #define FIRMWARE_FIFO_BASE 0x10270000 1524 #define TX_HIQ_BASE 0x10310000 1525 #define TX_MIQ_BASE 0x10320000 1526 #define TX_LOQ_BASE 0x10330000 1527 #define TX_EPQ_BASE 0x10350000 1528 #define RX_RX0FF_BASE 0x10340000 1529 1530 /* SDIO host local register space mapping. */ 1531 #define SDIO_LOCAL_MSK 0x0FFF 1532 #define WLAN_IOREG_MSK 0x7FFF 1533 #define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */ 1534 #define WLAN_RX0FF_MSK 0x0003 1535 1536 #define SDIO_WITHOUT_REF_DEVICE_ID 0 /* Without reference to the SDIO Device ID */ 1537 #define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */ 1538 #define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */ 1539 #define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */ 1540 #define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */ 1541 #define WLAN_TX_EXQ_DEVICE_ID 3 /* 0b[16], 011b[15:13] */ 1542 #define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */ 1543 #define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */ 1544 1545 /* SDIO Tx Free Page Index */ 1546 #define HI_QUEUE_IDX 0 1547 #define MID_QUEUE_IDX 1 1548 #define LOW_QUEUE_IDX 2 1549 #define PUBLIC_QUEUE_IDX 3 1550 1551 #define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */ 1552 #define SDIO_MAX_RX_QUEUE 1 1553 1554 #define SDIO_REG_TX_CTRL 0x0000 /* SDIO Tx Control */ 1555 #define SDIO_REG_HIMR 0x0014 /* SDIO Host Interrupt Mask */ 1556 #define SDIO_REG_HISR 0x0018 /* SDIO Host Interrupt Service Routine */ 1557 #define SDIO_REG_HCPWM 0x0019 /* HCI Current Power Mode */ 1558 #define SDIO_REG_RX0_REQ_LEN 0x001C /* RXDMA Request Length */ 1559 #define SDIO_REG_OQT_FREE_PG 0x001E /* OQT Free Page */ 1560 #define SDIO_REG_FREE_TXPG 0x0020 /* Free Tx Buffer Page */ 1561 #define SDIO_REG_HCPWM1 0x0024 /* HCI Current Power Mode 1 */ 1562 #define SDIO_REG_HCPWM2 0x0026 /* HCI Current Power Mode 2 */ 1563 #define SDIO_REG_FREE_TXPG_SEQ 0x0028 /* Free Tx Page Sequence */ 1564 #define SDIO_REG_HTSFR_INFO 0x0030 /* HTSF Informaion */ 1565 #define SDIO_REG_HRPWM1 0x0080 /* HCI Request Power Mode 1 */ 1566 #define SDIO_REG_HRPWM2 0x0082 /* HCI Request Power Mode 2 */ 1567 #define SDIO_REG_HPS_CLKR 0x0084 /* HCI Power Save Clock */ 1568 #define SDIO_REG_HSUS_CTRL 0x0086 /* SDIO HCI Suspend Control */ 1569 #define SDIO_REG_HIMR_ON 0x0090 /* SDIO Host Extension Interrupt Mask Always */ 1570 #define SDIO_REG_HISR_ON 0x0091 /* SDIO Host Extension Interrupt Status Always */ 1571 1572 #define SDIO_HIMR_DISABLED 0 1573 1574 /* RTL8723/RTL8188E SDIO Host Interrupt Mask Register */ 1575 #define SDIO_HIMR_RX_REQUEST_MSK BIT0 1576 #define SDIO_HIMR_AVAL_MSK BIT1 1577 #define SDIO_HIMR_TXERR_MSK BIT2 1578 #define SDIO_HIMR_RXERR_MSK BIT3 1579 #define SDIO_HIMR_TXFOVW_MSK BIT4 1580 #define SDIO_HIMR_RXFOVW_MSK BIT5 1581 #define SDIO_HIMR_TXBCNOK_MSK BIT6 1582 #define SDIO_HIMR_TXBCNERR_MSK BIT7 1583 #define SDIO_HIMR_BCNERLY_INT_MSK BIT16 1584 #define SDIO_HIMR_C2HCMD_MSK BIT17 1585 #define SDIO_HIMR_CPWM1_MSK BIT18 1586 #define SDIO_HIMR_CPWM2_MSK BIT19 1587 #define SDIO_HIMR_HSISR_IND_MSK BIT20 1588 #define SDIO_HIMR_GTINT3_IND_MSK BIT21 1589 #define SDIO_HIMR_GTINT4_IND_MSK BIT22 1590 #define SDIO_HIMR_PSTIMEOUT_MSK BIT23 1591 #define SDIO_HIMR_OCPINT_MSK BIT24 1592 #define SDIO_HIMR_ATIMEND_MSK BIT25 1593 #define SDIO_HIMR_ATIMEND_E_MSK BIT26 1594 #define SDIO_HIMR_CTWEND_MSK BIT27 1595 1596 /* RTL8188E SDIO Specific */ 1597 #define SDIO_HIMR_MCU_ERR_MSK BIT28 1598 #define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29 1599 1600 /* SDIO Host Interrupt Service Routine */ 1601 #define SDIO_HISR_RX_REQUEST BIT0 1602 #define SDIO_HISR_AVAL BIT1 1603 #define SDIO_HISR_TXERR BIT2 1604 #define SDIO_HISR_RXERR BIT3 1605 #define SDIO_HISR_TXFOVW BIT4 1606 #define SDIO_HISR_RXFOVW BIT5 1607 #define SDIO_HISR_TXBCNOK BIT6 1608 #define SDIO_HISR_TXBCNERR BIT7 1609 #define SDIO_HISR_BCNERLY_INT BIT16 1610 #define SDIO_HISR_C2HCMD BIT17 1611 #define SDIO_HISR_CPWM1 BIT18 1612 #define SDIO_HISR_CPWM2 BIT19 1613 #define SDIO_HISR_HSISR_IND BIT20 1614 #define SDIO_HISR_GTINT3_IND BIT21 1615 #define SDIO_HISR_GTINT4_IND BIT22 1616 #define SDIO_HISR_PSTIMEOUT BIT23 1617 #define SDIO_HISR_OCPINT BIT24 1618 #define SDIO_HISR_ATIMEND BIT25 1619 #define SDIO_HISR_ATIMEND_E BIT26 1620 #define SDIO_HISR_CTWEND BIT27 1621 1622 /* RTL8188E SDIO Specific */ 1623 #define SDIO_HISR_MCU_ERR BIT28 1624 #define SDIO_HISR_TSF_BIT32_TOGGLE BIT29 1625 1626 #define MASK_SDIO_HISR_CLEAR (SDIO_HISR_TXERR |\ 1627 SDIO_HISR_RXERR |\ 1628 SDIO_HISR_TXFOVW |\ 1629 SDIO_HISR_RXFOVW |\ 1630 SDIO_HISR_TXBCNOK |\ 1631 SDIO_HISR_TXBCNERR |\ 1632 SDIO_HISR_C2HCMD |\ 1633 SDIO_HISR_CPWM1 |\ 1634 SDIO_HISR_CPWM2 |\ 1635 SDIO_HISR_HSISR_IND |\ 1636 SDIO_HISR_GTINT3_IND |\ 1637 SDIO_HISR_GTINT4_IND |\ 1638 SDIO_HISR_PSTIMEOUT |\ 1639 SDIO_HISR_OCPINT) 1640 1641 /* SDIO HCI Suspend Control Register */ 1642 #define HCI_RESUME_PWR_RDY BIT1 1643 #define HCI_SUS_CTRL BIT0 1644 1645 /* SDIO Tx FIFO related */ 1646 #define SDIO_TX_FREE_PG_QUEUE 4 /* The number of Tx FIFO free page */ 1647 #define SDIO_TX_FIFO_PAGE_SZ 128 1648 1649 #define MAX_TX_AGG_PACKET_NUMBER 0x8 1650 1651 /* */ 1652 /* */ 1653 /* 0xFE00h ~ 0xFE55h USB Configuration */ 1654 /* */ 1655 /* */ 1656 1657 /* 2 USB Information (0xFE17) */ 1658 #define USB_IS_HIGH_SPEED 0 1659 #define USB_IS_FULL_SPEED 1 1660 #define USB_SPEED_MASK BIT(5) 1661 1662 #define USB_NORMAL_SIE_EP_MASK 0xF 1663 #define USB_NORMAL_SIE_EP_SHIFT 4 1664 1665 /* 2 Special Option */ 1666 #define USB_AGG_EN BIT(3) 1667 1668 /* 0; Use interrupt endpoint to upload interrupt pkt */ 1669 /* 1; Use bulk endpoint to upload interrupt pkt, */ 1670 #define INT_BULK_SEL BIT(4) 1671 1672 /* 2REG_C2HEVT_CLEAR */ 1673 #define C2H_EVT_HOST_CLOSE 0x00 /* Set by driver and notify FW that the driver has read the C2H command message */ 1674 #define C2H_EVT_FW_CLOSE 0xFF /* Set by FW indicating that FW had set the C2H command message and it's not yet read by driver. */ 1675 1676 1677 /* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */ 1678 #define WL_HWPDN_EN BIT0 /* Enable GPIO[9] as WiFi HW PDn source */ 1679 #define WL_HWPDN_SL BIT1 /* WiFi HW PDn polarity control */ 1680 #define WL_FUNC_EN BIT2 /* WiFi function enable */ 1681 #define WL_HWROF_EN BIT3 /* Enable GPIO[9] as WiFi RF HW PDn source */ 1682 #define BT_HWPDN_EN BIT16 /* Enable GPIO[11] as BT HW PDn source */ 1683 #define BT_HWPDN_SL BIT17 /* BT HW PDn polarity control */ 1684 #define BT_FUNC_EN BIT18 /* BT function enable */ 1685 #define BT_HWROF_EN BIT19 /* Enable GPIO[11] as BT/GPS RF HW PDn source */ 1686 #define GPS_HWPDN_EN BIT20 /* Enable GPIO[10] as GPS HW PDn source */ 1687 #define GPS_HWPDN_SL BIT21 /* GPS HW PDn polarity control */ 1688 #define GPS_FUNC_EN BIT22 /* GPS function enable */ 1689 1690 /* 3 REG_LIFECTRL_CTRL */ 1691 #define HAL92C_EN_PKT_LIFE_TIME_BK BIT3 1692 #define HAL92C_EN_PKT_LIFE_TIME_BE BIT2 1693 #define HAL92C_EN_PKT_LIFE_TIME_VI BIT1 1694 #define HAL92C_EN_PKT_LIFE_TIME_VO BIT0 1695 1696 #define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us, said by Tim. */ 1697 1698 /* 2 8192D PartNo. */ 1699 #define PARTNO_92D_NIC (BIT7|BIT6) 1700 #define PARTNO_92D_NIC_REMARK (BIT5|BIT4) 1701 #define PARTNO_SINGLE_BAND_VS BIT3 1702 #define PARTNO_SINGLE_BAND_VS_REMARK BIT1 1703 #define PARTNO_CONCURRENT_BAND_VC (BIT3|BIT2) 1704 #define PARTNO_CONCURRENT_BAND_VC_REMARK (BIT1|BIT0) 1705 1706 /* */ 1707 /* General definitions */ 1708 /* */ 1709 1710 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8188E 176 1711 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8812 255 1712 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8723B 255 1713 #define LAST_ENTRY_OF_TX_PKT_BUFFER_8192C 255 1714 #define LAST_ENTRY_OF_TX_PKT_BUFFER_DUAL_MAC 127 1715 1716 #define POLLING_LLT_THRESHOLD 20 1717 #define POLLING_READY_TIMEOUT_COUNT 1000 1718 1719 1720 /* GPIO BIT */ 1721 #define HAL_8192C_HW_GPIO_WPS_BIT BIT2 1722 #define HAL_8192EU_HW_GPIO_WPS_BIT BIT7 1723 #define HAL_8188E_HW_GPIO_WPS_BIT BIT7 1724 1725 #endif /* __HAL_COMMON_H__ */ 1726