1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #ifndef __HAL_COM_PHYCFG_H__ 8 #define __HAL_COM_PHYCFG_H__ 9 10 #define PathA 0x0 /* Useless */ 11 #define PathB 0x1 12 #define PathC 0x2 13 #define PathD 0x3 14 15 enum rate_section { 16 CCK = 0, 17 OFDM, 18 HT_MCS0_MCS7, 19 HT_MCS8_MCS15, 20 HT_MCS16_MCS23, 21 HT_MCS24_MCS31, 22 VHT_1SSMCS0_1SSMCS9, 23 VHT_2SSMCS0_2SSMCS9, 24 VHT_3SSMCS0_3SSMCS9, 25 VHT_4SSMCS0_4SSMCS9, 26 }; 27 28 enum { 29 RF_1TX = 0, 30 RF_2TX, 31 RF_3TX, 32 RF_4TX, 33 RF_MAX_TX_NUM, 34 RF_TX_NUM_NONIMPLEMENT, 35 }; 36 37 #define MAX_POWER_INDEX 0x3F 38 39 enum { 40 TXPWR_LMT_FCC = 0, 41 TXPWR_LMT_MKK, 42 TXPWR_LMT_ETSI, 43 TXPWR_LMT_WW, 44 TXPWR_LMT_MAX_REGULATION_NUM, 45 }; 46 47 /*------------------------------Define structure----------------------------*/ 48 struct bb_register_def { 49 u32 rfintfs; /* set software control: */ 50 /* 0x870~0x877[8 bytes] */ 51 52 u32 rfintfo; /* output data: */ 53 /* 0x860~0x86f [16 bytes] */ 54 55 u32 rfintfe; /* output enable: */ 56 /* 0x860~0x86f [16 bytes] */ 57 58 u32 rf3wireOffset; /* LSSI data: */ 59 /* 0x840~0x84f [16 bytes] */ 60 61 u32 rfHSSIPara2; /* wire parameter control2 : */ 62 /* 0x824~0x827, 0x82c~0x82f, 63 * 0x834~0x837, 0x83c~0x83f 64 */ 65 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 66 /* 0x8a0~0x8af [16 bytes] */ 67 68 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 69 * 0x8b8-8bc for Path A and B */ 70 71 }; 72 73 u8 74 PHY_GetTxPowerByRateBase( 75 struct adapter *Adapter, 76 u8 RfPath, 77 u8 TxNum, 78 enum rate_section RateSection 79 ); 80 81 u8 82 PHY_GetRateSectionIndexOfTxPowerByRate( 83 struct adapter *padapter, 84 u32 RegAddr, 85 u32 BitMask 86 ); 87 88 void 89 PHY_GetRateValuesOfTxPowerByRate( 90 struct adapter *padapter, 91 u32 RegAddr, 92 u32 BitMask, 93 u32 Value, 94 u8 *RateIndex, 95 s8 *PwrByRateVal, 96 u8 *RateNum 97 ); 98 99 u8 100 PHY_GetRateIndexOfTxPowerByRate( 101 u8 Rate 102 ); 103 104 void 105 PHY_SetTxPowerIndexByRateSection( 106 struct adapter *padapter, 107 u8 RFPath, 108 u8 Channel, 109 u8 RateSection 110 ); 111 112 s8 113 PHY_GetTxPowerByRate( 114 struct adapter *padapter, 115 u8 RFPath, 116 u8 TxNum, 117 u8 RateIndex 118 ); 119 120 void 121 PHY_SetTxPowerByRate( 122 struct adapter *padapter, 123 u8 RFPath, 124 u8 TxNum, 125 u8 Rate, 126 s8 Value 127 ); 128 129 void 130 PHY_SetTxPowerLevelByPath( 131 struct adapter *Adapter, 132 u8 channel, 133 u8 path 134 ); 135 136 void 137 PHY_SetTxPowerIndexByRateArray( 138 struct adapter *padapter, 139 u8 RFPath, 140 enum channel_width BandWidth, 141 u8 Channel, 142 u8 *Rates, 143 u8 RateArraySize 144 ); 145 146 void 147 PHY_InitTxPowerByRate( 148 struct adapter *padapter 149 ); 150 151 void 152 PHY_StoreTxPowerByRate( 153 struct adapter *padapter, 154 u32 RfPath, 155 u32 TxNum, 156 u32 RegAddr, 157 u32 BitMask, 158 u32 Data 159 ); 160 161 void 162 PHY_TxPowerByRateConfiguration( 163 struct adapter *padapter 164 ); 165 166 u8 167 PHY_GetTxPowerIndexBase( 168 struct adapter *padapter, 169 u8 RFPath, 170 u8 Rate, 171 enum channel_width BandWidth, 172 u8 Channel 173 ); 174 175 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 RegPwrTblSel, 176 enum channel_width Bandwidth, 177 u8 RfPath, 178 u8 DataRate, 179 u8 Channel 180 ); 181 182 void 183 PHY_SetTxPowerLimit( 184 struct adapter *Adapter, 185 u8 *Regulation, 186 u8 *Bandwidth, 187 u8 *RateSection, 188 u8 *RfPath, 189 u8 *Channel, 190 u8 *PowerLimit 191 ); 192 193 void 194 PHY_ConvertTxPowerLimitToPowerIndex( 195 struct adapter *Adapter 196 ); 197 198 void 199 PHY_InitTxPowerLimit( 200 struct adapter *Adapter 201 ); 202 203 s8 204 PHY_GetTxPowerTrackingOffset( 205 struct adapter *padapter, 206 u8 Rate, 207 u8 RFPath 208 ); 209 210 void 211 Hal_ChannelPlanToRegulation( 212 struct adapter *Adapter, 213 u16 ChannelPlan 214 ); 215 216 #endif /* __HAL_COMMON_H__ */ 217