1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 /***************************************************************************** 16 * 17 * Module: __INC_HAL8192CPHYREG_H 18 * 19 * 20 * Note: 1. Define PMAC/BB register map 21 * 2. Define RF register map 22 * 3. PMAC/BB register bit mask. 23 * 4. RF reg bit mask. 24 * 5. Other BB/RF relative definition. 25 * 26 * 27 * Export: Constants, macro, functions(API), global variables(None). 28 * 29 * Abbrev: 30 * 31 * History: 32 * Data Who Remark 33 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h. 34 * 2. Reorganize code architecture. 35 *09/25/2008 MH 1. Add RL6052 register definition 36 * 37 *****************************************************************************/ 38 #ifndef __INC_HAL8192CPHYREG_H 39 #define __INC_HAL8192CPHYREG_H 40 41 42 /*--------------------------Define Parameters-------------------------------*/ 43 44 /* */ 45 /* 8192S Regsiter offset definition */ 46 /* */ 47 48 /* */ 49 /* BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF */ 50 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 51 /* 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00 */ 52 /* 3. RF register 0x00-2E */ 53 /* 4. Bit Mask for BB/RF register */ 54 /* 5. Other defintion for BB/RF R/W */ 55 /* */ 56 57 58 /* */ 59 /* 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF */ 60 /* 1. Page1(0x100) */ 61 /* */ 62 #define rPMAC_Reset 0x100 63 #define rPMAC_TxStart 0x104 64 #define rPMAC_TxLegacySIG 0x108 65 #define rPMAC_TxHTSIG1 0x10c 66 #define rPMAC_TxHTSIG2 0x110 67 #define rPMAC_PHYDebug 0x114 68 #define rPMAC_TxPacketNum 0x118 69 #define rPMAC_TxIdle 0x11c 70 #define rPMAC_TxMACHeader0 0x120 71 #define rPMAC_TxMACHeader1 0x124 72 #define rPMAC_TxMACHeader2 0x128 73 #define rPMAC_TxMACHeader3 0x12c 74 #define rPMAC_TxMACHeader4 0x130 75 #define rPMAC_TxMACHeader5 0x134 76 #define rPMAC_TxDataType 0x138 77 #define rPMAC_TxRandomSeed 0x13c 78 #define rPMAC_CCKPLCPPreamble 0x140 79 #define rPMAC_CCKPLCPHeader 0x144 80 #define rPMAC_CCKCRC16 0x148 81 #define rPMAC_OFDMRxCRC32OK 0x170 82 #define rPMAC_OFDMRxCRC32Er 0x174 83 #define rPMAC_OFDMRxParityEr 0x178 84 #define rPMAC_OFDMRxCRC8Er 0x17c 85 #define rPMAC_CCKCRxRC16Er 0x180 86 #define rPMAC_CCKCRxRC32Er 0x184 87 #define rPMAC_CCKCRxRC32OK 0x188 88 #define rPMAC_TxStatus 0x18c 89 90 /* */ 91 /* 2. Page2(0x200) */ 92 /* */ 93 /* The following two definition are only used for USB interface. */ 94 #define RF_BB_CMD_ADDR 0x02c0 /* RF/BB read/write command address. */ 95 #define RF_BB_CMD_DATA 0x02c4 /* RF/BB read/write command data. */ 96 97 /* */ 98 /* 3. Page8(0x800) */ 99 /* */ 100 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ 101 102 #define rFPGA0_TxInfo 0x804 /* Status report?? */ 103 #define rFPGA0_PSDFunction 0x808 104 105 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ 106 107 #define rFPGA0_RFTiming1 0x810 /* Useless now */ 108 #define rFPGA0_RFTiming2 0x814 109 110 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */ 111 #define rFPGA0_XA_HSSIParameter2 0x824 112 #define rFPGA0_XB_HSSIParameter1 0x828 113 #define rFPGA0_XB_HSSIParameter2 0x82c 114 #define rTxAGC_B_Rate18_06 0x830 115 #define rTxAGC_B_Rate54_24 0x834 116 #define rTxAGC_B_CCK1_55_Mcs32 0x838 117 #define rTxAGC_B_Mcs03_Mcs00 0x83c 118 119 #define rTxAGC_B_Mcs07_Mcs04 0x848 120 #define rTxAGC_B_Mcs11_Mcs08 0x84c 121 122 #define rFPGA0_XA_LSSIParameter 0x840 123 #define rFPGA0_XB_LSSIParameter 0x844 124 125 #define rFPGA0_RFWakeUpParameter 0x850 /* Useless now */ 126 #define rFPGA0_RFSleepUpParameter 0x854 127 128 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */ 129 #define rFPGA0_XCD_SwitchControl 0x85c 130 131 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */ 132 #define rFPGA0_XB_RFInterfaceOE 0x864 133 134 #define rTxAGC_B_Mcs15_Mcs12 0x868 135 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c 136 137 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */ 138 #define rFPGA0_XCD_RFInterfaceSW 0x874 139 140 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */ 141 #define rFPGA0_XCD_RFParameter 0x87c 142 143 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */ 144 #define rFPGA0_AnalogParameter2 0x884 145 #define rFPGA0_AnalogParameter3 0x888 /* Useless now */ 146 #define rFPGA0_AnalogParameter4 0x88c 147 148 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */ 149 #define rFPGA0_XB_LSSIReadBack 0x8a4 150 #define rFPGA0_XC_LSSIReadBack 0x8a8 151 #define rFPGA0_XD_LSSIReadBack 0x8ac 152 153 #define rFPGA0_PSDReport 0x8b4 /* Useless now */ 154 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */ 155 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */ 156 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now RF Interface Readback Value */ 157 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */ 158 159 /* */ 160 /* 4. Page9(0x900) */ 161 /* */ 162 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC RF BW Setting?? */ 163 164 #define rFPGA1_TxBlock 0x904 /* Useless now */ 165 #define rFPGA1_DebugSelect 0x908 /* Useless now */ 166 #define rFPGA1_TxInfo 0x90c /* Useless now Status report?? */ 167 #define rS0S1_PathSwitch 0x948 168 169 /* */ 170 /* 5. PageA(0xA00) */ 171 /* */ 172 /* Set Control channel to upper or lower. These settings are required only for 40MHz */ 173 #define rCCK0_System 0xa00 174 175 #define rCCK0_AFESetting 0xa04 /* Disable init gain now Select RX path by RSSI */ 176 #define rCCK0_CCA 0xa08 /* Disable init gain now Init gain */ 177 178 #define rCCK0_RxAGC1 0xa0c /* AGC default value, saturation level Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series */ 179 #define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */ 180 181 #define rCCK0_RxHP 0xa14 182 183 #define rCCK0_DSPParameter1 0xa18 /* Timing recovery & Channel estimation threshold */ 184 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */ 185 186 #define rCCK0_TxFilter1 0xa20 187 #define rCCK0_TxFilter2 0xa24 188 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */ 189 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */ 190 #define rCCK0_TRSSIReport 0xa50 191 #define rCCK0_RxReport 0xa54 /* 0xa57 */ 192 #define rCCK0_FACounterLower 0xa5c /* 0xa5b */ 193 #define rCCK0_FACounterUpper 0xa58 /* 0xa5c */ 194 /* */ 195 /* PageB(0xB00) */ 196 /* */ 197 #define rPdp_AntA 0xb00 198 #define rPdp_AntA_4 0xb04 199 #define rConfig_Pmpd_AntA 0xb28 200 #define rConfig_AntA 0xb68 201 #define rConfig_AntB 0xb6c 202 #define rPdp_AntB 0xb70 203 #define rPdp_AntB_4 0xb74 204 #define rConfig_Pmpd_AntB 0xb98 205 #define rAPK 0xbd8 206 207 /* */ 208 /* 6. PageC(0xC00) */ 209 /* */ 210 #define rOFDM0_LSTF 0xc00 211 212 #define rOFDM0_TRxPathEnable 0xc04 213 #define rOFDM0_TRMuxPar 0xc08 214 #define rOFDM0_TRSWIsolation 0xc0c 215 216 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */ 217 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */ 218 #define rOFDM0_XBRxAFE 0xc18 219 #define rOFDM0_XBRxIQImbalance 0xc1c 220 #define rOFDM0_XCRxAFE 0xc20 221 #define rOFDM0_XCRxIQImbalance 0xc24 222 #define rOFDM0_XDRxAFE 0xc28 223 #define rOFDM0_XDRxIQImbalance 0xc2c 224 225 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD DM tune init gain */ 226 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */ 227 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */ 228 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */ 229 230 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */ 231 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */ 232 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */ 233 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */ 234 235 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */ 236 #define rOFDM0_XAAGCCore2 0xc54 237 #define rOFDM0_XBAGCCore1 0xc58 238 #define rOFDM0_XBAGCCore2 0xc5c 239 #define rOFDM0_XCAGCCore1 0xc60 240 #define rOFDM0_XCAGCCore2 0xc64 241 #define rOFDM0_XDAGCCore1 0xc68 242 #define rOFDM0_XDAGCCore2 0xc6c 243 244 #define rOFDM0_AGCParameter1 0xc70 245 #define rOFDM0_AGCParameter2 0xc74 246 #define rOFDM0_AGCRSSITable 0xc78 247 #define rOFDM0_HTSTFAGC 0xc7c 248 249 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */ 250 #define rOFDM0_XATxAFE 0xc84 251 #define rOFDM0_XBTxIQImbalance 0xc88 252 #define rOFDM0_XBTxAFE 0xc8c 253 #define rOFDM0_XCTxIQImbalance 0xc90 254 #define rOFDM0_XCTxAFE 0xc94 255 #define rOFDM0_XDTxIQImbalance 0xc98 256 #define rOFDM0_XDTxAFE 0xc9c 257 258 #define rOFDM0_RxIQExtAnta 0xca0 259 #define rOFDM0_TxCoeff1 0xca4 260 #define rOFDM0_TxCoeff2 0xca8 261 #define rOFDM0_TxCoeff3 0xcac 262 #define rOFDM0_TxCoeff4 0xcb0 263 #define rOFDM0_TxCoeff5 0xcb4 264 #define rOFDM0_TxCoeff6 0xcb8 265 #define rOFDM0_RxHPParameter 0xce0 266 #define rOFDM0_TxPseudoNoiseWgt 0xce4 267 #define rOFDM0_FrameSync 0xcf0 268 #define rOFDM0_DFSReport 0xcf4 269 270 /* */ 271 /* 7. PageD(0xD00) */ 272 /* */ 273 #define rOFDM1_LSTF 0xd00 274 #define rOFDM1_TRxPathEnable 0xd04 275 276 #define rOFDM1_CFO 0xd08 /* No setting now */ 277 #define rOFDM1_CSI1 0xd10 278 #define rOFDM1_SBD 0xd14 279 #define rOFDM1_CSI2 0xd18 280 #define rOFDM1_CFOTracking 0xd2c 281 #define rOFDM1_TRxMesaure1 0xd34 282 #define rOFDM1_IntfDet 0xd3c 283 #define rOFDM1_PseudoNoiseStateAB 0xd50 284 #define rOFDM1_PseudoNoiseStateCD 0xd54 285 #define rOFDM1_RxPseudoNoiseWgt 0xd58 286 287 #define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */ 288 #define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */ 289 #define rOFDM_PHYCounter3 0xda8 /* MCS not support */ 290 291 #define rOFDM_ShortCFOAB 0xdac /* No setting now */ 292 #define rOFDM_ShortCFOCD 0xdb0 293 #define rOFDM_LongCFOAB 0xdb4 294 #define rOFDM_LongCFOCD 0xdb8 295 #define rOFDM_TailCFOAB 0xdbc 296 #define rOFDM_TailCFOCD 0xdc0 297 #define rOFDM_PWMeasure1 0xdc4 298 #define rOFDM_PWMeasure2 0xdc8 299 #define rOFDM_BWReport 0xdcc 300 #define rOFDM_AGCReport 0xdd0 301 #define rOFDM_RxSNR 0xdd4 302 #define rOFDM_RxEVMCSI 0xdd8 303 #define rOFDM_SIGReport 0xddc 304 305 306 /* */ 307 /* 8. PageE(0xE00) */ 308 /* */ 309 #define rTxAGC_A_Rate18_06 0xe00 310 #define rTxAGC_A_Rate54_24 0xe04 311 #define rTxAGC_A_CCK1_Mcs32 0xe08 312 #define rTxAGC_A_Mcs03_Mcs00 0xe10 313 #define rTxAGC_A_Mcs07_Mcs04 0xe14 314 #define rTxAGC_A_Mcs11_Mcs08 0xe18 315 #define rTxAGC_A_Mcs15_Mcs12 0xe1c 316 317 #define rFPGA0_IQK 0xe28 318 #define rTx_IQK_Tone_A 0xe30 319 #define rRx_IQK_Tone_A 0xe34 320 #define rTx_IQK_PI_A 0xe38 321 #define rRx_IQK_PI_A 0xe3c 322 323 #define rTx_IQK 0xe40 324 #define rRx_IQK 0xe44 325 #define rIQK_AGC_Pts 0xe48 326 #define rIQK_AGC_Rsp 0xe4c 327 #define rTx_IQK_Tone_B 0xe50 328 #define rRx_IQK_Tone_B 0xe54 329 #define rTx_IQK_PI_B 0xe58 330 #define rRx_IQK_PI_B 0xe5c 331 #define rIQK_AGC_Cont 0xe60 332 333 #define rBlue_Tooth 0xe6c 334 #define rRx_Wait_CCA 0xe70 335 #define rTx_CCK_RFON 0xe74 336 #define rTx_CCK_BBON 0xe78 337 #define rTx_OFDM_RFON 0xe7c 338 #define rTx_OFDM_BBON 0xe80 339 #define rTx_To_Rx 0xe84 340 #define rTx_To_Tx 0xe88 341 #define rRx_CCK 0xe8c 342 343 #define rTx_Power_Before_IQK_A 0xe94 344 #define rTx_Power_After_IQK_A 0xe9c 345 346 #define rRx_Power_Before_IQK_A 0xea0 347 #define rRx_Power_Before_IQK_A_2 0xea4 348 #define rRx_Power_After_IQK_A 0xea8 349 #define rRx_Power_After_IQK_A_2 0xeac 350 351 #define rTx_Power_Before_IQK_B 0xeb4 352 #define rTx_Power_After_IQK_B 0xebc 353 354 #define rRx_Power_Before_IQK_B 0xec0 355 #define rRx_Power_Before_IQK_B_2 0xec4 356 #define rRx_Power_After_IQK_B 0xec8 357 #define rRx_Power_After_IQK_B_2 0xecc 358 359 #define rRx_OFDM 0xed0 360 #define rRx_Wait_RIFS 0xed4 361 #define rRx_TO_Rx 0xed8 362 #define rStandby 0xedc 363 #define rSleep 0xee0 364 #define rPMPD_ANAEN 0xeec 365 366 /* */ 367 /* 7. RF Register 0x00-0x2E (RF 8256) */ 368 /* RF-0222D 0x00-3F */ 369 /* */ 370 /* Zebra1 */ 371 #define rZebra1_HSSIEnable 0x0 /* Useless now */ 372 #define rZebra1_TRxEnable1 0x1 373 #define rZebra1_TRxEnable2 0x2 374 #define rZebra1_AGC 0x4 375 #define rZebra1_ChargePump 0x5 376 #define rZebra1_Channel 0x7 /* RF channel switch */ 377 378 /* endif */ 379 #define rZebra1_TxGain 0x8 /* Useless now */ 380 #define rZebra1_TxLPF 0x9 381 #define rZebra1_RxLPF 0xb 382 #define rZebra1_RxHPFCorner 0xc 383 384 /* Zebra4 */ 385 #define rGlobalCtrl 0 /* Useless now */ 386 #define rRTL8256_TxLPF 19 387 #define rRTL8256_RxLPF 11 388 389 /* RTL8258 */ 390 #define rRTL8258_TxLPF 0x11 /* Useless now */ 391 #define rRTL8258_RxLPF 0x13 392 #define rRTL8258_RSSILPF 0xa 393 394 /* */ 395 /* RL6052 Register definition */ 396 /* */ 397 #define RF_AC 0x00 /* */ 398 399 #define RF_IQADJ_G1 0x01 /* */ 400 #define RF_IQADJ_G2 0x02 /* */ 401 #define RF_BS_PA_APSET_G1_G4 0x03 402 #define RF_BS_PA_APSET_G5_G8 0x04 403 #define RF_POW_TRSW 0x05 /* */ 404 405 #define RF_GAIN_RX 0x06 /* */ 406 #define RF_GAIN_TX 0x07 /* */ 407 408 #define RF_TXM_IDAC 0x08 /* */ 409 #define RF_IPA_G 0x09 /* */ 410 #define RF_TXBIAS_G 0x0A 411 #define RF_TXPA_AG 0x0B 412 #define RF_IPA_A 0x0C /* */ 413 #define RF_TXBIAS_A 0x0D 414 #define RF_BS_PA_APSET_G9_G11 0x0E 415 #define RF_BS_IQGEN 0x0F /* */ 416 417 #define RF_MODE1 0x10 /* */ 418 #define RF_MODE2 0x11 /* */ 419 420 #define RF_RX_AGC_HP 0x12 /* */ 421 #define RF_TX_AGC 0x13 /* */ 422 #define RF_BIAS 0x14 /* */ 423 #define RF_IPA 0x15 /* */ 424 #define RF_TXBIAS 0x16 /* */ 425 #define RF_POW_ABILITY 0x17 /* */ 426 #define RF_MODE_AG 0x18 /* */ 427 #define rRfChannel 0x18 /* RF channel and BW switch */ 428 #define RF_CHNLBW 0x18 /* RF channel and BW switch */ 429 #define RF_TOP 0x19 /* */ 430 431 #define RF_RX_G1 0x1A /* */ 432 #define RF_RX_G2 0x1B /* */ 433 434 #define RF_RX_BB2 0x1C /* */ 435 #define RF_RX_BB1 0x1D /* */ 436 437 #define RF_RCK1 0x1E /* */ 438 #define RF_RCK2 0x1F /* */ 439 440 #define RF_TX_G1 0x20 /* */ 441 #define RF_TX_G2 0x21 /* */ 442 #define RF_TX_G3 0x22 /* */ 443 444 #define RF_TX_BB1 0x23 /* */ 445 446 #define RF_T_METER 0x24 /* */ 447 448 #define RF_SYN_G1 0x25 /* RF TX Power control */ 449 #define RF_SYN_G2 0x26 /* RF TX Power control */ 450 #define RF_SYN_G3 0x27 /* RF TX Power control */ 451 #define RF_SYN_G4 0x28 /* RF TX Power control */ 452 #define RF_SYN_G5 0x29 /* RF TX Power control */ 453 #define RF_SYN_G6 0x2A /* RF TX Power control */ 454 #define RF_SYN_G7 0x2B /* RF TX Power control */ 455 #define RF_SYN_G8 0x2C /* RF TX Power control */ 456 457 #define RF_RCK_OS 0x30 /* RF TX PA control */ 458 459 #define RF_TXPA_G1 0x31 /* RF TX PA control */ 460 #define RF_TXPA_G2 0x32 /* RF TX PA control */ 461 #define RF_TXPA_G3 0x33 /* RF TX PA control */ 462 #define RF_TX_BIAS_A 0x35 463 #define RF_TX_BIAS_D 0x36 464 #define RF_LOBF_9 0x38 465 #define RF_RXRF_A3 0x3C /* */ 466 #define RF_TRSW 0x3F 467 468 #define RF_TXRF_A2 0x41 469 #define RF_TXPA_G4 0x46 470 #define RF_TXPA_A4 0x4B 471 #define RF_0x52 0x52 472 #define RF_WE_LUT 0xEF 473 #define RF_S0S1 0xB0 474 475 /* */ 476 /* Bit Mask */ 477 /* */ 478 /* 1. Page1(0x100) */ 479 #define bBBResetB 0x100 /* Useless now? */ 480 #define bGlobalResetB 0x200 481 #define bOFDMTxStart 0x4 482 #define bCCKTxStart 0x8 483 #define bCRC32Debug 0x100 484 #define bPMACLoopback 0x10 485 #define bTxLSIG 0xffffff 486 #define bOFDMTxRate 0xf 487 #define bOFDMTxReserved 0x10 488 #define bOFDMTxLength 0x1ffe0 489 #define bOFDMTxParity 0x20000 490 #define bTxHTSIG1 0xffffff 491 #define bTxHTMCSRate 0x7f 492 #define bTxHTBW 0x80 493 #define bTxHTLength 0xffff00 494 #define bTxHTSIG2 0xffffff 495 #define bTxHTSmoothing 0x1 496 #define bTxHTSounding 0x2 497 #define bTxHTReserved 0x4 498 #define bTxHTAggreation 0x8 499 #define bTxHTSTBC 0x30 500 #define bTxHTAdvanceCoding 0x40 501 #define bTxHTShortGI 0x80 502 #define bTxHTNumberHT_LTF 0x300 503 #define bTxHTCRC8 0x3fc00 504 #define bCounterReset 0x10000 505 #define bNumOfOFDMTx 0xffff 506 #define bNumOfCCKTx 0xffff0000 507 #define bTxIdleInterval 0xffff 508 #define bOFDMService 0xffff0000 509 #define bTxMACHeader 0xffffffff 510 #define bTxDataInit 0xff 511 #define bTxHTMode 0x100 512 #define bTxDataType 0x30000 513 #define bTxRandomSeed 0xffffffff 514 #define bCCKTxPreamble 0x1 515 #define bCCKTxSFD 0xffff0000 516 #define bCCKTxSIG 0xff 517 #define bCCKTxService 0xff00 518 #define bCCKLengthExt 0x8000 519 #define bCCKTxLength 0xffff0000 520 #define bCCKTxCRC16 0xffff 521 #define bCCKTxStatus 0x1 522 #define bOFDMTxStatus 0x2 523 524 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff)) 525 526 /* 2. Page8(0x800) */ 527 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */ 528 #define bJapanMode 0x2 529 #define bCCKTxSC 0x30 530 #define bCCKEn 0x1000000 531 #define bOFDMEn 0x2000000 532 533 #define bOFDMRxADCPhase 0x10000 /* Useless now */ 534 #define bOFDMTxDACPhase 0x40000 535 #define bXATxAGC 0x3f 536 537 #define bAntennaSelect 0x0300 538 539 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */ 540 #define bXCTxAGC 0xf000 541 #define bXDTxAGC 0xf0000 542 543 #define bPAStart 0xf0000000 /* Useless now */ 544 #define bTRStart 0x00f00000 545 #define bRFStart 0x0000f000 546 #define bBBStart 0x000000f0 547 #define bBBCCKStart 0x0000000f 548 #define bPAEnd 0xf /* Reg0x814 */ 549 #define bTREnd 0x0f000000 550 #define bRFEnd 0x000f0000 551 #define bCCAMask 0x000000f0 /* T2R */ 552 #define bR2RCCAMask 0x00000f00 553 #define bHSSI_R2TDelay 0xf8000000 554 #define bHSSI_T2RDelay 0xf80000 555 #define bContTxHSSI 0x400 /* chane gain at continue Tx */ 556 #define bIGFromCCK 0x200 557 #define bAGCAddress 0x3f 558 #define bRxHPTx 0x7000 559 #define bRxHPT2R 0x38000 560 #define bRxHPCCKIni 0xc0000 561 #define bAGCTxCode 0xc00000 562 #define bAGCRxCode 0x300000 563 564 #define b3WireDataLength 0x800 /* Reg 0x820~84f rFPGA0_XA_HSSIParameter1 */ 565 #define b3WireAddressLength 0x400 566 567 #define b3WireRFPowerDown 0x1 /* Useless now */ 568 /* define bHWSISelect 0x8 */ 569 #define b5GPAPEPolarity 0x40000000 570 #define b2GPAPEPolarity 0x80000000 571 #define bRFSW_TxDefaultAnt 0x3 572 #define bRFSW_TxOptionAnt 0x30 573 #define bRFSW_RxDefaultAnt 0x300 574 #define bRFSW_RxOptionAnt 0x3000 575 #define bRFSI_3WireData 0x1 576 #define bRFSI_3WireClock 0x2 577 #define bRFSI_3WireLoad 0x4 578 #define bRFSI_3WireRW 0x8 579 #define bRFSI_3Wire 0xf 580 581 #define bRFSI_RFENV 0x10 /* Reg 0x870 rFPGA0_XAB_RFInterfaceSW */ 582 583 #define bRFSI_TRSW 0x20 /* Useless now */ 584 #define bRFSI_TRSWB 0x40 585 #define bRFSI_ANTSW 0x100 586 #define bRFSI_ANTSWB 0x200 587 #define bRFSI_PAPE 0x400 588 #define bRFSI_PAPE5G 0x800 589 #define bBandSelect 0x1 590 #define bHTSIG2_GI 0x80 591 #define bHTSIG2_Smoothing 0x01 592 #define bHTSIG2_Sounding 0x02 593 #define bHTSIG2_Aggreaton 0x08 594 #define bHTSIG2_STBC 0x30 595 #define bHTSIG2_AdvCoding 0x40 596 #define bHTSIG2_NumOfHTLTF 0x300 597 #define bHTSIG2_CRC8 0x3fc 598 #define bHTSIG1_MCS 0x7f 599 #define bHTSIG1_BandWidth 0x80 600 #define bHTSIG1_HTLength 0xffff 601 #define bLSIG_Rate 0xf 602 #define bLSIG_Reserved 0x10 603 #define bLSIG_Length 0x1fffe 604 #define bLSIG_Parity 0x20 605 #define bCCKRxPhase 0x4 606 607 #define bLSSIReadAddress 0x7f800000 /* T65 RF */ 608 609 #define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */ 610 611 #define bLSSIReadBackData 0xfffff /* T65 RF */ 612 613 #define bLSSIReadOKFlag 0x1000 /* Useless now */ 614 #define bCCKSampleRate 0x8 /* 0: 44MHz, 1:88MHz */ 615 #define bRegulator0Standby 0x1 616 #define bRegulatorPLLStandby 0x2 617 #define bRegulator1Standby 0x4 618 #define bPLLPowerUp 0x8 619 #define bDPLLPowerUp 0x10 620 #define bDA10PowerUp 0x20 621 #define bAD7PowerUp 0x200 622 #define bDA6PowerUp 0x2000 623 #define bXtalPowerUp 0x4000 624 #define b40MDClkPowerUP 0x8000 625 #define bDA6DebugMode 0x20000 626 #define bDA6Swing 0x380000 627 628 #define bADClkPhase 0x4000000 /* Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ */ 629 630 #define b80MClkDelay 0x18000000 /* Useless */ 631 #define bAFEWatchDogEnable 0x20000000 632 633 #define bXtalCap01 0xc0000000 /* Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap */ 634 #define bXtalCap23 0x3 635 #define bXtalCap92x 0x0f000000 636 #define bXtalCap 0x0f000000 637 638 #define bIntDifClkEnable 0x400 /* Useless */ 639 #define bExtSigClkEnable 0x800 640 #define bBandgapMbiasPowerUp 0x10000 641 #define bAD11SHGain 0xc0000 642 #define bAD11InputRange 0x700000 643 #define bAD11OPCurrent 0x3800000 644 #define bIPathLoopback 0x4000000 645 #define bQPathLoopback 0x8000000 646 #define bAFELoopback 0x10000000 647 #define bDA10Swing 0x7e0 648 #define bDA10Reverse 0x800 649 #define bDAClkSource 0x1000 650 #define bAD7InputRange 0x6000 651 #define bAD7Gain 0x38000 652 #define bAD7OutputCMMode 0x40000 653 #define bAD7InputCMMode 0x380000 654 #define bAD7Current 0xc00000 655 #define bRegulatorAdjust 0x7000000 656 #define bAD11PowerUpAtTx 0x1 657 #define bDA10PSAtTx 0x10 658 #define bAD11PowerUpAtRx 0x100 659 #define bDA10PSAtRx 0x1000 660 #define bCCKRxAGCFormat 0x200 661 #define bPSDFFTSamplepPoint 0xc000 662 #define bPSDAverageNum 0x3000 663 #define bIQPathControl 0xc00 664 #define bPSDFreq 0x3ff 665 #define bPSDAntennaPath 0x30 666 #define bPSDIQSwitch 0x40 667 #define bPSDRxTrigger 0x400000 668 #define bPSDTxTrigger 0x80000000 669 #define bPSDSineToneScale 0x7f000000 670 #define bPSDReport 0xffff 671 672 /* 3. Page9(0x900) */ 673 #define bOFDMTxSC 0x30000000 /* Useless */ 674 #define bCCKTxOn 0x1 675 #define bOFDMTxOn 0x2 676 #define bDebugPage 0xfff /* reset debug page and also HWord, LWord */ 677 #define bDebugItem 0xff /* reset debug page and LWord */ 678 #define bAntL 0x10 679 #define bAntNonHT 0x100 680 #define bAntHT1 0x1000 681 #define bAntHT2 0x10000 682 #define bAntHT1S1 0x100000 683 #define bAntNonHTS1 0x1000000 684 685 /* 4. PageA(0xA00) */ 686 #define bCCKBBMode 0x3 /* Useless */ 687 #define bCCKTxPowerSaving 0x80 688 #define bCCKRxPowerSaving 0x40 689 690 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */ 691 692 #define bCCKScramble 0x8 /* Useless */ 693 #define bCCKAntDiversity 0x8000 694 #define bCCKCarrierRecovery 0x4000 695 #define bCCKTxRate 0x3000 696 #define bCCKDCCancel 0x0800 697 #define bCCKISICancel 0x0400 698 #define bCCKMatchFilter 0x0200 699 #define bCCKEqualizer 0x0100 700 #define bCCKPreambleDetect 0x800000 701 #define bCCKFastFalseCCA 0x400000 702 #define bCCKChEstStart 0x300000 703 #define bCCKCCACount 0x080000 704 #define bCCKcs_lim 0x070000 705 #define bCCKBistMode 0x80000000 706 #define bCCKCCAMask 0x40000000 707 #define bCCKTxDACPhase 0x4 708 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */ 709 #define bCCKr_cp_mode0 0x0100 710 #define bCCKTxDCOffset 0xf0 711 #define bCCKRxDCOffset 0xf 712 #define bCCKCCAMode 0xc000 713 #define bCCKFalseCS_lim 0x3f00 714 #define bCCKCS_ratio 0xc00000 715 #define bCCKCorgBit_sel 0x300000 716 #define bCCKPD_lim 0x0f0000 717 #define bCCKNewCCA 0x80000000 718 #define bCCKRxHPofIG 0x8000 719 #define bCCKRxIG 0x7f00 720 #define bCCKLNAPolarity 0x800000 721 #define bCCKRx1stGain 0x7f0000 722 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */ 723 #define bCCKRxAGCSatLevel 0x1f000000 724 #define bCCKRxAGCSatCount 0xe0 725 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */ 726 #define bCCKFixedRxAGC 0x8000 727 #define bCCKAntennaPolarity 0x2000 728 #define bCCKTxFilterType 0x0c00 729 #define bCCKRxAGCReportType 0x0300 730 #define bCCKRxDAGCEn 0x80000000 731 #define bCCKRxDAGCPeriod 0x20000000 732 #define bCCKRxDAGCSatLevel 0x1f000000 733 #define bCCKTimingRecovery 0x800000 734 #define bCCKTxC0 0x3f0000 735 #define bCCKTxC1 0x3f000000 736 #define bCCKTxC2 0x3f 737 #define bCCKTxC3 0x3f00 738 #define bCCKTxC4 0x3f0000 739 #define bCCKTxC5 0x3f000000 740 #define bCCKTxC6 0x3f 741 #define bCCKTxC7 0x3f00 742 #define bCCKDebugPort 0xff0000 743 #define bCCKDACDebug 0x0f000000 744 #define bCCKFalseAlarmEnable 0x8000 745 #define bCCKFalseAlarmRead 0x4000 746 #define bCCKTRSSI 0x7f 747 #define bCCKRxAGCReport 0xfe 748 #define bCCKRxReport_AntSel 0x80000000 749 #define bCCKRxReport_MFOff 0x40000000 750 #define bCCKRxRxReport_SQLoss 0x20000000 751 #define bCCKRxReport_Pktloss 0x10000000 752 #define bCCKRxReport_Lockedbit 0x08000000 753 #define bCCKRxReport_RateError 0x04000000 754 #define bCCKRxReport_RxRate 0x03000000 755 #define bCCKRxFACounterLower 0xff 756 #define bCCKRxFACounterUpper 0xff000000 757 #define bCCKRxHPAGCStart 0xe000 758 #define bCCKRxHPAGCFinal 0x1c00 759 #define bCCKRxFalseAlarmEnable 0x8000 760 #define bCCKFACounterFreeze 0x4000 761 #define bCCKTxPathSel 0x10000000 762 #define bCCKDefaultRxPath 0xc000000 763 #define bCCKOptionRxPath 0x3000000 764 765 /* 5. PageC(0xC00) */ 766 #define bNumOfSTF 0x3 /* Useless */ 767 #define bShift_L 0xc0 768 #define bGI_TH 0xc 769 #define bRxPathA 0x1 770 #define bRxPathB 0x2 771 #define bRxPathC 0x4 772 #define bRxPathD 0x8 773 #define bTxPathA 0x1 774 #define bTxPathB 0x2 775 #define bTxPathC 0x4 776 #define bTxPathD 0x8 777 #define bTRSSIFreq 0x200 778 #define bADCBackoff 0x3000 779 #define bDFIRBackoff 0xc000 780 #define bTRSSILatchPhase 0x10000 781 #define bRxIDCOffset 0xff 782 #define bRxQDCOffset 0xff00 783 #define bRxDFIRMode 0x1800000 784 #define bRxDCNFType 0xe000000 785 #define bRXIQImb_A 0x3ff 786 #define bRXIQImb_B 0xfc00 787 #define bRXIQImb_C 0x3f0000 788 #define bRXIQImb_D 0xffc00000 789 #define bDC_dc_Notch 0x60000 790 #define bRxNBINotch 0x1f000000 791 #define bPD_TH 0xf 792 #define bPD_TH_Opt2 0xc000 793 #define bPWED_TH 0x700 794 #define bIfMF_Win_L 0x800 795 #define bPD_Option 0x1000 796 #define bMF_Win_L 0xe000 797 #define bBW_Search_L 0x30000 798 #define bwin_enh_L 0xc0000 799 #define bBW_TH 0x700000 800 #define bED_TH2 0x3800000 801 #define bBW_option 0x4000000 802 #define bRatio_TH 0x18000000 803 #define bWindow_L 0xe0000000 804 #define bSBD_Option 0x1 805 #define bFrame_TH 0x1c 806 #define bFS_Option 0x60 807 #define bDC_Slope_check 0x80 808 #define bFGuard_Counter_DC_L 0xe00 809 #define bFrame_Weight_Short 0x7000 810 #define bSub_Tune 0xe00000 811 #define bFrame_DC_Length 0xe000000 812 #define bSBD_start_offset 0x30000000 813 #define bFrame_TH_2 0x7 814 #define bFrame_GI2_TH 0x38 815 #define bGI2_Sync_en 0x40 816 #define bSarch_Short_Early 0x300 817 #define bSarch_Short_Late 0xc00 818 #define bSarch_GI2_Late 0x70000 819 #define bCFOAntSum 0x1 820 #define bCFOAcc 0x2 821 #define bCFOStartOffset 0xc 822 #define bCFOLookBack 0x70 823 #define bCFOSumWeight 0x80 824 #define bDAGCEnable 0x10000 825 #define bTXIQImb_A 0x3ff 826 #define bTXIQImb_B 0xfc00 827 #define bTXIQImb_C 0x3f0000 828 #define bTXIQImb_D 0xffc00000 829 #define bTxIDCOffset 0xff 830 #define bTxQDCOffset 0xff00 831 #define bTxDFIRMode 0x10000 832 #define bTxPesudoNoiseOn 0x4000000 833 #define bTxPesudoNoise_A 0xff 834 #define bTxPesudoNoise_B 0xff00 835 #define bTxPesudoNoise_C 0xff0000 836 #define bTxPesudoNoise_D 0xff000000 837 #define bCCADropOption 0x20000 838 #define bCCADropThres 0xfff00000 839 #define bEDCCA_H 0xf 840 #define bEDCCA_L 0xf0 841 #define bLambda_ED 0x300 842 #define bRxInitialGain 0x7f 843 #define bRxAntDivEn 0x80 844 #define bRxAGCAddressForLNA 0x7f00 845 #define bRxHighPowerFlow 0x8000 846 #define bRxAGCFreezeThres 0xc0000 847 #define bRxFreezeStep_AGC1 0x300000 848 #define bRxFreezeStep_AGC2 0xc00000 849 #define bRxFreezeStep_AGC3 0x3000000 850 #define bRxFreezeStep_AGC0 0xc000000 851 #define bRxRssi_Cmp_En 0x10000000 852 #define bRxQuickAGCEn 0x20000000 853 #define bRxAGCFreezeThresMode 0x40000000 854 #define bRxOverFlowCheckType 0x80000000 855 #define bRxAGCShift 0x7f 856 #define bTRSW_Tri_Only 0x80 857 #define bPowerThres 0x300 858 #define bRxAGCEn 0x1 859 #define bRxAGCTogetherEn 0x2 860 #define bRxAGCMin 0x4 861 #define bRxHP_Ini 0x7 862 #define bRxHP_TRLNA 0x70 863 #define bRxHP_RSSI 0x700 864 #define bRxHP_BBP1 0x7000 865 #define bRxHP_BBP2 0x70000 866 #define bRxHP_BBP3 0x700000 867 #define bRSSI_H 0x7f0000 /* the threshold for high power */ 868 #define bRSSI_Gen 0x7f000000 /* the threshold for ant diversity */ 869 #define bRxSettle_TRSW 0x7 870 #define bRxSettle_LNA 0x38 871 #define bRxSettle_RSSI 0x1c0 872 #define bRxSettle_BBP 0xe00 873 #define bRxSettle_RxHP 0x7000 874 #define bRxSettle_AntSW_RSSI 0x38000 875 #define bRxSettle_AntSW 0xc0000 876 #define bRxProcessTime_DAGC 0x300000 877 #define bRxSettle_HSSI 0x400000 878 #define bRxProcessTime_BBPPW 0x800000 879 #define bRxAntennaPowerShift 0x3000000 880 #define bRSSITableSelect 0xc000000 881 #define bRxHP_Final 0x7000000 882 #define bRxHTSettle_BBP 0x7 883 #define bRxHTSettle_HSSI 0x8 884 #define bRxHTSettle_RxHP 0x70 885 #define bRxHTSettle_BBPPW 0x80 886 #define bRxHTSettle_Idle 0x300 887 #define bRxHTSettle_Reserved 0x1c00 888 #define bRxHTRxHPEn 0x8000 889 #define bRxHTAGCFreezeThres 0x30000 890 #define bRxHTAGCTogetherEn 0x40000 891 #define bRxHTAGCMin 0x80000 892 #define bRxHTAGCEn 0x100000 893 #define bRxHTDAGCEn 0x200000 894 #define bRxHTRxHP_BBP 0x1c00000 895 #define bRxHTRxHP_Final 0xe0000000 896 #define bRxPWRatioTH 0x3 897 #define bRxPWRatioEn 0x4 898 #define bRxMFHold 0x3800 899 #define bRxPD_Delay_TH1 0x38 900 #define bRxPD_Delay_TH2 0x1c0 901 #define bRxPD_DC_COUNT_MAX 0x600 902 /* define bRxMF_Hold 0x3800 */ 903 #define bRxPD_Delay_TH 0x8000 904 #define bRxProcess_Delay 0xf0000 905 #define bRxSearchrange_GI2_Early 0x700000 906 #define bRxFrame_Guard_Counter_L 0x3800000 907 #define bRxSGI_Guard_L 0xc000000 908 #define bRxSGI_Search_L 0x30000000 909 #define bRxSGI_TH 0xc0000000 910 #define bDFSCnt0 0xff 911 #define bDFSCnt1 0xff00 912 #define bDFSFlag 0xf0000 913 #define bMFWeightSum 0x300000 914 #define bMinIdxTH 0x7f000000 915 #define bDAFormat 0x40000 916 #define bTxChEmuEnable 0x01000000 917 #define bTRSWIsolation_A 0x7f 918 #define bTRSWIsolation_B 0x7f00 919 #define bTRSWIsolation_C 0x7f0000 920 #define bTRSWIsolation_D 0x7f000000 921 #define bExtLNAGain 0x7c00 922 923 /* 6. PageE(0xE00) */ 924 #define bSTBCEn 0x4 /* Useless */ 925 #define bAntennaMapping 0x10 926 #define bNss 0x20 927 #define bCFOAntSumD 0x200 928 #define bPHYCounterReset 0x8000000 929 #define bCFOReportGet 0x4000000 930 #define bOFDMContinueTx 0x10000000 931 #define bOFDMSingleCarrier 0x20000000 932 #define bOFDMSingleTone 0x40000000 933 /* define bRxPath1 0x01 */ 934 /* define bRxPath2 0x02 */ 935 /* define bRxPath3 0x04 */ 936 /* define bRxPath4 0x08 */ 937 /* define bTxPath1 0x10 */ 938 /* define bTxPath2 0x20 */ 939 #define bHTDetect 0x100 940 #define bCFOEn 0x10000 941 #define bCFOValue 0xfff00000 942 #define bSigTone_Re 0x3f 943 #define bSigTone_Im 0x7f00 944 #define bCounter_CCA 0xffff 945 #define bCounter_ParityFail 0xffff0000 946 #define bCounter_RateIllegal 0xffff 947 #define bCounter_CRC8Fail 0xffff0000 948 #define bCounter_MCSNoSupport 0xffff 949 #define bCounter_FastSync 0xffff 950 #define bShortCFO 0xfff 951 #define bShortCFOTLength 12 /* total */ 952 #define bShortCFOFLength 11 /* fraction */ 953 #define bLongCFO 0x7ff 954 #define bLongCFOTLength 11 955 #define bLongCFOFLength 11 956 #define bTailCFO 0x1fff 957 #define bTailCFOTLength 13 958 #define bTailCFOFLength 12 959 #define bmax_en_pwdB 0xffff 960 #define bCC_power_dB 0xffff0000 961 #define bnoise_pwdB 0xffff 962 #define bPowerMeasTLength 10 963 #define bPowerMeasFLength 3 964 #define bRx_HT_BW 0x1 965 #define bRxSC 0x6 966 #define bRx_HT 0x8 967 #define bNB_intf_det_on 0x1 968 #define bIntf_win_len_cfg 0x30 969 #define bNB_Intf_TH_cfg 0x1c0 970 #define bRFGain 0x3f 971 #define bTableSel 0x40 972 #define bTRSW 0x80 973 #define bRxSNR_A 0xff 974 #define bRxSNR_B 0xff00 975 #define bRxSNR_C 0xff0000 976 #define bRxSNR_D 0xff000000 977 #define bSNREVMTLength 8 978 #define bSNREVMFLength 1 979 #define bCSI1st 0xff 980 #define bCSI2nd 0xff00 981 #define bRxEVM1st 0xff0000 982 #define bRxEVM2nd 0xff000000 983 #define bSIGEVM 0xff 984 #define bPWDB 0xff00 985 #define bSGIEN 0x10000 986 987 #define bSFactorQAM1 0xf /* Useless */ 988 #define bSFactorQAM2 0xf0 989 #define bSFactorQAM3 0xf00 990 #define bSFactorQAM4 0xf000 991 #define bSFactorQAM5 0xf0000 992 #define bSFactorQAM6 0xf0000 993 #define bSFactorQAM7 0xf00000 994 #define bSFactorQAM8 0xf000000 995 #define bSFactorQAM9 0xf0000000 996 #define bCSIScheme 0x100000 997 998 #define bNoiseLvlTopSet 0x3 /* Useless */ 999 #define bChSmooth 0x4 1000 #define bChSmoothCfg1 0x38 1001 #define bChSmoothCfg2 0x1c0 1002 #define bChSmoothCfg3 0xe00 1003 #define bChSmoothCfg4 0x7000 1004 #define bMRCMode 0x800000 1005 #define bTHEVMCfg 0x7000000 1006 1007 #define bLoopFitType 0x1 /* Useless */ 1008 #define bUpdCFO 0x40 1009 #define bUpdCFOOffData 0x80 1010 #define bAdvUpdCFO 0x100 1011 #define bAdvTimeCtrl 0x800 1012 #define bUpdClko 0x1000 1013 #define bFC 0x6000 1014 #define bTrackingMode 0x8000 1015 #define bPhCmpEnable 0x10000 1016 #define bUpdClkoLTF 0x20000 1017 #define bComChCFO 0x40000 1018 #define bCSIEstiMode 0x80000 1019 #define bAdvUpdEqz 0x100000 1020 #define bUChCfg 0x7000000 1021 #define bUpdEqz 0x8000000 1022 1023 /* Rx Pseduo noise */ 1024 #define bRxPesudoNoiseOn 0x20000000 /* Useless */ 1025 #define bRxPesudoNoise_A 0xff 1026 #define bRxPesudoNoise_B 0xff00 1027 #define bRxPesudoNoise_C 0xff0000 1028 #define bRxPesudoNoise_D 0xff000000 1029 #define bPesudoNoiseState_A 0xffff 1030 #define bPesudoNoiseState_B 0xffff0000 1031 #define bPesudoNoiseState_C 0xffff 1032 #define bPesudoNoiseState_D 0xffff0000 1033 1034 /* 7. RF Register */ 1035 /* Zebra1 */ 1036 #define bZebra1_HSSIEnable 0x8 /* Useless */ 1037 #define bZebra1_TRxControl 0xc00 1038 #define bZebra1_TRxGainSetting 0x07f 1039 #define bZebra1_RxCorner 0xc00 1040 #define bZebra1_TxChargePump 0x38 1041 #define bZebra1_RxChargePump 0x7 1042 #define bZebra1_ChannelNum 0xf80 1043 #define bZebra1_TxLPFBW 0x400 1044 #define bZebra1_RxLPFBW 0x600 1045 1046 /* Zebra4 */ 1047 #define bRTL8256RegModeCtrl1 0x100 /* Useless */ 1048 #define bRTL8256RegModeCtrl0 0x40 1049 #define bRTL8256_TxLPFBW 0x18 1050 #define bRTL8256_RxLPFBW 0x600 1051 1052 /* RTL8258 */ 1053 #define bRTL8258_TxLPFBW 0xc /* Useless */ 1054 #define bRTL8258_RxLPFBW 0xc00 1055 #define bRTL8258_RSSILPFBW 0xc0 1056 1057 1058 /* */ 1059 /* Other Definition */ 1060 /* */ 1061 1062 /* byte endable for sb_write */ 1063 #define bByte0 0x1 /* Useless */ 1064 #define bByte1 0x2 1065 #define bByte2 0x4 1066 #define bByte3 0x8 1067 #define bWord0 0x3 1068 #define bWord1 0xc 1069 #define bDWord 0xf 1070 1071 /* for PutRegsetting & GetRegSetting BitMask */ 1072 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */ 1073 #define bMaskByte1 0xff00 1074 #define bMaskByte2 0xff0000 1075 #define bMaskByte3 0xff000000 1076 #define bMaskHWord 0xffff0000 1077 #define bMaskLWord 0x0000ffff 1078 #define bMaskDWord 0xffffffff 1079 #define bMaskH3Bytes 0xffffff00 1080 #define bMask12Bits 0xfff 1081 #define bMaskH4Bits 0xf0000000 1082 #define bMaskOFDM_D 0xffc00000 1083 #define bMaskCCK 0x3f3f3f3f 1084 1085 1086 #define bEnable 0x1 /* Useless */ 1087 #define bDisable 0x0 1088 1089 #define LeftAntenna 0x0 /* Useless */ 1090 #define RightAntenna 0x1 1091 1092 #define tCheckTxStatus 500 /* 500ms Useless */ 1093 #define tUpdateRxCounter 100 /* 100ms */ 1094 1095 #define rateCCK 0 /* Useless */ 1096 #define rateOFDM 1 1097 #define rateHT 2 1098 1099 /* define Register-End */ 1100 #define bPMAC_End 0x1ff /* Useless */ 1101 #define bFPGAPHY0_End 0x8ff 1102 #define bFPGAPHY1_End 0x9ff 1103 #define bCCKPHY0_End 0xaff 1104 #define bOFDMPHY0_End 0xcff 1105 #define bOFDMPHY1_End 0xdff 1106 1107 /* define max debug item in each debug page */ 1108 /* define bMaxItem_FPGA_PHY0 0x9 */ 1109 /* define bMaxItem_FPGA_PHY1 0x3 */ 1110 /* define bMaxItem_PHY_11B 0x16 */ 1111 /* define bMaxItem_OFDM_PHY0 0x29 */ 1112 /* define bMaxItem_OFDM_PHY1 0x0 */ 1113 1114 #define bPMACControl 0x0 /* Useless */ 1115 #define bWMACControl 0x1 1116 #define bWNICControl 0x2 1117 1118 #define PathA 0x0 /* Useless */ 1119 #define PathB 0x1 1120 #define PathC 0x2 1121 #define PathD 0x3 1122 1123 /*--------------------------Define Parameters-------------------------------*/ 1124 1125 1126 #endif /* __INC_HAL8192SPHYREG_H */ 1127