1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #define _SDIO_HALINIT_C_ 8 9 #include <drv_types.h> 10 #include <rtw_debug.h> 11 #include <rtl8723b_hal.h> 12 13 #include "hal_com_h2c.h" 14 /* 15 * Description: 16 *Call power on sequence to enable card 17 * 18 * Return: 19 *_SUCCESS enable success 20 *_FAIL enable fail 21 */ 22 static u8 CardEnable(struct adapter *padapter) 23 { 24 u8 bMacPwrCtrlOn; 25 u8 ret = _FAIL; 26 27 28 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 29 if (!bMacPwrCtrlOn) { 30 /* RSV_CTRL 0x1C[7:0] = 0x00 */ 31 /* unlock ISO/CLK/Power control register */ 32 rtw_write8(padapter, REG_RSV_CTRL, 0x0); 33 34 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow); 35 if (ret == _SUCCESS) { 36 u8 bMacPwrCtrlOn = true; 37 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 38 } 39 } else 40 ret = _SUCCESS; 41 42 return ret; 43 } 44 45 static 46 u8 _InitPowerOn_8723BS(struct adapter *padapter) 47 { 48 u8 value8; 49 u16 value16; 50 u32 value32; 51 u8 ret; 52 /* u8 bMacPwrCtrlOn; */ 53 54 55 /* all of these MUST be configured before power on */ 56 57 /* only cmd52 can be used before power on(card enable) */ 58 ret = CardEnable(padapter); 59 if (!ret) 60 return _FAIL; 61 62 /* Radio-Off Pin Trigger */ 63 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1); 64 value8 |= BIT(1); /* Enable falling edge triggering interrupt */ 65 rtw_write8(padapter, REG_GPIO_INTM + 1, value8); 66 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1); 67 value8 |= BIT(1); 68 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8); 69 70 /* Enable power down and GPIO interrupt */ 71 value16 = rtw_read16(padapter, REG_APS_FSMCO); 72 value16 |= EnPDN; /* Enable HW power down and RF on */ 73 rtw_write16(padapter, REG_APS_FSMCO, value16); 74 75 /* Enable CMD53 R/W Operation */ 76 /* bMacPwrCtrlOn = true; */ 77 /* rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */ 78 79 rtw_write8(padapter, REG_CR, 0x00); 80 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 81 value16 = rtw_read16(padapter, REG_CR); 82 value16 |= ( 83 HCI_TXDMA_EN | 84 HCI_RXDMA_EN | 85 TXDMA_EN | 86 RXDMA_EN | 87 PROTOCOL_EN | 88 SCHEDULE_EN | 89 ENSEC | 90 CALTMR_EN 91 ); 92 rtw_write16(padapter, REG_CR, value16); 93 94 hal_btcoex_PowerOnSetting(padapter); 95 96 /* external switch to S1 */ 97 /* 0x38[11] = 0x1 */ 98 /* 0x4c[23] = 0x1 */ 99 /* 0x64[0] = 0 */ 100 value16 = rtw_read16(padapter, REG_PWR_DATA); 101 /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */ 102 value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */ 103 rtw_write16(padapter, REG_PWR_DATA, value16); 104 105 value32 = rtw_read32(padapter, REG_LEDCFG0); 106 value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */ 107 rtw_write32(padapter, REG_LEDCFG0, value32); 108 109 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B); 110 value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */ 111 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8); 112 113 return _SUCCESS; 114 } 115 116 /* Tx Page FIFO threshold */ 117 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ) 118 { 119 u16 HQ_threshold, NQ_threshold, LQ_threshold; 120 121 HQ_threshold = (numPubQ + numHQ + 1) >> 1; 122 HQ_threshold |= (HQ_threshold << 8); 123 124 NQ_threshold = (numPubQ + numNQ + 1) >> 1; 125 NQ_threshold |= (NQ_threshold << 8); 126 127 LQ_threshold = (numPubQ + numLQ + 1) >> 1; 128 LQ_threshold |= (LQ_threshold << 8); 129 130 rtw_write16(padapter, 0x218, HQ_threshold); 131 rtw_write16(padapter, 0x21A, NQ_threshold); 132 rtw_write16(padapter, 0x21C, LQ_threshold); 133 } 134 135 static void _InitQueueReservedPage(struct adapter *padapter) 136 { 137 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 138 struct registry_priv *pregistrypriv = &padapter->registrypriv; 139 u32 numHQ = 0; 140 u32 numLQ = 0; 141 u32 numNQ = 0; 142 u32 numPubQ; 143 u32 value32; 144 u8 value8; 145 bool bWiFiConfig = pregistrypriv->wifi_spec; 146 147 if (pHalData->OutEpQueueSel & TX_SELE_HQ) 148 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B; 149 150 if (pHalData->OutEpQueueSel & TX_SELE_LQ) 151 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B; 152 153 /* NOTE: This step shall be proceed before writing REG_RQPN. */ 154 if (pHalData->OutEpQueueSel & TX_SELE_NQ) 155 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B; 156 157 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ; 158 159 value8 = (u8)_NPQ(numNQ); 160 rtw_write8(padapter, REG_RQPN_NPQ, value8); 161 162 /* TX DMA */ 163 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 164 rtw_write32(padapter, REG_RQPN, value32); 165 166 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ); 167 168 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ); 169 } 170 171 static void _InitTxBufferBoundary(struct adapter *padapter) 172 { 173 struct registry_priv *pregistrypriv = &padapter->registrypriv; 174 175 /* u16 txdmactrl; */ 176 u8 txpktbuf_bndy; 177 178 if (!pregistrypriv->wifi_spec) { 179 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B; 180 } else { 181 /* for WMM */ 182 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B; 183 } 184 185 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy); 186 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy); 187 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy); 188 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy); 189 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy); 190 } 191 192 static void _InitNormalChipRegPriority( 193 struct adapter *Adapter, 194 u16 beQ, 195 u16 bkQ, 196 u16 viQ, 197 u16 voQ, 198 u16 mgtQ, 199 u16 hiQ 200 ) 201 { 202 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7); 203 204 value16 |= 205 _TXDMA_BEQ_MAP(beQ) | 206 _TXDMA_BKQ_MAP(bkQ) | 207 _TXDMA_VIQ_MAP(viQ) | 208 _TXDMA_VOQ_MAP(voQ) | 209 _TXDMA_MGQ_MAP(mgtQ) | 210 _TXDMA_HIQ_MAP(hiQ); 211 212 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); 213 } 214 215 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter) 216 { 217 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 218 219 u16 value = 0; 220 switch (pHalData->OutEpQueueSel) { 221 case TX_SELE_HQ: 222 value = QUEUE_HIGH; 223 break; 224 case TX_SELE_LQ: 225 value = QUEUE_LOW; 226 break; 227 case TX_SELE_NQ: 228 value = QUEUE_NORMAL; 229 break; 230 default: 231 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 232 break; 233 } 234 235 _InitNormalChipRegPriority( 236 Adapter, value, value, value, value, value, value 237 ); 238 239 } 240 241 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter) 242 { 243 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 244 struct registry_priv *pregistrypriv = &Adapter->registrypriv; 245 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 246 247 248 u16 valueHi = 0; 249 u16 valueLow = 0; 250 251 switch (pHalData->OutEpQueueSel) { 252 case (TX_SELE_HQ | TX_SELE_LQ): 253 valueHi = QUEUE_HIGH; 254 valueLow = QUEUE_LOW; 255 break; 256 case (TX_SELE_NQ | TX_SELE_LQ): 257 valueHi = QUEUE_NORMAL; 258 valueLow = QUEUE_LOW; 259 break; 260 case (TX_SELE_HQ | TX_SELE_NQ): 261 valueHi = QUEUE_HIGH; 262 valueLow = QUEUE_NORMAL; 263 break; 264 default: 265 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 266 break; 267 } 268 269 if (!pregistrypriv->wifi_spec) { 270 beQ = valueLow; 271 bkQ = valueLow; 272 viQ = valueHi; 273 voQ = valueHi; 274 mgtQ = valueHi; 275 hiQ = valueHi; 276 } else { 277 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */ 278 beQ = valueLow; 279 bkQ = valueHi; 280 viQ = valueHi; 281 voQ = valueLow; 282 mgtQ = valueHi; 283 hiQ = valueHi; 284 } 285 286 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 287 288 } 289 290 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter) 291 { 292 struct registry_priv *pregistrypriv = &padapter->registrypriv; 293 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 294 295 if (!pregistrypriv->wifi_spec) { 296 /* typical setting */ 297 beQ = QUEUE_LOW; 298 bkQ = QUEUE_LOW; 299 viQ = QUEUE_NORMAL; 300 voQ = QUEUE_HIGH; 301 mgtQ = QUEUE_HIGH; 302 hiQ = QUEUE_HIGH; 303 } else { 304 /* for WMM */ 305 beQ = QUEUE_LOW; 306 bkQ = QUEUE_NORMAL; 307 viQ = QUEUE_NORMAL; 308 voQ = QUEUE_HIGH; 309 mgtQ = QUEUE_HIGH; 310 hiQ = QUEUE_HIGH; 311 } 312 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 313 } 314 315 static void _InitQueuePriority(struct adapter *Adapter) 316 { 317 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 318 319 switch (pHalData->OutEpNumber) { 320 case 1: 321 _InitNormalChipOneOutEpPriority(Adapter); 322 break; 323 case 2: 324 _InitNormalChipTwoOutEpPriority(Adapter); 325 break; 326 case 3: 327 _InitNormalChipThreeOutEpPriority(Adapter); 328 break; 329 default: 330 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 331 break; 332 } 333 334 335 } 336 337 static void _InitPageBoundary(struct adapter *padapter) 338 { 339 /* RX Page Boundary */ 340 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B; 341 342 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy); 343 } 344 345 static void _InitTransferPageSize(struct adapter *padapter) 346 { 347 /* Tx page size is always 128. */ 348 349 u8 value8; 350 value8 = _PSRX(PBP_128) | _PSTX(PBP_128); 351 rtw_write8(padapter, REG_PBP, value8); 352 } 353 354 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize) 355 { 356 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize); 357 } 358 359 static void _InitNetworkType(struct adapter *padapter) 360 { 361 u32 value32; 362 363 value32 = rtw_read32(padapter, REG_CR); 364 365 /* TODO: use the other function to set network type */ 366 /* value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */ 367 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); 368 369 rtw_write32(padapter, REG_CR, value32); 370 } 371 372 static void _InitWMACSetting(struct adapter *padapter) 373 { 374 struct hal_com_data *pHalData; 375 u16 value16; 376 377 378 pHalData = GET_HAL_DATA(padapter); 379 380 pHalData->ReceiveConfig = 0; 381 pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB; 382 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF; 383 pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL; 384 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; 385 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig); 386 387 /* Accept all multicast address */ 388 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF); 389 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF); 390 391 /* Accept all data frames */ 392 value16 = 0xFFFF; 393 rtw_write16(padapter, REG_RXFLTMAP2, value16); 394 395 /* 2010.09.08 hpfan */ 396 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */ 397 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */ 398 value16 = 0x400; 399 rtw_write16(padapter, REG_RXFLTMAP1, value16); 400 401 /* Accept all management frames */ 402 value16 = 0xFFFF; 403 rtw_write16(padapter, REG_RXFLTMAP0, value16); 404 } 405 406 static void _InitAdaptiveCtrl(struct adapter *padapter) 407 { 408 u16 value16; 409 u32 value32; 410 411 /* Response Rate Set */ 412 value32 = rtw_read32(padapter, REG_RRSR); 413 value32 &= ~RATE_BITMAP_ALL; 414 value32 |= RATE_RRSR_CCK_ONLY_1M; 415 rtw_write32(padapter, REG_RRSR, value32); 416 417 /* CF-END Threshold */ 418 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */ 419 420 /* SIFS (used in NAV) */ 421 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 422 rtw_write16(padapter, REG_SPEC_SIFS, value16); 423 424 /* Retry Limit */ 425 value16 = _LRL(0x30) | _SRL(0x30); 426 rtw_write16(padapter, REG_RL, value16); 427 } 428 429 static void _InitEDCA(struct adapter *padapter) 430 { 431 /* Set Spec SIFS (used in NAV) */ 432 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a); 433 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a); 434 435 /* Set SIFS for CCK */ 436 rtw_write16(padapter, REG_SIFS_CTX, 0x100a); 437 438 /* Set SIFS for OFDM */ 439 rtw_write16(padapter, REG_SIFS_TRX, 0x100a); 440 441 /* TXOP */ 442 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B); 443 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F); 444 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324); 445 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226); 446 } 447 448 static void _InitRetryFunction(struct adapter *padapter) 449 { 450 u8 value8; 451 452 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL); 453 value8 |= EN_AMPDU_RTY_NEW; 454 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8); 455 456 /* Set ACK timeout */ 457 rtw_write8(padapter, REG_ACKTO, 0x40); 458 } 459 460 static void HalRxAggr8723BSdio(struct adapter *padapter) 461 { 462 u8 valueDMATimeout; 463 u8 valueDMAPageCount; 464 465 valueDMATimeout = 0x06; 466 valueDMAPageCount = 0x06; 467 468 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout); 469 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount); 470 } 471 472 static void sdio_AggSettingRxUpdate(struct adapter *padapter) 473 { 474 u8 valueDMA; 475 u8 valueRxAggCtrl = 0; 476 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */ 477 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */ 478 479 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL); 480 valueDMA |= RXDMA_AGG_EN; 481 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA); 482 483 valueRxAggCtrl |= RXDMA_AGG_MODE_EN; 484 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C); 485 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30); 486 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */ 487 } 488 489 static void _initSdioAggregationSetting(struct adapter *padapter) 490 { 491 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 492 493 /* Tx aggregation setting */ 494 /* sdio_AggSettingTxUpdate(padapter); */ 495 496 /* Rx aggregation setting */ 497 HalRxAggr8723BSdio(padapter); 498 499 sdio_AggSettingRxUpdate(padapter); 500 501 /* 201/12/10 MH Add for USB agg mode dynamic switch. */ 502 pHalData->UsbRxHighSpeedMode = false; 503 } 504 505 static void _InitOperationMode(struct adapter *padapter) 506 { 507 struct mlme_ext_priv *pmlmeext; 508 u8 regBwOpMode = 0; 509 510 pmlmeext = &padapter->mlmeextpriv; 511 512 /* 1 This part need to modified according to the rate set we filtered!! */ 513 /* */ 514 /* Set RRSR, RATR, and REG_BWOPMODE registers */ 515 /* */ 516 switch (pmlmeext->cur_wireless_mode) { 517 case WIRELESS_MODE_B: 518 regBwOpMode = BW_OPMODE_20MHZ; 519 break; 520 case WIRELESS_MODE_A: 521 /* RT_ASSERT(false, ("Error wireless a mode\n")); */ 522 break; 523 case WIRELESS_MODE_G: 524 regBwOpMode = BW_OPMODE_20MHZ; 525 break; 526 case WIRELESS_MODE_AUTO: 527 regBwOpMode = BW_OPMODE_20MHZ; 528 break; 529 case WIRELESS_MODE_N_24G: 530 /* It support CCK rate by default. */ 531 /* CCK rate will be filtered out only when associated AP does not support it. */ 532 regBwOpMode = BW_OPMODE_20MHZ; 533 break; 534 case WIRELESS_MODE_N_5G: 535 /* RT_ASSERT(false, ("Error wireless mode")); */ 536 regBwOpMode = BW_OPMODE_5G; 537 break; 538 539 default: /* for MacOSX compiler warning. */ 540 break; 541 } 542 543 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode); 544 545 } 546 547 static void _InitInterrupt(struct adapter *padapter) 548 { 549 /* HISR - turn all off */ 550 rtw_write32(padapter, REG_HISR, 0); 551 552 /* HIMR - turn all off */ 553 rtw_write32(padapter, REG_HIMR, 0); 554 555 /* */ 556 /* Initialize and enable SDIO Host Interrupt. */ 557 /* */ 558 InitInterrupt8723BSdio(padapter); 559 560 /* */ 561 /* Initialize system Host Interrupt. */ 562 /* */ 563 InitSysInterrupt8723BSdio(padapter); 564 } 565 566 static void _InitRFType(struct adapter *padapter) 567 { 568 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 569 570 #if DISABLE_BB_RF 571 pHalData->rf_chip = RF_PSEUDO_11N; 572 return; 573 #endif 574 575 pHalData->rf_chip = RF_6052; 576 577 pHalData->rf_type = RF_1T1R; 578 } 579 580 static void _RfPowerSave(struct adapter *padapter) 581 { 582 /* YJ, TODO */ 583 } 584 585 /* */ 586 /* 2010/08/09 MH Add for power down check. */ 587 /* */ 588 static bool HalDetectPwrDownMode(struct adapter *Adapter) 589 { 590 u8 tmpvalue; 591 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 592 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); 593 594 595 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue); 596 597 /* 2010/08/25 MH INF priority > PDN Efuse value. */ 598 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode) 599 pHalData->pwrdown = true; 600 else 601 pHalData->pwrdown = false; 602 603 return pHalData->pwrdown; 604 } /* HalDetectPwrDownMode */ 605 606 static u32 rtl8723bs_hal_init(struct adapter *padapter) 607 { 608 s32 ret; 609 struct hal_com_data *pHalData; 610 struct pwrctrl_priv *pwrctrlpriv; 611 u32 NavUpper = WiFiNavUpperUs; 612 u8 u1bTmp; 613 614 pHalData = GET_HAL_DATA(padapter); 615 pwrctrlpriv = adapter_to_pwrctl(padapter); 616 617 if ( 618 adapter_to_pwrctl(padapter)->bips_processing == true && 619 adapter_to_pwrctl(padapter)->pre_ips_type == 0 620 ) { 621 unsigned long start_time; 622 u8 cpwm_orig, cpwm_now; 623 u8 val8, bMacPwrCtrlOn = true; 624 625 /* for polling cpwm */ 626 cpwm_orig = 0; 627 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); 628 629 /* ser rpwm */ 630 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); 631 val8 &= 0x80; 632 val8 += 0x80; 633 val8 |= BIT(6); 634 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 635 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; 636 637 /* do polling cpwm */ 638 start_time = jiffies; 639 do { 640 641 mdelay(1); 642 643 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); 644 if ((cpwm_orig ^ cpwm_now) & 0x80) 645 break; 646 647 if (jiffies_to_msecs(jiffies - start_time) > 100) 648 break; 649 650 } while (1); 651 652 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0); 653 654 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 655 656 hal_btcoex_InitHwConfig(padapter, false); 657 658 return _SUCCESS; 659 } 660 661 /* Disable Interrupt first. */ 662 /* rtw_hal_disable_interrupt(padapter); */ 663 664 ret = _InitPowerOn_8723BS(padapter); 665 if (ret == _FAIL) 666 return _FAIL; 667 668 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0); 669 670 ret = rtl8723b_FirmwareDownload(padapter, false); 671 if (ret != _SUCCESS) { 672 padapter->bFWReady = false; 673 pHalData->fw_ractrl = false; 674 return ret; 675 } else { 676 padapter->bFWReady = true; 677 pHalData->fw_ractrl = true; 678 } 679 680 rtl8723b_InitializeFirmwareVars(padapter); 681 682 /* SIC_Init(padapter); */ 683 684 if (pwrctrlpriv->reg_rfoff) 685 pwrctrlpriv->rf_pwrstate = rf_off; 686 687 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ 688 /* HW GPIO pin. Before PHY_RFConfig8192C. */ 689 HalDetectPwrDownMode(padapter); 690 691 /* Set RF type for BB/RF configuration */ 692 _InitRFType(padapter); 693 694 /* Save target channel */ 695 /* <Roger_Notes> Current Channel will be updated again later. */ 696 pHalData->CurrentChannel = 6; 697 698 #if (HAL_MAC_ENABLE == 1) 699 ret = PHY_MACConfig8723B(padapter); 700 if (ret != _SUCCESS) 701 return ret; 702 #endif 703 /* */ 704 /* d. Initialize BB related configurations. */ 705 /* */ 706 #if (HAL_BB_ENABLE == 1) 707 ret = PHY_BBConfig8723B(padapter); 708 if (ret != _SUCCESS) 709 return ret; 710 #endif 711 712 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */ 713 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */ 714 /* if (pHalData->eRFPowerState == eRfOn) */ 715 { 716 #if (HAL_RF_ENABLE == 1) 717 ret = PHY_RFConfig8723B(padapter); 718 if (ret != _SUCCESS) 719 return ret; 720 #endif 721 } 722 723 /* */ 724 /* Joseph Note: Keep RfRegChnlVal for later use. */ 725 /* */ 726 pHalData->RfRegChnlVal[0] = 727 PHY_QueryRFReg(padapter, (enum rf_path)0, RF_CHNLBW, bRFRegOffsetMask); 728 pHalData->RfRegChnlVal[1] = 729 PHY_QueryRFReg(padapter, (enum rf_path)1, RF_CHNLBW, bRFRegOffsetMask); 730 731 732 /* if (!pHalData->bMACFuncEnable) { */ 733 _InitQueueReservedPage(padapter); 734 _InitTxBufferBoundary(padapter); 735 736 /* init LLT after tx buffer boundary is defined */ 737 ret = rtl8723b_InitLLTTable(padapter); 738 if (ret != _SUCCESS) 739 return _FAIL; 740 741 /* */ 742 _InitQueuePriority(padapter); 743 _InitPageBoundary(padapter); 744 _InitTransferPageSize(padapter); 745 746 /* Get Rx PHY status in order to report RSSI and others. */ 747 _InitDriverInfoSize(padapter, DRVINFO_SZ); 748 hal_init_macaddr(padapter); 749 _InitNetworkType(padapter); 750 _InitWMACSetting(padapter); 751 _InitAdaptiveCtrl(padapter); 752 _InitEDCA(padapter); 753 _InitRetryFunction(padapter); 754 _initSdioAggregationSetting(padapter); 755 _InitOperationMode(padapter); 756 rtl8723b_InitBeaconParameters(padapter); 757 _InitInterrupt(padapter); 758 _InitBurstPktLen_8723BS(padapter); 759 760 /* YJ, TODO */ 761 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */ 762 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */ 763 764 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 765 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 766 767 invalidate_cam_all(padapter); 768 769 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel, 770 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE); 771 772 /* Record original value for template. This is arough data, we can only use the data */ 773 /* for power adjust. The value can not be adjustde according to different power!!! */ 774 /* pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */ 775 /* pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */ 776 777 rtl8723b_InitAntenna_Selection(padapter); 778 779 /* */ 780 /* Disable BAR, suggested by Scott */ 781 /* 2010.04.09 add by hpfan */ 782 /* */ 783 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff); 784 785 /* HW SEQ CTRL */ 786 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 787 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); 788 789 790 /* */ 791 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */ 792 /* 2010.02.24. */ 793 /* */ 794 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0); 795 796 _RfPowerSave(padapter); 797 798 799 rtl8723b_InitHalDm(padapter); 800 801 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */ 802 803 /* */ 804 /* Update current Tx FIFO page status. */ 805 /* */ 806 HalQueryTxBufferStatus8723BSdio(padapter); 807 HalQueryTxOQTBufferStatus8723BSdio(padapter); 808 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace; 809 810 /* Enable MACTXEN/MACRXEN block */ 811 u1bTmp = rtw_read8(padapter, REG_CR); 812 u1bTmp |= (MACTXEN | MACRXEN); 813 rtw_write8(padapter, REG_CR, u1bTmp); 814 815 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper); 816 817 /* ack for xmit mgmt frames. */ 818 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12)); 819 820 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */ 821 822 { 823 pwrctrlpriv->rf_pwrstate = rf_on; 824 825 if (pwrctrlpriv->rf_pwrstate == rf_on) { 826 struct pwrctrl_priv *pwrpriv; 827 unsigned long start_time; 828 u8 restore_iqk_rst; 829 u8 b2Ant; 830 u8 h2cCmdBuf; 831 832 pwrpriv = adapter_to_pwrctl(padapter); 833 834 PHY_LCCalibrate_8723B(&pHalData->odmpriv); 835 836 /* Inform WiFi FW that it is the beginning of IQK */ 837 h2cCmdBuf = 1; 838 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); 839 840 start_time = jiffies; 841 do { 842 if (rtw_read8(padapter, 0x1e7) & 0x01) 843 break; 844 845 msleep(50); 846 } while (jiffies_to_msecs(jiffies - start_time) <= 400); 847 848 hal_btcoex_IQKNotify(padapter, true); 849 850 restore_iqk_rst = pwrpriv->bips_processing; 851 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2; 852 PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path); 853 pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true; 854 855 hal_btcoex_IQKNotify(padapter, false); 856 857 /* Inform WiFi FW that it is the finish of IQK */ 858 h2cCmdBuf = 0; 859 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); 860 861 ODM_TXPowerTrackingCheck(&pHalData->odmpriv); 862 } 863 } 864 865 /* Init BT hw config. */ 866 hal_btcoex_InitHwConfig(padapter, false); 867 868 return _SUCCESS; 869 } 870 871 /* */ 872 /* Description: */ 873 /* RTL8723e card disable power sequence v003 which suggested by Scott. */ 874 /* */ 875 /* First created by tynli. 2011.01.28. */ 876 /* */ 877 static void CardDisableRTL8723BSdio(struct adapter *padapter) 878 { 879 u8 u1bTmp; 880 u8 bMacPwrCtrlOn; 881 u8 ret = _FAIL; 882 883 /* Run LPS WL RFOFF flow */ 884 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow); 885 886 /* ==== Reset digital sequence ====== */ 887 888 u1bTmp = rtw_read8(padapter, REG_MCUFWDL); 889 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */ 890 rtl8723b_FirmwareSelfReset(padapter); 891 892 /* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */ 893 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); 894 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ 895 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp); 896 897 /* MCUFWDL 0x80[1:0]= 0 */ 898 /* reset MCU ready status */ 899 rtw_write8(padapter, REG_MCUFWDL, 0); 900 901 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */ 902 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1); 903 u1bTmp &= ~BIT(0); 904 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp); 905 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1); 906 u1bTmp |= BIT(0); 907 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp); 908 909 /* ==== Reset digital sequence end ====== */ 910 911 bMacPwrCtrlOn = false; /* Disable CMD53 R/W */ 912 ret = false; 913 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 914 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow); 915 } 916 917 static u32 rtl8723bs_hal_deinit(struct adapter *padapter) 918 { 919 struct dvobj_priv *psdpriv = padapter->dvobj; 920 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; 921 922 if (padapter->hw_init_completed) { 923 if (adapter_to_pwrctl(padapter)->bips_processing) { 924 if (padapter->netif_up) { 925 int cnt = 0; 926 u8 val8 = 0; 927 928 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3); 929 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */ 930 do { 931 val8 = rtw_read8(padapter, REG_HMETFR); 932 cnt++; 933 mdelay(10); 934 } while (cnt < 100 && (val8 != 0)); 935 /* H2C done, enter 32k */ 936 if (val8 == 0) { 937 /* ser rpwm to enter 32k */ 938 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); 939 val8 += 0x80; 940 val8 |= BIT(0); 941 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 942 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; 943 cnt = val8 = 0; 944 do { 945 val8 = rtw_read8(padapter, REG_CR); 946 cnt++; 947 mdelay(10); 948 } while (cnt < 100 && (val8 != 0xEA)); 949 } 950 951 adapter_to_pwrctl(padapter)->pre_ips_type = 0; 952 953 } else { 954 pdbgpriv->dbg_carddisable_cnt++; 955 CardDisableRTL8723BSdio(padapter); 956 957 adapter_to_pwrctl(padapter)->pre_ips_type = 1; 958 } 959 960 } else { 961 pdbgpriv->dbg_carddisable_cnt++; 962 CardDisableRTL8723BSdio(padapter); 963 } 964 } else 965 pdbgpriv->dbg_deinit_fail_cnt++; 966 967 return _SUCCESS; 968 } 969 970 static u32 rtl8723bs_inirp_init(struct adapter *padapter) 971 { 972 return _SUCCESS; 973 } 974 975 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter) 976 { 977 return _SUCCESS; 978 } 979 980 static void rtl8723bs_init_default_value(struct adapter *padapter) 981 { 982 struct hal_com_data *pHalData; 983 984 985 pHalData = GET_HAL_DATA(padapter); 986 987 rtl8723b_init_default_value(padapter); 988 989 /* interface related variable */ 990 pHalData->SdioRxFIFOCnt = 0; 991 } 992 993 static void rtl8723bs_interface_configure(struct adapter *padapter) 994 { 995 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 996 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); 997 struct registry_priv *pregistrypriv = &padapter->registrypriv; 998 bool bWiFiConfig = pregistrypriv->wifi_spec; 999 1000 1001 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID; 1002 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID; 1003 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID; 1004 1005 if (bWiFiConfig) 1006 pHalData->OutEpNumber = 2; 1007 else 1008 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE; 1009 1010 switch (pHalData->OutEpNumber) { 1011 case 3: 1012 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ; 1013 break; 1014 case 2: 1015 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ; 1016 break; 1017 case 1: 1018 pHalData->OutEpQueueSel = TX_SELE_HQ; 1019 break; 1020 default: 1021 break; 1022 } 1023 1024 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber); 1025 } 1026 1027 /* */ 1028 /* Description: */ 1029 /* We should set Efuse cell selection to WiFi cell in default. */ 1030 /* */ 1031 /* Assumption: */ 1032 /* PASSIVE_LEVEL */ 1033 /* */ 1034 /* Added by Roger, 2010.11.23. */ 1035 /* */ 1036 static void _EfuseCellSel(struct adapter *padapter) 1037 { 1038 u32 value32; 1039 1040 value32 = rtw_read32(padapter, EFUSE_TEST); 1041 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1042 rtw_write32(padapter, EFUSE_TEST, value32); 1043 } 1044 1045 static void _ReadRFType(struct adapter *Adapter) 1046 { 1047 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1048 1049 #if DISABLE_BB_RF 1050 pHalData->rf_chip = RF_PSEUDO_11N; 1051 #else 1052 pHalData->rf_chip = RF_6052; 1053 #endif 1054 } 1055 1056 1057 static void Hal_EfuseParseMACAddr_8723BS( 1058 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 1059 ) 1060 { 1061 u16 i; 1062 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00}; 1063 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1064 1065 if (AutoLoadFail) { 1066 /* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */ 1067 for (i = 0; i < 6; i++) 1068 pEEPROM->mac_addr[i] = sMacAddr[i]; 1069 } else { 1070 /* Read Permanent MAC address */ 1071 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN); 1072 } 1073 } 1074 1075 static void Hal_EfuseParseBoardType_8723BS( 1076 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 1077 ) 1078 { 1079 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1080 1081 if (!AutoLoadFail) { 1082 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5; 1083 if (pHalData->BoardType == 0xFF) 1084 pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5; 1085 } else 1086 pHalData->BoardType = 0; 1087 } 1088 1089 static void _ReadEfuseInfo8723BS(struct adapter *padapter) 1090 { 1091 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1092 u8 *hwinfo = NULL; 1093 1094 /* */ 1095 /* This part read and parse the eeprom/efuse content */ 1096 /* */ 1097 1098 hwinfo = pEEPROM->efuse_eeprom_data; 1099 1100 Hal_InitPGData(padapter, hwinfo); 1101 1102 Hal_EfuseParseIDCode(padapter, hwinfo); 1103 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1104 1105 Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1106 1107 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1108 Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1109 1110 /* */ 1111 /* Read Bluetooth co-exist and initialize */ 1112 /* */ 1113 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1114 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1115 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1116 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1117 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1118 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1119 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1120 1121 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1122 1123 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1124 } 1125 1126 static void _ReadPROMContent(struct adapter *padapter) 1127 { 1128 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1129 u8 eeValue; 1130 1131 eeValue = rtw_read8(padapter, REG_9346CR); 1132 /* To check system boot selection. */ 1133 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false; 1134 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true; 1135 1136 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */ 1137 1138 _ReadEfuseInfo8723BS(padapter); 1139 } 1140 1141 static void _InitOtherVariable(struct adapter *Adapter) 1142 { 1143 } 1144 1145 /* */ 1146 /* Description: */ 1147 /* Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */ 1148 /* */ 1149 /* Assumption: */ 1150 /* PASSIVE_LEVEL (SDIO interface) */ 1151 /* */ 1152 /* */ 1153 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter) 1154 { 1155 u8 val8; 1156 1157 /* before access eFuse, make sure card enable has been called */ 1158 if (!padapter->hw_init_completed) 1159 _InitPowerOn_8723BS(padapter); 1160 1161 1162 val8 = rtw_read8(padapter, 0x4e); 1163 val8 |= BIT(6); 1164 rtw_write8(padapter, 0x4e, val8); 1165 1166 _EfuseCellSel(padapter); 1167 _ReadRFType(padapter); 1168 _ReadPROMContent(padapter); 1169 _InitOtherVariable(padapter); 1170 1171 if (!padapter->hw_init_completed) { 1172 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */ 1173 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue, wifi ko module is loaded during booting, but wifi GUI is off */ 1174 } 1175 1176 return _SUCCESS; 1177 } 1178 1179 static void ReadAdapterInfo8723BS(struct adapter *padapter) 1180 { 1181 /* Read EEPROM size before call any EEPROM function */ 1182 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter); 1183 1184 _ReadAdapterInfo8723BS(padapter); 1185 } 1186 1187 /* 1188 * If variable not handled here, 1189 * some variables will be processed in SetHwReg8723B() 1190 */ 1191 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) 1192 { 1193 u8 val8; 1194 1195 switch (variable) { 1196 case HW_VAR_SET_RPWM: 1197 /* rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */ 1198 /* BIT0 value - 1: 32k, 0:40MHz. */ 1199 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */ 1200 /* BIT7 value - Toggle bit change. */ 1201 { 1202 val8 = *val; 1203 val8 &= 0xC1; 1204 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 1205 } 1206 break; 1207 case HW_VAR_SET_REQ_FW_PS: 1208 { 1209 u8 req_fw_ps = 0; 1210 req_fw_ps = rtw_read8(padapter, 0x8f); 1211 req_fw_ps |= 0x10; 1212 rtw_write8(padapter, 0x8f, req_fw_ps); 1213 } 1214 break; 1215 case HW_VAR_RXDMA_AGG_PG_TH: 1216 val8 = *val; 1217 break; 1218 1219 case HW_VAR_DM_IN_LPS: 1220 rtl8723b_hal_dm_in_lps(padapter); 1221 break; 1222 default: 1223 SetHwReg8723B(padapter, variable, val); 1224 break; 1225 } 1226 } 1227 1228 /* 1229 * If variable not handled here, 1230 * some variables will be processed in GetHwReg8723B() 1231 */ 1232 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) 1233 { 1234 switch (variable) { 1235 case HW_VAR_CPWM: 1236 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B); 1237 break; 1238 1239 case HW_VAR_FW_PS_STATE: 1240 { 1241 /* 3. read dword 0x88 driver read fw ps state */ 1242 *((u16 *)val) = rtw_read16(padapter, 0x88); 1243 } 1244 break; 1245 default: 1246 GetHwReg8723B(padapter, variable, val); 1247 break; 1248 } 1249 } 1250 1251 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len) 1252 { 1253 switch (variable) { 1254 case HW_VAR_C2H_HANDLE: 1255 C2HPacketHandler_8723B(padapter, pbuf, len); 1256 break; 1257 default: 1258 break; 1259 } 1260 } 1261 1262 /* */ 1263 /* Description: */ 1264 /* Query setting of specified variable. */ 1265 /* */ 1266 static u8 GetHalDefVar8723BSDIO( 1267 struct adapter *Adapter, enum hal_def_variable eVariable, void *pValue 1268 ) 1269 { 1270 u8 bResult = _SUCCESS; 1271 1272 switch (eVariable) { 1273 case HAL_DEF_IS_SUPPORT_ANT_DIV: 1274 break; 1275 case HAL_DEF_CURRENT_ANTENNA: 1276 break; 1277 case HW_VAR_MAX_RX_AMPDU_FACTOR: 1278 /* Stanley@BB.SD3 suggests 16K can get stable performance */ 1279 /* coding by Lucas@20130730 */ 1280 *(u32 *)pValue = IEEE80211_HT_MAX_AMPDU_16K; 1281 break; 1282 default: 1283 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue); 1284 break; 1285 } 1286 1287 return bResult; 1288 } 1289 1290 /* */ 1291 /* Description: */ 1292 /* Change default setting of specified variable. */ 1293 /* */ 1294 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter, 1295 enum hal_def_variable eVariable, void *pValue) 1296 { 1297 return SetHalDefVar8723B(Adapter, eVariable, pValue); 1298 } 1299 1300 void rtl8723bs_set_hal_ops(struct adapter *padapter) 1301 { 1302 struct hal_ops *pHalFunc = &padapter->HalFunc; 1303 1304 rtl8723b_set_hal_ops(pHalFunc); 1305 1306 pHalFunc->hal_init = &rtl8723bs_hal_init; 1307 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit; 1308 1309 pHalFunc->inirp_init = &rtl8723bs_inirp_init; 1310 pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit; 1311 1312 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv; 1313 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv; 1314 1315 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv; 1316 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv; 1317 1318 pHalFunc->init_default_value = &rtl8723bs_init_default_value; 1319 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure; 1320 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS; 1321 1322 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio; 1323 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio; 1324 pHalFunc->check_ips_status = &CheckIPSStatus; 1325 pHalFunc->SetHwRegHandler = &SetHwReg8723BS; 1326 pHalFunc->GetHwRegHandler = &GetHwReg8723BS; 1327 pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B; 1328 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO; 1329 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO; 1330 1331 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit; 1332 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit; 1333 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue; 1334 } 1335