1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #define _SDIO_HALINIT_C_ 8 9 #include <drv_types.h> 10 #include <rtw_debug.h> 11 #include <rtl8723b_hal.h> 12 13 #include "hal_com_h2c.h" 14 /* 15 * Description: 16 *Call power on sequence to enable card 17 * 18 * Return: 19 *_SUCCESS enable success 20 *_FAIL enable fail 21 */ 22 static u8 CardEnable(struct adapter *padapter) 23 { 24 u8 bMacPwrCtrlOn; 25 u8 ret = _FAIL; 26 27 28 rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 29 if (!bMacPwrCtrlOn) { 30 /* RSV_CTRL 0x1C[7:0] = 0x00 */ 31 /* unlock ISO/CLK/Power control register */ 32 rtw_write8(padapter, REG_RSV_CTRL, 0x0); 33 34 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow); 35 if (ret == _SUCCESS) { 36 u8 bMacPwrCtrlOn = true; 37 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 38 } 39 } else 40 ret = _SUCCESS; 41 42 return ret; 43 } 44 45 #ifdef CONFIG_GPIO_WAKEUP 46 /* we set it high under init and fw will */ 47 /* give us Low Pulse when host wake up */ 48 void HostWakeUpGpioClear(struct adapter *Adapter) 49 { 50 u32 value32; 51 52 value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2); 53 54 /* set GPIO 12 1 */ 55 value32 |= BIT(12);/* 4+8 */ 56 /* GPIO 12 out put */ 57 value32 |= BIT(20);/* 4+16 */ 58 59 rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32); 60 } /* HostWakeUpGpioClear */ 61 62 void HalSetOutPutGPIO(struct adapter *padapter, u8 index, u8 OutPutValue) 63 { 64 if (index <= 7) { 65 /* config GPIO mode */ 66 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index)); 67 68 /* config GPIO Sel */ 69 /* 0: input */ 70 /* 1: output */ 71 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index)); 72 73 /* set output value */ 74 if (OutPutValue) 75 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index)); 76 else 77 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index)); 78 } else { 79 /* 88C Series: */ 80 /* index: 11~8 transform to 3~0 */ 81 /* 8723 Series: */ 82 /* index: 12~8 transform to 4~0 */ 83 index -= 8; 84 85 /* config GPIO mode */ 86 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index)); 87 88 /* config GPIO Sel */ 89 /* 0: input */ 90 /* 1: output */ 91 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index)); 92 93 /* set output value */ 94 if (OutPutValue) 95 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index)); 96 else 97 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index)); 98 } 99 } 100 #endif 101 102 static 103 u8 _InitPowerOn_8723BS(struct adapter *padapter) 104 { 105 u8 value8; 106 u16 value16; 107 u32 value32; 108 u8 ret; 109 /* u8 bMacPwrCtrlOn; */ 110 111 112 /* all of these MUST be configured before power on */ 113 #ifdef CONFIG_EXT_CLK 114 /* Use external crystal(XTAL) */ 115 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B + 2); 116 value8 |= BIT(7); 117 rtw_write8(padapter, REG_PAD_CTRL1_8723B + 2, value8); 118 119 /* CLK_REQ High active or Low Active */ 120 /* Request GPIO polarity: */ 121 /* 0: low active */ 122 /* 1: high active */ 123 value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL + 1); 124 value8 |= BIT(5); 125 rtw_write8(padapter, REG_MULTI_FUNC_CTRL + 1, value8); 126 #endif /* CONFIG_EXT_CLK */ 127 128 /* only cmd52 can be used before power on(card enable) */ 129 ret = CardEnable(padapter); 130 if (!ret) { 131 RT_TRACE( 132 _module_hci_hal_init_c_, 133 _drv_emerg_, 134 ("%s: run power on flow fail\n", __func__) 135 ); 136 return _FAIL; 137 } 138 139 /* Radio-Off Pin Trigger */ 140 value8 = rtw_read8(padapter, REG_GPIO_INTM + 1); 141 value8 |= BIT(1); /* Enable falling edge triggering interrupt */ 142 rtw_write8(padapter, REG_GPIO_INTM + 1, value8); 143 value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2 + 1); 144 value8 |= BIT(1); 145 rtw_write8(padapter, REG_GPIO_IO_SEL_2 + 1, value8); 146 147 /* Enable power down and GPIO interrupt */ 148 value16 = rtw_read16(padapter, REG_APS_FSMCO); 149 value16 |= EnPDN; /* Enable HW power down and RF on */ 150 rtw_write16(padapter, REG_APS_FSMCO, value16); 151 152 /* Enable CMD53 R/W Operation */ 153 /* bMacPwrCtrlOn = true; */ 154 /* rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */ 155 156 rtw_write8(padapter, REG_CR, 0x00); 157 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */ 158 value16 = rtw_read16(padapter, REG_CR); 159 value16 |= ( 160 HCI_TXDMA_EN | 161 HCI_RXDMA_EN | 162 TXDMA_EN | 163 RXDMA_EN | 164 PROTOCOL_EN | 165 SCHEDULE_EN | 166 ENSEC | 167 CALTMR_EN 168 ); 169 rtw_write16(padapter, REG_CR, value16); 170 171 hal_btcoex_PowerOnSetting(padapter); 172 173 /* external switch to S1 */ 174 /* 0x38[11] = 0x1 */ 175 /* 0x4c[23] = 0x1 */ 176 /* 0x64[0] = 0 */ 177 value16 = rtw_read16(padapter, REG_PWR_DATA); 178 /* Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */ 179 value16 |= BIT(11); /* BIT_EEPRPAD_RFE_CTRL_EN */ 180 rtw_write16(padapter, REG_PWR_DATA, value16); 181 /* DBG_8192C("%s: REG_PWR_DATA(0x%x) = 0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */ 182 183 value32 = rtw_read32(padapter, REG_LEDCFG0); 184 value32 |= BIT(23); /* DPDT_SEL_EN, 1 for SW control */ 185 rtw_write32(padapter, REG_LEDCFG0, value32); 186 /* DBG_8192C("%s: REG_LEDCFG0(0x%x) = 0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */ 187 188 value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B); 189 value8 &= ~BIT(0); /* BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */ 190 rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8); 191 /* DBG_8192C("%s: REG_PAD_CTRL1(0x%x) = 0x%02X\n", __func__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B)); */ 192 193 #ifdef CONFIG_GPIO_WAKEUP 194 HostWakeUpGpioClear(padapter); 195 #endif 196 197 return _SUCCESS; 198 } 199 200 /* Tx Page FIFO threshold */ 201 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ) 202 { 203 u16 HQ_threshold, NQ_threshold, LQ_threshold; 204 205 HQ_threshold = (numPubQ + numHQ + 1) >> 1; 206 HQ_threshold |= (HQ_threshold << 8); 207 208 NQ_threshold = (numPubQ + numNQ + 1) >> 1; 209 NQ_threshold |= (NQ_threshold << 8); 210 211 LQ_threshold = (numPubQ + numLQ + 1) >> 1; 212 LQ_threshold |= (LQ_threshold << 8); 213 214 rtw_write16(padapter, 0x218, HQ_threshold); 215 rtw_write16(padapter, 0x21A, NQ_threshold); 216 rtw_write16(padapter, 0x21C, LQ_threshold); 217 DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x, N:0x%x, L:0x%x\n", __func__, HQ_threshold, NQ_threshold, LQ_threshold); 218 } 219 220 static void _InitQueueReservedPage(struct adapter *padapter) 221 { 222 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 223 struct registry_priv *pregistrypriv = &padapter->registrypriv; 224 u32 numHQ = 0; 225 u32 numLQ = 0; 226 u32 numNQ = 0; 227 u32 numPubQ; 228 u32 value32; 229 u8 value8; 230 bool bWiFiConfig = pregistrypriv->wifi_spec; 231 232 if (pHalData->OutEpQueueSel & TX_SELE_HQ) 233 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B; 234 235 if (pHalData->OutEpQueueSel & TX_SELE_LQ) 236 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B; 237 238 /* NOTE: This step shall be proceed before writing REG_RQPN. */ 239 if (pHalData->OutEpQueueSel & TX_SELE_NQ) 240 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B; 241 242 numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ; 243 244 value8 = (u8)_NPQ(numNQ); 245 rtw_write8(padapter, REG_RQPN_NPQ, value8); 246 247 /* TX DMA */ 248 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN; 249 rtw_write32(padapter, REG_RQPN, value32); 250 251 rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ); 252 253 _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ); 254 } 255 256 static void _InitTxBufferBoundary(struct adapter *padapter) 257 { 258 struct registry_priv *pregistrypriv = &padapter->registrypriv; 259 260 /* u16 txdmactrl; */ 261 u8 txpktbuf_bndy; 262 263 if (!pregistrypriv->wifi_spec) { 264 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B; 265 } else { 266 /* for WMM */ 267 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B; 268 } 269 270 rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy); 271 rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy); 272 rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy); 273 rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy); 274 rtw_write8(padapter, REG_TDECTRL + 1, txpktbuf_bndy); 275 } 276 277 static void _InitNormalChipRegPriority( 278 struct adapter *Adapter, 279 u16 beQ, 280 u16 bkQ, 281 u16 viQ, 282 u16 voQ, 283 u16 mgtQ, 284 u16 hiQ 285 ) 286 { 287 u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7); 288 289 value16 |= 290 _TXDMA_BEQ_MAP(beQ) | 291 _TXDMA_BKQ_MAP(bkQ) | 292 _TXDMA_VIQ_MAP(viQ) | 293 _TXDMA_VOQ_MAP(voQ) | 294 _TXDMA_MGQ_MAP(mgtQ) | 295 _TXDMA_HIQ_MAP(hiQ); 296 297 rtw_write16(Adapter, REG_TRXDMA_CTRL, value16); 298 } 299 300 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter) 301 { 302 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 303 304 u16 value = 0; 305 switch (pHalData->OutEpQueueSel) { 306 case TX_SELE_HQ: 307 value = QUEUE_HIGH; 308 break; 309 case TX_SELE_LQ: 310 value = QUEUE_LOW; 311 break; 312 case TX_SELE_NQ: 313 value = QUEUE_NORMAL; 314 break; 315 default: 316 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 317 break; 318 } 319 320 _InitNormalChipRegPriority( 321 Adapter, value, value, value, value, value, value 322 ); 323 324 } 325 326 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter) 327 { 328 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 329 struct registry_priv *pregistrypriv = &Adapter->registrypriv; 330 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 331 332 333 u16 valueHi = 0; 334 u16 valueLow = 0; 335 336 switch (pHalData->OutEpQueueSel) { 337 case (TX_SELE_HQ | TX_SELE_LQ): 338 valueHi = QUEUE_HIGH; 339 valueLow = QUEUE_LOW; 340 break; 341 case (TX_SELE_NQ | TX_SELE_LQ): 342 valueHi = QUEUE_NORMAL; 343 valueLow = QUEUE_LOW; 344 break; 345 case (TX_SELE_HQ | TX_SELE_NQ): 346 valueHi = QUEUE_HIGH; 347 valueLow = QUEUE_NORMAL; 348 break; 349 default: 350 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 351 break; 352 } 353 354 if (!pregistrypriv->wifi_spec) { 355 beQ = valueLow; 356 bkQ = valueLow; 357 viQ = valueHi; 358 voQ = valueHi; 359 mgtQ = valueHi; 360 hiQ = valueHi; 361 } else { 362 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */ 363 beQ = valueLow; 364 bkQ = valueHi; 365 viQ = valueHi; 366 voQ = valueLow; 367 mgtQ = valueHi; 368 hiQ = valueHi; 369 } 370 371 _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 372 373 } 374 375 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter) 376 { 377 struct registry_priv *pregistrypriv = &padapter->registrypriv; 378 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ; 379 380 if (!pregistrypriv->wifi_spec) { 381 /* typical setting */ 382 beQ = QUEUE_LOW; 383 bkQ = QUEUE_LOW; 384 viQ = QUEUE_NORMAL; 385 voQ = QUEUE_HIGH; 386 mgtQ = QUEUE_HIGH; 387 hiQ = QUEUE_HIGH; 388 } else { 389 /* for WMM */ 390 beQ = QUEUE_LOW; 391 bkQ = QUEUE_NORMAL; 392 viQ = QUEUE_NORMAL; 393 voQ = QUEUE_HIGH; 394 mgtQ = QUEUE_HIGH; 395 hiQ = QUEUE_HIGH; 396 } 397 _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ); 398 } 399 400 static void _InitQueuePriority(struct adapter *Adapter) 401 { 402 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 403 404 switch (pHalData->OutEpNumber) { 405 case 1: 406 _InitNormalChipOneOutEpPriority(Adapter); 407 break; 408 case 2: 409 _InitNormalChipTwoOutEpPriority(Adapter); 410 break; 411 case 3: 412 _InitNormalChipThreeOutEpPriority(Adapter); 413 break; 414 default: 415 /* RT_ASSERT(false, ("Shall not reach here!\n")); */ 416 break; 417 } 418 419 420 } 421 422 static void _InitPageBoundary(struct adapter *padapter) 423 { 424 /* RX Page Boundary */ 425 u16 rxff_bndy = RX_DMA_BOUNDARY_8723B; 426 427 rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy); 428 } 429 430 static void _InitTransferPageSize(struct adapter *padapter) 431 { 432 /* Tx page size is always 128. */ 433 434 u8 value8; 435 value8 = _PSRX(PBP_128) | _PSTX(PBP_128); 436 rtw_write8(padapter, REG_PBP, value8); 437 } 438 439 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize) 440 { 441 rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize); 442 } 443 444 static void _InitNetworkType(struct adapter *padapter) 445 { 446 u32 value32; 447 448 value32 = rtw_read32(padapter, REG_CR); 449 450 /* TODO: use the other function to set network type */ 451 /* value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */ 452 value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP); 453 454 rtw_write32(padapter, REG_CR, value32); 455 } 456 457 static void _InitWMACSetting(struct adapter *padapter) 458 { 459 struct hal_com_data *pHalData; 460 u16 value16; 461 462 463 pHalData = GET_HAL_DATA(padapter); 464 465 pHalData->ReceiveConfig = 0; 466 pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB; 467 pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF; 468 pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL; 469 pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC; 470 rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig); 471 472 /* Accept all multicast address */ 473 rtw_write32(padapter, REG_MAR, 0xFFFFFFFF); 474 rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF); 475 476 /* Accept all data frames */ 477 value16 = 0xFFFF; 478 rtw_write16(padapter, REG_RXFLTMAP2, value16); 479 480 /* 2010.09.08 hpfan */ 481 /* Since ADF is removed from RCR, ps-poll will not be indicate to driver, */ 482 /* RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */ 483 value16 = 0x400; 484 rtw_write16(padapter, REG_RXFLTMAP1, value16); 485 486 /* Accept all management frames */ 487 value16 = 0xFFFF; 488 rtw_write16(padapter, REG_RXFLTMAP0, value16); 489 } 490 491 static void _InitAdaptiveCtrl(struct adapter *padapter) 492 { 493 u16 value16; 494 u32 value32; 495 496 /* Response Rate Set */ 497 value32 = rtw_read32(padapter, REG_RRSR); 498 value32 &= ~RATE_BITMAP_ALL; 499 value32 |= RATE_RRSR_CCK_ONLY_1M; 500 rtw_write32(padapter, REG_RRSR, value32); 501 502 /* CF-END Threshold */ 503 /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */ 504 505 /* SIFS (used in NAV) */ 506 value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10); 507 rtw_write16(padapter, REG_SPEC_SIFS, value16); 508 509 /* Retry Limit */ 510 value16 = _LRL(0x30) | _SRL(0x30); 511 rtw_write16(padapter, REG_RL, value16); 512 } 513 514 static void _InitEDCA(struct adapter *padapter) 515 { 516 /* Set Spec SIFS (used in NAV) */ 517 rtw_write16(padapter, REG_SPEC_SIFS, 0x100a); 518 rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a); 519 520 /* Set SIFS for CCK */ 521 rtw_write16(padapter, REG_SIFS_CTX, 0x100a); 522 523 /* Set SIFS for OFDM */ 524 rtw_write16(padapter, REG_SIFS_TRX, 0x100a); 525 526 /* TXOP */ 527 rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B); 528 rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F); 529 rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324); 530 rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226); 531 } 532 533 static void _InitRetryFunction(struct adapter *padapter) 534 { 535 u8 value8; 536 537 value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL); 538 value8 |= EN_AMPDU_RTY_NEW; 539 rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8); 540 541 /* Set ACK timeout */ 542 rtw_write8(padapter, REG_ACKTO, 0x40); 543 } 544 545 static void HalRxAggr8723BSdio(struct adapter *padapter) 546 { 547 struct registry_priv *pregistrypriv; 548 u8 valueDMATimeout; 549 u8 valueDMAPageCount; 550 551 552 pregistrypriv = &padapter->registrypriv; 553 554 valueDMATimeout = 0x06; 555 valueDMAPageCount = 0x06; 556 557 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH + 1, valueDMATimeout); 558 rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount); 559 } 560 561 static void sdio_AggSettingRxUpdate(struct adapter *padapter) 562 { 563 u8 valueDMA; 564 u8 valueRxAggCtrl = 0; 565 u8 aggBurstNum = 3; /* 0:1, 1:2, 2:3, 3:4 */ 566 u8 aggBurstSize = 0; /* 0:1K, 1:512Byte, 2:256Byte... */ 567 568 valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL); 569 valueDMA |= RXDMA_AGG_EN; 570 rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA); 571 572 valueRxAggCtrl |= RXDMA_AGG_MODE_EN; 573 valueRxAggCtrl |= ((aggBurstNum << 2) & 0x0C); 574 valueRxAggCtrl |= ((aggBurstSize << 4) & 0x30); 575 rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */ 576 } 577 578 static void _initSdioAggregationSetting(struct adapter *padapter) 579 { 580 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 581 582 /* Tx aggregation setting */ 583 /* sdio_AggSettingTxUpdate(padapter); */ 584 585 /* Rx aggregation setting */ 586 HalRxAggr8723BSdio(padapter); 587 588 sdio_AggSettingRxUpdate(padapter); 589 590 /* 201/12/10 MH Add for USB agg mode dynamic switch. */ 591 pHalData->UsbRxHighSpeedMode = false; 592 } 593 594 static void _InitOperationMode(struct adapter *padapter) 595 { 596 struct mlme_ext_priv *pmlmeext; 597 u8 regBwOpMode = 0; 598 599 pmlmeext = &padapter->mlmeextpriv; 600 601 /* 1 This part need to modified according to the rate set we filtered!! */ 602 /* */ 603 /* Set RRSR, RATR, and REG_BWOPMODE registers */ 604 /* */ 605 switch (pmlmeext->cur_wireless_mode) { 606 case WIRELESS_MODE_B: 607 regBwOpMode = BW_OPMODE_20MHZ; 608 break; 609 case WIRELESS_MODE_A: 610 /* RT_ASSERT(false, ("Error wireless a mode\n")); */ 611 break; 612 case WIRELESS_MODE_G: 613 regBwOpMode = BW_OPMODE_20MHZ; 614 break; 615 case WIRELESS_MODE_AUTO: 616 regBwOpMode = BW_OPMODE_20MHZ; 617 break; 618 case WIRELESS_MODE_N_24G: 619 /* It support CCK rate by default. */ 620 /* CCK rate will be filtered out only when associated AP does not support it. */ 621 regBwOpMode = BW_OPMODE_20MHZ; 622 break; 623 case WIRELESS_MODE_N_5G: 624 /* RT_ASSERT(false, ("Error wireless mode")); */ 625 regBwOpMode = BW_OPMODE_5G; 626 break; 627 628 default: /* for MacOSX compiler warning. */ 629 break; 630 } 631 632 rtw_write8(padapter, REG_BWOPMODE, regBwOpMode); 633 634 } 635 636 static void _InitInterrupt(struct adapter *padapter) 637 { 638 /* HISR - turn all off */ 639 rtw_write32(padapter, REG_HISR, 0); 640 641 /* HIMR - turn all off */ 642 rtw_write32(padapter, REG_HIMR, 0); 643 644 /* */ 645 /* Initialize and enable SDIO Host Interrupt. */ 646 /* */ 647 InitInterrupt8723BSdio(padapter); 648 649 /* */ 650 /* Initialize system Host Interrupt. */ 651 /* */ 652 InitSysInterrupt8723BSdio(padapter); 653 } 654 655 static void _InitRFType(struct adapter *padapter) 656 { 657 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 658 659 #if DISABLE_BB_RF 660 pHalData->rf_chip = RF_PSEUDO_11N; 661 return; 662 #endif 663 664 pHalData->rf_chip = RF_6052; 665 666 pHalData->rf_type = RF_1T1R; 667 DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n"); 668 } 669 670 static void _RfPowerSave(struct adapter *padapter) 671 { 672 /* YJ, TODO */ 673 } 674 675 /* */ 676 /* 2010/08/09 MH Add for power down check. */ 677 /* */ 678 static bool HalDetectPwrDownMode(struct adapter *Adapter) 679 { 680 u8 tmpvalue; 681 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 682 struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter); 683 684 685 EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue); 686 687 /* 2010/08/25 MH INF priority > PDN Efuse value. */ 688 if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode) 689 pHalData->pwrdown = true; 690 else 691 pHalData->pwrdown = false; 692 693 DBG_8192C("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown); 694 695 return pHalData->pwrdown; 696 } /* HalDetectPwrDownMode */ 697 698 static u32 rtl8723bs_hal_init(struct adapter *padapter) 699 { 700 s32 ret; 701 struct hal_com_data *pHalData; 702 struct pwrctrl_priv *pwrctrlpriv; 703 u32 NavUpper = WiFiNavUpperUs; 704 u8 u1bTmp; 705 706 pHalData = GET_HAL_DATA(padapter); 707 pwrctrlpriv = adapter_to_pwrctl(padapter); 708 709 if ( 710 adapter_to_pwrctl(padapter)->bips_processing == true && 711 adapter_to_pwrctl(padapter)->pre_ips_type == 0 712 ) { 713 unsigned long start_time; 714 u8 cpwm_orig, cpwm_now; 715 u8 val8, bMacPwrCtrlOn = true; 716 717 DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__); 718 719 /* for polling cpwm */ 720 cpwm_orig = 0; 721 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig); 722 723 /* ser rpwm */ 724 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); 725 val8 &= 0x80; 726 val8 += 0x80; 727 val8 |= BIT(6); 728 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 729 DBG_871X("%s: write rpwm =%02x\n", __func__, val8); 730 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; 731 732 /* do polling cpwm */ 733 start_time = jiffies; 734 do { 735 736 mdelay(1); 737 738 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now); 739 if ((cpwm_orig ^ cpwm_now) & 0x80) 740 break; 741 742 if (jiffies_to_msecs(jiffies - start_time) > 100) { 743 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__); 744 break; 745 } 746 } while (1); 747 748 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0); 749 750 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 751 752 hal_btcoex_InitHwConfig(padapter, false); 753 754 return _SUCCESS; 755 } 756 757 #ifdef CONFIG_WOWLAN 758 if (rtw_read8(padapter, REG_MCUFWDL) & BIT7) { 759 u8 reg_val = 0; 760 DBG_871X("+Reset Entry+\n"); 761 rtw_write8(padapter, REG_MCUFWDL, 0x00); 762 _8051Reset8723(padapter); 763 /* reset BB */ 764 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN); 765 reg_val &= ~(BIT(0) | BIT(1)); 766 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val); 767 /* reset RF */ 768 rtw_write8(padapter, REG_RF_CTRL, 0); 769 /* reset TRX path */ 770 rtw_write16(padapter, REG_CR, 0); 771 /* reset MAC, Digital Core */ 772 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); 773 reg_val &= ~(BIT(4) | BIT(7)); 774 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val); 775 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); 776 reg_val |= BIT(4) | BIT(7); 777 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, reg_val); 778 DBG_871X("-Reset Entry-\n"); 779 } 780 #endif /* CONFIG_WOWLAN */ 781 /* Disable Interrupt first. */ 782 /* rtw_hal_disable_interrupt(padapter); */ 783 784 ret = _InitPowerOn_8723BS(padapter); 785 if (_FAIL == ret) { 786 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n")); 787 return _FAIL; 788 } 789 790 rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0); 791 792 ret = rtl8723b_FirmwareDownload(padapter, false); 793 if (ret != _SUCCESS) { 794 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __func__)); 795 padapter->bFWReady = false; 796 pHalData->fw_ractrl = false; 797 return ret; 798 } else { 799 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n")); 800 padapter->bFWReady = true; 801 pHalData->fw_ractrl = true; 802 } 803 804 rtl8723b_InitializeFirmwareVars(padapter); 805 806 /* SIC_Init(padapter); */ 807 808 if (pwrctrlpriv->reg_rfoff) 809 pwrctrlpriv->rf_pwrstate = rf_off; 810 811 /* 2010/08/09 MH We need to check if we need to turnon or off RF after detecting */ 812 /* HW GPIO pin. Before PHY_RFConfig8192C. */ 813 HalDetectPwrDownMode(padapter); 814 815 /* Set RF type for BB/RF configuration */ 816 _InitRFType(padapter); 817 818 /* Save target channel */ 819 /* <Roger_Notes> Current Channel will be updated again later. */ 820 pHalData->CurrentChannel = 6; 821 822 #if (HAL_MAC_ENABLE == 1) 823 ret = PHY_MACConfig8723B(padapter); 824 if (ret != _SUCCESS) { 825 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n")); 826 return ret; 827 } 828 #endif 829 /* */ 830 /* d. Initialize BB related configurations. */ 831 /* */ 832 #if (HAL_BB_ENABLE == 1) 833 ret = PHY_BBConfig8723B(padapter); 834 if (ret != _SUCCESS) { 835 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n")); 836 return ret; 837 } 838 #endif 839 840 /* If RF is on, we need to init RF. Otherwise, skip the procedure. */ 841 /* We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */ 842 /* if (pHalData->eRFPowerState == eRfOn) */ 843 { 844 #if (HAL_RF_ENABLE == 1) 845 ret = PHY_RFConfig8723B(padapter); 846 if (ret != _SUCCESS) { 847 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n")); 848 return ret; 849 } 850 #endif 851 } 852 853 /* */ 854 /* Joseph Note: Keep RfRegChnlVal for later use. */ 855 /* */ 856 pHalData->RfRegChnlVal[0] = 857 PHY_QueryRFReg(padapter, (enum RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask); 858 pHalData->RfRegChnlVal[1] = 859 PHY_QueryRFReg(padapter, (enum RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask); 860 861 862 /* if (!pHalData->bMACFuncEnable) { */ 863 _InitQueueReservedPage(padapter); 864 _InitTxBufferBoundary(padapter); 865 866 /* init LLT after tx buffer boundary is defined */ 867 ret = rtl8723b_InitLLTTable(padapter); 868 if (_SUCCESS != ret) { 869 DBG_8192C("%s: Failed to init LLT Table!\n", __func__); 870 return _FAIL; 871 } 872 /* */ 873 _InitQueuePriority(padapter); 874 _InitPageBoundary(padapter); 875 _InitTransferPageSize(padapter); 876 877 /* Get Rx PHY status in order to report RSSI and others. */ 878 _InitDriverInfoSize(padapter, DRVINFO_SZ); 879 hal_init_macaddr(padapter); 880 _InitNetworkType(padapter); 881 _InitWMACSetting(padapter); 882 _InitAdaptiveCtrl(padapter); 883 _InitEDCA(padapter); 884 _InitRetryFunction(padapter); 885 _initSdioAggregationSetting(padapter); 886 _InitOperationMode(padapter); 887 rtl8723b_InitBeaconParameters(padapter); 888 _InitInterrupt(padapter); 889 _InitBurstPktLen_8723BS(padapter); 890 891 /* YJ, TODO */ 892 rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3); /* CCA */ 893 rtw_write8(padapter, 0x976, 0); /* hpfan_todo: 2nd CCA related */ 894 895 rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 896 rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */ 897 898 invalidate_cam_all(padapter); 899 900 rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel, 901 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE); 902 903 /* Record original value for template. This is arough data, we can only use the data */ 904 /* for power adjust. The value can not be adjustde according to different power!!! */ 905 /* pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */ 906 /* pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */ 907 908 rtl8723b_InitAntenna_Selection(padapter); 909 910 /* */ 911 /* Disable BAR, suggested by Scott */ 912 /* 2010.04.09 add by hpfan */ 913 /* */ 914 rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff); 915 916 /* HW SEQ CTRL */ 917 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */ 918 rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF); 919 920 921 /* */ 922 /* Configure SDIO TxRx Control to enable Rx DMA timer masking. */ 923 /* 2010.02.24. */ 924 /* */ 925 rtw_write32(padapter, SDIO_LOCAL_BASE | SDIO_REG_TX_CTRL, 0); 926 927 _RfPowerSave(padapter); 928 929 930 rtl8723b_InitHalDm(padapter); 931 932 /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */ 933 934 /* */ 935 /* Update current Tx FIFO page status. */ 936 /* */ 937 HalQueryTxBufferStatus8723BSdio(padapter); 938 HalQueryTxOQTBufferStatus8723BSdio(padapter); 939 pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace; 940 941 /* Enable MACTXEN/MACRXEN block */ 942 u1bTmp = rtw_read8(padapter, REG_CR); 943 u1bTmp |= (MACTXEN | MACRXEN); 944 rtw_write8(padapter, REG_CR, u1bTmp); 945 946 rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper); 947 948 /* ack for xmit mgmt frames. */ 949 rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL) | BIT(12)); 950 951 /* pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */ 952 953 { 954 pwrctrlpriv->rf_pwrstate = rf_on; 955 956 if (pwrctrlpriv->rf_pwrstate == rf_on) { 957 struct pwrctrl_priv *pwrpriv; 958 unsigned long start_time; 959 u8 restore_iqk_rst; 960 u8 b2Ant; 961 u8 h2cCmdBuf; 962 963 pwrpriv = adapter_to_pwrctl(padapter); 964 965 PHY_LCCalibrate_8723B(&pHalData->odmpriv); 966 967 /* Inform WiFi FW that it is the beginning of IQK */ 968 h2cCmdBuf = 1; 969 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); 970 971 start_time = jiffies; 972 do { 973 if (rtw_read8(padapter, 0x1e7) & 0x01) 974 break; 975 976 msleep(50); 977 } while (jiffies_to_msecs(jiffies - start_time) <= 400); 978 979 hal_btcoex_IQKNotify(padapter, true); 980 981 restore_iqk_rst = pwrpriv->bips_processing; 982 b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2; 983 PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path); 984 pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true; 985 986 hal_btcoex_IQKNotify(padapter, false); 987 988 /* Inform WiFi FW that it is the finish of IQK */ 989 h2cCmdBuf = 0; 990 FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf); 991 992 ODM_TXPowerTrackingCheck(&pHalData->odmpriv); 993 } 994 } 995 996 /* Init BT hw config. */ 997 hal_btcoex_InitHwConfig(padapter, false); 998 999 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __func__)); 1000 1001 return _SUCCESS; 1002 } 1003 1004 /* */ 1005 /* Description: */ 1006 /* RTL8723e card disable power sequence v003 which suggested by Scott. */ 1007 /* */ 1008 /* First created by tynli. 2011.01.28. */ 1009 /* */ 1010 static void CardDisableRTL8723BSdio(struct adapter *padapter) 1011 { 1012 u8 u1bTmp; 1013 u8 bMacPwrCtrlOn; 1014 u8 ret = _FAIL; 1015 1016 /* Run LPS WL RFOFF flow */ 1017 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow); 1018 if (ret == _FAIL) { 1019 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__); 1020 } 1021 1022 /* ==== Reset digital sequence ====== */ 1023 1024 u1bTmp = rtw_read8(padapter, REG_MCUFWDL); 1025 if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */ 1026 rtl8723b_FirmwareSelfReset(padapter); 1027 1028 /* Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */ 1029 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN + 1); 1030 u1bTmp &= ~BIT(2); /* 0x2[10], FEN_CPUEN */ 1031 rtw_write8(padapter, REG_SYS_FUNC_EN + 1, u1bTmp); 1032 1033 /* MCUFWDL 0x80[1:0]= 0 */ 1034 /* reset MCU ready status */ 1035 rtw_write8(padapter, REG_MCUFWDL, 0); 1036 1037 /* Reset MCU IO Wrapper, added by Roger, 2011.08.30 */ 1038 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1); 1039 u1bTmp &= ~BIT(0); 1040 rtw_write8(padapter, REG_RSV_CTRL + 1, u1bTmp); 1041 u1bTmp = rtw_read8(padapter, REG_RSV_CTRL + 1); 1042 u1bTmp |= BIT(0); 1043 rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp); 1044 1045 /* ==== Reset digital sequence end ====== */ 1046 1047 bMacPwrCtrlOn = false; /* Disable CMD53 R/W */ 1048 ret = false; 1049 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); 1050 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow); 1051 if (!ret) { 1052 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__); 1053 } 1054 } 1055 1056 static u32 rtl8723bs_hal_deinit(struct adapter *padapter) 1057 { 1058 struct dvobj_priv *psdpriv = padapter->dvobj; 1059 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; 1060 1061 if (padapter->hw_init_completed) { 1062 if (adapter_to_pwrctl(padapter)->bips_processing) { 1063 if (padapter->netif_up) { 1064 int cnt = 0; 1065 u8 val8 = 0; 1066 1067 DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__); 1068 1069 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3); 1070 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */ 1071 do { 1072 val8 = rtw_read8(padapter, REG_HMETFR); 1073 cnt++; 1074 DBG_871X("%s polling REG_HMETFR = 0x%x, cnt =%d\n", __func__, val8, cnt); 1075 mdelay(10); 1076 } while (cnt < 100 && (val8 != 0)); 1077 /* H2C done, enter 32k */ 1078 if (val8 == 0) { 1079 /* ser rpwm to enter 32k */ 1080 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1); 1081 val8 += 0x80; 1082 val8 |= BIT(0); 1083 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 1084 DBG_871X("%s: write rpwm =%02x\n", __func__, val8); 1085 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80; 1086 cnt = val8 = 0; 1087 do { 1088 val8 = rtw_read8(padapter, REG_CR); 1089 cnt++; 1090 DBG_871X("%s polling 0x100 = 0x%x, cnt =%d\n", __func__, val8, cnt); 1091 mdelay(10); 1092 } while (cnt < 100 && (val8 != 0xEA)); 1093 } else { 1094 DBG_871X( 1095 "MAC_1C0 =%08x, MAC_1C4 =%08x, MAC_1C8 =%08x, MAC_1CC =%08x\n", 1096 rtw_read32(padapter, 0x1c0), 1097 rtw_read32(padapter, 0x1c4), 1098 rtw_read32(padapter, 0x1c8), 1099 rtw_read32(padapter, 0x1cc) 1100 ); 1101 } 1102 1103 DBG_871X( 1104 "polling done when entering IPS, check result : 0x100 = 0x%x, cnt =%d, MAC_1cc = 0x%02x\n", 1105 rtw_read8(padapter, REG_CR), 1106 cnt, 1107 rtw_read8(padapter, REG_HMETFR) 1108 ); 1109 1110 adapter_to_pwrctl(padapter)->pre_ips_type = 0; 1111 1112 } else { 1113 pdbgpriv->dbg_carddisable_cnt++; 1114 CardDisableRTL8723BSdio(padapter); 1115 1116 adapter_to_pwrctl(padapter)->pre_ips_type = 1; 1117 } 1118 1119 } else { 1120 pdbgpriv->dbg_carddisable_cnt++; 1121 CardDisableRTL8723BSdio(padapter); 1122 } 1123 } else 1124 pdbgpriv->dbg_deinit_fail_cnt++; 1125 1126 return _SUCCESS; 1127 } 1128 1129 static u32 rtl8723bs_inirp_init(struct adapter *padapter) 1130 { 1131 return _SUCCESS; 1132 } 1133 1134 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter) 1135 { 1136 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+rtl8723bs_inirp_deinit\n")); 1137 1138 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-rtl8723bs_inirp_deinit\n")); 1139 1140 return _SUCCESS; 1141 } 1142 1143 static void rtl8723bs_init_default_value(struct adapter *padapter) 1144 { 1145 struct hal_com_data *pHalData; 1146 1147 1148 pHalData = GET_HAL_DATA(padapter); 1149 1150 rtl8723b_init_default_value(padapter); 1151 1152 /* interface related variable */ 1153 pHalData->SdioRxFIFOCnt = 0; 1154 } 1155 1156 static void rtl8723bs_interface_configure(struct adapter *padapter) 1157 { 1158 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1159 struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter); 1160 struct registry_priv *pregistrypriv = &padapter->registrypriv; 1161 bool bWiFiConfig = pregistrypriv->wifi_spec; 1162 1163 1164 pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID; 1165 pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID; 1166 pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID; 1167 1168 if (bWiFiConfig) 1169 pHalData->OutEpNumber = 2; 1170 else 1171 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE; 1172 1173 switch (pHalData->OutEpNumber) { 1174 case 3: 1175 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ | TX_SELE_NQ; 1176 break; 1177 case 2: 1178 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ; 1179 break; 1180 case 1: 1181 pHalData->OutEpQueueSel = TX_SELE_HQ; 1182 break; 1183 default: 1184 break; 1185 } 1186 1187 Hal_MappingOutPipe(padapter, pHalData->OutEpNumber); 1188 } 1189 1190 /* */ 1191 /* Description: */ 1192 /* We should set Efuse cell selection to WiFi cell in default. */ 1193 /* */ 1194 /* Assumption: */ 1195 /* PASSIVE_LEVEL */ 1196 /* */ 1197 /* Added by Roger, 2010.11.23. */ 1198 /* */ 1199 static void _EfuseCellSel(struct adapter *padapter) 1200 { 1201 u32 value32; 1202 1203 value32 = rtw_read32(padapter, EFUSE_TEST); 1204 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 1205 rtw_write32(padapter, EFUSE_TEST, value32); 1206 } 1207 1208 static void _ReadRFType(struct adapter *Adapter) 1209 { 1210 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1211 1212 #if DISABLE_BB_RF 1213 pHalData->rf_chip = RF_PSEUDO_11N; 1214 #else 1215 pHalData->rf_chip = RF_6052; 1216 #endif 1217 } 1218 1219 1220 static void Hal_EfuseParseMACAddr_8723BS( 1221 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 1222 ) 1223 { 1224 u16 i; 1225 u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00}; 1226 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1227 1228 if (AutoLoadFail) { 1229 /* sMacAddr[5] = (u8)GetRandomNumber(1, 254); */ 1230 for (i = 0; i < 6; i++) 1231 pEEPROM->mac_addr[i] = sMacAddr[i]; 1232 } else { 1233 /* Read Permanent MAC address */ 1234 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN); 1235 } 1236 /* NicIFSetMacAddress(padapter, padapter->PermanentAddress); */ 1237 1238 RT_TRACE( 1239 _module_hci_hal_init_c_, 1240 _drv_notice_, 1241 ( 1242 "Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n", 1243 pEEPROM->mac_addr[0], 1244 pEEPROM->mac_addr[1], 1245 pEEPROM->mac_addr[2], 1246 pEEPROM->mac_addr[3], 1247 pEEPROM->mac_addr[4], 1248 pEEPROM->mac_addr[5] 1249 ) 1250 ); 1251 } 1252 1253 static void Hal_EfuseParseBoardType_8723BS( 1254 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 1255 ) 1256 { 1257 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1258 1259 if (!AutoLoadFail) { 1260 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5; 1261 if (pHalData->BoardType == 0xFF) 1262 pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION & 0xE0) >> 5; 1263 } else 1264 pHalData->BoardType = 0; 1265 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType)); 1266 } 1267 1268 static void _ReadEfuseInfo8723BS(struct adapter *padapter) 1269 { 1270 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1271 u8 *hwinfo = NULL; 1272 1273 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n")); 1274 1275 /* */ 1276 /* This part read and parse the eeprom/efuse content */ 1277 /* */ 1278 1279 if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B) 1280 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n"); 1281 1282 hwinfo = pEEPROM->efuse_eeprom_data; 1283 1284 Hal_InitPGData(padapter, hwinfo); 1285 1286 Hal_EfuseParseIDCode(padapter, hwinfo); 1287 Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1288 1289 Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1290 1291 Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1292 Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1293 1294 /* */ 1295 /* Read Bluetooth co-exist and initialize */ 1296 /* */ 1297 Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1298 Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1299 Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1300 Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1301 Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1302 Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1303 Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1304 1305 Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1306 1307 #ifdef CONFIG_WOWLAN 1308 Hal_DetectWoWMode(padapter); 1309 #endif 1310 1311 Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag); 1312 1313 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n")); 1314 } 1315 1316 static void _ReadPROMContent(struct adapter *padapter) 1317 { 1318 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 1319 u8 eeValue; 1320 1321 eeValue = rtw_read8(padapter, REG_9346CR); 1322 /* To check system boot selection. */ 1323 pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false; 1324 pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true; 1325 1326 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, 1327 ("%s: 9346CR = 0x%02X, Boot from %s, Autoload %s\n", 1328 __func__, eeValue, 1329 (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"), 1330 (pEEPROM->bautoload_fail_flag ? "Fail" : "OK"))); 1331 1332 /* pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */ 1333 1334 _ReadEfuseInfo8723BS(padapter); 1335 } 1336 1337 static void _InitOtherVariable(struct adapter *Adapter) 1338 { 1339 } 1340 1341 /* */ 1342 /* Description: */ 1343 /* Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */ 1344 /* */ 1345 /* Assumption: */ 1346 /* PASSIVE_LEVEL (SDIO interface) */ 1347 /* */ 1348 /* */ 1349 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter) 1350 { 1351 u8 val8; 1352 unsigned long start; 1353 1354 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n")); 1355 1356 /* before access eFuse, make sure card enable has been called */ 1357 if (!padapter->hw_init_completed) 1358 _InitPowerOn_8723BS(padapter); 1359 1360 1361 val8 = rtw_read8(padapter, 0x4e); 1362 MSG_8192C("%s, 0x4e = 0x%x\n", __func__, val8); 1363 val8 |= BIT(6); 1364 rtw_write8(padapter, 0x4e, val8); 1365 1366 1367 start = jiffies; 1368 1369 _EfuseCellSel(padapter); 1370 _ReadRFType(padapter); 1371 _ReadPROMContent(padapter); 1372 _InitOtherVariable(padapter); 1373 1374 if (!padapter->hw_init_completed) { 1375 rtw_write8(padapter, 0x67, 0x00); /* for BT, Switch Ant control to BT */ 1376 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue, wifi ko module is loaded during booting, but wifi GUI is off */ 1377 } 1378 1379 1380 MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", jiffies_to_msecs(jiffies - start)); 1381 1382 return _SUCCESS; 1383 } 1384 1385 static void ReadAdapterInfo8723BS(struct adapter *padapter) 1386 { 1387 /* Read EEPROM size before call any EEPROM function */ 1388 padapter->EepromAddressSize = GetEEPROMSize8723B(padapter); 1389 1390 _ReadAdapterInfo8723BS(padapter); 1391 } 1392 1393 /* 1394 * If variable not handled here, 1395 * some variables will be processed in SetHwReg8723B() 1396 */ 1397 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) 1398 { 1399 u8 val8; 1400 1401 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 1402 struct wowlan_ioctl_param *poidparam; 1403 struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter); 1404 int res; 1405 u32 tmp; 1406 u16 len = 0; 1407 u8 trycnt = 100; 1408 u32 himr = 0; 1409 #if defined(CONFIG_WOWLAN) 1410 struct security_priv *psecuritypriv = &padapter->securitypriv; 1411 struct mlme_priv *pmlmepriv = &padapter->mlmepriv; 1412 struct sta_info *psta = NULL; 1413 u64 iv_low = 0, iv_high = 0; 1414 u8 mstatus = (*(u8 *)val); 1415 #endif 1416 #endif 1417 1418 switch (variable) { 1419 case HW_VAR_SET_RPWM: 1420 /* rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */ 1421 /* BIT0 value - 1: 32k, 0:40MHz. */ 1422 /* BIT6 value - 1: report cpwm value after success set, 0:do not report. */ 1423 /* BIT7 value - Toggle bit change. */ 1424 { 1425 val8 = *val; 1426 val8 &= 0xC1; 1427 rtw_write8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HRPWM1, val8); 1428 } 1429 break; 1430 case HW_VAR_SET_REQ_FW_PS: 1431 { 1432 u8 req_fw_ps = 0; 1433 req_fw_ps = rtw_read8(padapter, 0x8f); 1434 req_fw_ps |= 0x10; 1435 rtw_write8(padapter, 0x8f, req_fw_ps); 1436 } 1437 break; 1438 case HW_VAR_RXDMA_AGG_PG_TH: 1439 val8 = *val; 1440 break; 1441 1442 #ifdef CONFIG_WOWLAN 1443 case HW_VAR_WOWLAN: 1444 { 1445 poidparam = (struct wowlan_ioctl_param *)val; 1446 switch (poidparam->subcode) { 1447 case WOWLAN_ENABLE: 1448 DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n"); 1449 1450 /* backup data rate to register 0x8b for wowlan FW */ 1451 rtw_write8(padapter, 0x8d, 1); 1452 rtw_write8(padapter, 0x8c, 0); 1453 rtw_write8(padapter, 0x8f, 0x40); 1454 rtw_write8(padapter, 0x8b, 1455 rtw_read8(padapter, 0x2f0)); 1456 1457 /* 1. Download WOWLAN FW */ 1458 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n"); 1459 SetFwRelatedForWoWLAN8723b(padapter, true); 1460 1461 /* 2. RX DMA stop */ 1462 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n"); 1463 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN)); 1464 do { 1465 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) { 1466 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n"); 1467 break; 1468 } else { 1469 /* If RX_DMA is not idle, receive one pkt from DMA */ 1470 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp); 1471 len = le16_to_cpu(tmp); 1472 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len); 1473 if (len > 0) 1474 res = RecvOnePkt(padapter, len); 1475 else 1476 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len); 1477 1478 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res); 1479 } 1480 } while (trycnt--); 1481 if (trycnt == 0) 1482 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n"); 1483 1484 /* 3. Clear IMR and ISR */ 1485 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n"); 1486 tmp = 0; 1487 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp); 1488 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1489 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp); 1490 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp); 1491 1492 /* 4. Enable CPWM2 only */ 1493 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n"); 1494 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1495 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp); 1496 1497 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK; 1498 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr); 1499 1500 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1501 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp); 1502 1503 /* 5. Set Enable WOWLAN H2C command. */ 1504 DBG_871X_LEVEL(_drv_always_, "Set Enable WOWLan cmd\n"); 1505 rtl8723b_set_wowlan_cmd(padapter, 1); 1506 1507 /* 6. Check EnableWoWlan CMD is ready */ 1508 if (!pwrctl->wowlan_pno_enable) { 1509 DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n"); 1510 mstatus = rtw_read8(padapter, REG_WOW_CTRL); 1511 trycnt = 10; 1512 while (!(mstatus & BIT1) && trycnt > 1) { 1513 mstatus = rtw_read8(padapter, REG_WOW_CTRL); 1514 DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus); 1515 trycnt--; 1516 msleep(2); 1517 } 1518 } 1519 break; 1520 1521 case WOWLAN_DISABLE: 1522 DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n"); 1523 1524 psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv)); 1525 if (psta) 1526 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_DISCONNECT, psta->mac_id); 1527 else 1528 DBG_871X("psta is null\n"); 1529 1530 /* 1. Read wakeup reason */ 1531 pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON); 1532 DBG_871X_LEVEL( 1533 _drv_always_, 1534 "wakeup_reason: 0x%02x, mac_630 = 0x%08x, mac_634 = 0x%08x, mac_1c0 = 0x%08x, mac_1c4 = 0x%08x" 1535 ", mac_494 = 0x%08x, , mac_498 = 0x%08x, mac_49c = 0x%08x, mac_608 = 0x%08x, mac_4a0 = 0x%08x, mac_4a4 = 0x%08x\n" 1536 ", mac_1cc = 0x%08x, mac_2f0 = 0x%08x, mac_2f4 = 0x%08x, mac_2f8 = 0x%08x, mac_2fc = 0x%08x, mac_8c = 0x%08x", 1537 pwrctl->wowlan_wake_reason, 1538 rtw_read32(padapter, REG_WOWLAN_GTK_DBG1), 1539 rtw_read32(padapter, REG_WOWLAN_GTK_DBG2), 1540 rtw_read32(padapter, 0x1c0), 1541 rtw_read32(padapter, 0x1c4), 1542 rtw_read32(padapter, 0x494), 1543 rtw_read32(padapter, 0x498), 1544 rtw_read32(padapter, 0x49c), 1545 rtw_read32(padapter, 0x608), 1546 rtw_read32(padapter, 0x4a0), 1547 rtw_read32(padapter, 0x4a4), 1548 rtw_read32(padapter, 0x1cc), 1549 rtw_read32(padapter, 0x2f0), 1550 rtw_read32(padapter, 0x2f4), 1551 rtw_read32(padapter, 0x2f8), 1552 rtw_read32(padapter, 0x2fc), 1553 rtw_read32(padapter, 0x8c) 1554 ); 1555 #ifdef CONFIG_PNO_SET_DEBUG 1556 DBG_871X("0x1b9: 0x%02x, 0x632: 0x%02x\n", rtw_read8(padapter, 0x1b9), rtw_read8(padapter, 0x632)); 1557 DBG_871X("0x4fc: 0x%02x, 0x4fd: 0x%02x\n", rtw_read8(padapter, 0x4fc), rtw_read8(padapter, 0x4fd)); 1558 DBG_871X("TXDMA STATUS: 0x%08x\n", rtw_read32(padapter, REG_TXDMA_STATUS)); 1559 #endif 1560 1561 { 1562 /* 2. Set Disable WOWLAN H2C command. */ 1563 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n"); 1564 rtl8723b_set_wowlan_cmd(padapter, 0); 1565 1566 /* 3. Check Disable WoWlan CMD ready. */ 1567 DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n"); 1568 mstatus = rtw_read8(padapter, REG_WOW_CTRL); 1569 trycnt = 50; 1570 while (mstatus & BIT1 && trycnt > 1) { 1571 mstatus = rtw_read8(padapter, REG_WOW_CTRL); 1572 DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus); 1573 trycnt--; 1574 msleep(10); 1575 } 1576 1577 if (mstatus & BIT1) { 1578 DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n"); 1579 DBG_871X("Set 0x690 = 0x00\n"); 1580 rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL) & 0xf0)); 1581 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n"); 1582 rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN))); 1583 } 1584 1585 /* 3.1 read fw iv */ 1586 iv_low = rtw_read32(padapter, REG_TXPKTBUF_IV_LOW); 1587 /* only low two bytes is PN, check AES_IV macro for detail */ 1588 iv_low &= 0xffff; 1589 iv_high = rtw_read32(padapter, REG_TXPKTBUF_IV_HIGH); 1590 /* get the real packet number */ 1591 pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low; 1592 DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv); 1593 /* Update TX iv data. */ 1594 rtw_set_sec_pn(padapter); 1595 1596 /* 3.2 read GTK index and key */ 1597 if ( 1598 psecuritypriv->binstallKCK_KEK == true && 1599 psecuritypriv->dot11PrivacyAlgrthm == _AES_ 1600 ) { 1601 u8 gtk_keyindex = 0; 1602 u8 get_key[16]; 1603 /* read gtk key index */ 1604 gtk_keyindex = rtw_read8(padapter, 0x48c); 1605 1606 if (gtk_keyindex < 4) { 1607 psecuritypriv->dot118021XGrpKeyid = gtk_keyindex; 1608 read_cam(padapter, gtk_keyindex, get_key); 1609 memcpy(psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, get_key, 16); 1610 DBG_871X_LEVEL( 1611 _drv_always_, 1612 "GTK (%d) = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n", 1613 gtk_keyindex, 1614 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[0], 1615 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[1], 1616 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[2], 1617 psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[3] 1618 ); 1619 } else 1620 DBG_871X_LEVEL(_drv_always_, "GTK index =%d\n", gtk_keyindex); 1621 } 1622 1623 /* 4. Re-download Normal FW. */ 1624 DBG_871X_LEVEL(_drv_always_, "Re-download Normal FW!\n"); 1625 SetFwRelatedForWoWLAN8723b(padapter, false); 1626 } 1627 #ifdef CONFIG_GPIO_WAKEUP 1628 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n"); 1629 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1); 1630 #endif 1631 1632 /* 5. Download reserved pages and report media status if needed. */ 1633 if ( 1634 (pwrctl->wowlan_wake_reason != FWDecisionDisconnect) && 1635 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) && 1636 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) && 1637 (pwrctl->wowlan_wake_reason != Rx_DeAuth) 1638 ) { 1639 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT); 1640 if (psta) 1641 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_CONNECT, psta->mac_id); 1642 } 1643 #ifdef CONFIG_PNO_SUPPORT 1644 rtw_write8(padapter, 0x1b8, 0); 1645 DBG_871X("reset 0x1b8: %d\n", rtw_read8(padapter, 0x1b8)); 1646 rtw_write8(padapter, 0x1b9, 0); 1647 DBG_871X("reset 0x1b9: %d\n", rtw_read8(padapter, 0x1b9)); 1648 rtw_write8(padapter, REG_PNO_STATUS, 0); 1649 DBG_871X("reset REG_PNO_STATUS: %d\n", rtw_read8(padapter, REG_PNO_STATUS)); 1650 #endif 1651 break; 1652 1653 default: 1654 break; 1655 } 1656 } 1657 break; 1658 #endif /* CONFIG_WOWLAN */ 1659 #ifdef CONFIG_AP_WOWLAN 1660 case HW_VAR_AP_WOWLAN: 1661 { 1662 poidparam = (struct wowlan_ioctl_param *)val; 1663 switch (poidparam->subcode) { 1664 case WOWLAN_AP_ENABLE: 1665 DBG_871X("%s, WOWLAN_AP_ENABLE\n", __func__); 1666 /* 1. Download WOWLAN FW */ 1667 DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n"); 1668 SetFwRelatedForWoWLAN8723b(padapter, true); 1669 1670 /* 2. RX DMA stop */ 1671 DBG_871X_LEVEL(_drv_always_, "Pause DMA\n"); 1672 rtw_write32(padapter, REG_RXPKT_NUM, 1673 (rtw_read32(padapter, REG_RXPKT_NUM) | RW_RELEASE_EN)); 1674 do { 1675 if ((rtw_read32(padapter, REG_RXPKT_NUM) & RXDMA_IDLE)) { 1676 DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n"); 1677 break; 1678 } else { 1679 /* If RX_DMA is not idle, receive one pkt from DMA */ 1680 res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp); 1681 len = le16_to_cpu(tmp); 1682 1683 DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len); 1684 if (len > 0) 1685 res = RecvOnePkt(padapter, len); 1686 else 1687 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len); 1688 1689 DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res); 1690 } 1691 } while (trycnt--); 1692 1693 if (trycnt == 0) 1694 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n"); 1695 1696 /* 3. Clear IMR and ISR */ 1697 DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n"); 1698 tmp = 0; 1699 sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp); 1700 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1701 sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp); 1702 sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp); 1703 1704 /* 4. Enable CPWM2 only */ 1705 DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n"); 1706 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1707 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp); 1708 1709 himr = cpu_to_le32(SDIO_HIMR_DISABLED) | SDIO_HIMR_CPWM2_MSK; 1710 sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr); 1711 1712 sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp); 1713 DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp); 1714 1715 /* 5. Set Enable WOWLAN H2C command. */ 1716 DBG_871X_LEVEL(_drv_always_, "Set Enable AP WOWLan cmd\n"); 1717 rtl8723b_set_ap_wowlan_cmd(padapter, 1); 1718 /* 6. add some delay for H2C cmd ready */ 1719 msleep(10); 1720 1721 rtw_write8(padapter, REG_WOWLAN_WAKE_REASON, 0); 1722 break; 1723 case WOWLAN_AP_DISABLE: 1724 DBG_871X("%s, WOWLAN_AP_DISABLE\n", __func__); 1725 /* 1. Read wakeup reason */ 1726 pwrctl->wowlan_wake_reason = 1727 rtw_read8(padapter, REG_WOWLAN_WAKE_REASON); 1728 1729 DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n", 1730 pwrctl->wowlan_wake_reason); 1731 1732 /* 2. Set Disable WOWLAN H2C command. */ 1733 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n"); 1734 rtl8723b_set_ap_wowlan_cmd(padapter, 0); 1735 /* 6. add some delay for H2C cmd ready */ 1736 msleep(2); 1737 1738 DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n"); 1739 1740 rtw_write32(padapter, REG_RXPKT_NUM, 1741 (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN))); 1742 1743 SetFwRelatedForWoWLAN8723b(padapter, false); 1744 1745 #ifdef CONFIG_GPIO_WAKEUP 1746 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n"); 1747 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1); 1748 #endif /* CONFIG_GPIO_WAKEUP */ 1749 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT); 1750 issue_beacon(padapter, 0); 1751 break; 1752 default: 1753 break; 1754 } 1755 } 1756 break; 1757 #endif /* CONFIG_AP_WOWLAN */ 1758 case HW_VAR_DM_IN_LPS: 1759 rtl8723b_hal_dm_in_lps(padapter); 1760 break; 1761 default: 1762 SetHwReg8723B(padapter, variable, val); 1763 break; 1764 } 1765 } 1766 1767 /* 1768 * If variable not handled here, 1769 * some variables will be processed in GetHwReg8723B() 1770 */ 1771 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val) 1772 { 1773 switch (variable) { 1774 case HW_VAR_CPWM: 1775 *val = rtw_read8(padapter, SDIO_LOCAL_BASE | SDIO_REG_HCPWM1_8723B); 1776 break; 1777 1778 case HW_VAR_FW_PS_STATE: 1779 { 1780 /* 3. read dword 0x88 driver read fw ps state */ 1781 *((u16 *)val) = rtw_read16(padapter, 0x88); 1782 } 1783 break; 1784 default: 1785 GetHwReg8723B(padapter, variable, val); 1786 break; 1787 } 1788 } 1789 1790 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len) 1791 { 1792 switch (variable) { 1793 case HW_VAR_C2H_HANDLE: 1794 /* DBG_8192C("%s len =%d\n", __func__, len); */ 1795 C2HPacketHandler_8723B(padapter, pbuf, len); 1796 break; 1797 default: 1798 break; 1799 } 1800 } 1801 1802 /* */ 1803 /* Description: */ 1804 /* Query setting of specified variable. */ 1805 /* */ 1806 static u8 GetHalDefVar8723BSDIO( 1807 struct adapter *Adapter, enum HAL_DEF_VARIABLE eVariable, void *pValue 1808 ) 1809 { 1810 u8 bResult = _SUCCESS; 1811 1812 switch (eVariable) { 1813 case HAL_DEF_IS_SUPPORT_ANT_DIV: 1814 break; 1815 case HAL_DEF_CURRENT_ANTENNA: 1816 break; 1817 case HW_VAR_MAX_RX_AMPDU_FACTOR: 1818 /* Stanley@BB.SD3 suggests 16K can get stable performance */ 1819 /* coding by Lucas@20130730 */ 1820 *(u32 *)pValue = MAX_AMPDU_FACTOR_16K; 1821 break; 1822 default: 1823 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue); 1824 break; 1825 } 1826 1827 return bResult; 1828 } 1829 1830 /* */ 1831 /* Description: */ 1832 /* Change default setting of specified variable. */ 1833 /* */ 1834 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter, 1835 enum HAL_DEF_VARIABLE eVariable, void *pValue) 1836 { 1837 return SetHalDefVar8723B(Adapter, eVariable, pValue); 1838 } 1839 1840 void rtl8723bs_set_hal_ops(struct adapter *padapter) 1841 { 1842 struct hal_ops *pHalFunc = &padapter->HalFunc; 1843 1844 rtl8723b_set_hal_ops(pHalFunc); 1845 1846 pHalFunc->hal_init = &rtl8723bs_hal_init; 1847 pHalFunc->hal_deinit = &rtl8723bs_hal_deinit; 1848 1849 pHalFunc->inirp_init = &rtl8723bs_inirp_init; 1850 pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit; 1851 1852 pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv; 1853 pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv; 1854 1855 pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv; 1856 pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv; 1857 1858 pHalFunc->init_default_value = &rtl8723bs_init_default_value; 1859 pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure; 1860 pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS; 1861 1862 pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio; 1863 pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio; 1864 pHalFunc->check_ips_status = &CheckIPSStatus; 1865 #ifdef CONFIG_WOWLAN 1866 pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio; 1867 #endif 1868 pHalFunc->SetHwRegHandler = &SetHwReg8723BS; 1869 pHalFunc->GetHwRegHandler = &GetHwReg8723BS; 1870 pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B; 1871 pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO; 1872 pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO; 1873 1874 pHalFunc->hal_xmit = &rtl8723bs_hal_xmit; 1875 pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit; 1876 pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue; 1877 1878 #if defined(CONFIG_CHECK_BT_HANG) 1879 pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue; 1880 pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue; 1881 pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue; 1882 pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang; 1883 #endif 1884 } 1885