1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #define _RTL8723B_PHYCFG_C_ 8 9 #include <drv_types.h> 10 #include <rtw_debug.h> 11 #include <rtl8723b_hal.h> 12 13 14 /*---------------------------Define Local Constant---------------------------*/ 15 /* Channel switch:The size of command tables for switch channel*/ 16 #define MAX_PRECMD_CNT 16 17 #define MAX_RFDEPENDCMD_CNT 16 18 #define MAX_POSTCMD_CNT 16 19 20 #define MAX_DOZE_WAITING_TIMES_9x 64 21 22 /** 23 * Function: phy_CalculateBitShift 24 * 25 * OverView: Get shifted position of the BitMask 26 * 27 * Input: 28 * u32 BitMask, 29 * 30 * Output: none 31 * Return: u32 Return the shift bit bit position of the mask 32 */ 33 static u32 phy_CalculateBitShift(u32 BitMask) 34 { 35 u32 i; 36 37 for (i = 0; i <= 31; i++) { 38 if (((BitMask>>i) & 0x1) == 1) 39 break; 40 } 41 return i; 42 } 43 44 45 /** 46 * Function: PHY_QueryBBReg 47 * 48 * OverView: Read "specific bits" from BB register 49 * 50 * Input: 51 * struct adapter * Adapter, 52 * u32 RegAddr, The target address to be readback 53 * u32 BitMask The target bit position in the target address 54 * to be readback 55 * Output: None 56 * Return: u32 Data The readback register value 57 * Note: This function is equal to "GetRegSetting" in PHY programming guide 58 */ 59 u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask) 60 { 61 u32 OriginalValue, BitShift; 62 63 #if (DISABLE_BB_RF == 1) 64 return 0; 65 #endif 66 67 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */ 68 69 OriginalValue = rtw_read32(Adapter, RegAddr); 70 BitShift = phy_CalculateBitShift(BitMask); 71 72 return (OriginalValue & BitMask) >> BitShift; 73 74 } 75 76 77 /** 78 * Function: PHY_SetBBReg 79 * 80 * OverView: Write "Specific bits" to BB register (page 8~) 81 * 82 * Input: 83 * struct adapter * Adapter, 84 * u32 RegAddr, The target address to be modified 85 * u32 BitMask The target bit position in the target address 86 * to be modified 87 * u32 Data The new register value in the target bit position 88 * of the target address 89 * 90 * Output: None 91 * Return: None 92 * Note: This function is equal to "PutRegSetting" in PHY programming guide 93 */ 94 95 void PHY_SetBBReg_8723B( 96 struct adapter *Adapter, 97 u32 RegAddr, 98 u32 BitMask, 99 u32 Data 100 ) 101 { 102 /* u16 BBWaitCounter = 0; */ 103 u32 OriginalValue, BitShift; 104 105 #if (DISABLE_BB_RF == 1) 106 return; 107 #endif 108 109 /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */ 110 111 if (BitMask != bMaskDWord) { /* if not "double word" write */ 112 OriginalValue = rtw_read32(Adapter, RegAddr); 113 BitShift = phy_CalculateBitShift(BitMask); 114 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask)); 115 } 116 117 rtw_write32(Adapter, RegAddr, Data); 118 119 } 120 121 122 /* */ 123 /* 2. RF register R/W API */ 124 /* */ 125 126 static u32 phy_RFSerialRead_8723B( 127 struct adapter *Adapter, enum RF_PATH eRFPath, u32 Offset 128 ) 129 { 130 u32 retValue = 0; 131 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 132 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; 133 u32 NewOffset; 134 u32 tmplong2; 135 u8 RfPiEnable = 0; 136 u32 MaskforPhySet = 0; 137 int i = 0; 138 139 /* */ 140 /* Make sure RF register offset is correct */ 141 /* */ 142 Offset &= 0xff; 143 144 NewOffset = Offset; 145 146 if (eRFPath == RF_PATH_A) { 147 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); 148 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ 149 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); 150 } else { 151 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord); 152 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; /* T65 RF */ 153 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge)); 154 } 155 156 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord); 157 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge)); 158 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge); 159 160 udelay(10); 161 162 for (i = 0; i < 2; i++) 163 udelay(MAX_STALL_TIME); 164 udelay(10); 165 166 if (eRFPath == RF_PATH_A) 167 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8); 168 else if (eRFPath == RF_PATH_B) 169 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8); 170 171 if (RfPiEnable) { 172 /* Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */ 173 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData); 174 175 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */ 176 } else { 177 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */ 178 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData); 179 180 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-SI : 0x%x\n", retValue)); */ 181 } 182 return retValue; 183 184 } 185 186 /** 187 * Function: phy_RFSerialWrite_8723B 188 * 189 * OverView: Write data to RF register (page 8~) 190 * 191 * Input: 192 * struct adapter * Adapter, 193 * RF_PATH eRFPath, Radio path of A/B/C/D 194 * u32 Offset, The target address to be read 195 * u32 Data The new register Data in the target bit position 196 * of the target to be read 197 * 198 * Output: None 199 * Return: None 200 * Note: Threre are three types of serial operations: 201 * 1. Software serial write 202 * 2. Hardware LSSI-Low Speed Serial Interface 203 * 3. Hardware HSSI-High speed 204 * serial write. Driver need to implement (1) and (2). 205 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead() 206 * 207 * Note: For RF8256 only 208 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs 209 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10]) 210 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration 211 * programming guide" for more details. 212 * Thus, we define a sub-finction for RTL8526 register address conversion 213 * =========================================================== 214 * Register Mode RegCTL[1] RegCTL[0] Note 215 * (Reg00[12]) (Reg00[10]) 216 * =========================================================== 217 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) 218 * ------------------------------------------------------------------ 219 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) 220 * ------------------------------------------------------------------ 221 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 222 * ------------------------------------------------------------------ 223 * 224 *2008/09/02 MH Add 92S RF definition 225 * 226 * 227 * 228 */ 229 static void phy_RFSerialWrite_8723B( 230 struct adapter *Adapter, 231 enum RF_PATH eRFPath, 232 u32 Offset, 233 u32 Data 234 ) 235 { 236 u32 DataAndAddr = 0; 237 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 238 struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath]; 239 u32 NewOffset; 240 241 Offset &= 0xff; 242 243 /* */ 244 /* Switch page for 8256 RF IC */ 245 /* */ 246 NewOffset = Offset; 247 248 /* */ 249 /* Put write addr in [5:0] and write data in [31:16] */ 250 /* */ 251 /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */ 252 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; /* T65 RF */ 253 254 /* */ 255 /* Write Operation */ 256 /* */ 257 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 258 /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */ 259 260 } 261 262 263 /** 264 * Function: PHY_QueryRFReg 265 * 266 * OverView: Query "Specific bits" to RF register (page 8~) 267 * 268 * Input: 269 * struct adapter * Adapter, 270 * RF_PATH eRFPath, Radio path of A/B/C/D 271 * u32 RegAddr, The target address to be read 272 * u32 BitMask The target bit position in the target address 273 * to be read 274 * 275 * Output: None 276 * Return: u32 Readback value 277 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide 278 */ 279 u32 PHY_QueryRFReg_8723B( 280 struct adapter *Adapter, 281 u8 eRFPath, 282 u32 RegAddr, 283 u32 BitMask 284 ) 285 { 286 u32 Original_Value, BitShift; 287 288 #if (DISABLE_BB_RF == 1) 289 return 0; 290 #endif 291 292 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr); 293 BitShift = phy_CalculateBitShift(BitMask); 294 295 return (Original_Value & BitMask) >> BitShift; 296 } 297 298 /** 299 * Function: PHY_SetRFReg 300 * 301 * OverView: Write "Specific bits" to RF register (page 8~) 302 * 303 * Input: 304 * struct adapter * Adapter, 305 * RF_PATH eRFPath, Radio path of A/B/C/D 306 * u32 RegAddr, The target address to be modified 307 * u32 BitMask The target bit position in the target address 308 * to be modified 309 * u32 Data The new register Data in the target bit position 310 * of the target address 311 * 312 * Output: None 313 * Return: None 314 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide 315 */ 316 void PHY_SetRFReg_8723B( 317 struct adapter *Adapter, 318 u8 eRFPath, 319 u32 RegAddr, 320 u32 BitMask, 321 u32 Data 322 ) 323 { 324 u32 Original_Value, BitShift; 325 326 #if (DISABLE_BB_RF == 1) 327 return; 328 #endif 329 330 /* RF data is 12 bits only */ 331 if (BitMask != bRFRegOffsetMask) { 332 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr); 333 BitShift = phy_CalculateBitShift(BitMask); 334 Data = ((Original_Value & (~BitMask)) | (Data<<BitShift)); 335 } 336 337 phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data); 338 } 339 340 341 /* */ 342 /* 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */ 343 /* */ 344 345 346 /*----------------------------------------------------------------------------- 347 * Function: PHY_MACConfig8192C 348 * 349 * Overview: Condig MAC by header file or parameter file. 350 * 351 * Input: NONE 352 * 353 * Output: NONE 354 * 355 * Return: NONE 356 * 357 * Revised History: 358 * When Who Remark 359 * 08/12/2008 MHC Create Version 0. 360 * 361 *--------------------------------------------------------------------------- 362 */ 363 s32 PHY_MACConfig8723B(struct adapter *Adapter) 364 { 365 int rtStatus = _SUCCESS; 366 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 367 s8 *pszMACRegFile; 368 s8 sz8723MACRegFile[] = RTL8723B_PHY_MACREG; 369 370 371 pszMACRegFile = sz8723MACRegFile; 372 373 /* */ 374 /* Config MAC */ 375 /* */ 376 rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile); 377 if (rtStatus == _FAIL) { 378 ODM_ReadAndConfig_MP_8723B_MAC_REG(&pHalData->odmpriv); 379 rtStatus = _SUCCESS; 380 } 381 382 return rtStatus; 383 } 384 385 /** 386 * Function: phy_InitBBRFRegisterDefinition 387 * 388 * OverView: Initialize Register definition offset for Radio Path A/B/C/D 389 * 390 * Input: 391 * struct adapter * Adapter, 392 * 393 * Output: None 394 * Return: None 395 * Note: The initialization value is constant and it should never be changes 396 */ 397 static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter) 398 { 399 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 400 401 /* RF Interface Sowrtware Control */ 402 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 LSBs if read 32-bit from 0x870 */ 403 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 404 405 /* RF Interface Output (and Enable) */ 406 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x860 */ 407 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /* 16 LSBs if read 32-bit from 0x864 */ 408 409 /* RF Interface (Output and) Enable */ 410 pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 411 pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 412 413 pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ 414 pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 415 416 pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; /* wire control parameter2 */ 417 pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; /* wire control parameter2 */ 418 419 /* Tranceiver Readback LSSI/HSPI mode */ 420 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 421 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 422 pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback; 423 pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback; 424 425 } 426 427 static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter) 428 { 429 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 430 int rtStatus = _SUCCESS; 431 u8 sz8723BBRegFile[] = RTL8723B_PHY_REG; 432 u8 sz8723AGCTableFile[] = RTL8723B_AGC_TAB; 433 u8 sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG; 434 u8 sz8723BBRegMpFile[] = RTL8723B_PHY_REG_MP; 435 u8 sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT; 436 u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile = NULL, *pszRFTxPwrLmtFile = NULL; 437 438 pszBBRegFile = sz8723BBRegFile; 439 pszAGCTableFile = sz8723AGCTableFile; 440 pszBBRegPgFile = sz8723BBBRegPgFile; 441 pszBBRegMpFile = sz8723BBRegMpFile; 442 pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile; 443 444 /* Read Tx Power Limit File */ 445 PHY_InitTxPowerLimit(Adapter); 446 if ( 447 Adapter->registrypriv.RegEnableTxPowerLimit == 1 || 448 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1) 449 ) { 450 if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) { 451 if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0)) 452 rtStatus = _FAIL; 453 } 454 455 if (rtStatus != _SUCCESS) { 456 DBG_871X("%s():Read Tx power limit fail\n", __func__); 457 goto phy_BB8190_Config_ParaFile_Fail; 458 } 459 } 460 461 /* */ 462 /* 1. Read PHY_REG.TXT BB INIT!! */ 463 /* */ 464 if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) == 465 _FAIL) { 466 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG)) 467 rtStatus = _FAIL; 468 } 469 470 if (rtStatus != _SUCCESS) { 471 DBG_8192C("%s():Write BB Reg Fail!!", __func__); 472 goto phy_BB8190_Config_ParaFile_Fail; 473 } 474 475 /* If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */ 476 PHY_InitTxPowerByRate(Adapter); 477 if ( 478 Adapter->registrypriv.RegEnableTxPowerByRate == 1 || 479 (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2) 480 ) { 481 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) == 482 _FAIL) { 483 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG)) 484 rtStatus = _FAIL; 485 } 486 487 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) 488 PHY_TxPowerByRateConfiguration(Adapter); 489 490 if ( 491 Adapter->registrypriv.RegEnableTxPowerLimit == 1 || 492 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1) 493 ) 494 PHY_ConvertTxPowerLimitToPowerIndex(Adapter); 495 496 if (rtStatus != _SUCCESS) { 497 DBG_8192C("%s():BB_PG Reg Fail!!\n", __func__); 498 } 499 } 500 501 /* */ 502 /* 2. Read BB AGC table Initialization */ 503 /* */ 504 if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile, 505 CONFIG_BB_AGC_TAB) == _FAIL) { 506 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB)) 507 rtStatus = _FAIL; 508 } 509 510 if (rtStatus != _SUCCESS) { 511 DBG_8192C("%s():AGC Table Fail\n", __func__); 512 goto phy_BB8190_Config_ParaFile_Fail; 513 } 514 515 phy_BB8190_Config_ParaFile_Fail: 516 517 return rtStatus; 518 } 519 520 521 int PHY_BBConfig8723B(struct adapter *Adapter) 522 { 523 int rtStatus = _SUCCESS; 524 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 525 u32 RegVal; 526 u8 CrystalCap; 527 528 phy_InitBBRFRegisterDefinition(Adapter); 529 530 /* Enable BB and RF */ 531 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN); 532 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1)); 533 534 rtw_write32(Adapter, 0x948, 0x280); /* Others use Antenna S1 */ 535 536 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB); 537 538 msleep(1); 539 540 PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780); 541 542 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB); 543 544 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80); 545 546 /* */ 547 /* Config BB and AGC */ 548 /* */ 549 rtStatus = phy_BB8723b_Config_ParaFile(Adapter); 550 551 /* 0x2C[23:18] = 0x2C[17:12] = CrystalCap */ 552 CrystalCap = pHalData->CrystalCap & 0x3F; 553 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6))); 554 555 return rtStatus; 556 } 557 558 static void phy_LCK_8723B(struct adapter *Adapter) 559 { 560 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); 561 PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01); 562 mdelay(200); 563 PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); 564 } 565 566 int PHY_RFConfig8723B(struct adapter *Adapter) 567 { 568 int rtStatus = _SUCCESS; 569 570 /* */ 571 /* RF config */ 572 /* */ 573 rtStatus = PHY_RF6052_Config8723B(Adapter); 574 575 phy_LCK_8723B(Adapter); 576 /* PHY_BB8723B_Config_1T(Adapter); */ 577 578 return rtStatus; 579 } 580 581 /************************************************************************************************************** 582 * Description: 583 * The low-level interface to set TxAGC , called by both MP and Normal Driver. 584 * 585 * <20120830, Kordan> 586 **************************************************************************************************************/ 587 588 void PHY_SetTxPowerIndex_8723B( 589 struct adapter *Adapter, 590 u32 PowerIndex, 591 u8 RFPath, 592 u8 Rate 593 ) 594 { 595 if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) { 596 switch (Rate) { 597 case MGN_1M: 598 PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex); 599 break; 600 case MGN_2M: 601 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex); 602 break; 603 case MGN_5_5M: 604 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex); 605 break; 606 case MGN_11M: 607 PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex); 608 break; 609 610 case MGN_6M: 611 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex); 612 break; 613 case MGN_9M: 614 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex); 615 break; 616 case MGN_12M: 617 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex); 618 break; 619 case MGN_18M: 620 PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex); 621 break; 622 623 case MGN_24M: 624 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex); 625 break; 626 case MGN_36M: 627 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex); 628 break; 629 case MGN_48M: 630 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex); 631 break; 632 case MGN_54M: 633 PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex); 634 break; 635 636 case MGN_MCS0: 637 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex); 638 break; 639 case MGN_MCS1: 640 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex); 641 break; 642 case MGN_MCS2: 643 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex); 644 break; 645 case MGN_MCS3: 646 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex); 647 break; 648 649 case MGN_MCS4: 650 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex); 651 break; 652 case MGN_MCS5: 653 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex); 654 break; 655 case MGN_MCS6: 656 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex); 657 break; 658 case MGN_MCS7: 659 PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex); 660 break; 661 662 default: 663 DBG_871X("Invalid Rate!!\n"); 664 break; 665 } 666 } else { 667 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n")); 668 } 669 } 670 671 u8 PHY_GetTxPowerIndex_8723B( 672 struct adapter *padapter, 673 u8 RFPath, 674 u8 Rate, 675 enum CHANNEL_WIDTH BandWidth, 676 u8 Channel 677 ) 678 { 679 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 680 s8 txPower = 0, powerDiffByRate = 0, limit = 0; 681 bool bIn24G = false; 682 683 /* DBG_871X("===>%s\n", __func__); */ 684 685 txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel, &bIn24G); 686 powerDiffByRate = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate); 687 688 limit = phy_get_tx_pwr_lmt( 689 padapter, 690 padapter->registrypriv.RegPwrTblSel, 691 (u8)(!bIn24G), 692 pHalData->CurrentChannelBW, 693 RFPath, 694 Rate, 695 pHalData->CurrentChannel 696 ); 697 698 powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate; 699 txPower += powerDiffByRate; 700 701 txPower += PHY_GetTxPowerTrackingOffset(padapter, RFPath, Rate); 702 703 if (txPower > MAX_POWER_INDEX) 704 txPower = MAX_POWER_INDEX; 705 706 /* DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath == 0)?'A':'B'), Channel, txPower, txPower)); */ 707 return (u8) txPower; 708 } 709 710 void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel) 711 { 712 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 713 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 714 pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable; 715 u8 RFPath = ODM_RF_PATH_A; 716 717 if (pHalData->AntDivCfg) {/* antenna diversity Enable */ 718 RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B); 719 } else { /* antenna diversity disable */ 720 RFPath = pHalData->ant_path; 721 } 722 723 RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8723B()\n")); 724 725 PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath); 726 727 RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8723B()\n")); 728 } 729 730 void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel) 731 { 732 } 733 734 static void phy_SetRegBW_8723B( 735 struct adapter *Adapter, enum CHANNEL_WIDTH CurrentBW 736 ) 737 { 738 u16 RegRfMod_BW, u2tmp = 0; 739 RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B); 740 741 switch (CurrentBW) { 742 case CHANNEL_WIDTH_20: 743 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); /* BIT 7 = 0, BIT 8 = 0 */ 744 break; 745 746 case CHANNEL_WIDTH_40: 747 u2tmp = RegRfMod_BW | BIT7; 748 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /* BIT 7 = 1, BIT 8 = 0 */ 749 break; 750 751 case CHANNEL_WIDTH_80: 752 u2tmp = RegRfMod_BW | BIT8; 753 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /* BIT 7 = 0, BIT 8 = 1 */ 754 break; 755 756 default: 757 DBG_871X("phy_PostSetBWMode8723B(): unknown Bandwidth: %#X\n", CurrentBW); 758 break; 759 } 760 } 761 762 static u8 phy_GetSecondaryChnl_8723B(struct adapter *Adapter) 763 { 764 u8 SCSettingOf40 = 0, SCSettingOf20 = 0; 765 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 766 767 RT_TRACE( 768 _module_hal_init_c_, 769 _drv_info_, 770 ( 771 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n", 772 pHalData->CurrentChannelBW, 773 pHalData->nCur80MhzPrimeSC, 774 pHalData->nCur40MhzPrimeSC 775 ) 776 ); 777 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { 778 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 779 SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ; 780 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 781 SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ; 782 else 783 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); 784 785 if ( 786 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && 787 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 788 ) 789 SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ; 790 else if ( 791 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && 792 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 793 ) 794 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 795 else if ( 796 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && 797 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 798 ) 799 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 800 else if ( 801 (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && 802 (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 803 ) 804 SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ; 805 else 806 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); 807 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { 808 RT_TRACE( 809 _module_hal_init_c_, 810 _drv_info_, 811 ( 812 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n", 813 pHalData->CurrentChannelBW, 814 pHalData->nCur40MhzPrimeSC 815 ) 816 ); 817 818 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 819 SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ; 820 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 821 SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ; 822 else 823 RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n")); 824 } 825 826 RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20))); 827 return (SCSettingOf40 << 4) | SCSettingOf20; 828 } 829 830 static void phy_PostSetBwMode8723B(struct adapter *Adapter) 831 { 832 u8 SubChnlNum = 0; 833 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 834 835 836 /* 3 Set Reg668 Reg440 BW */ 837 phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW); 838 839 /* 3 Set Reg483 */ 840 SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter); 841 rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum); 842 843 /* 3 */ 844 /* 3<2>Set PHY related register */ 845 /* 3 */ 846 switch (pHalData->CurrentChannelBW) { 847 /* 20 MHz channel*/ 848 case CHANNEL_WIDTH_20: 849 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); 850 851 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0); 852 853 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */ 854 855 PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0); 856 break; 857 858 /* 40 MHz channel*/ 859 case CHANNEL_WIDTH_40: 860 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); 861 862 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1); 863 864 /* Set Control channel to upper or lower. These settings are required only for 40MHz */ 865 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1)); 866 867 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC); 868 869 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */ 870 871 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1); 872 873 break; 874 875 default: 876 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\ 877 , pHalData->CurrentChannelBW));*/ 878 break; 879 } 880 881 /* 3<3>Set RF related register */ 882 PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW); 883 } 884 885 static void phy_SwChnl8723B(struct adapter *padapter) 886 { 887 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 888 u8 channelToSW = pHalData->CurrentChannel; 889 890 if (pHalData->rf_chip == RF_PSEUDO_11N) { 891 /* RT_TRACE(COMP_MLME, DBG_LOUD, ("phy_SwChnl8723B: return for PSEUDO\n")); */ 892 return; 893 } 894 pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW); 895 PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 896 PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]); 897 898 DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW); 899 } 900 901 static void phy_SwChnlAndSetBwMode8723B(struct adapter *Adapter) 902 { 903 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 904 905 /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */ 906 if (Adapter->bNotifyChannelChange) { 907 DBG_871X("[%s] bSwChnl =%d, ch =%d, bSetChnlBW =%d, bw =%d\n", 908 __func__, 909 pHalData->bSwChnl, 910 pHalData->CurrentChannel, 911 pHalData->bSetChnlBW, 912 pHalData->CurrentChannelBW); 913 } 914 915 if (Adapter->bDriverStopped || Adapter->bSurpriseRemoved) 916 return; 917 918 if (pHalData->bSwChnl) { 919 phy_SwChnl8723B(Adapter); 920 pHalData->bSwChnl = false; 921 } 922 923 if (pHalData->bSetChnlBW) { 924 phy_PostSetBwMode8723B(Adapter); 925 pHalData->bSetChnlBW = false; 926 } 927 928 PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel); 929 } 930 931 static void PHY_HandleSwChnlAndSetBW8723B( 932 struct adapter *Adapter, 933 bool bSwitchChannel, 934 bool bSetBandWidth, 935 u8 ChannelNum, 936 enum CHANNEL_WIDTH ChnlWidth, 937 enum EXTCHNL_OFFSET ExtChnlOffsetOf40MHz, 938 enum EXTCHNL_OFFSET ExtChnlOffsetOf80MHz, 939 u8 CenterFrequencyIndex1 940 ) 941 { 942 /* static bool bInitialzed = false; */ 943 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 944 u8 tmpChannel = pHalData->CurrentChannel; 945 enum CHANNEL_WIDTH tmpBW = pHalData->CurrentChannelBW; 946 u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC; 947 u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC; 948 u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1; 949 950 /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */ 951 952 /* check is swchnl or setbw */ 953 if (!bSwitchChannel && !bSetBandWidth) { 954 DBG_871X("PHY_HandleSwChnlAndSetBW8812: not switch channel and not set bandwidth\n"); 955 return; 956 } 957 958 /* skip change for channel or bandwidth is the same */ 959 if (bSwitchChannel) { 960 /* if (pHalData->CurrentChannel != ChannelNum) */ 961 { 962 if (HAL_IsLegalChannel(Adapter, ChannelNum)) 963 pHalData->bSwChnl = true; 964 } 965 } 966 967 if (bSetBandWidth) 968 pHalData->bSetChnlBW = true; 969 970 if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) { 971 /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */ 972 return; 973 } 974 975 976 if (pHalData->bSwChnl) { 977 pHalData->CurrentChannel = ChannelNum; 978 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum; 979 } 980 981 982 if (pHalData->bSetChnlBW) { 983 pHalData->CurrentChannelBW = ChnlWidth; 984 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz; 985 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz; 986 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1; 987 } 988 989 /* Switch workitem or set timer to do switch channel or setbandwidth operation */ 990 if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) { 991 phy_SwChnlAndSetBwMode8723B(Adapter); 992 } else { 993 if (pHalData->bSwChnl) { 994 pHalData->CurrentChannel = tmpChannel; 995 pHalData->CurrentCenterFrequencyIndex1 = tmpChannel; 996 } 997 998 if (pHalData->bSetChnlBW) { 999 pHalData->CurrentChannelBW = tmpBW; 1000 pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC; 1001 pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC; 1002 pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1; 1003 } 1004 } 1005 } 1006 1007 void PHY_SetBWMode8723B( 1008 struct adapter *Adapter, 1009 enum CHANNEL_WIDTH Bandwidth, /* 20M or 40M */ 1010 unsigned char Offset /* Upper, Lower, or Don't care */ 1011 ) 1012 { 1013 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1014 1015 PHY_HandleSwChnlAndSetBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel); 1016 } 1017 1018 /* Call after initialization */ 1019 void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel) 1020 { 1021 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, false, channel, 0, 0, 0, channel); 1022 } 1023 1024 void PHY_SetSwChnlBWMode8723B( 1025 struct adapter *Adapter, 1026 u8 channel, 1027 enum CHANNEL_WIDTH Bandwidth, 1028 u8 Offset40, 1029 u8 Offset80 1030 ) 1031 { 1032 /* DBG_871X("%s() ===>\n", __func__); */ 1033 1034 PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Offset40, Offset80, channel); 1035 1036 /* DBG_871X("<==%s()\n", __func__); */ 1037 } 1038