1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 #define _HAL_INIT_C_ 16 17 #include <linux/firmware.h> 18 #include <linux/slab.h> 19 #include <drv_types.h> 20 #include <rtw_debug.h> 21 #include <rtl8723b_hal.h> 22 #include "hal_com_h2c.h" 23 24 static void _FWDownloadEnable(struct adapter *padapter, bool enable) 25 { 26 u8 tmp, count = 0; 27 28 if (enable) { 29 /* 8051 enable */ 30 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 31 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04); 32 33 tmp = rtw_read8(padapter, REG_MCUFWDL); 34 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); 35 36 do { 37 tmp = rtw_read8(padapter, REG_MCUFWDL); 38 if (tmp & 0x01) 39 break; 40 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); 41 msleep(1); 42 } while (count++ < 100); 43 44 if (count > 0) 45 DBG_871X("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count); 46 47 /* 8051 reset */ 48 tmp = rtw_read8(padapter, REG_MCUFWDL+2); 49 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); 50 } else { 51 /* MCU firmware download disable. */ 52 tmp = rtw_read8(padapter, REG_MCUFWDL); 53 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe); 54 } 55 } 56 57 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize) 58 { 59 int ret = _SUCCESS; 60 61 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */ 62 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */ 63 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */ 64 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; 65 u32 remainSize_p1 = 0, remainSize_p2 = 0; 66 u8 *bufferPtr = buffer; 67 u32 i = 0, offset = 0; 68 69 /* printk("====>%s %d\n", __func__, __LINE__); */ 70 71 /* 3 Phase #1 */ 72 blockCount_p1 = buffSize / blockSize_p1; 73 remainSize_p1 = buffSize % blockSize_p1; 74 75 if (blockCount_p1) { 76 RT_TRACE( 77 _module_hal_init_c_, 78 _drv_notice_, 79 ( 80 "_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n", 81 buffSize, 82 blockSize_p1, 83 blockCount_p1, 84 remainSize_p1 85 ) 86 ); 87 } 88 89 for (i = 0; i < blockCount_p1; i++) { 90 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1))); 91 if (ret == _FAIL) { 92 printk("====>%s %d i:%d\n", __func__, __LINE__, i); 93 goto exit; 94 } 95 } 96 97 /* 3 Phase #2 */ 98 if (remainSize_p1) { 99 offset = blockCount_p1 * blockSize_p1; 100 101 blockCount_p2 = remainSize_p1/blockSize_p2; 102 remainSize_p2 = remainSize_p1%blockSize_p2; 103 104 if (blockCount_p2) { 105 RT_TRACE( 106 _module_hal_init_c_, 107 _drv_notice_, 108 ( 109 "_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n", 110 (buffSize-offset), 111 blockSize_p2, 112 blockCount_p2, 113 remainSize_p2 114 ) 115 ); 116 } 117 118 } 119 120 /* 3 Phase #3 */ 121 if (remainSize_p2) { 122 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); 123 124 blockCount_p3 = remainSize_p2 / blockSize_p3; 125 126 RT_TRACE(_module_hal_init_c_, _drv_notice_, 127 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n", 128 (buffSize-offset), blockSize_p3, blockCount_p3)); 129 130 for (i = 0; i < blockCount_p3; i++) { 131 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); 132 133 if (ret == _FAIL) { 134 printk("====>%s %d i:%d\n", __func__, __LINE__, i); 135 goto exit; 136 } 137 } 138 } 139 exit: 140 return ret; 141 } 142 143 static int _PageWrite( 144 struct adapter *padapter, 145 u32 page, 146 void *buffer, 147 u32 size 148 ) 149 { 150 u8 value8; 151 u8 u8Page = (u8) (page & 0x07); 152 153 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page; 154 rtw_write8(padapter, REG_MCUFWDL+2, value8); 155 156 return _BlockWrite(padapter, buffer, size); 157 } 158 159 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size) 160 { 161 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */ 162 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */ 163 int ret = _SUCCESS; 164 u32 pageNums, remainSize; 165 u32 page, offset; 166 u8 *bufferPtr = buffer; 167 168 pageNums = size / MAX_DLFW_PAGE_SIZE; 169 /* RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */ 170 remainSize = size % MAX_DLFW_PAGE_SIZE; 171 172 for (page = 0; page < pageNums; page++) { 173 offset = page * MAX_DLFW_PAGE_SIZE; 174 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE); 175 176 if (ret == _FAIL) { 177 printk("====>%s %d\n", __func__, __LINE__); 178 goto exit; 179 } 180 } 181 182 if (remainSize) { 183 offset = pageNums * MAX_DLFW_PAGE_SIZE; 184 page = pageNums; 185 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize); 186 187 if (ret == _FAIL) { 188 printk("====>%s %d\n", __func__, __LINE__); 189 goto exit; 190 } 191 } 192 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n")); 193 194 exit: 195 return ret; 196 } 197 198 void _8051Reset8723(struct adapter *padapter) 199 { 200 u8 cpu_rst; 201 u8 io_rst; 202 203 204 /* Reset 8051(WLMCU) IO wrapper */ 205 /* 0x1c[8] = 0 */ 206 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */ 207 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1); 208 io_rst &= ~BIT(0); 209 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst); 210 211 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 212 cpu_rst &= ~BIT(2); 213 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst); 214 215 /* Enable 8051 IO wrapper */ 216 /* 0x1c[8] = 1 */ 217 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1); 218 io_rst |= BIT(0); 219 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst); 220 221 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 222 cpu_rst |= BIT(2); 223 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst); 224 225 DBG_8192C("%s: Finish\n", __func__); 226 } 227 228 u8 g_fwdl_chksum_fail = 0; 229 230 static s32 polling_fwdl_chksum( 231 struct adapter *adapter, u32 min_cnt, u32 timeout_ms 232 ) 233 { 234 s32 ret = _FAIL; 235 u32 value32; 236 unsigned long start = jiffies; 237 u32 cnt = 0; 238 239 /* polling CheckSum report */ 240 do { 241 cnt++; 242 value32 = rtw_read32(adapter, REG_MCUFWDL); 243 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped) 244 break; 245 yield(); 246 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt); 247 248 if (!(value32 & FWDL_ChkSum_rpt)) { 249 goto exit; 250 } 251 252 if (g_fwdl_chksum_fail) { 253 DBG_871X("%s: fwdl test case: fwdl_chksum_fail\n", __func__); 254 g_fwdl_chksum_fail--; 255 goto exit; 256 } 257 258 ret = _SUCCESS; 259 260 exit: 261 DBG_871X( 262 "%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", 263 __func__, 264 (ret == _SUCCESS) ? "OK" : "Fail", 265 cnt, 266 jiffies_to_msecs(jiffies-start), 267 value32 268 ); 269 270 return ret; 271 } 272 273 u8 g_fwdl_wintint_rdy_fail = 0; 274 275 static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms) 276 { 277 s32 ret = _FAIL; 278 u32 value32; 279 unsigned long start = jiffies; 280 u32 cnt = 0; 281 282 value32 = rtw_read32(adapter, REG_MCUFWDL); 283 value32 |= MCUFWDL_RDY; 284 value32 &= ~WINTINI_RDY; 285 rtw_write32(adapter, REG_MCUFWDL, value32); 286 287 _8051Reset8723(adapter); 288 289 /* polling for FW ready */ 290 do { 291 cnt++; 292 value32 = rtw_read32(adapter, REG_MCUFWDL); 293 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped) 294 break; 295 yield(); 296 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt); 297 298 if (!(value32 & WINTINI_RDY)) { 299 goto exit; 300 } 301 302 if (g_fwdl_wintint_rdy_fail) { 303 DBG_871X("%s: fwdl test case: wintint_rdy_fail\n", __func__); 304 g_fwdl_wintint_rdy_fail--; 305 goto exit; 306 } 307 308 ret = _SUCCESS; 309 310 exit: 311 DBG_871X( 312 "%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", 313 __func__, 314 (ret == _SUCCESS) ? "OK" : "Fail", 315 cnt, 316 jiffies_to_msecs(jiffies-start), 317 value32 318 ); 319 320 return ret; 321 } 322 323 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0) 324 325 void rtl8723b_FirmwareSelfReset(struct adapter *padapter) 326 { 327 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 328 u8 u1bTmp; 329 u8 Delay = 100; 330 331 if ( 332 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01))) 333 ) { /* after 88C Fw v33.1 */ 334 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */ 335 rtw_write8(padapter, REG_HMETFR+3, 0x20); 336 337 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 338 while (u1bTmp & BIT2) { 339 Delay--; 340 if (Delay == 0) 341 break; 342 udelay(50); 343 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 344 } 345 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("-%s: 8051 reset success (%d)\n", __func__, Delay)); 346 347 if (Delay == 0) { 348 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("%s: Force 8051 reset!!!\n", __func__)); 349 /* force firmware reset */ 350 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 351 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); 352 } 353 } 354 } 355 356 /* */ 357 /* Description: */ 358 /* Download 8192C firmware code. */ 359 /* */ 360 /* */ 361 s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw) 362 { 363 s32 rtStatus = _SUCCESS; 364 u8 write_fw = 0; 365 unsigned long fwdl_start_time; 366 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 367 struct rt_firmware *pFirmware; 368 struct rt_firmware *pBTFirmware; 369 struct rt_firmware_hdr *pFwHdr = NULL; 370 u8 *pFirmwareBuf; 371 u32 FirmwareLen; 372 const struct firmware *fw; 373 struct device *device = dvobj_to_dev(padapter->dvobj); 374 u8 *fwfilepath; 375 struct dvobj_priv *psdpriv = padapter->dvobj; 376 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; 377 u8 tmp_ps; 378 379 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__)); 380 #ifdef CONFIG_WOWLAN 381 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("+%s, bUsedWoWLANFw:%d\n", __func__, bUsedWoWLANFw)); 382 #endif 383 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL); 384 if (!pFirmware) 385 return _FAIL; 386 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL); 387 if (!pBTFirmware) { 388 kfree(pFirmware); 389 return _FAIL; 390 } 391 tmp_ps = rtw_read8(padapter, 0xa3); 392 tmp_ps &= 0xf8; 393 tmp_ps |= 0x02; 394 /* 1. write 0xA3[:2:0] = 3b'010 */ 395 rtw_write8(padapter, 0xa3, tmp_ps); 396 /* 2. read power_state = 0xA0[1:0] */ 397 tmp_ps = rtw_read8(padapter, 0xa0); 398 tmp_ps &= 0x03; 399 if (tmp_ps != 0x01) { 400 DBG_871X(FUNC_ADPT_FMT" tmp_ps =%x\n", FUNC_ADPT_ARG(padapter), tmp_ps); 401 pdbgpriv->dbg_downloadfw_pwr_state_cnt++; 402 } 403 404 #ifdef CONFIG_WOWLAN 405 if (bUsedWoWLANFw) 406 fwfilepath = "rtlwifi/rtl8723bs_wowlan.bin"; 407 else 408 #endif /* CONFIG_WOWLAN */ 409 fwfilepath = "rtlwifi/rtl8723bs_nic.bin"; 410 411 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath); 412 413 rtStatus = request_firmware(&fw, fwfilepath, device); 414 if (rtStatus) { 415 pr_err("Request firmware failed with error 0x%x\n", rtStatus); 416 rtStatus = _FAIL; 417 goto exit; 418 } 419 420 if (!fw) { 421 pr_err("Firmware %s not available\n", fwfilepath); 422 rtStatus = _FAIL; 423 goto exit; 424 } 425 426 if (fw->size > FW_8723B_SIZE) { 427 rtStatus = _FAIL; 428 RT_TRACE( 429 _module_hal_init_c_, 430 _drv_err_, 431 ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE) 432 ); 433 goto exit; 434 } 435 436 pFirmware->szFwBuffer = kzalloc(fw->size, GFP_KERNEL); 437 if (!pFirmware->szFwBuffer) { 438 rtStatus = _FAIL; 439 goto exit; 440 } 441 442 memcpy(pFirmware->szFwBuffer, fw->data, fw->size); 443 pFirmware->ulFwLength = fw->size; 444 release_firmware(fw); 445 if (pFirmware->ulFwLength > FW_8723B_SIZE) { 446 rtStatus = _FAIL; 447 DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", pFirmware->ulFwLength, FW_8723B_SIZE); 448 goto release_fw1; 449 } 450 451 pFirmwareBuf = pFirmware->szFwBuffer; 452 FirmwareLen = pFirmware->ulFwLength; 453 454 /* To Check Fw header. Added by tynli. 2009.12.04. */ 455 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf; 456 457 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->Version); 458 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->Subversion); 459 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->Signature); 460 461 DBG_871X( 462 "%s: fw_ver =%x fw_subver =%04x sig = 0x%x, Month =%02x, Date =%02x, Hour =%02x, Minute =%02x\n", 463 __func__, 464 pHalData->FirmwareVersion, 465 pHalData->FirmwareSubVersion, 466 pHalData->FirmwareSignature, 467 pFwHdr->Month, 468 pFwHdr->Date, 469 pFwHdr->Hour, 470 pFwHdr->Minute 471 ); 472 473 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) { 474 DBG_871X("%s(): Shift for fw header!\n", __func__); 475 /* Shift 32 bytes for FW header */ 476 pFirmwareBuf = pFirmwareBuf + 32; 477 FirmwareLen = FirmwareLen - 32; 478 } 479 480 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */ 481 /* or it will cause download Fw fail. 2010.02.01. by tynli. */ 482 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */ 483 rtw_write8(padapter, REG_MCUFWDL, 0x00); 484 rtl8723b_FirmwareSelfReset(padapter); 485 } 486 487 _FWDownloadEnable(padapter, true); 488 fwdl_start_time = jiffies; 489 while ( 490 !padapter->bDriverStopped && 491 !padapter->bSurpriseRemoved && 492 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500) 493 ) { 494 /* reset FWDL chksum */ 495 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt); 496 497 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); 498 if (rtStatus != _SUCCESS) 499 continue; 500 501 rtStatus = polling_fwdl_chksum(padapter, 5, 50); 502 if (rtStatus == _SUCCESS) 503 break; 504 } 505 _FWDownloadEnable(padapter, false); 506 if (_SUCCESS != rtStatus) 507 goto fwdl_stat; 508 509 rtStatus = _FWFreeToGo(padapter, 10, 200); 510 if (_SUCCESS != rtStatus) 511 goto fwdl_stat; 512 513 fwdl_stat: 514 DBG_871X( 515 "FWDL %s. write_fw:%u, %dms\n", 516 (rtStatus == _SUCCESS)?"success":"fail", 517 write_fw, 518 jiffies_to_msecs(jiffies - fwdl_start_time) 519 ); 520 521 exit: 522 kfree(pFirmware->szFwBuffer); 523 kfree(pFirmware); 524 release_fw1: 525 kfree(pBTFirmware); 526 DBG_871X(" <=== rtl8723b_FirmwareDownload()\n"); 527 return rtStatus; 528 } 529 530 void rtl8723b_InitializeFirmwareVars(struct adapter *padapter) 531 { 532 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 533 534 /* Init Fw LPS related. */ 535 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = false; 536 537 /* Init H2C cmd. */ 538 rtw_write8(padapter, REG_HMETFR, 0x0f); 539 540 /* Init H2C counter. by tynli. 2009.12.09. */ 541 pHalData->LastHMEBoxNum = 0; 542 /* pHalData->H2CQueueHead = 0; */ 543 /* pHalData->H2CQueueTail = 0; */ 544 /* pHalData->H2CStopInsertQueue = false; */ 545 } 546 547 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 548 /* */ 549 550 /* */ 551 /* Description: Prepare some information to Fw for WoWLAN. */ 552 /* (1) Download wowlan Fw. */ 553 /* (2) Download RSVD page packets. */ 554 /* (3) Enable AP offload if needed. */ 555 /* */ 556 /* 2011.04.12 by tynli. */ 557 /* */ 558 void SetFwRelatedForWoWLAN8723b( 559 struct adapter *padapter, u8 bHostIsGoingtoSleep 560 ) 561 { 562 int status = _FAIL; 563 /* */ 564 /* 1. Before WoWLAN we need to re-download WoWLAN Fw. */ 565 /* */ 566 status = rtl8723b_FirmwareDownload(padapter, bHostIsGoingtoSleep); 567 if (status != _SUCCESS) { 568 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware failed!!\n"); 569 return; 570 } else { 571 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware Success !!\n"); 572 } 573 /* */ 574 /* 2. Re-Init the variables about Fw related setting. */ 575 /* */ 576 rtl8723b_InitializeFirmwareVars(padapter); 577 } 578 #endif /* CONFIG_WOWLAN */ 579 580 static void rtl8723b_free_hal_data(struct adapter *padapter) 581 { 582 } 583 584 /* */ 585 /* Efuse related code */ 586 /* */ 587 static u8 hal_EfuseSwitchToBank( 588 struct adapter *padapter, u8 bank, bool bPseudoTest 589 ) 590 { 591 u8 bRet = false; 592 u32 value32 = 0; 593 #ifdef HAL_EFUSE_MEMORY 594 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 595 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 596 #endif 597 598 599 DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank); 600 if (bPseudoTest) { 601 #ifdef HAL_EFUSE_MEMORY 602 pEfuseHal->fakeEfuseBank = bank; 603 #else 604 fakeEfuseBank = bank; 605 #endif 606 bRet = true; 607 } else { 608 value32 = rtw_read32(padapter, EFUSE_TEST); 609 bRet = true; 610 switch (bank) { 611 case 0: 612 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 613 break; 614 case 1: 615 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); 616 break; 617 case 2: 618 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); 619 break; 620 case 3: 621 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); 622 break; 623 default: 624 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 625 bRet = false; 626 break; 627 } 628 rtw_write32(padapter, EFUSE_TEST, value32); 629 } 630 631 return bRet; 632 } 633 634 static void Hal_GetEfuseDefinition( 635 struct adapter *padapter, 636 u8 efuseType, 637 u8 type, 638 void *pOut, 639 bool bPseudoTest 640 ) 641 { 642 switch (type) { 643 case TYPE_EFUSE_MAX_SECTION: 644 { 645 u8 *pMax_section; 646 pMax_section = pOut; 647 648 if (efuseType == EFUSE_WIFI) 649 *pMax_section = EFUSE_MAX_SECTION_8723B; 650 else 651 *pMax_section = EFUSE_BT_MAX_SECTION; 652 } 653 break; 654 655 case TYPE_EFUSE_REAL_CONTENT_LEN: 656 { 657 u16 *pu2Tmp; 658 pu2Tmp = pOut; 659 660 if (efuseType == EFUSE_WIFI) 661 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B; 662 else 663 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN; 664 } 665 break; 666 667 case TYPE_AVAILABLE_EFUSE_BYTES_BANK: 668 { 669 u16 *pu2Tmp; 670 pu2Tmp = pOut; 671 672 if (efuseType == EFUSE_WIFI) 673 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES); 674 else 675 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK); 676 } 677 break; 678 679 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: 680 { 681 u16 *pu2Tmp; 682 pu2Tmp = pOut; 683 684 if (efuseType == EFUSE_WIFI) 685 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES); 686 else 687 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3)); 688 } 689 break; 690 691 case TYPE_EFUSE_MAP_LEN: 692 { 693 u16 *pu2Tmp; 694 pu2Tmp = pOut; 695 696 if (efuseType == EFUSE_WIFI) 697 *pu2Tmp = EFUSE_MAX_MAP_LEN; 698 else 699 *pu2Tmp = EFUSE_BT_MAP_LEN; 700 } 701 break; 702 703 case TYPE_EFUSE_PROTECT_BYTES_BANK: 704 { 705 u8 *pu1Tmp; 706 pu1Tmp = pOut; 707 708 if (efuseType == EFUSE_WIFI) 709 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES; 710 else 711 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK; 712 } 713 break; 714 715 case TYPE_EFUSE_CONTENT_LEN_BANK: 716 { 717 u16 *pu2Tmp; 718 pu2Tmp = pOut; 719 720 if (efuseType == EFUSE_WIFI) 721 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B; 722 else 723 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN; 724 } 725 break; 726 727 default: 728 { 729 u8 *pu1Tmp; 730 pu1Tmp = pOut; 731 *pu1Tmp = 0; 732 } 733 break; 734 } 735 } 736 737 #define VOLTAGE_V25 0x03 738 #define LDOE25_SHIFT 28 739 740 /* */ 741 /* The following is for compile ok */ 742 /* That should be merged with the original in the future */ 743 /* */ 744 #define EFUSE_ACCESS_ON_8723 0x69 /* For RTL8723 only. */ 745 #define EFUSE_ACCESS_OFF_8723 0x00 /* For RTL8723 only. */ 746 #define REG_EFUSE_ACCESS_8723 0x00CF /* Efuse access protection for RTL8723 */ 747 748 /* */ 749 static void Hal_BT_EfusePowerSwitch( 750 struct adapter *padapter, u8 bWrite, u8 PwrState 751 ) 752 { 753 u8 tempval; 754 if (PwrState == true) { 755 /* enable BT power cut */ 756 /* 0x6A[14] = 1 */ 757 tempval = rtw_read8(padapter, 0x6B); 758 tempval |= BIT(6); 759 rtw_write8(padapter, 0x6B, tempval); 760 761 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ 762 /* So don't wirte 0x6A[14]= 1 and 0x6A[15]= 0 together! */ 763 msleep(1); 764 /* disable BT output isolation */ 765 /* 0x6A[15] = 0 */ 766 tempval = rtw_read8(padapter, 0x6B); 767 tempval &= ~BIT(7); 768 rtw_write8(padapter, 0x6B, tempval); 769 } else { 770 /* enable BT output isolation */ 771 /* 0x6A[15] = 1 */ 772 tempval = rtw_read8(padapter, 0x6B); 773 tempval |= BIT(7); 774 rtw_write8(padapter, 0x6B, tempval); 775 776 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ 777 /* So don't wirte 0x6A[14]= 1 and 0x6A[15]= 0 together! */ 778 779 /* disable BT power cut */ 780 /* 0x6A[14] = 1 */ 781 tempval = rtw_read8(padapter, 0x6B); 782 tempval &= ~BIT(6); 783 rtw_write8(padapter, 0x6B, tempval); 784 } 785 786 } 787 static void Hal_EfusePowerSwitch( 788 struct adapter *padapter, u8 bWrite, u8 PwrState 789 ) 790 { 791 u8 tempval; 792 u16 tmpV16; 793 794 795 if (PwrState == true) { 796 /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */ 797 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */ 798 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL); 799 if (tempval & BIT(0)) { /* SDIO local register is suspend */ 800 u8 count = 0; 801 802 803 tempval &= ~BIT(0); 804 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval); 805 806 /* check 0x86[1:0]= 10'2h, wait power state to leave suspend */ 807 do { 808 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL); 809 tempval &= 0x3; 810 if (tempval == 0x02) 811 break; 812 813 count++; 814 if (count >= 100) 815 break; 816 817 mdelay(10); 818 } while (1); 819 820 if (count >= 100) { 821 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86 =%#X\n", 822 FUNC_ADPT_ARG(padapter), tempval); 823 } else { 824 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86 =%#X\n", 825 FUNC_ADPT_ARG(padapter), tempval); 826 } 827 } 828 829 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723); 830 831 /* Reset: 0x0000h[28], default valid */ 832 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN); 833 if (!(tmpV16 & FEN_ELDR)) { 834 tmpV16 |= FEN_ELDR; 835 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16); 836 } 837 838 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */ 839 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR); 840 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) { 841 tmpV16 |= (LOADER_CLK_EN | ANA8M); 842 rtw_write16(padapter, REG_SYS_CLKR, tmpV16); 843 } 844 845 if (bWrite == true) { 846 /* Enable LDO 2.5V before read/write action */ 847 tempval = rtw_read8(padapter, EFUSE_TEST+3); 848 tempval &= 0x0F; 849 tempval |= (VOLTAGE_V25 << 4); 850 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80)); 851 852 /* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */ 853 } 854 } else { 855 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 856 857 if (bWrite == true) { 858 /* Disable LDO 2.5V after read/write action */ 859 tempval = rtw_read8(padapter, EFUSE_TEST+3); 860 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F)); 861 } 862 863 } 864 } 865 866 static void hal_ReadEFuse_WiFi( 867 struct adapter *padapter, 868 u16 _offset, 869 u16 _size_byte, 870 u8 *pbuf, 871 bool bPseudoTest 872 ) 873 { 874 #ifdef HAL_EFUSE_MEMORY 875 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 876 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 877 #endif 878 u8 *efuseTbl = NULL; 879 u16 eFuse_Addr = 0; 880 u8 offset, wden; 881 u8 efuseHeader, efuseExtHdr, efuseData; 882 u16 i, total, used; 883 u8 efuse_usage = 0; 884 885 /* DBG_871X("YJ: ====>%s():_offset =%d _size_byte =%d bPseudoTest =%d\n", __func__, _offset, _size_byte, bPseudoTest); */ 886 /* */ 887 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ 888 /* */ 889 if ((_offset+_size_byte) > EFUSE_MAX_MAP_LEN) { 890 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); 891 return; 892 } 893 894 efuseTbl = (u8 *)rtw_malloc(EFUSE_MAX_MAP_LEN); 895 if (efuseTbl == NULL) { 896 DBG_8192C("%s: alloc efuseTbl fail!\n", __func__); 897 return; 898 } 899 /* 0xff will be efuse default value instead of 0x00. */ 900 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN); 901 902 903 #ifdef DEBUG 904 if (0) { 905 for (i = 0; i < 256; i++) 906 efuse_OneByteRead(padapter, i, &efuseTbl[i], false); 907 DBG_871X("Efuse Content:\n"); 908 for (i = 0; i < 256; i++) { 909 if (i % 16 == 0) 910 printk("\n"); 911 printk("%02X ", efuseTbl[i]); 912 } 913 printk("\n"); 914 } 915 #endif 916 917 918 /* switch bank back to bank 0 for later BT and wifi use. */ 919 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 920 921 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { 922 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); 923 if (efuseHeader == 0xFF) { 924 DBG_8192C("%s: data end at address =%#x\n", __func__, eFuse_Addr-1); 925 break; 926 } 927 /* DBG_8192C("%s: efuse[0x%X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseHeader); */ 928 929 /* Check PG header for section num. */ 930 if (EXT_HEADER(efuseHeader)) { /* extended header */ 931 offset = GET_HDR_OFFSET_2_0(efuseHeader); 932 /* DBG_8192C("%s: extended header offset = 0x%X\n", __func__, offset); */ 933 934 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); 935 /* DBG_8192C("%s: efuse[0x%X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseExtHdr); */ 936 if (ALL_WORDS_DISABLED(efuseExtHdr)) 937 continue; 938 939 offset |= ((efuseExtHdr & 0xF0) >> 1); 940 wden = (efuseExtHdr & 0x0F); 941 } else { 942 offset = ((efuseHeader >> 4) & 0x0f); 943 wden = (efuseHeader & 0x0f); 944 } 945 /* DBG_8192C("%s: Offset =%d Worden = 0x%X\n", __func__, offset, wden); */ 946 947 if (offset < EFUSE_MAX_SECTION_8723B) { 948 u16 addr; 949 /* Get word enable value from PG header */ 950 /* DBG_8192C("%s: Offset =%d Worden = 0x%X\n", __func__, offset, wden); */ 951 952 addr = offset * PGPKT_DATA_SIZE; 953 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 954 /* Check word enable condition in the section */ 955 if (!(wden & (0x01<<i))) { 956 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 957 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ 958 efuseTbl[addr] = efuseData; 959 960 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 961 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ 962 efuseTbl[addr+1] = efuseData; 963 } 964 addr += 2; 965 } 966 } else { 967 DBG_8192C(KERN_ERR "%s: offset(%d) is illegal!!\n", __func__, offset); 968 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2; 969 } 970 } 971 972 /* Copy from Efuse map to output pointer memory!!! */ 973 for (i = 0; i < _size_byte; i++) 974 pbuf[i] = efuseTbl[_offset+i]; 975 976 #ifdef DEBUG 977 if (1) { 978 DBG_871X("Efuse Realmap:\n"); 979 for (i = 0; i < _size_byte; i++) { 980 if (i % 16 == 0) 981 printk("\n"); 982 printk("%02X ", pbuf[i]); 983 } 984 printk("\n"); 985 } 986 #endif 987 /* Calculate Efuse utilization */ 988 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); 989 used = eFuse_Addr - 1; 990 efuse_usage = (u8)((used*100)/total); 991 if (bPseudoTest) { 992 #ifdef HAL_EFUSE_MEMORY 993 pEfuseHal->fakeEfuseUsedBytes = used; 994 #else 995 fakeEfuseUsedBytes = used; 996 #endif 997 } else { 998 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used); 999 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage); 1000 } 1001 1002 kfree(efuseTbl); 1003 } 1004 1005 static void hal_ReadEFuse_BT( 1006 struct adapter *padapter, 1007 u16 _offset, 1008 u16 _size_byte, 1009 u8 *pbuf, 1010 bool bPseudoTest 1011 ) 1012 { 1013 #ifdef HAL_EFUSE_MEMORY 1014 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1015 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1016 #endif 1017 u8 *efuseTbl; 1018 u8 bank; 1019 u16 eFuse_Addr; 1020 u8 efuseHeader, efuseExtHdr, efuseData; 1021 u8 offset, wden; 1022 u16 i, total, used; 1023 u8 efuse_usage; 1024 1025 1026 /* */ 1027 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ 1028 /* */ 1029 if ((_offset+_size_byte) > EFUSE_BT_MAP_LEN) { 1030 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); 1031 return; 1032 } 1033 1034 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); 1035 if (efuseTbl == NULL) { 1036 DBG_8192C("%s: efuseTbl malloc fail!\n", __func__); 1037 return; 1038 } 1039 /* 0xff will be efuse default value instead of 0x00. */ 1040 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN); 1041 1042 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest); 1043 1044 for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */ 1045 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { 1046 DBG_8192C("%s: hal_EfuseSwitchToBank Fail!!\n", __func__); 1047 goto exit; 1048 } 1049 1050 eFuse_Addr = 0; 1051 1052 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { 1053 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); 1054 if (efuseHeader == 0xFF) 1055 break; 1056 DBG_8192C("%s: efuse[%#X]= 0x%02x (header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseHeader); 1057 1058 /* Check PG header for section num. */ 1059 if (EXT_HEADER(efuseHeader)) { /* extended header */ 1060 offset = GET_HDR_OFFSET_2_0(efuseHeader); 1061 DBG_8192C("%s: extended header offset_2_0 = 0x%X\n", __func__, offset); 1062 1063 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); 1064 DBG_8192C("%s: efuse[%#X]= 0x%02x (ext header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseExtHdr); 1065 if (ALL_WORDS_DISABLED(efuseExtHdr)) 1066 continue; 1067 1068 1069 offset |= ((efuseExtHdr & 0xF0) >> 1); 1070 wden = (efuseExtHdr & 0x0F); 1071 } else { 1072 offset = ((efuseHeader >> 4) & 0x0f); 1073 wden = (efuseHeader & 0x0f); 1074 } 1075 1076 if (offset < EFUSE_BT_MAX_SECTION) { 1077 u16 addr; 1078 1079 /* Get word enable value from PG header */ 1080 DBG_8192C("%s: Offset =%d Worden =%#X\n", __func__, offset, wden); 1081 1082 addr = offset * PGPKT_DATA_SIZE; 1083 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1084 /* Check word enable condition in the section */ 1085 if (!(wden & (0x01<<i))) { 1086 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 1087 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); 1088 efuseTbl[addr] = efuseData; 1089 1090 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 1091 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); 1092 efuseTbl[addr+1] = efuseData; 1093 } 1094 addr += 2; 1095 } 1096 } else { 1097 DBG_8192C("%s: offset(%d) is illegal!!\n", __func__, offset); 1098 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2; 1099 } 1100 } 1101 1102 if ((eFuse_Addr-1) < total) { 1103 DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr-1); 1104 break; 1105 } 1106 } 1107 1108 /* switch bank back to bank 0 for later BT and wifi use. */ 1109 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 1110 1111 /* Copy from Efuse map to output pointer memory!!! */ 1112 for (i = 0; i < _size_byte; i++) 1113 pbuf[i] = efuseTbl[_offset+i]; 1114 1115 /* */ 1116 /* Calculate Efuse utilization. */ 1117 /* */ 1118 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); 1119 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1; 1120 DBG_8192C("%s: bank(%d) data end at %#x , used =%d\n", __func__, bank, eFuse_Addr-1, used); 1121 efuse_usage = (u8)((used*100)/total); 1122 if (bPseudoTest) { 1123 #ifdef HAL_EFUSE_MEMORY 1124 pEfuseHal->fakeBTEfuseUsedBytes = used; 1125 #else 1126 fakeBTEfuseUsedBytes = used; 1127 #endif 1128 } else { 1129 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used); 1130 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage); 1131 } 1132 1133 exit: 1134 kfree(efuseTbl); 1135 } 1136 1137 static void Hal_ReadEFuse( 1138 struct adapter *padapter, 1139 u8 efuseType, 1140 u16 _offset, 1141 u16 _size_byte, 1142 u8 *pbuf, 1143 bool bPseudoTest 1144 ) 1145 { 1146 if (efuseType == EFUSE_WIFI) 1147 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest); 1148 else 1149 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest); 1150 } 1151 1152 static u16 hal_EfuseGetCurrentSize_WiFi( 1153 struct adapter *padapter, bool bPseudoTest 1154 ) 1155 { 1156 #ifdef HAL_EFUSE_MEMORY 1157 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1158 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1159 #endif 1160 u16 efuse_addr = 0; 1161 u16 start_addr = 0; /* for debug */ 1162 u8 hoffset = 0, hworden = 0; 1163 u8 efuse_data, word_cnts = 0; 1164 u32 count = 0; /* for debug */ 1165 1166 1167 if (bPseudoTest) { 1168 #ifdef HAL_EFUSE_MEMORY 1169 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes; 1170 #else 1171 efuse_addr = (u16)fakeEfuseUsedBytes; 1172 #endif 1173 } else 1174 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); 1175 1176 start_addr = efuse_addr; 1177 DBG_8192C("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr); 1178 1179 /* switch bank back to bank 0 for later BT and wifi use. */ 1180 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 1181 1182 count = 0; 1183 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1184 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) { 1185 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr); 1186 goto error; 1187 } 1188 1189 if (efuse_data == 0xFF) 1190 break; 1191 1192 if ((start_addr != 0) && (efuse_addr == start_addr)) { 1193 count++; 1194 DBG_8192C(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X = 0x%02X not 0xFF!!(%d times)\n", 1195 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count); 1196 1197 efuse_data = 0xFF; 1198 if (count < 4) { 1199 /* try again! */ 1200 1201 if (count > 2) { 1202 /* try again form address 0 */ 1203 efuse_addr = 0; 1204 start_addr = 0; 1205 } 1206 1207 continue; 1208 } 1209 1210 goto error; 1211 } 1212 1213 if (EXT_HEADER(efuse_data)) { 1214 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1215 efuse_addr++; 1216 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1217 if (ALL_WORDS_DISABLED(efuse_data)) 1218 continue; 1219 1220 hoffset |= ((efuse_data & 0xF0) >> 1); 1221 hworden = efuse_data & 0x0F; 1222 } else { 1223 hoffset = (efuse_data>>4) & 0x0F; 1224 hworden = efuse_data & 0x0F; 1225 } 1226 1227 word_cnts = Efuse_CalculateWordCnts(hworden); 1228 efuse_addr += (word_cnts*2)+1; 1229 } 1230 1231 if (bPseudoTest) { 1232 #ifdef HAL_EFUSE_MEMORY 1233 pEfuseHal->fakeEfuseUsedBytes = efuse_addr; 1234 #else 1235 fakeEfuseUsedBytes = efuse_addr; 1236 #endif 1237 } else 1238 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); 1239 1240 goto exit; 1241 1242 error: 1243 /* report max size to prevent wirte efuse */ 1244 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest); 1245 1246 exit: 1247 DBG_8192C("%s: CurrentSize =%d\n", __func__, efuse_addr); 1248 1249 return efuse_addr; 1250 } 1251 1252 static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest) 1253 { 1254 #ifdef HAL_EFUSE_MEMORY 1255 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1256 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1257 #endif 1258 u16 btusedbytes; 1259 u16 efuse_addr; 1260 u8 bank, startBank; 1261 u8 hoffset = 0, hworden = 0; 1262 u8 efuse_data, word_cnts = 0; 1263 u16 retU2 = 0; 1264 1265 if (bPseudoTest) { 1266 #ifdef HAL_EFUSE_MEMORY 1267 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes; 1268 #else 1269 btusedbytes = fakeBTEfuseUsedBytes; 1270 #endif 1271 } else 1272 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes); 1273 1274 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN)); 1275 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN)); 1276 1277 DBG_8192C("%s: start from bank =%d addr = 0x%X\n", __func__, startBank, efuse_addr); 1278 1279 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest); 1280 1281 for (bank = startBank; bank < 3; bank++) { 1282 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { 1283 DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank); 1284 /* bank = EFUSE_MAX_BANK; */ 1285 break; 1286 } 1287 1288 /* only when bank is switched we have to reset the efuse_addr. */ 1289 if (bank != startBank) 1290 efuse_addr = 0; 1291 #if 1 1292 1293 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1294 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) { 1295 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr); 1296 /* bank = EFUSE_MAX_BANK; */ 1297 break; 1298 } 1299 DBG_8192C("%s: efuse_OneByteRead ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); 1300 1301 if (efuse_data == 0xFF) 1302 break; 1303 1304 if (EXT_HEADER(efuse_data)) { 1305 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1306 efuse_addr++; 1307 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1308 DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); 1309 1310 if (ALL_WORDS_DISABLED(efuse_data)) { 1311 efuse_addr++; 1312 continue; 1313 } 1314 1315 /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */ 1316 hoffset |= ((efuse_data & 0xF0) >> 1); 1317 hworden = efuse_data & 0x0F; 1318 } else { 1319 hoffset = (efuse_data>>4) & 0x0F; 1320 hworden = efuse_data & 0x0F; 1321 } 1322 1323 DBG_8192C(FUNC_ADPT_FMT": Offset =%d Worden =%#X\n", 1324 FUNC_ADPT_ARG(padapter), hoffset, hworden); 1325 1326 word_cnts = Efuse_CalculateWordCnts(hworden); 1327 /* read next header */ 1328 efuse_addr += (word_cnts*2)+1; 1329 } 1330 #else 1331 while ( 1332 bContinual && 1333 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) && 1334 AVAILABLE_EFUSE_ADDR(efuse_addr) 1335 ) { 1336 if (efuse_data != 0xFF) { 1337 if ((efuse_data&0x1F) == 0x0F) { /* extended header */ 1338 hoffset = efuse_data; 1339 efuse_addr++; 1340 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1341 if ((efuse_data & 0x0F) == 0x0F) { 1342 efuse_addr++; 1343 continue; 1344 } else { 1345 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); 1346 hworden = efuse_data & 0x0F; 1347 } 1348 } else { 1349 hoffset = (efuse_data>>4) & 0x0F; 1350 hworden = efuse_data & 0x0F; 1351 } 1352 word_cnts = Efuse_CalculateWordCnts(hworden); 1353 /* read next header */ 1354 efuse_addr = efuse_addr + (word_cnts*2)+1; 1355 } else 1356 bContinual = false; 1357 } 1358 #endif 1359 1360 1361 /* Check if we need to check next bank efuse */ 1362 if (efuse_addr < retU2) 1363 break; /* don't need to check next bank. */ 1364 } 1365 1366 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr; 1367 if (bPseudoTest) { 1368 pEfuseHal->fakeBTEfuseUsedBytes = retU2; 1369 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */ 1370 } else { 1371 pEfuseHal->BTEfuseUsedBytes = retU2; 1372 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */ 1373 } 1374 1375 DBG_8192C("%s: CurrentSize =%d\n", __func__, retU2); 1376 return retU2; 1377 } 1378 1379 static u16 Hal_EfuseGetCurrentSize( 1380 struct adapter *padapter, u8 efuseType, bool bPseudoTest 1381 ) 1382 { 1383 u16 ret = 0; 1384 1385 if (efuseType == EFUSE_WIFI) 1386 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest); 1387 else 1388 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest); 1389 1390 return ret; 1391 } 1392 1393 static u8 Hal_EfuseWordEnableDataWrite( 1394 struct adapter *padapter, 1395 u16 efuse_addr, 1396 u8 word_en, 1397 u8 *data, 1398 bool bPseudoTest 1399 ) 1400 { 1401 u16 tmpaddr = 0; 1402 u16 start_addr = efuse_addr; 1403 u8 badworden = 0x0F; 1404 u8 tmpdata[PGPKT_DATA_SIZE]; 1405 1406 1407 /* DBG_8192C("%s: efuse_addr =%#x word_en =%#x\n", __func__, efuse_addr, word_en); */ 1408 memset(tmpdata, 0xFF, PGPKT_DATA_SIZE); 1409 1410 if (!(word_en & BIT(0))) { 1411 tmpaddr = start_addr; 1412 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest); 1413 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest); 1414 1415 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest); 1416 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[1], bPseudoTest); 1417 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) { 1418 badworden &= (~BIT(0)); 1419 } 1420 } 1421 if (!(word_en & BIT(1))) { 1422 tmpaddr = start_addr; 1423 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest); 1424 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest); 1425 1426 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest); 1427 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[3], bPseudoTest); 1428 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) { 1429 badworden &= (~BIT(1)); 1430 } 1431 } 1432 1433 if (!(word_en & BIT(2))) { 1434 tmpaddr = start_addr; 1435 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest); 1436 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest); 1437 1438 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest); 1439 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[5], bPseudoTest); 1440 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) { 1441 badworden &= (~BIT(2)); 1442 } 1443 } 1444 1445 if (!(word_en & BIT(3))) { 1446 tmpaddr = start_addr; 1447 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest); 1448 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest); 1449 1450 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest); 1451 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[7], bPseudoTest); 1452 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) { 1453 badworden &= (~BIT(3)); 1454 } 1455 } 1456 1457 return badworden; 1458 } 1459 1460 static s32 Hal_EfusePgPacketRead( 1461 struct adapter *padapter, 1462 u8 offset, 1463 u8 *data, 1464 bool bPseudoTest 1465 ) 1466 { 1467 u8 efuse_data, word_cnts = 0; 1468 u16 efuse_addr = 0; 1469 u8 hoffset = 0, hworden = 0; 1470 u8 i; 1471 u8 max_section = 0; 1472 s32 ret; 1473 1474 1475 if (data == NULL) 1476 return false; 1477 1478 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest); 1479 if (offset > max_section) { 1480 DBG_8192C("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section); 1481 return false; 1482 } 1483 1484 memset(data, 0xFF, PGPKT_DATA_SIZE); 1485 ret = true; 1486 1487 /* */ 1488 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */ 1489 /* Skip dummy parts to prevent unexpected data read from Efuse. */ 1490 /* By pass right now. 2009.02.19. */ 1491 /* */ 1492 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1493 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == false) { 1494 ret = false; 1495 break; 1496 } 1497 1498 if (efuse_data == 0xFF) 1499 break; 1500 1501 if (EXT_HEADER(efuse_data)) { 1502 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1503 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1504 if (ALL_WORDS_DISABLED(efuse_data)) { 1505 DBG_8192C("%s: Error!! All words disabled!\n", __func__); 1506 continue; 1507 } 1508 1509 hoffset |= ((efuse_data & 0xF0) >> 1); 1510 hworden = efuse_data & 0x0F; 1511 } else { 1512 hoffset = (efuse_data>>4) & 0x0F; 1513 hworden = efuse_data & 0x0F; 1514 } 1515 1516 if (hoffset == offset) { 1517 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1518 /* Check word enable condition in the section */ 1519 if (!(hworden & (0x01<<i))) { 1520 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1521 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ 1522 data[i*2] = efuse_data; 1523 1524 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1525 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ 1526 data[(i*2)+1] = efuse_data; 1527 } 1528 } 1529 } else { 1530 word_cnts = Efuse_CalculateWordCnts(hworden); 1531 efuse_addr += word_cnts*2; 1532 } 1533 } 1534 1535 return ret; 1536 } 1537 1538 static u8 hal_EfusePgCheckAvailableAddr( 1539 struct adapter *padapter, u8 efuseType, u8 bPseudoTest 1540 ) 1541 { 1542 u16 max_available = 0; 1543 u16 current_size; 1544 1545 1546 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest); 1547 /* DBG_8192C("%s: max_available =%d\n", __func__, max_available); */ 1548 1549 current_size = Efuse_GetCurrentSize(padapter, efuseType, bPseudoTest); 1550 if (current_size >= max_available) { 1551 DBG_8192C("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available); 1552 return false; 1553 } 1554 return true; 1555 } 1556 1557 static void hal_EfuseConstructPGPkt( 1558 u8 offset, 1559 u8 word_en, 1560 u8 *pData, 1561 PPGPKT_STRUCT pTargetPkt 1562 ) 1563 { 1564 memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE); 1565 pTargetPkt->offset = offset; 1566 pTargetPkt->word_en = word_en; 1567 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); 1568 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); 1569 } 1570 1571 static u8 hal_EfusePartialWriteCheck( 1572 struct adapter *padapter, 1573 u8 efuseType, 1574 u16 *pAddr, 1575 PPGPKT_STRUCT pTargetPkt, 1576 u8 bPseudoTest 1577 ) 1578 { 1579 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1580 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1581 u8 bRet = false; 1582 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0; 1583 u8 efuse_data = 0; 1584 1585 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest); 1586 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest); 1587 1588 if (efuseType == EFUSE_WIFI) { 1589 if (bPseudoTest) { 1590 #ifdef HAL_EFUSE_MEMORY 1591 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes; 1592 #else 1593 startAddr = (u16)fakeEfuseUsedBytes; 1594 #endif 1595 } else 1596 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); 1597 } else { 1598 if (bPseudoTest) { 1599 #ifdef HAL_EFUSE_MEMORY 1600 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes; 1601 #else 1602 startAddr = (u16)fakeBTEfuseUsedBytes; 1603 #endif 1604 } else 1605 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr); 1606 } 1607 startAddr %= efuse_max; 1608 DBG_8192C("%s: startAddr =%#X\n", __func__, startAddr); 1609 1610 while (1) { 1611 if (startAddr >= efuse_max_available_len) { 1612 bRet = false; 1613 DBG_8192C("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", __func__, startAddr, efuse_max_available_len); 1614 break; 1615 } 1616 1617 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) { 1618 #if 1 1619 bRet = false; 1620 DBG_8192C("%s: Something Wrong! last bytes(%#X = 0x%02X) is not 0xFF\n", 1621 __func__, startAddr, efuse_data); 1622 break; 1623 #else 1624 if (EXT_HEADER(efuse_data)) { 1625 cur_header = efuse_data; 1626 startAddr++; 1627 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest); 1628 if (ALL_WORDS_DISABLED(efuse_data)) { 1629 DBG_8192C("%s: Error condition, all words disabled!", __func__); 1630 bRet = false; 1631 break; 1632 } else { 1633 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); 1634 curPkt.word_en = efuse_data & 0x0F; 1635 } 1636 } else { 1637 cur_header = efuse_data; 1638 curPkt.offset = (cur_header>>4) & 0x0F; 1639 curPkt.word_en = cur_header & 0x0F; 1640 } 1641 1642 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); 1643 /* if same header is found but no data followed */ 1644 /* write some part of data followed by the header. */ 1645 if ( 1646 (curPkt.offset == pTargetPkt->offset) && 1647 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr+1, bPseudoTest) == false) && 1648 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == true 1649 ) { 1650 DBG_8192C("%s: Need to partial write data by the previous wrote header\n", __func__); 1651 /* Here to write partial data */ 1652 badworden = Efuse_WordEnableDataWrite(padapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest); 1653 if (badworden != 0x0F) { 1654 u32 PgWriteSuccess = 0; 1655 /* if write fail on some words, write these bad words again */ 1656 if (efuseType == EFUSE_WIFI) 1657 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); 1658 else 1659 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); 1660 1661 if (!PgWriteSuccess) { 1662 bRet = false; /* write fail, return */ 1663 break; 1664 } 1665 } 1666 /* partial write ok, update the target packet for later use */ 1667 for (i = 0; i < 4; i++) { 1668 if ((matched_wden & (0x1<<i)) == 0) { /* this word has been written */ 1669 pTargetPkt->word_en |= (0x1<<i); /* disable the word */ 1670 } 1671 } 1672 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); 1673 } 1674 /* read from next header */ 1675 startAddr = startAddr + (curPkt.word_cnts*2) + 1; 1676 #endif 1677 } else { 1678 /* not used header, 0xff */ 1679 *pAddr = startAddr; 1680 /* DBG_8192C("%s: Started from unused header offset =%d\n", __func__, startAddr)); */ 1681 bRet = true; 1682 break; 1683 } 1684 } 1685 1686 return bRet; 1687 } 1688 1689 static u8 hal_EfusePgPacketWrite1ByteHeader( 1690 struct adapter *padapter, 1691 u8 efuseType, 1692 u16 *pAddr, 1693 PPGPKT_STRUCT pTargetPkt, 1694 u8 bPseudoTest 1695 ) 1696 { 1697 u8 pg_header = 0, tmp_header = 0; 1698 u16 efuse_addr = *pAddr; 1699 u8 repeatcnt = 0; 1700 1701 1702 /* DBG_8192C("%s\n", __func__); */ 1703 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en; 1704 1705 do { 1706 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1707 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1708 if (tmp_header != 0xFF) 1709 break; 1710 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1711 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__); 1712 return false; 1713 } 1714 } while (1); 1715 1716 if (tmp_header != pg_header) { 1717 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1718 return false; 1719 } 1720 1721 *pAddr = efuse_addr; 1722 1723 return true; 1724 } 1725 1726 static u8 hal_EfusePgPacketWrite2ByteHeader( 1727 struct adapter *padapter, 1728 u8 efuseType, 1729 u16 *pAddr, 1730 PPGPKT_STRUCT pTargetPkt, 1731 u8 bPseudoTest 1732 ) 1733 { 1734 u16 efuse_addr, efuse_max_available_len = 0; 1735 u8 pg_header = 0, tmp_header = 0; 1736 u8 repeatcnt = 0; 1737 1738 1739 /* DBG_8192C("%s\n", __func__); */ 1740 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest); 1741 1742 efuse_addr = *pAddr; 1743 if (efuse_addr >= efuse_max_available_len) { 1744 DBG_8192C("%s: addr(%d) over available (%d)!!\n", __func__, 1745 efuse_addr, efuse_max_available_len); 1746 return false; 1747 } 1748 1749 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; 1750 /* DBG_8192C("%s: pg_header = 0x%x\n", __func__, pg_header); */ 1751 1752 do { 1753 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1754 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1755 if (tmp_header != 0xFF) 1756 break; 1757 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1758 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__); 1759 return false; 1760 } 1761 } while (1); 1762 1763 if (tmp_header != pg_header) { 1764 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1765 return false; 1766 } 1767 1768 /* to write ext_header */ 1769 efuse_addr++; 1770 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; 1771 1772 do { 1773 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1774 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1775 if (tmp_header != 0xFF) 1776 break; 1777 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1778 DBG_8192C("%s: Repeat over limit for ext_header!!\n", __func__); 1779 return false; 1780 } 1781 } while (1); 1782 1783 if (tmp_header != pg_header) { /* offset PG fail */ 1784 DBG_8192C(KERN_ERR "%s: PG EXT Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1785 return false; 1786 } 1787 1788 *pAddr = efuse_addr; 1789 1790 return true; 1791 } 1792 1793 static u8 hal_EfusePgPacketWriteHeader( 1794 struct adapter *padapter, 1795 u8 efuseType, 1796 u16 *pAddr, 1797 PPGPKT_STRUCT pTargetPkt, 1798 u8 bPseudoTest 1799 ) 1800 { 1801 u8 bRet = false; 1802 1803 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) 1804 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); 1805 else 1806 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); 1807 1808 return bRet; 1809 } 1810 1811 static u8 hal_EfusePgPacketWriteData( 1812 struct adapter *padapter, 1813 u8 efuseType, 1814 u16 *pAddr, 1815 PPGPKT_STRUCT pTargetPkt, 1816 u8 bPseudoTest 1817 ) 1818 { 1819 u16 efuse_addr; 1820 u8 badworden; 1821 1822 1823 efuse_addr = *pAddr; 1824 badworden = Efuse_WordEnableDataWrite(padapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); 1825 if (badworden != 0x0F) { 1826 DBG_8192C("%s: Fail!!\n", __func__); 1827 return false; 1828 } 1829 1830 /* DBG_8192C("%s: ok\n", __func__); */ 1831 return true; 1832 } 1833 1834 static s32 Hal_EfusePgPacketWrite( 1835 struct adapter *padapter, 1836 u8 offset, 1837 u8 word_en, 1838 u8 *pData, 1839 bool bPseudoTest 1840 ) 1841 { 1842 PGPKT_STRUCT targetPkt; 1843 u16 startAddr = 0; 1844 u8 efuseType = EFUSE_WIFI; 1845 1846 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest)) 1847 return false; 1848 1849 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); 1850 1851 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1852 return false; 1853 1854 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1855 return false; 1856 1857 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1858 return false; 1859 1860 return true; 1861 } 1862 1863 static bool Hal_EfusePgPacketWrite_BT( 1864 struct adapter *padapter, 1865 u8 offset, 1866 u8 word_en, 1867 u8 *pData, 1868 bool bPseudoTest 1869 ) 1870 { 1871 PGPKT_STRUCT targetPkt; 1872 u16 startAddr = 0; 1873 u8 efuseType = EFUSE_BT; 1874 1875 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest)) 1876 return false; 1877 1878 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); 1879 1880 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1881 return false; 1882 1883 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1884 return false; 1885 1886 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1887 return false; 1888 1889 return true; 1890 } 1891 1892 static HAL_VERSION ReadChipVersion8723B(struct adapter *padapter) 1893 { 1894 u32 value32; 1895 HAL_VERSION ChipVersion; 1896 struct hal_com_data *pHalData; 1897 1898 /* YJ, TODO, move read chip type here */ 1899 pHalData = GET_HAL_DATA(padapter); 1900 1901 value32 = rtw_read32(padapter, REG_SYS_CFG); 1902 ChipVersion.ICType = CHIP_8723B; 1903 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP); 1904 ChipVersion.RFType = RF_TYPE_1T1R; 1905 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC); 1906 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */ 1907 1908 /* For regulator mode. by tynli. 2011.01.14 */ 1909 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); 1910 1911 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS); 1912 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */ 1913 1914 /* For multi-function consideration. Added by Roger, 2010.10.06. */ 1915 pHalData->MultiFunc = RT_MULTI_FUNC_NONE; 1916 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL); 1917 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0); 1918 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0); 1919 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0); 1920 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT); 1921 #if 1 1922 dump_chip_info(ChipVersion); 1923 #endif 1924 pHalData->VersionID = ChipVersion; 1925 if (IS_1T2R(ChipVersion)) 1926 pHalData->rf_type = RF_1T2R; 1927 else if (IS_2T2R(ChipVersion)) 1928 pHalData->rf_type = RF_2T2R; 1929 else 1930 pHalData->rf_type = RF_1T1R; 1931 1932 MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type); 1933 1934 return ChipVersion; 1935 } 1936 1937 static void rtl8723b_read_chip_version(struct adapter *padapter) 1938 { 1939 ReadChipVersion8723B(padapter); 1940 } 1941 1942 void rtl8723b_InitBeaconParameters(struct adapter *padapter) 1943 { 1944 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1945 u16 val16; 1946 u8 val8; 1947 1948 1949 val8 = DIS_TSF_UDT; 1950 val16 = val8 | (val8 << 8); /* port0 and port1 */ 1951 1952 /* Enable prot0 beacon function for PSTDMA */ 1953 val16 |= EN_BCN_FUNCTION; 1954 1955 rtw_write16(padapter, REG_BCN_CTRL, val16); 1956 1957 /* TODO: Remove these magic number */ 1958 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */ 1959 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 1960 /* so don't set this register on STA mode. */ 1961 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false) 1962 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B); /* 5ms */ 1963 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B); /* 2ms */ 1964 1965 /* Suggested by designer timchen. Change beacon AIFS to the largest number */ 1966 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ 1967 rtw_write16(padapter, REG_BCNTCFG, 0x660F); 1968 1969 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL); 1970 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); 1971 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); 1972 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2); 1973 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1); 1974 } 1975 1976 void _InitBurstPktLen_8723BS(struct adapter *Adapter) 1977 { 1978 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1979 1980 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */ 1981 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18); /* for VHT packet length 11K */ 1982 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F); 1983 rtw_write8(Adapter, REG_PIFS_8723B, 0x00); 1984 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7))); 1985 if (pHalData->AMPDUBurstMode) 1986 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F); 1987 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70); 1988 1989 /* ARFB table 9 for 11ac 5G 2SS */ 1990 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010); 1991 if (IS_NORMAL_CHIP(pHalData->VersionID)) 1992 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000); 1993 else 1994 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000); 1995 1996 /* ARFB table 10 for 11ac 5G 1SS */ 1997 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010); 1998 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000); 1999 } 2000 2001 static void ResumeTxBeacon(struct adapter *padapter) 2002 { 2003 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2004 2005 2006 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ 2007 /* which should be read from register to a global variable. */ 2008 2009 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n")); 2010 2011 pHalData->RegFwHwTxQCtrl |= BIT(6); 2012 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); 2013 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff); 2014 pHalData->RegReg542 |= BIT(0); 2015 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); 2016 } 2017 2018 static void StopTxBeacon(struct adapter *padapter) 2019 { 2020 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2021 2022 2023 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ 2024 /* which should be read from register to a global variable. */ 2025 2026 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n")); 2027 2028 pHalData->RegFwHwTxQCtrl &= ~BIT(6); 2029 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); 2030 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); 2031 pHalData->RegReg542 &= ~BIT(0); 2032 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); 2033 2034 CheckFwRsvdPageContent(padapter); /* 2010.06.23. Added by tynli. */ 2035 } 2036 2037 static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked) 2038 { 2039 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); 2040 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F); 2041 } 2042 2043 static void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter) 2044 { 2045 u8 val8; 2046 u32 value32; 2047 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; 2048 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; 2049 u32 bcn_ctrl_reg; 2050 2051 /* reset TSF, enable update TSF, correcting TSF On Beacon */ 2052 2053 /* REG_BCN_INTERVAL */ 2054 /* REG_BCNDMATIM */ 2055 /* REG_ATIMWND */ 2056 /* REG_TBTT_PROHIBIT */ 2057 /* REG_DRVERLYINT */ 2058 /* REG_BCN_MAX_ERR */ 2059 /* REG_BCNTCFG (0x510) */ 2060 /* REG_DUAL_TSF_RST */ 2061 /* REG_BCN_CTRL (0x550) */ 2062 2063 2064 bcn_ctrl_reg = REG_BCN_CTRL; 2065 2066 /* */ 2067 /* ATIM window */ 2068 /* */ 2069 rtw_write16(padapter, REG_ATIMWND, 2); 2070 2071 /* */ 2072 /* Beacon interval (in unit of TU). */ 2073 /* */ 2074 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); 2075 2076 rtl8723b_InitBeaconParameters(padapter); 2077 2078 rtw_write8(padapter, REG_SLOT, 0x09); 2079 2080 /* */ 2081 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */ 2082 /* */ 2083 value32 = rtw_read32(padapter, REG_TCR); 2084 value32 &= ~TSFRST; 2085 rtw_write32(padapter, REG_TCR, value32); 2086 2087 value32 |= TSFRST; 2088 rtw_write32(padapter, REG_TCR, value32); 2089 2090 /* NOTE: Fix test chip's bug (about contention windows's randomness) */ 2091 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) { 2092 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); 2093 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); 2094 } 2095 2096 _BeaconFunctionEnable(padapter, true, true); 2097 2098 ResumeTxBeacon(padapter); 2099 val8 = rtw_read8(padapter, bcn_ctrl_reg); 2100 val8 |= DIS_BCNQ_SUB; 2101 rtw_write8(padapter, bcn_ctrl_reg, val8); 2102 } 2103 2104 static void rtl8723b_GetHalODMVar( 2105 struct adapter *Adapter, 2106 enum HAL_ODM_VARIABLE eVariable, 2107 void *pValue1, 2108 void *pValue2 2109 ) 2110 { 2111 GetHalODMVar(Adapter, eVariable, pValue1, pValue2); 2112 } 2113 2114 static void rtl8723b_SetHalODMVar( 2115 struct adapter *Adapter, 2116 enum HAL_ODM_VARIABLE eVariable, 2117 void *pValue1, 2118 bool bSet 2119 ) 2120 { 2121 SetHalODMVar(Adapter, eVariable, pValue1, bSet); 2122 } 2123 2124 static void hal_notch_filter_8723b(struct adapter *adapter, bool enable) 2125 { 2126 if (enable) { 2127 DBG_871X("Enable notch filter\n"); 2128 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1); 2129 } else { 2130 DBG_871X("Disable notch filter\n"); 2131 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); 2132 } 2133 } 2134 2135 static void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level) 2136 { 2137 u32 mask, rate_bitmap; 2138 u8 shortGIrate = false; 2139 struct sta_info *psta; 2140 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2141 struct dm_priv *pdmpriv = &pHalData->dmpriv; 2142 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; 2143 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 2144 2145 DBG_871X("%s(): mac_id =%d rssi_level =%d\n", __func__, mac_id, rssi_level); 2146 2147 if (mac_id >= NUM_STA) /* CAM_SIZE */ 2148 return; 2149 2150 psta = pmlmeinfo->FW_sta_info[mac_id].psta; 2151 if (psta == NULL) 2152 return; 2153 2154 shortGIrate = query_ra_short_GI(psta); 2155 2156 mask = psta->ra_mask; 2157 2158 rate_bitmap = 0xffffffff; 2159 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); 2160 DBG_871X("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", 2161 __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap); 2162 2163 mask &= rate_bitmap; 2164 2165 rate_bitmap = rtw_btcoex_GetRaMask(padapter); 2166 mask &= ~rate_bitmap; 2167 2168 #ifdef CONFIG_CMCC_TEST 2169 if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { 2170 if (mac_id == 0) { 2171 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); 2172 mask &= 0xffffff00; /* disable CCK & <24M OFDM rate for 11G mode for CMCC */ 2173 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); 2174 } 2175 } 2176 #endif 2177 2178 if (pHalData->fw_ractrl == true) { 2179 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask); 2180 } 2181 2182 /* set correct initial date rate for each mac_id */ 2183 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate; 2184 DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x init_rate = 0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate); 2185 } 2186 2187 2188 void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc) 2189 { 2190 pHalFunc->free_hal_data = &rtl8723b_free_hal_data; 2191 2192 pHalFunc->dm_init = &rtl8723b_init_dm_priv; 2193 2194 pHalFunc->read_chip_version = &rtl8723b_read_chip_version; 2195 2196 pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8723B; 2197 2198 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8723B; 2199 pHalFunc->set_channel_handler = &PHY_SwChnl8723B; 2200 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8723B; 2201 2202 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8723B; 2203 pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8723B; 2204 2205 pHalFunc->hal_dm_watchdog = &rtl8723b_HalDmWatchDog; 2206 pHalFunc->hal_dm_watchdog_in_lps = &rtl8723b_HalDmWatchDog_in_LPS; 2207 2208 2209 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723b_SetBeaconRelatedRegisters; 2210 2211 pHalFunc->Add_RateATid = &rtl8723b_Add_RateATid; 2212 2213 pHalFunc->run_thread = &rtl8723b_start_thread; 2214 pHalFunc->cancel_thread = &rtl8723b_stop_thread; 2215 2216 pHalFunc->read_bbreg = &PHY_QueryBBReg_8723B; 2217 pHalFunc->write_bbreg = &PHY_SetBBReg_8723B; 2218 pHalFunc->read_rfreg = &PHY_QueryRFReg_8723B; 2219 pHalFunc->write_rfreg = &PHY_SetRFReg_8723B; 2220 2221 /* Efuse related function */ 2222 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch; 2223 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch; 2224 pHalFunc->ReadEFuse = &Hal_ReadEFuse; 2225 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition; 2226 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize; 2227 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead; 2228 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite; 2229 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite; 2230 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT; 2231 2232 pHalFunc->GetHalODMVarHandler = &rtl8723b_GetHalODMVar; 2233 pHalFunc->SetHalODMVarHandler = &rtl8723b_SetHalODMVar; 2234 2235 pHalFunc->xmit_thread_handler = &hal_xmit_handler; 2236 pHalFunc->hal_notch_filter = &hal_notch_filter_8723b; 2237 2238 pHalFunc->c2h_handler = c2h_handler_8723b; 2239 pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8723b; 2240 2241 pHalFunc->fill_h2c_cmd = &FillH2CCmd8723B; 2242 } 2243 2244 void rtl8723b_InitAntenna_Selection(struct adapter *padapter) 2245 { 2246 struct hal_com_data *pHalData; 2247 u8 val; 2248 2249 2250 pHalData = GET_HAL_DATA(padapter); 2251 2252 val = rtw_read8(padapter, REG_LEDCFG2); 2253 /* Let 8051 take control antenna settting */ 2254 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */ 2255 rtw_write8(padapter, REG_LEDCFG2, val); 2256 } 2257 2258 void rtl8723b_init_default_value(struct adapter *padapter) 2259 { 2260 struct hal_com_data *pHalData; 2261 struct dm_priv *pdmpriv; 2262 u8 i; 2263 2264 2265 pHalData = GET_HAL_DATA(padapter); 2266 pdmpriv = &pHalData->dmpriv; 2267 2268 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N; 2269 2270 /* init default value */ 2271 pHalData->fw_ractrl = false; 2272 pHalData->bIQKInitialized = false; 2273 if (!adapter_to_pwrctl(padapter)->bkeepfwalive) 2274 pHalData->LastHMEBoxNum = 0; 2275 2276 pHalData->bIQKInitialized = false; 2277 2278 /* init dm default value */ 2279 pdmpriv->TM_Trigger = 0;/* for IQK */ 2280 /* pdmpriv->binitialized = false; */ 2281 /* pdmpriv->prv_traffic_idx = 3; */ 2282 /* pdmpriv->initialize = 0; */ 2283 2284 pdmpriv->ThermalValue_HP_index = 0; 2285 for (i = 0; i < HP_THERMAL_NUM; i++) 2286 pdmpriv->ThermalValue_HP[i] = 0; 2287 2288 /* init Efuse variables */ 2289 pHalData->EfuseUsedBytes = 0; 2290 pHalData->EfuseUsedPercentage = 0; 2291 #ifdef HAL_EFUSE_MEMORY 2292 pHalData->EfuseHal.fakeEfuseBank = 0; 2293 pHalData->EfuseHal.fakeEfuseUsedBytes = 0; 2294 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE); 2295 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN); 2296 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN); 2297 pHalData->EfuseHal.BTEfuseUsedBytes = 0; 2298 pHalData->EfuseHal.BTEfuseUsedPercentage = 0; 2299 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE); 2300 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2301 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2302 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0; 2303 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE); 2304 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2305 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2306 #endif 2307 } 2308 2309 u8 GetEEPROMSize8723B(struct adapter *padapter) 2310 { 2311 u8 size = 0; 2312 u32 cr; 2313 2314 cr = rtw_read16(padapter, REG_9346CR); 2315 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */ 2316 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4; 2317 2318 MSG_8192C("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46"); 2319 2320 return size; 2321 } 2322 2323 /* */ 2324 /* */ 2325 /* LLT R/W/Init function */ 2326 /* */ 2327 /* */ 2328 s32 rtl8723b_InitLLTTable(struct adapter *padapter) 2329 { 2330 unsigned long start, passing_time; 2331 u32 val32; 2332 s32 ret; 2333 2334 2335 ret = _FAIL; 2336 2337 val32 = rtw_read32(padapter, REG_AUTO_LLT); 2338 val32 |= BIT_AUTO_INIT_LLT; 2339 rtw_write32(padapter, REG_AUTO_LLT, val32); 2340 2341 start = jiffies; 2342 2343 do { 2344 val32 = rtw_read32(padapter, REG_AUTO_LLT); 2345 if (!(val32 & BIT_AUTO_INIT_LLT)) { 2346 ret = _SUCCESS; 2347 break; 2348 } 2349 2350 passing_time = jiffies_to_msecs(jiffies - start); 2351 if (passing_time > 1000) { 2352 DBG_8192C( 2353 "%s: FAIL!! REG_AUTO_LLT(0x%X) =%08x\n", 2354 __func__, 2355 REG_AUTO_LLT, 2356 val32 2357 ); 2358 break; 2359 } 2360 2361 msleep(1); 2362 } while (1); 2363 2364 return ret; 2365 } 2366 2367 static bool Hal_GetChnlGroup8723B(u8 Channel, u8 *pGroup) 2368 { 2369 bool bIn24G = true; 2370 2371 if (Channel <= 14) { 2372 bIn24G = true; 2373 2374 if (1 <= Channel && Channel <= 2) 2375 *pGroup = 0; 2376 else if (3 <= Channel && Channel <= 5) 2377 *pGroup = 1; 2378 else if (6 <= Channel && Channel <= 8) 2379 *pGroup = 2; 2380 else if (9 <= Channel && Channel <= 11) 2381 *pGroup = 3; 2382 else if (12 <= Channel && Channel <= 14) 2383 *pGroup = 4; 2384 else { 2385 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 2.4 G, but Channel %d in Group not found\n", Channel)); 2386 } 2387 } else { 2388 bIn24G = false; 2389 2390 if (36 <= Channel && Channel <= 42) 2391 *pGroup = 0; 2392 else if (44 <= Channel && Channel <= 48) 2393 *pGroup = 1; 2394 else if (50 <= Channel && Channel <= 58) 2395 *pGroup = 2; 2396 else if (60 <= Channel && Channel <= 64) 2397 *pGroup = 3; 2398 else if (100 <= Channel && Channel <= 106) 2399 *pGroup = 4; 2400 else if (108 <= Channel && Channel <= 114) 2401 *pGroup = 5; 2402 else if (116 <= Channel && Channel <= 122) 2403 *pGroup = 6; 2404 else if (124 <= Channel && Channel <= 130) 2405 *pGroup = 7; 2406 else if (132 <= Channel && Channel <= 138) 2407 *pGroup = 8; 2408 else if (140 <= Channel && Channel <= 144) 2409 *pGroup = 9; 2410 else if (149 <= Channel && Channel <= 155) 2411 *pGroup = 10; 2412 else if (157 <= Channel && Channel <= 161) 2413 *pGroup = 11; 2414 else if (165 <= Channel && Channel <= 171) 2415 *pGroup = 12; 2416 else if (173 <= Channel && Channel <= 177) 2417 *pGroup = 13; 2418 else { 2419 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 5G, but Channel %d in Group not found\n", Channel)); 2420 } 2421 2422 } 2423 RT_TRACE( 2424 _module_hci_hal_init_c_, 2425 _drv_info_, 2426 ( 2427 "<==Hal_GetChnlGroup8723B, (%s) Channel = %d, Group =%d,\n", 2428 bIn24G ? "2.4G" : "5G", 2429 Channel, 2430 *pGroup 2431 ) 2432 ); 2433 return bIn24G; 2434 } 2435 2436 void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent) 2437 { 2438 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2439 2440 if (false == pEEPROM->bautoload_fail_flag) { /* autoload OK. */ 2441 if (!pEEPROM->EepromOrEfuse) { 2442 /* Read EFUSE real map to shadow. */ 2443 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); 2444 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B); 2445 } 2446 } else {/* autoload fail */ 2447 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n")); 2448 if (false == pEEPROM->EepromOrEfuse) 2449 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); 2450 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B); 2451 } 2452 } 2453 2454 void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo) 2455 { 2456 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2457 /* struct hal_com_data *pHalData = GET_HAL_DATA(padapter); */ 2458 u16 EEPROMId; 2459 2460 2461 /* Checl 0x8129 again for making sure autoload status!! */ 2462 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo)); 2463 if (EEPROMId != RTL_EEPROM_ID) { 2464 DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); 2465 pEEPROM->bautoload_fail_flag = true; 2466 } else 2467 pEEPROM->bautoload_fail_flag = false; 2468 2469 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("EEPROM ID = 0x%04x\n", EEPROMId)); 2470 } 2471 2472 static void Hal_ReadPowerValueFromPROM_8723B( 2473 struct adapter *Adapter, 2474 struct TxPowerInfo24G *pwrInfo24G, 2475 u8 *PROMContent, 2476 bool AutoLoadFail 2477 ) 2478 { 2479 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2480 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0; 2481 2482 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G)); 2483 2484 if (0xFF == PROMContent[eeAddr+1]) 2485 AutoLoadFail = true; 2486 2487 if (AutoLoadFail) { 2488 DBG_871X("%s(): Use Default value!\n", __func__); 2489 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { 2490 /* 2.4G default value */ 2491 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 2492 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2493 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2494 } 2495 2496 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2497 if (TxCount == 0) { 2498 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; 2499 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; 2500 } else { 2501 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2502 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2503 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2504 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2505 } 2506 } 2507 } 2508 2509 return; 2510 } 2511 2512 pHalData->bTXPowerDataReadFromEEPORM = true; /* YJ, move, 120316 */ 2513 2514 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { 2515 /* 2 2.4G default value */ 2516 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 2517 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; 2518 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) 2519 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2520 } 2521 2522 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) { 2523 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; 2524 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) 2525 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2526 } 2527 2528 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2529 if (TxCount == 0) { 2530 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0; 2531 if (PROMContent[eeAddr] == 0xFF) 2532 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF; 2533 else { 2534 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2535 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2536 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; 2537 } 2538 2539 if (PROMContent[eeAddr] == 0xFF) 2540 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF; 2541 else { 2542 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2543 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2544 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; 2545 } 2546 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; 2547 eeAddr++; 2548 } else { 2549 if (PROMContent[eeAddr] == 0xFF) 2550 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2551 else { 2552 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2553 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2554 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; 2555 } 2556 2557 if (PROMContent[eeAddr] == 0xFF) 2558 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2559 else { 2560 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2561 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2562 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; 2563 } 2564 eeAddr++; 2565 2566 if (PROMContent[eeAddr] == 0xFF) 2567 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2568 else { 2569 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2570 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2571 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; 2572 } 2573 2574 if (PROMContent[eeAddr] == 0xFF) 2575 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2576 else { 2577 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2578 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2579 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; 2580 } 2581 eeAddr++; 2582 } 2583 } 2584 } 2585 } 2586 2587 2588 void Hal_EfuseParseTxPowerInfo_8723B( 2589 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail 2590 ) 2591 { 2592 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2593 struct TxPowerInfo24G pwrInfo24G; 2594 u8 rfPath, ch, TxCount = 1; 2595 2596 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail); 2597 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2598 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) { 2599 u8 group = 0; 2600 2601 Hal_GetChnlGroup8723B(ch+1, &group); 2602 2603 if (ch == 14-1) { 2604 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5]; 2605 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; 2606 } else { 2607 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group]; 2608 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; 2609 } 2610 #ifdef DEBUG 2611 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======= Path %d, ChannelIndex %d, Group %d =======\n", rfPath, ch, group)); 2612 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch])); 2613 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch])); 2614 #endif 2615 } 2616 2617 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2618 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount]; 2619 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount]; 2620 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount]; 2621 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount]; 2622 2623 #ifdef DEBUG 2624 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("--------------------------------------- 2.4G ---------------------------------------\n")); 2625 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CCK_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount])); 2626 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("OFDM_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount])); 2627 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW20_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount])); 2628 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW40_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount])); 2629 #endif 2630 } 2631 } 2632 2633 /* 2010/10/19 MH Add Regulator recognize for CU. */ 2634 if (!AutoLoadFail) { 2635 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7); /* bit0~2 */ 2636 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF) 2637 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */ 2638 } else 2639 pHalData->EEPROMRegulatory = 0; 2640 2641 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory)); 2642 } 2643 2644 void Hal_EfuseParseBTCoexistInfo_8723B( 2645 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2646 ) 2647 { 2648 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2649 u8 tempval; 2650 u32 tmpu4; 2651 2652 if (!AutoLoadFail) { 2653 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL); 2654 if (tmpu4 & BT_FUNC_EN) 2655 pHalData->EEPROMBluetoothCoexist = true; 2656 else 2657 pHalData->EEPROMBluetoothCoexist = false; 2658 2659 pHalData->EEPROMBluetoothType = BT_RTL8723B; 2660 2661 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B]; 2662 if (tempval != 0xFF) { 2663 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0); 2664 /* EFUSE_0xC3[6] == 0, S1(Main)-ODM_RF_PATH_A; */ 2665 /* EFUSE_0xC3[6] == 1, S0(Aux)-ODM_RF_PATH_B */ 2666 pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A; 2667 } else { 2668 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2669 if (pHalData->PackageType == PACKAGE_QFN68) 2670 pHalData->ant_path = ODM_RF_PATH_B; 2671 else 2672 pHalData->ant_path = ODM_RF_PATH_A; 2673 } 2674 } else { 2675 pHalData->EEPROMBluetoothCoexist = false; 2676 pHalData->EEPROMBluetoothType = BT_RTL8723B; 2677 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2678 pHalData->ant_path = ODM_RF_PATH_A; 2679 } 2680 2681 if (padapter->registrypriv.ant_num > 0) { 2682 DBG_8192C( 2683 "%s: Apply driver defined antenna number(%d) to replace origin(%d)\n", 2684 __func__, 2685 padapter->registrypriv.ant_num, 2686 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1 2687 ); 2688 2689 switch (padapter->registrypriv.ant_num) { 2690 case 1: 2691 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2692 break; 2693 case 2: 2694 pHalData->EEPROMBluetoothAntNum = Ant_x2; 2695 break; 2696 default: 2697 DBG_8192C( 2698 "%s: Discard invalid driver defined antenna number(%d)!\n", 2699 __func__, 2700 padapter->registrypriv.ant_num 2701 ); 2702 break; 2703 } 2704 } 2705 2706 rtw_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist); 2707 rtw_btcoex_SetChipType(padapter, pHalData->EEPROMBluetoothType); 2708 rtw_btcoex_SetPGAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1); 2709 if (pHalData->EEPROMBluetoothAntNum == Ant_x1) 2710 rtw_btcoex_SetSingleAntPath(padapter, pHalData->ant_path); 2711 2712 DBG_8192C( 2713 "%s: %s BT-coex, ant_num =%d\n", 2714 __func__, 2715 pHalData->EEPROMBluetoothCoexist == true ? "Enable" : "Disable", 2716 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1 2717 ); 2718 } 2719 2720 void Hal_EfuseParseEEPROMVer_8723B( 2721 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2722 ) 2723 { 2724 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2725 2726 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2727 if (!AutoLoadFail) 2728 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B]; 2729 else 2730 pHalData->EEPROMVersion = 1; 2731 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n", 2732 pHalData->EEPROMVersion)); 2733 } 2734 2735 2736 2737 void Hal_EfuseParsePackageType_8723B( 2738 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2739 ) 2740 { 2741 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2742 u8 package; 2743 u8 efuseContent; 2744 2745 Efuse_PowerSwitch(padapter, false, true); 2746 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false); 2747 DBG_871X("%s phy efuse read 0x1FB =%x\n", __func__, efuseContent); 2748 Efuse_PowerSwitch(padapter, false, false); 2749 2750 package = efuseContent & 0x7; 2751 switch (package) { 2752 case 0x4: 2753 pHalData->PackageType = PACKAGE_TFBGA79; 2754 break; 2755 case 0x5: 2756 pHalData->PackageType = PACKAGE_TFBGA90; 2757 break; 2758 case 0x6: 2759 pHalData->PackageType = PACKAGE_QFN68; 2760 break; 2761 case 0x7: 2762 pHalData->PackageType = PACKAGE_TFBGA80; 2763 break; 2764 2765 default: 2766 pHalData->PackageType = PACKAGE_DEFAULT; 2767 break; 2768 } 2769 2770 DBG_871X("PackageType = 0x%X\n", pHalData->PackageType); 2771 } 2772 2773 2774 void Hal_EfuseParseVoltage_8723B( 2775 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2776 ) 2777 { 2778 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2779 2780 /* memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8723B], 1); */ 2781 DBG_871X("%s hwinfo[EEPROM_Voltage_ADDR_8723B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8723B]); 2782 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4; 2783 DBG_871X("%s pEEPROM->adjuseVoltageVal =%x\n", __func__, pEEPROM->adjuseVoltageVal); 2784 } 2785 2786 void Hal_EfuseParseChnlPlan_8723B( 2787 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2788 ) 2789 { 2790 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( 2791 padapter, 2792 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF, 2793 padapter->registrypriv.channel_plan, 2794 RT_CHANNEL_DOMAIN_WORLD_NULL, 2795 AutoLoadFail 2796 ); 2797 2798 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan); 2799 2800 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan)); 2801 } 2802 2803 void Hal_EfuseParseCustomerID_8723B( 2804 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2805 ) 2806 { 2807 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2808 2809 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2810 if (!AutoLoadFail) 2811 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B]; 2812 else 2813 pHalData->EEPROMCustomerID = 0; 2814 2815 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID)); 2816 } 2817 2818 void Hal_EfuseParseAntennaDiversity_8723B( 2819 struct adapter *padapter, 2820 u8 *hwinfo, 2821 bool AutoLoadFail 2822 ) 2823 { 2824 } 2825 2826 void Hal_EfuseParseXtal_8723B( 2827 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2828 ) 2829 { 2830 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2831 2832 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2833 if (!AutoLoadFail) { 2834 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B]; 2835 if (pHalData->CrystalCap == 0xFF) 2836 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; /* what value should 8812 set? */ 2837 } else 2838 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; 2839 2840 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM CrystalCap: 0x%2x\n", pHalData->CrystalCap)); 2841 } 2842 2843 2844 void Hal_EfuseParseThermalMeter_8723B( 2845 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail 2846 ) 2847 { 2848 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2849 2850 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2851 /* */ 2852 /* ThermalMeter from EEPROM */ 2853 /* */ 2854 if (false == AutoLoadFail) 2855 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B]; 2856 else 2857 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B; 2858 2859 if ((pHalData->EEPROMThermalMeter == 0xff) || (true == AutoLoadFail)) { 2860 pHalData->bAPKThermalMeterIgnore = true; 2861 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B; 2862 } 2863 2864 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter)); 2865 } 2866 2867 2868 void Hal_ReadRFGainOffset( 2869 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail 2870 ) 2871 { 2872 /* */ 2873 /* BB_RF Gain Offset from EEPROM */ 2874 /* */ 2875 2876 if (!AutoloadFail) { 2877 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET]; 2878 DBG_871X("AutoloadFail =%x,\n", AutoloadFail); 2879 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL); 2880 DBG_871X("Adapter->eeprompriv.EEPROMRFGainVal =%x\n", Adapter->eeprompriv.EEPROMRFGainVal); 2881 } else { 2882 Adapter->eeprompriv.EEPROMRFGainOffset = 0; 2883 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF; 2884 DBG_871X("else AutoloadFail =%x,\n", AutoloadFail); 2885 } 2886 DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset); 2887 } 2888 2889 u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib) 2890 { 2891 u8 BWSettingOfDesc = 0; 2892 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2893 2894 /* DBG_871X("BWMapping pHalData->CurrentChannelBW %d, pattrib->bwmode %d\n", pHalData->CurrentChannelBW, pattrib->bwmode); */ 2895 2896 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { 2897 if (pattrib->bwmode == CHANNEL_WIDTH_80) 2898 BWSettingOfDesc = 2; 2899 else if (pattrib->bwmode == CHANNEL_WIDTH_40) 2900 BWSettingOfDesc = 1; 2901 else 2902 BWSettingOfDesc = 0; 2903 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { 2904 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80)) 2905 BWSettingOfDesc = 1; 2906 else 2907 BWSettingOfDesc = 0; 2908 } else 2909 BWSettingOfDesc = 0; 2910 2911 /* if (pTcb->bBTTxPacket) */ 2912 /* BWSettingOfDesc = 0; */ 2913 2914 return BWSettingOfDesc; 2915 } 2916 2917 u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib) 2918 { 2919 u8 SCSettingOfDesc = 0; 2920 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2921 2922 /* DBG_871X("SCMapping: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur80MhzPrimeSC, pHalData->nCur40MhzPrimeSC); */ 2923 2924 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { 2925 if (pattrib->bwmode == CHANNEL_WIDTH_80) { 2926 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2927 } else if (pattrib->bwmode == CHANNEL_WIDTH_40) { 2928 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 2929 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ; 2930 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 2931 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ; 2932 else 2933 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n"); 2934 } else { 2935 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) 2936 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ; 2937 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) 2938 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; 2939 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) 2940 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; 2941 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) 2942 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ; 2943 else 2944 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n"); 2945 } 2946 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { 2947 /* DBG_871X("SCMapping: HT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur40MhzPrimeSC); */ 2948 2949 if (pattrib->bwmode == CHANNEL_WIDTH_40) { 2950 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2951 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) { 2952 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) { 2953 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; 2954 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) { 2955 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; 2956 } else { 2957 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2958 } 2959 } 2960 } else { 2961 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2962 } 2963 2964 return SCSettingOfDesc; 2965 } 2966 2967 static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc) 2968 { 2969 u16 *usPtr = (u16 *)ptxdesc; 2970 u32 count; 2971 u32 index; 2972 u16 checksum = 0; 2973 2974 2975 /* Clear first */ 2976 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); 2977 2978 /* checksume is always calculated by first 32 bytes, */ 2979 /* and it doesn't depend on TX DESC length. */ 2980 /* Thomas, Lucas@SD4, 20130515 */ 2981 count = 16; 2982 2983 for (index = 0; index < count; index++) { 2984 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index)); 2985 } 2986 2987 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff); 2988 } 2989 2990 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib) 2991 { 2992 u8 sectype = 0; 2993 if ((pattrib->encrypt > 0) && !pattrib->bswenc) { 2994 switch (pattrib->encrypt) { 2995 /* SEC_TYPE */ 2996 case _WEP40_: 2997 case _WEP104_: 2998 case _TKIP_: 2999 case _TKIP_WTMIC_: 3000 sectype = 1; 3001 break; 3002 3003 case _AES_: 3004 sectype = 3; 3005 break; 3006 3007 case _NO_PRIVACY_: 3008 default: 3009 break; 3010 } 3011 } 3012 return sectype; 3013 } 3014 3015 static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc) 3016 { 3017 /* DBG_8192C("cvs_mode =%d\n", pattrib->vcs_mode); */ 3018 3019 if (pattrib->vcs_mode) { 3020 switch (pattrib->vcs_mode) { 3021 case RTS_CTS: 3022 ptxdesc->rtsen = 1; 3023 /* ENABLE HW RTS */ 3024 ptxdesc->hw_rts_en = 1; 3025 break; 3026 3027 case CTS_TO_SELF: 3028 ptxdesc->cts2self = 1; 3029 break; 3030 3031 case NONE_VCS: 3032 default: 3033 break; 3034 } 3035 3036 ptxdesc->rtsrate = 8; /* RTS Rate =24M */ 3037 ptxdesc->rts_ratefb_lmt = 0xF; 3038 3039 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT) 3040 ptxdesc->rts_short = 1; 3041 3042 /* Set RTS BW */ 3043 if (pattrib->ht_en) 3044 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib); 3045 } 3046 } 3047 3048 static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc) 3049 { 3050 /* DBG_8192C("bwmode =%d, ch_off =%d\n", pattrib->bwmode, pattrib->ch_offset); */ 3051 3052 if (pattrib->ht_en) { 3053 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib); 3054 3055 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib); 3056 } 3057 } 3058 3059 static void rtl8723b_fill_default_txdesc( 3060 struct xmit_frame *pxmitframe, u8 *pbuf 3061 ) 3062 { 3063 struct adapter *padapter; 3064 struct hal_com_data *pHalData; 3065 struct dm_priv *pdmpriv; 3066 struct mlme_ext_priv *pmlmeext; 3067 struct mlme_ext_info *pmlmeinfo; 3068 struct pkt_attrib *pattrib; 3069 PTXDESC_8723B ptxdesc; 3070 s32 bmcst; 3071 3072 memset(pbuf, 0, TXDESC_SIZE); 3073 3074 padapter = pxmitframe->padapter; 3075 pHalData = GET_HAL_DATA(padapter); 3076 pdmpriv = &pHalData->dmpriv; 3077 pmlmeext = &padapter->mlmeextpriv; 3078 pmlmeinfo = &(pmlmeext->mlmext_info); 3079 3080 pattrib = &pxmitframe->attrib; 3081 bmcst = IS_MCAST(pattrib->ra); 3082 3083 ptxdesc = (PTXDESC_8723B)pbuf; 3084 3085 if (pxmitframe->frame_tag == DATA_FRAMETAG) { 3086 u8 drv_userate = 0; 3087 3088 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3089 ptxdesc->rate_id = pattrib->raid; 3090 ptxdesc->qsel = pattrib->qsel; 3091 ptxdesc->seq = pattrib->seqnum; 3092 3093 ptxdesc->sectype = fill_txdesc_sectype(pattrib); 3094 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc); 3095 3096 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1) 3097 drv_userate = 1; 3098 3099 if ( 3100 (pattrib->ether_type != 0x888e) && 3101 (pattrib->ether_type != 0x0806) && 3102 (pattrib->ether_type != 0x88B4) && 3103 (pattrib->dhcp_pkt != 1) && 3104 (drv_userate != 1) 3105 #ifdef CONFIG_AUTO_AP_MODE 3106 && (pattrib->pctrl != true) 3107 #endif 3108 ) { 3109 /* Non EAP & ARP & DHCP type data packet */ 3110 3111 if (pattrib->ampdu_en == true) { 3112 ptxdesc->agg_en = 1; /* AGG EN */ 3113 ptxdesc->max_agg_num = 0x1f; 3114 ptxdesc->ampdu_density = pattrib->ampdu_spacing; 3115 } else 3116 ptxdesc->bk = 1; /* AGG BK */ 3117 3118 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc); 3119 3120 ptxdesc->data_ratefb_lmt = 0x1F; 3121 3122 if (pHalData->fw_ractrl == false) { 3123 ptxdesc->userate = 1; 3124 3125 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7)) 3126 ptxdesc->data_short = 1; 3127 3128 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F; 3129 } 3130 3131 if (padapter->fix_rate != 0xFF) { /* modify data rate by iwpriv */ 3132 ptxdesc->userate = 1; 3133 if (padapter->fix_rate & BIT(7)) 3134 ptxdesc->data_short = 1; 3135 3136 ptxdesc->datarate = (padapter->fix_rate & 0x7F); 3137 ptxdesc->disdatafb = 1; 3138 } 3139 3140 if (pattrib->ldpc) 3141 ptxdesc->data_ldpc = 1; 3142 if (pattrib->stbc) 3143 ptxdesc->data_stbc = 1; 3144 3145 #ifdef CONFIG_CMCC_TEST 3146 ptxdesc->data_short = 1; /* use cck short premble */ 3147 #endif 3148 } else { 3149 /* EAP data packet and ARP packet. */ 3150 /* Use the 1M data rate to send the EAP/ARP packet. */ 3151 /* This will maybe make the handshake smooth. */ 3152 3153 ptxdesc->bk = 1; /* AGG BK */ 3154 ptxdesc->userate = 1; /* driver uses rate */ 3155 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) 3156 ptxdesc->data_short = 1;/* DATA_SHORT */ 3157 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3158 DBG_871X("YJ: %s(): ARP Data: userate =%d, datarate = 0x%x\n", __func__, ptxdesc->userate, ptxdesc->datarate); 3159 } 3160 3161 ptxdesc->usb_txagg_num = pxmitframe->agg_num; 3162 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) { 3163 /* RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MGNT_FRAMETAG\n", __func__)); */ 3164 3165 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3166 ptxdesc->qsel = pattrib->qsel; 3167 ptxdesc->rate_id = pattrib->raid; /* Rate ID */ 3168 ptxdesc->seq = pattrib->seqnum; 3169 ptxdesc->userate = 1; /* driver uses rate, 1M */ 3170 3171 ptxdesc->mbssid = pattrib->mbssid & 0xF; 3172 3173 ptxdesc->rty_lmt_en = 1; /* retry limit enable */ 3174 if (pattrib->retry_ctrl == true) { 3175 ptxdesc->data_rt_lmt = 6; 3176 } else { 3177 ptxdesc->data_rt_lmt = 12; 3178 } 3179 3180 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3181 3182 /* CCX-TXRPT ack for xmit mgmt frames. */ 3183 if (pxmitframe->ack_report) { 3184 #ifdef DBG_CCX 3185 DBG_8192C("%s set spe_rpt\n", __func__); 3186 #endif 3187 ptxdesc->spe_rpt = 1; 3188 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no); 3189 } 3190 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) { 3191 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __func__)); 3192 } else { 3193 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag = 0x%x\n", __func__, pxmitframe->frame_tag)); 3194 3195 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3196 ptxdesc->rate_id = pattrib->raid; /* Rate ID */ 3197 ptxdesc->qsel = pattrib->qsel; 3198 ptxdesc->seq = pattrib->seqnum; 3199 ptxdesc->userate = 1; /* driver uses rate */ 3200 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3201 } 3202 3203 ptxdesc->pktlen = pattrib->last_txcmdsz; 3204 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ; 3205 3206 if (bmcst) 3207 ptxdesc->bmc = 1; 3208 3209 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. */ 3210 /* (1) The sequence number of each non-Qos frame / broadcast / multicast / */ 3211 /* mgnt frame should be controled by Hw because Fw will also send null data */ 3212 /* which we cannot control when Fw LPS enable. */ 3213 /* --> default enable non-Qos data sequense number. 2010.06.23. by tynli. */ 3214 /* (2) Enable HW SEQ control for beacon packet, because we use Hw beacon. */ 3215 /* (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos packets. */ 3216 /* 2010.06.23. Added by tynli. */ 3217 if (!pattrib->qos_en) /* Hw set sequence number */ 3218 ptxdesc->en_hwseq = 1; /* HWSEQ_EN */ 3219 } 3220 3221 /* 3222 *Description: 3223 * 3224 *Parameters: 3225 * pxmitframe xmitframe 3226 * pbuf where to fill tx desc 3227 */ 3228 void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) 3229 { 3230 struct tx_desc *pdesc; 3231 3232 rtl8723b_fill_default_txdesc(pxmitframe, pbuf); 3233 3234 pdesc = (struct tx_desc *)pbuf; 3235 pdesc->txdw0 = pdesc->txdw0; 3236 pdesc->txdw1 = pdesc->txdw1; 3237 pdesc->txdw2 = pdesc->txdw2; 3238 pdesc->txdw3 = pdesc->txdw3; 3239 pdesc->txdw4 = pdesc->txdw4; 3240 pdesc->txdw5 = pdesc->txdw5; 3241 pdesc->txdw6 = pdesc->txdw6; 3242 pdesc->txdw7 = pdesc->txdw7; 3243 pdesc->txdw8 = pdesc->txdw8; 3244 pdesc->txdw9 = pdesc->txdw9; 3245 3246 rtl8723b_cal_txdesc_chksum(pdesc); 3247 } 3248 3249 /* */ 3250 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */ 3251 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */ 3252 /* Fw can tell Hw to send these packet derectly. */ 3253 /* Added by tynli. 2009.10.15. */ 3254 /* */ 3255 /* type1:pspoll, type2:null */ 3256 void rtl8723b_fill_fake_txdesc( 3257 struct adapter *padapter, 3258 u8 *pDesc, 3259 u32 BufferLen, 3260 u8 IsPsPoll, 3261 u8 IsBTQosNull, 3262 u8 bDataFrame 3263 ) 3264 { 3265 /* Clear all status */ 3266 memset(pDesc, 0, TXDESC_SIZE); 3267 3268 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1); /* bFirstSeg; */ 3269 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1); /* bLastSeg; */ 3270 3271 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28); /* Offset = 32 */ 3272 3273 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen); /* Buffer size + command header */ 3274 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ 3275 3276 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */ 3277 if (true == IsPsPoll) { 3278 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1); 3279 } else { 3280 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1); /* Hw set sequence number */ 3281 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0); 3282 } 3283 3284 if (true == IsBTQosNull) { 3285 SET_TX_DESC_BT_INT_8723B(pDesc, 1); 3286 } 3287 3288 SET_TX_DESC_USE_RATE_8723B(pDesc, 1); /* use data rate which is set by Sw */ 3289 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1); 3290 3291 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M); 3292 3293 /* */ 3294 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */ 3295 /* */ 3296 if (true == bDataFrame) { 3297 u32 EncAlg; 3298 3299 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm; 3300 switch (EncAlg) { 3301 case _NO_PRIVACY_: 3302 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0); 3303 break; 3304 case _WEP40_: 3305 case _WEP104_: 3306 case _TKIP_: 3307 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1); 3308 break; 3309 case _SMS4_: 3310 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2); 3311 break; 3312 case _AES_: 3313 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3); 3314 break; 3315 default: 3316 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0); 3317 break; 3318 } 3319 } 3320 3321 /* USB interface drop packet if the checksum of descriptor isn't correct. */ 3322 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */ 3323 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc); 3324 } 3325 3326 static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val) 3327 { 3328 u8 val8; 3329 u8 mode = *((u8 *)val); 3330 3331 { 3332 /* disable Port0 TSF update */ 3333 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3334 val8 |= DIS_TSF_UDT; 3335 rtw_write8(padapter, REG_BCN_CTRL, val8); 3336 3337 /* set net_type */ 3338 Set_MSR(padapter, mode); 3339 DBG_871X("#### %s() -%d iface_type(0) mode = %d ####\n", __func__, __LINE__, mode); 3340 3341 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { 3342 { 3343 StopTxBeacon(padapter); 3344 #ifdef CONFIG_INTERRUPT_BASED_TXBCN 3345 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT 3346 rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */ 3347 UpdateInterruptMask8812AU(padapter, true, 0, IMR_BCNDMAINT0_8723B); 3348 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ 3349 3350 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR 3351 UpdateInterruptMask8812AU(padapter, true, 0, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B)); 3352 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ 3353 3354 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ 3355 } 3356 3357 /* disable atim wnd */ 3358 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM); 3359 /* rtw_write8(padapter, REG_BCN_CTRL, 0x18); */ 3360 } else if ((mode == _HW_STATE_ADHOC_) /*|| (mode == _HW_STATE_AP_)*/) { 3361 ResumeTxBeacon(padapter); 3362 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB); 3363 } else if (mode == _HW_STATE_AP_) { 3364 #ifdef CONFIG_INTERRUPT_BASED_TXBCN 3365 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT 3366 UpdateInterruptMask8723BU(padapter, true, IMR_BCNDMAINT0_8723B, 0); 3367 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ 3368 3369 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR 3370 UpdateInterruptMask8723BU(padapter, true, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B), 0); 3371 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ 3372 3373 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ 3374 3375 ResumeTxBeacon(padapter); 3376 3377 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB); 3378 3379 /* Set RCR */ 3380 rtw_write32(padapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0, reject ICV_ERR packet */ 3381 /* enable to rx data frame */ 3382 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3383 /* enable to rx ps-poll */ 3384 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400); 3385 3386 /* Beacon Control related register for first time */ 3387 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */ 3388 3389 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */ 3390 rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */ 3391 rtw_write16(padapter, REG_BCNTCFG, 0x00); 3392 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04); 3393 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ 3394 3395 /* reset TSF */ 3396 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); 3397 3398 /* enable BCN0 Function for if1 */ 3399 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ 3400 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB)); 3401 3402 /* SW_BCN_SEL - Port0 */ 3403 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */ 3404 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); 3405 3406 /* select BCN on port 0 */ 3407 rtw_write8( 3408 padapter, 3409 REG_CCK_CHECK_8723B, 3410 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL) 3411 ); 3412 3413 /* dis BCN1 ATIM WND if if2 is station */ 3414 val8 = rtw_read8(padapter, REG_BCN_CTRL_1); 3415 val8 |= DIS_ATIM; 3416 rtw_write8(padapter, REG_BCN_CTRL_1, val8); 3417 } 3418 } 3419 } 3420 3421 static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val) 3422 { 3423 u8 idx = 0; 3424 u32 reg_macid; 3425 3426 reg_macid = REG_MACID; 3427 3428 for (idx = 0 ; idx < 6; idx++) 3429 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]); 3430 } 3431 3432 static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val) 3433 { 3434 u8 idx = 0; 3435 u32 reg_bssid; 3436 3437 reg_bssid = REG_BSSID; 3438 3439 for (idx = 0 ; idx < 6; idx++) 3440 rtw_write8(padapter, (reg_bssid+idx), val[idx]); 3441 } 3442 3443 static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val) 3444 { 3445 u32 bcn_ctrl_reg; 3446 3447 bcn_ctrl_reg = REG_BCN_CTRL; 3448 3449 if (*(u8 *)val) 3450 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); 3451 else { 3452 u8 val8; 3453 val8 = rtw_read8(padapter, bcn_ctrl_reg); 3454 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT); 3455 3456 /* Always enable port0 beacon function for PSTDMA */ 3457 if (REG_BCN_CTRL == bcn_ctrl_reg) 3458 val8 |= EN_BCN_FUNCTION; 3459 3460 rtw_write8(padapter, bcn_ctrl_reg, val8); 3461 } 3462 } 3463 3464 static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val) 3465 { 3466 u8 val8; 3467 u64 tsf; 3468 struct mlme_ext_priv *pmlmeext; 3469 struct mlme_ext_info *pmlmeinfo; 3470 3471 3472 pmlmeext = &padapter->mlmeextpriv; 3473 pmlmeinfo = &pmlmeext->mlmext_info; 3474 3475 tsf = pmlmeext->TSFValue-rtw_modular64(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024; /* us */ 3476 3477 if ( 3478 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || 3479 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) 3480 ) 3481 StopTxBeacon(padapter); 3482 3483 { 3484 /* disable related TSF function */ 3485 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3486 val8 &= ~EN_BCN_FUNCTION; 3487 rtw_write8(padapter, REG_BCN_CTRL, val8); 3488 3489 rtw_write32(padapter, REG_TSFTR, tsf); 3490 rtw_write32(padapter, REG_TSFTR+4, tsf>>32); 3491 3492 /* enable related TSF function */ 3493 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3494 val8 |= EN_BCN_FUNCTION; 3495 rtw_write8(padapter, REG_BCN_CTRL, val8); 3496 } 3497 3498 if ( 3499 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || 3500 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) 3501 ) 3502 ResumeTxBeacon(padapter); 3503 } 3504 3505 static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val) 3506 { 3507 u8 val8; 3508 3509 /* Set RCR to not to receive data frame when NO LINK state */ 3510 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */ 3511 /* reject all data frames */ 3512 rtw_write16(padapter, REG_RXFLTMAP2, 0); 3513 3514 /* reset TSF */ 3515 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); 3516 3517 /* disable update TSF */ 3518 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3519 val8 |= DIS_TSF_UDT; 3520 rtw_write8(padapter, REG_BCN_CTRL, val8); 3521 } 3522 3523 static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val) 3524 { 3525 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl; 3526 u16 value_rxfltmap2; 3527 u8 val8; 3528 struct hal_com_data *pHalData; 3529 struct mlme_priv *pmlmepriv; 3530 3531 3532 pHalData = GET_HAL_DATA(padapter); 3533 pmlmepriv = &padapter->mlmepriv; 3534 3535 reg_bcn_ctl = REG_BCN_CTRL; 3536 3537 rcr_clear_bit = RCR_CBSSID_BCN; 3538 3539 /* config RCR to receive different BSSID & not to receive data frame */ 3540 value_rxfltmap2 = 0; 3541 3542 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true)) 3543 rcr_clear_bit = RCR_CBSSID_BCN; 3544 3545 value_rcr = rtw_read32(padapter, REG_RCR); 3546 3547 if (*((u8 *)val)) { 3548 /* under sitesurvey */ 3549 value_rcr &= ~(rcr_clear_bit); 3550 rtw_write32(padapter, REG_RCR, value_rcr); 3551 3552 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2); 3553 3554 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { 3555 /* disable update TSF */ 3556 val8 = rtw_read8(padapter, reg_bcn_ctl); 3557 val8 |= DIS_TSF_UDT; 3558 rtw_write8(padapter, reg_bcn_ctl, val8); 3559 } 3560 3561 /* Save orignal RRSR setting. */ 3562 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR); 3563 } else { 3564 /* sitesurvey done */ 3565 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE))) 3566 /* enable to rx data frame */ 3567 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3568 3569 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { 3570 /* enable update TSF */ 3571 val8 = rtw_read8(padapter, reg_bcn_ctl); 3572 val8 &= ~DIS_TSF_UDT; 3573 rtw_write8(padapter, reg_bcn_ctl, val8); 3574 } 3575 3576 value_rcr |= rcr_clear_bit; 3577 rtw_write32(padapter, REG_RCR, value_rcr); 3578 3579 /* Restore orignal RRSR setting. */ 3580 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR); 3581 } 3582 } 3583 3584 static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val) 3585 { 3586 u8 val8; 3587 u16 val16; 3588 u32 val32; 3589 u8 RetryLimit; 3590 u8 type; 3591 struct hal_com_data *pHalData; 3592 struct mlme_priv *pmlmepriv; 3593 struct eeprom_priv *pEEPROM; 3594 3595 3596 RetryLimit = 0x30; 3597 type = *(u8 *)val; 3598 pHalData = GET_HAL_DATA(padapter); 3599 pmlmepriv = &padapter->mlmepriv; 3600 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 3601 3602 if (type == 0) { /* prepare to join */ 3603 /* enable to rx data frame.Accept all data frame */ 3604 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */ 3605 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3606 3607 val32 = rtw_read32(padapter, REG_RCR); 3608 if (padapter->in_cta_test) 3609 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */ 3610 else 3611 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN; 3612 rtw_write32(padapter, REG_RCR, val32); 3613 3614 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true) 3615 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48; 3616 else /* Ad-hoc Mode */ 3617 RetryLimit = 0x7; 3618 } else if (type == 1) /* joinbss_event call back when join res < 0 */ 3619 rtw_write16(padapter, REG_RXFLTMAP2, 0x00); 3620 else if (type == 2) { /* sta add event call back */ 3621 /* enable update TSF */ 3622 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3623 val8 &= ~DIS_TSF_UDT; 3624 rtw_write8(padapter, REG_BCN_CTRL, val8); 3625 3626 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) 3627 RetryLimit = 0x7; 3628 } 3629 3630 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT); 3631 rtw_write16(padapter, REG_RL, val16); 3632 } 3633 3634 void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len) 3635 { 3636 u8 seq_no; 3637 3638 #define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) 3639 #define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) 3640 3641 /* DBG_871X("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, */ 3642 /* *pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */ 3643 3644 seq_no = *(pdata+6); 3645 3646 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) { 3647 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); 3648 } 3649 /* 3650 else if (seq_no != padapter->xmitpriv.seq_no) { 3651 DBG_871X("tx_seq_no =%d, rpt_seq_no =%d\n", padapter->xmitpriv.seq_no, seq_no); 3652 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); 3653 } 3654 */ 3655 else 3656 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); 3657 } 3658 3659 s32 c2h_id_filter_ccx_8723b(u8 *buf) 3660 { 3661 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf; 3662 s32 ret = false; 3663 if (c2h_evt->id == C2H_CCX_TX_RPT) 3664 ret = true; 3665 3666 return ret; 3667 } 3668 3669 3670 s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf) 3671 { 3672 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf; 3673 s32 ret = _SUCCESS; 3674 u8 index = 0; 3675 3676 if (pC2hEvent == NULL) { 3677 DBG_8192C("%s(): pC2hEventis NULL\n", __func__); 3678 ret = _FAIL; 3679 goto exit; 3680 } 3681 3682 switch (pC2hEvent->id) { 3683 case C2H_AP_RPT_RSP: 3684 break; 3685 case C2H_DBG: 3686 { 3687 RT_TRACE(_module_hal_init_c_, _drv_info_, ("c2h_handler_8723b: %s\n", pC2hEvent->payload)); 3688 } 3689 break; 3690 3691 case C2H_CCX_TX_RPT: 3692 /* CCX_FwC2HTxRpt(padapter, QueueID, pC2hEvent->payload); */ 3693 break; 3694 3695 case C2H_EXT_RA_RPT: 3696 /* C2HExtRaRptHandler(padapter, pC2hEvent->payload, C2hEvent.CmdLen); */ 3697 break; 3698 3699 case C2H_HW_INFO_EXCH: 3700 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n")); 3701 for (index = 0; index < pC2hEvent->plen; index++) { 3702 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, pC2hEvent->payload[index])); 3703 } 3704 break; 3705 3706 case C2H_8723B_BT_INFO: 3707 rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload); 3708 break; 3709 3710 default: 3711 break; 3712 } 3713 3714 /* Clear event to notify FW we have read the command. */ 3715 /* Note: */ 3716 /* If this field isn't clear, the FW won't update the next command message. */ 3717 /* rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); */ 3718 exit: 3719 return ret; 3720 } 3721 3722 static void process_c2h_event(struct adapter *padapter, PC2H_EVT_HDR pC2hEvent, u8 *c2hBuf) 3723 { 3724 u8 index = 0; 3725 3726 if (c2hBuf == NULL) { 3727 DBG_8192C("%s c2hbuff is NULL\n", __func__); 3728 return; 3729 } 3730 3731 switch (pC2hEvent->CmdID) { 3732 case C2H_AP_RPT_RSP: 3733 break; 3734 case C2H_DBG: 3735 { 3736 RT_TRACE(_module_hal_init_c_, _drv_info_, ("C2HCommandHandler: %s\n", c2hBuf)); 3737 } 3738 break; 3739 3740 case C2H_CCX_TX_RPT: 3741 /* CCX_FwC2HTxRpt(padapter, QueueID, tmpBuf); */ 3742 break; 3743 3744 case C2H_EXT_RA_RPT: 3745 /* C2HExtRaRptHandler(padapter, tmpBuf, C2hEvent.CmdLen); */ 3746 break; 3747 3748 case C2H_HW_INFO_EXCH: 3749 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n")); 3750 for (index = 0; index < pC2hEvent->CmdLen; index++) { 3751 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, c2hBuf[index])); 3752 } 3753 break; 3754 3755 case C2H_8723B_BT_INFO: 3756 rtw_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf); 3757 break; 3758 3759 default: 3760 break; 3761 } 3762 } 3763 3764 void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length) 3765 { 3766 C2H_EVT_HDR C2hEvent; 3767 u8 *tmpBuf = NULL; 3768 #ifdef CONFIG_WOWLAN 3769 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); 3770 3771 if (pwrpriv->wowlan_mode == true) { 3772 DBG_871X("%s(): return because wowolan_mode ==true! CMDID =%d\n", __func__, pbuffer[0]); 3773 return; 3774 } 3775 #endif 3776 C2hEvent.CmdID = pbuffer[0]; 3777 C2hEvent.CmdSeq = pbuffer[1]; 3778 C2hEvent.CmdLen = length-2; 3779 tmpBuf = pbuffer+2; 3780 3781 /* DBG_871X("%s C2hEvent.CmdID:%x C2hEvent.CmdLen:%x C2hEvent.CmdSeq:%x\n", */ 3782 /* __func__, C2hEvent.CmdID, C2hEvent.CmdLen, C2hEvent.CmdSeq); */ 3783 RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HPacketHandler_8723B(): Command Content:\n", tmpBuf, C2hEvent.CmdLen); 3784 3785 process_c2h_event(padapter, &C2hEvent, tmpBuf); 3786 /* c2h_handler_8723b(padapter,&C2hEvent); */ 3787 return; 3788 } 3789 3790 void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) 3791 { 3792 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 3793 u8 val8; 3794 u32 val32; 3795 3796 switch (variable) { 3797 case HW_VAR_MEDIA_STATUS: 3798 val8 = rtw_read8(padapter, MSR) & 0x0c; 3799 val8 |= *val; 3800 rtw_write8(padapter, MSR, val8); 3801 break; 3802 3803 case HW_VAR_MEDIA_STATUS1: 3804 val8 = rtw_read8(padapter, MSR) & 0x03; 3805 val8 |= *val << 2; 3806 rtw_write8(padapter, MSR, val8); 3807 break; 3808 3809 case HW_VAR_SET_OPMODE: 3810 hw_var_set_opmode(padapter, variable, val); 3811 break; 3812 3813 case HW_VAR_MAC_ADDR: 3814 hw_var_set_macaddr(padapter, variable, val); 3815 break; 3816 3817 case HW_VAR_BSSID: 3818 hw_var_set_bssid(padapter, variable, val); 3819 break; 3820 3821 case HW_VAR_BASIC_RATE: 3822 { 3823 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info; 3824 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0; 3825 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M); 3826 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES); 3827 3828 HalSetBrateCfg(padapter, val, &BrateCfg); 3829 input_b = BrateCfg; 3830 3831 /* apply force and allow mask */ 3832 BrateCfg |= rrsr_2g_force_mask; 3833 BrateCfg &= rrsr_2g_allow_mask; 3834 masked = BrateCfg; 3835 3836 #ifdef CONFIG_CMCC_TEST 3837 BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M); /* use 11M to send ACK */ 3838 BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M); /* CMCC_OFDM_ACK 12/18/24M */ 3839 #endif 3840 3841 /* IOT consideration */ 3842 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) { 3843 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */ 3844 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0) 3845 BrateCfg |= RRSR_6M; 3846 } 3847 ioted = BrateCfg; 3848 3849 pHalData->BasicRateSet = BrateCfg; 3850 3851 DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted); 3852 3853 /* Set RRSR rate table. */ 3854 rtw_write16(padapter, REG_RRSR, BrateCfg); 3855 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0); 3856 } 3857 break; 3858 3859 case HW_VAR_TXPAUSE: 3860 rtw_write8(padapter, REG_TXPAUSE, *val); 3861 break; 3862 3863 case HW_VAR_BCN_FUNC: 3864 hw_var_set_bcn_func(padapter, variable, val); 3865 break; 3866 3867 case HW_VAR_CORRECT_TSF: 3868 hw_var_set_correct_tsf(padapter, variable, val); 3869 break; 3870 3871 case HW_VAR_CHECK_BSSID: 3872 { 3873 u32 val32; 3874 val32 = rtw_read32(padapter, REG_RCR); 3875 if (*val) 3876 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN; 3877 else 3878 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN); 3879 rtw_write32(padapter, REG_RCR, val32); 3880 } 3881 break; 3882 3883 case HW_VAR_MLME_DISCONNECT: 3884 hw_var_set_mlme_disconnect(padapter, variable, val); 3885 break; 3886 3887 case HW_VAR_MLME_SITESURVEY: 3888 hw_var_set_mlme_sitesurvey(padapter, variable, val); 3889 3890 rtw_btcoex_ScanNotify(padapter, *val?true:false); 3891 break; 3892 3893 case HW_VAR_MLME_JOIN: 3894 hw_var_set_mlme_join(padapter, variable, val); 3895 3896 switch (*val) { 3897 case 0: 3898 /* prepare to join */ 3899 rtw_btcoex_ConnectNotify(padapter, true); 3900 break; 3901 case 1: 3902 /* joinbss_event callback when join res < 0 */ 3903 rtw_btcoex_ConnectNotify(padapter, false); 3904 break; 3905 case 2: 3906 /* sta add event callback */ 3907 /* rtw_btcoex_MediaStatusNotify(padapter, RT_MEDIA_CONNECT); */ 3908 break; 3909 } 3910 break; 3911 3912 case HW_VAR_ON_RCR_AM: 3913 val32 = rtw_read32(padapter, REG_RCR); 3914 val32 |= RCR_AM; 3915 rtw_write32(padapter, REG_RCR, val32); 3916 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); 3917 break; 3918 3919 case HW_VAR_OFF_RCR_AM: 3920 val32 = rtw_read32(padapter, REG_RCR); 3921 val32 &= ~RCR_AM; 3922 rtw_write32(padapter, REG_RCR, val32); 3923 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); 3924 break; 3925 3926 case HW_VAR_BEACON_INTERVAL: 3927 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val)); 3928 break; 3929 3930 case HW_VAR_SLOT_TIME: 3931 rtw_write8(padapter, REG_SLOT, *val); 3932 break; 3933 3934 case HW_VAR_RESP_SIFS: 3935 /* SIFS_Timer = 0x0a0a0808; */ 3936 /* RESP_SIFS for CCK */ 3937 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */ 3938 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]); /* SIFS_R2T_CCK(0x08) */ 3939 /* RESP_SIFS for OFDM */ 3940 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */ 3941 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */ 3942 break; 3943 3944 case HW_VAR_ACK_PREAMBLE: 3945 { 3946 u8 regTmp; 3947 u8 bShortPreamble = *val; 3948 3949 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */ 3950 /* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */ 3951 regTmp = 0; 3952 if (bShortPreamble) 3953 regTmp |= 0x80; 3954 rtw_write8(padapter, REG_RRSR+2, regTmp); 3955 } 3956 break; 3957 3958 case HW_VAR_CAM_EMPTY_ENTRY: 3959 { 3960 u8 ucIndex = *val; 3961 u8 i; 3962 u32 ulCommand = 0; 3963 u32 ulContent = 0; 3964 u32 ulEncAlgo = CAM_AES; 3965 3966 for (i = 0; i < CAM_CONTENT_COUNT; i++) { 3967 /* filled id in CAM config 2 byte */ 3968 if (i == 0) { 3969 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2); 3970 /* ulContent |= CAM_VALID; */ 3971 } else 3972 ulContent = 0; 3973 3974 /* polling bit, and No Write enable, and address */ 3975 ulCommand = CAM_CONTENT_COUNT*ucIndex+i; 3976 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE; 3977 /* write content 0 is equall to mark invalid */ 3978 rtw_write32(padapter, WCAMI, ulContent); /* mdelay(40); */ 3979 /* RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx\n", ulContent)); */ 3980 rtw_write32(padapter, RWCAM, ulCommand); /* mdelay(40); */ 3981 /* RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx\n", ulCommand)); */ 3982 } 3983 } 3984 break; 3985 3986 case HW_VAR_CAM_INVALID_ALL: 3987 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30)); 3988 break; 3989 3990 case HW_VAR_CAM_WRITE: 3991 { 3992 u32 cmd; 3993 u32 *cam_val = (u32 *)val; 3994 3995 rtw_write32(padapter, WCAMI, cam_val[0]); 3996 3997 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1]; 3998 rtw_write32(padapter, RWCAM, cmd); 3999 } 4000 break; 4001 4002 case HW_VAR_AC_PARAM_VO: 4003 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val)); 4004 break; 4005 4006 case HW_VAR_AC_PARAM_VI: 4007 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val)); 4008 break; 4009 4010 case HW_VAR_AC_PARAM_BE: 4011 pHalData->AcParam_BE = ((u32 *)(val))[0]; 4012 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val)); 4013 break; 4014 4015 case HW_VAR_AC_PARAM_BK: 4016 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val)); 4017 break; 4018 4019 case HW_VAR_ACM_CTRL: 4020 { 4021 u8 ctrl = *((u8 *)val); 4022 u8 hwctrl = 0; 4023 4024 if (ctrl != 0) { 4025 hwctrl |= AcmHw_HwEn; 4026 4027 if (ctrl & BIT(1)) /* BE */ 4028 hwctrl |= AcmHw_BeqEn; 4029 4030 if (ctrl & BIT(2)) /* VI */ 4031 hwctrl |= AcmHw_ViqEn; 4032 4033 if (ctrl & BIT(3)) /* VO */ 4034 hwctrl |= AcmHw_VoqEn; 4035 } 4036 4037 DBG_8192C("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl); 4038 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl); 4039 } 4040 break; 4041 4042 case HW_VAR_AMPDU_FACTOR: 4043 { 4044 u32 AMPDULen = (*((u8 *)val)); 4045 4046 if (AMPDULen < HT_AGG_SIZE_32K) 4047 AMPDULen = (0x2000 << (*((u8 *)val)))-1; 4048 else 4049 AMPDULen = 0x7fff; 4050 4051 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen); 4052 } 4053 break; 4054 4055 case HW_VAR_H2C_FW_PWRMODE: 4056 { 4057 u8 psmode = *val; 4058 4059 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */ 4060 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */ 4061 if (psmode != PS_MODE_ACTIVE) { 4062 ODM_RF_Saving(&pHalData->odmpriv, true); 4063 } 4064 4065 /* if (psmode != PS_MODE_ACTIVE) { */ 4066 /* rtl8723b_set_lowpwr_lps_cmd(padapter, true); */ 4067 /* else { */ 4068 /* rtl8723b_set_lowpwr_lps_cmd(padapter, false); */ 4069 /* */ 4070 rtl8723b_set_FwPwrMode_cmd(padapter, psmode); 4071 } 4072 break; 4073 case HW_VAR_H2C_PS_TUNE_PARAM: 4074 rtl8723b_set_FwPsTuneParam_cmd(padapter); 4075 break; 4076 4077 case HW_VAR_H2C_FW_JOINBSSRPT: 4078 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val); 4079 break; 4080 4081 case HW_VAR_INITIAL_GAIN: 4082 { 4083 DIG_T *pDigTable = &pHalData->odmpriv.DM_DigTable; 4084 u32 rx_gain = *(u32 *)val; 4085 4086 if (rx_gain == 0xff) {/* restore rx gain */ 4087 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue); 4088 } else { 4089 pDigTable->BackupIGValue = pDigTable->CurIGValue; 4090 ODM_Write_DIG(&pHalData->odmpriv, rx_gain); 4091 } 4092 } 4093 break; 4094 4095 case HW_VAR_EFUSE_USAGE: 4096 pHalData->EfuseUsedPercentage = *val; 4097 break; 4098 4099 case HW_VAR_EFUSE_BYTES: 4100 pHalData->EfuseUsedBytes = *((u16 *)val); 4101 break; 4102 4103 case HW_VAR_EFUSE_BT_USAGE: 4104 #ifdef HAL_EFUSE_MEMORY 4105 pHalData->EfuseHal.BTEfuseUsedPercentage = *val; 4106 #endif 4107 break; 4108 4109 case HW_VAR_EFUSE_BT_BYTES: 4110 #ifdef HAL_EFUSE_MEMORY 4111 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val); 4112 #else 4113 BTEfuseUsedBytes = *((u16 *)val); 4114 #endif 4115 break; 4116 4117 case HW_VAR_FIFO_CLEARN_UP: 4118 { 4119 #define RW_RELEASE_EN BIT(18) 4120 #define RXDMA_IDLE BIT(17) 4121 4122 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); 4123 u8 trycnt = 100; 4124 4125 /* pause tx */ 4126 rtw_write8(padapter, REG_TXPAUSE, 0xff); 4127 4128 /* keep sn */ 4129 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ); 4130 4131 if (pwrpriv->bkeepfwalive != true) { 4132 /* RX DMA stop */ 4133 val32 = rtw_read32(padapter, REG_RXPKT_NUM); 4134 val32 |= RW_RELEASE_EN; 4135 rtw_write32(padapter, REG_RXPKT_NUM, val32); 4136 do { 4137 val32 = rtw_read32(padapter, REG_RXPKT_NUM); 4138 val32 &= RXDMA_IDLE; 4139 if (val32) 4140 break; 4141 4142 DBG_871X("%s: [HW_VAR_FIFO_CLEARN_UP] val =%x times:%d\n", __func__, val32, trycnt); 4143 } while (--trycnt); 4144 4145 if (trycnt == 0) { 4146 DBG_8192C("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n"); 4147 } 4148 4149 /* RQPN Load 0 */ 4150 rtw_write16(padapter, REG_RQPN_NPQ, 0); 4151 rtw_write32(padapter, REG_RQPN, 0x80000000); 4152 mdelay(2); 4153 } 4154 } 4155 break; 4156 4157 case HW_VAR_APFM_ON_MAC: 4158 pHalData->bMacPwrCtrlOn = *val; 4159 DBG_8192C("%s: bMacPwrCtrlOn =%d\n", __func__, pHalData->bMacPwrCtrlOn); 4160 break; 4161 4162 case HW_VAR_NAV_UPPER: 4163 { 4164 u32 usNavUpper = *((u32 *)val); 4165 4166 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF) { 4167 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", usNavUpper, HAL_NAV_UPPER_UNIT_8723B)); 4168 break; 4169 } 4170 4171 /* The value of ((usNavUpper + HAL_NAV_UPPER_UNIT_8723B - 1) / HAL_NAV_UPPER_UNIT_8723B) */ 4172 /* is getting the upper integer. */ 4173 usNavUpper = (usNavUpper + HAL_NAV_UPPER_UNIT_8723B - 1) / HAL_NAV_UPPER_UNIT_8723B; 4174 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper); 4175 } 4176 break; 4177 4178 case HW_VAR_H2C_MEDIA_STATUS_RPT: 4179 { 4180 u16 mstatus_rpt = (*(u16 *)val); 4181 u8 mstatus, macId; 4182 4183 mstatus = (u8) (mstatus_rpt & 0xFF); 4184 macId = (u8)(mstatus_rpt >> 8); 4185 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId); 4186 } 4187 break; 4188 case HW_VAR_BCN_VALID: 4189 { 4190 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ 4191 val8 = rtw_read8(padapter, REG_TDECTRL+2); 4192 val8 |= BIT(0); 4193 rtw_write8(padapter, REG_TDECTRL+2, val8); 4194 } 4195 break; 4196 4197 case HW_VAR_DL_BCN_SEL: 4198 { 4199 /* SW_BCN_SEL - Port0 */ 4200 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2); 4201 val8 &= ~BIT(4); 4202 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8); 4203 } 4204 break; 4205 4206 case HW_VAR_DO_IQK: 4207 pHalData->bNeedIQK = true; 4208 break; 4209 4210 case HW_VAR_DL_RSVD_PAGE: 4211 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true) 4212 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter); 4213 else 4214 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT); 4215 break; 4216 4217 case HW_VAR_MACID_SLEEP: 4218 /* Input is MACID */ 4219 val32 = *(u32 *)val; 4220 if (val32 > 31) { 4221 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] Invalid macid(%d)\n", 4222 FUNC_ADPT_ARG(padapter), val32); 4223 break; 4224 } 4225 val8 = (u8)val32; /* macid is between 0~31 */ 4226 4227 val32 = rtw_read32(padapter, REG_MACID_SLEEP); 4228 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid =%d, org MACID_SLEEP = 0x%08X\n", 4229 FUNC_ADPT_ARG(padapter), val8, val32); 4230 if (val32 & BIT(val8)) 4231 break; 4232 val32 |= BIT(val8); 4233 rtw_write32(padapter, REG_MACID_SLEEP, val32); 4234 break; 4235 4236 case HW_VAR_MACID_WAKEUP: 4237 /* Input is MACID */ 4238 val32 = *(u32 *)val; 4239 if (val32 > 31) { 4240 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] Invalid macid(%d)\n", 4241 FUNC_ADPT_ARG(padapter), val32); 4242 break; 4243 } 4244 val8 = (u8)val32; /* macid is between 0~31 */ 4245 4246 val32 = rtw_read32(padapter, REG_MACID_SLEEP); 4247 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid =%d, org MACID_SLEEP = 0x%08X\n", 4248 FUNC_ADPT_ARG(padapter), val8, val32); 4249 if (!(val32 & BIT(val8))) 4250 break; 4251 val32 &= ~BIT(val8); 4252 rtw_write32(padapter, REG_MACID_SLEEP, val32); 4253 break; 4254 4255 default: 4256 SetHwReg(padapter, variable, val); 4257 break; 4258 } 4259 } 4260 4261 void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) 4262 { 4263 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 4264 u8 val8; 4265 u16 val16; 4266 4267 switch (variable) { 4268 case HW_VAR_TXPAUSE: 4269 *val = rtw_read8(padapter, REG_TXPAUSE); 4270 break; 4271 4272 case HW_VAR_BCN_VALID: 4273 { 4274 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */ 4275 val8 = rtw_read8(padapter, REG_TDECTRL+2); 4276 *val = (BIT(0) & val8) ? true : false; 4277 } 4278 break; 4279 4280 case HW_VAR_FWLPS_RF_ON: 4281 { 4282 /* When we halt NIC, we should check if FW LPS is leave. */ 4283 u32 valRCR; 4284 4285 if ( 4286 (padapter->bSurpriseRemoved == true) || 4287 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off) 4288 ) { 4289 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */ 4290 /* because Fw is unload. */ 4291 *val = true; 4292 } else { 4293 valRCR = rtw_read32(padapter, REG_RCR); 4294 valRCR &= 0x00070000; 4295 if (valRCR) 4296 *val = false; 4297 else 4298 *val = true; 4299 } 4300 } 4301 break; 4302 4303 case HW_VAR_EFUSE_USAGE: 4304 *val = pHalData->EfuseUsedPercentage; 4305 break; 4306 4307 case HW_VAR_EFUSE_BYTES: 4308 *((u16 *)val) = pHalData->EfuseUsedBytes; 4309 break; 4310 4311 case HW_VAR_EFUSE_BT_USAGE: 4312 #ifdef HAL_EFUSE_MEMORY 4313 *val = pHalData->EfuseHal.BTEfuseUsedPercentage; 4314 #endif 4315 break; 4316 4317 case HW_VAR_EFUSE_BT_BYTES: 4318 #ifdef HAL_EFUSE_MEMORY 4319 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes; 4320 #else 4321 *((u16 *)val) = BTEfuseUsedBytes; 4322 #endif 4323 break; 4324 4325 case HW_VAR_APFM_ON_MAC: 4326 *val = pHalData->bMacPwrCtrlOn; 4327 break; 4328 case HW_VAR_CHK_HI_QUEUE_EMPTY: 4329 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY); 4330 *val = (val16 & BIT(10)) ? true:false; 4331 break; 4332 #ifdef CONFIG_WOWLAN 4333 case HW_VAR_RPWM_TOG: 4334 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7; 4335 break; 4336 case HW_VAR_WAKEUP_REASON: 4337 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON); 4338 if (*val == 0xEA) 4339 *val = 0; 4340 break; 4341 case HW_VAR_SYS_CLKR: 4342 *val = rtw_read8(padapter, REG_SYS_CLKR); 4343 break; 4344 #endif 4345 default: 4346 GetHwReg(padapter, variable, val); 4347 break; 4348 } 4349 } 4350 4351 /* 4352 *Description: 4353 * Change default setting of specified variable. 4354 */ 4355 u8 SetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval) 4356 { 4357 struct hal_com_data *pHalData; 4358 u8 bResult; 4359 4360 4361 pHalData = GET_HAL_DATA(padapter); 4362 bResult = _SUCCESS; 4363 4364 switch (variable) { 4365 default: 4366 bResult = SetHalDefVar(padapter, variable, pval); 4367 break; 4368 } 4369 4370 return bResult; 4371 } 4372 4373 /* 4374 *Description: 4375 * Query setting of specified variable. 4376 */ 4377 u8 GetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval) 4378 { 4379 struct hal_com_data *pHalData; 4380 u8 bResult; 4381 4382 4383 pHalData = GET_HAL_DATA(padapter); 4384 bResult = _SUCCESS; 4385 4386 switch (variable) { 4387 case HAL_DEF_MAX_RECVBUF_SZ: 4388 *((u32 *)pval) = MAX_RECVBUF_SZ; 4389 break; 4390 4391 case HAL_DEF_RX_PACKET_OFFSET: 4392 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8; 4393 break; 4394 4395 case HW_VAR_MAX_RX_AMPDU_FACTOR: 4396 /* Stanley@BB.SD3 suggests 16K can get stable performance */ 4397 /* The experiment was done on SDIO interface */ 4398 /* coding by Lucas@20130730 */ 4399 *(u32 *)pval = MAX_AMPDU_FACTOR_16K; 4400 break; 4401 case HAL_DEF_TX_LDPC: 4402 case HAL_DEF_RX_LDPC: 4403 *((u8 *)pval) = false; 4404 break; 4405 case HAL_DEF_TX_STBC: 4406 *((u8 *)pval) = 0; 4407 break; 4408 case HAL_DEF_RX_STBC: 4409 *((u8 *)pval) = 1; 4410 break; 4411 case HAL_DEF_EXPLICIT_BEAMFORMER: 4412 case HAL_DEF_EXPLICIT_BEAMFORMEE: 4413 *((u8 *)pval) = false; 4414 break; 4415 4416 case HW_DEF_RA_INFO_DUMP: 4417 { 4418 u8 mac_id = *(u8 *)pval; 4419 u32 cmd; 4420 u32 ra_info1, ra_info2; 4421 u32 rate_mask1, rate_mask2; 4422 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate; 4423 4424 DBG_8192C("============ RA status check Mac_id:%d ===================\n", mac_id); 4425 4426 cmd = 0x40000100 | mac_id; 4427 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd); 4428 msleep(10); 4429 ra_info1 = rtw_read32(padapter, 0x2F0); 4430 curr_tx_rate = ra_info1&0x7F; 4431 curr_tx_sgi = (ra_info1>>7)&0x01; 4432 DBG_8192C("[ ra_info1:0x%08x ] =>cur_tx_rate = %s, cur_sgi:%d, PWRSTS = 0x%02x \n", 4433 ra_info1, 4434 HDATA_RATE(curr_tx_rate), 4435 curr_tx_sgi, 4436 (ra_info1>>8) & 0x07); 4437 4438 cmd = 0x40000400 | mac_id; 4439 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd); 4440 msleep(10); 4441 ra_info1 = rtw_read32(padapter, 0x2F0); 4442 ra_info2 = rtw_read32(padapter, 0x2F4); 4443 rate_mask1 = rtw_read32(padapter, 0x2F8); 4444 rate_mask2 = rtw_read32(padapter, 0x2FC); 4445 hight_rate = ra_info2&0xFF; 4446 lowest_rate = (ra_info2>>8) & 0xFF; 4447 4448 DBG_8192C("[ ra_info1:0x%08x ] =>RSSI =%d, BW_setting = 0x%02x, DISRA = 0x%02x, VHT_EN = 0x%02x\n", 4449 ra_info1, 4450 ra_info1&0xFF, 4451 (ra_info1>>8) & 0xFF, 4452 (ra_info1>>16) & 0xFF, 4453 (ra_info1>>24) & 0xFF); 4454 4455 DBG_8192C("[ ra_info2:0x%08x ] =>hight_rate =%s, lowest_rate =%s, SGI = 0x%02x, RateID =%d\n", 4456 ra_info2, 4457 HDATA_RATE(hight_rate), 4458 HDATA_RATE(lowest_rate), 4459 (ra_info2>>16) & 0xFF, 4460 (ra_info2>>24) & 0xFF); 4461 4462 DBG_8192C("rate_mask2 = 0x%08x, rate_mask1 = 0x%08x\n", rate_mask2, rate_mask1); 4463 4464 } 4465 break; 4466 4467 case HAL_DEF_TX_PAGE_BOUNDARY: 4468 if (!padapter->registrypriv.wifi_spec) { 4469 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B; 4470 } else { 4471 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B; 4472 } 4473 break; 4474 4475 case HAL_DEF_MACID_SLEEP: 4476 *(u8 *)pval = true; /* support macid sleep */ 4477 break; 4478 4479 default: 4480 bResult = GetHalDefVar(padapter, variable, pval); 4481 break; 4482 } 4483 4484 return bResult; 4485 } 4486 4487 #ifdef CONFIG_WOWLAN 4488 void Hal_DetectWoWMode(struct adapter *padapter) 4489 { 4490 adapter_to_pwrctl(padapter)->bSupportRemoteWakeup = true; 4491 DBG_871X("%s\n", __func__); 4492 } 4493 #endif /* CONFIG_WOWLAN */ 4494 4495 void rtl8723b_start_thread(struct adapter *padapter) 4496 { 4497 #ifndef CONFIG_SDIO_TX_TASKLET 4498 struct xmit_priv *xmitpriv = &padapter->xmitpriv; 4499 4500 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT"); 4501 if (IS_ERR(xmitpriv->SdioXmitThread)) { 4502 RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8723bs_xmit_thread FAIL!!\n", __func__)); 4503 } 4504 #endif 4505 } 4506 4507 void rtl8723b_stop_thread(struct adapter *padapter) 4508 { 4509 #ifndef CONFIG_SDIO_TX_TASKLET 4510 struct xmit_priv *xmitpriv = &padapter->xmitpriv; 4511 4512 /* stop xmit_buf_thread */ 4513 if (xmitpriv->SdioXmitThread) { 4514 up(&xmitpriv->SdioXmitSema); 4515 down(&xmitpriv->SdioXmitTerminateSema); 4516 xmitpriv->SdioXmitThread = NULL; 4517 } 4518 #endif 4519 } 4520 4521 #if defined(CONFIG_CHECK_BT_HANG) 4522 extern void check_bt_status_work(void *data); 4523 void rtl8723bs_init_checkbthang_workqueue(struct adapter *adapter) 4524 { 4525 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0); 4526 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work); 4527 } 4528 4529 void rtl8723bs_free_checkbthang_workqueue(struct adapter *adapter) 4530 { 4531 if (adapter->priv_checkbt_wq) { 4532 cancel_delayed_work_sync(&adapter->checkbt_work); 4533 flush_workqueue(adapter->priv_checkbt_wq); 4534 destroy_workqueue(adapter->priv_checkbt_wq); 4535 adapter->priv_checkbt_wq = NULL; 4536 } 4537 } 4538 4539 void rtl8723bs_cancle_checkbthang_workqueue(struct adapter *adapter) 4540 { 4541 if (adapter->priv_checkbt_wq) 4542 cancel_delayed_work_sync(&adapter->checkbt_work); 4543 } 4544 4545 void rtl8723bs_hal_check_bt_hang(struct adapter *adapter) 4546 { 4547 if (adapter->priv_checkbt_wq) 4548 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0); 4549 } 4550 #endif 4551