1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #define _HAL_INIT_C_ 8 9 #include <linux/firmware.h> 10 #include <linux/slab.h> 11 #include <drv_types.h> 12 #include <rtw_debug.h> 13 #include <rtl8723b_hal.h> 14 #include "hal_com_h2c.h" 15 16 static void _FWDownloadEnable(struct adapter *padapter, bool enable) 17 { 18 u8 tmp, count = 0; 19 20 if (enable) { 21 /* 8051 enable */ 22 tmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 23 rtw_write8(padapter, REG_SYS_FUNC_EN+1, tmp|0x04); 24 25 tmp = rtw_read8(padapter, REG_MCUFWDL); 26 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); 27 28 do { 29 tmp = rtw_read8(padapter, REG_MCUFWDL); 30 if (tmp & 0x01) 31 break; 32 rtw_write8(padapter, REG_MCUFWDL, tmp|0x01); 33 msleep(1); 34 } while (count++ < 100); 35 36 if (count > 0) 37 DBG_871X("%s: !!!!!!!!Write 0x80 Fail!: count = %d\n", __func__, count); 38 39 /* 8051 reset */ 40 tmp = rtw_read8(padapter, REG_MCUFWDL+2); 41 rtw_write8(padapter, REG_MCUFWDL+2, tmp&0xf7); 42 } else { 43 /* MCU firmware download disable. */ 44 tmp = rtw_read8(padapter, REG_MCUFWDL); 45 rtw_write8(padapter, REG_MCUFWDL, tmp&0xfe); 46 } 47 } 48 49 static int _BlockWrite(struct adapter *padapter, void *buffer, u32 buffSize) 50 { 51 int ret = _SUCCESS; 52 53 u32 blockSize_p1 = 4; /* (Default) Phase #1 : PCI muse use 4-byte write to download FW */ 54 u32 blockSize_p2 = 8; /* Phase #2 : Use 8-byte, if Phase#1 use big size to write FW. */ 55 u32 blockSize_p3 = 1; /* Phase #3 : Use 1-byte, the remnant of FW image. */ 56 u32 blockCount_p1 = 0, blockCount_p2 = 0, blockCount_p3 = 0; 57 u32 remainSize_p1 = 0, remainSize_p2 = 0; 58 u8 *bufferPtr = buffer; 59 u32 i = 0, offset = 0; 60 61 /* printk("====>%s %d\n", __func__, __LINE__); */ 62 63 /* 3 Phase #1 */ 64 blockCount_p1 = buffSize / blockSize_p1; 65 remainSize_p1 = buffSize % blockSize_p1; 66 67 if (blockCount_p1) { 68 RT_TRACE( 69 _module_hal_init_c_, 70 _drv_notice_, 71 ( 72 "_BlockWrite: [P1] buffSize(%d) blockSize_p1(%d) blockCount_p1(%d) remainSize_p1(%d)\n", 73 buffSize, 74 blockSize_p1, 75 blockCount_p1, 76 remainSize_p1 77 ) 78 ); 79 } 80 81 for (i = 0; i < blockCount_p1; i++) { 82 ret = rtw_write32(padapter, (FW_8723B_START_ADDRESS + i * blockSize_p1), *((u32 *)(bufferPtr + i * blockSize_p1))); 83 if (ret == _FAIL) { 84 printk("====>%s %d i:%d\n", __func__, __LINE__, i); 85 goto exit; 86 } 87 } 88 89 /* 3 Phase #2 */ 90 if (remainSize_p1) { 91 offset = blockCount_p1 * blockSize_p1; 92 93 blockCount_p2 = remainSize_p1/blockSize_p2; 94 remainSize_p2 = remainSize_p1%blockSize_p2; 95 96 if (blockCount_p2) { 97 RT_TRACE( 98 _module_hal_init_c_, 99 _drv_notice_, 100 ( 101 "_BlockWrite: [P2] buffSize_p2(%d) blockSize_p2(%d) blockCount_p2(%d) remainSize_p2(%d)\n", 102 (buffSize-offset), 103 blockSize_p2, 104 blockCount_p2, 105 remainSize_p2 106 ) 107 ); 108 } 109 110 } 111 112 /* 3 Phase #3 */ 113 if (remainSize_p2) { 114 offset = (blockCount_p1 * blockSize_p1) + (blockCount_p2 * blockSize_p2); 115 116 blockCount_p3 = remainSize_p2 / blockSize_p3; 117 118 RT_TRACE(_module_hal_init_c_, _drv_notice_, 119 ("_BlockWrite: [P3] buffSize_p3(%d) blockSize_p3(%d) blockCount_p3(%d)\n", 120 (buffSize-offset), blockSize_p3, blockCount_p3)); 121 122 for (i = 0; i < blockCount_p3; i++) { 123 ret = rtw_write8(padapter, (FW_8723B_START_ADDRESS + offset + i), *(bufferPtr + offset + i)); 124 125 if (ret == _FAIL) { 126 printk("====>%s %d i:%d\n", __func__, __LINE__, i); 127 goto exit; 128 } 129 } 130 } 131 exit: 132 return ret; 133 } 134 135 static int _PageWrite( 136 struct adapter *padapter, 137 u32 page, 138 void *buffer, 139 u32 size 140 ) 141 { 142 u8 value8; 143 u8 u8Page = (u8) (page & 0x07); 144 145 value8 = (rtw_read8(padapter, REG_MCUFWDL+2) & 0xF8) | u8Page; 146 rtw_write8(padapter, REG_MCUFWDL+2, value8); 147 148 return _BlockWrite(padapter, buffer, size); 149 } 150 151 static int _WriteFW(struct adapter *padapter, void *buffer, u32 size) 152 { 153 /* Since we need dynamic decide method of dwonload fw, so we call this function to get chip version. */ 154 /* We can remove _ReadChipVersion from ReadpadapterInfo8192C later. */ 155 int ret = _SUCCESS; 156 u32 pageNums, remainSize; 157 u32 page, offset; 158 u8 *bufferPtr = buffer; 159 160 pageNums = size / MAX_DLFW_PAGE_SIZE; 161 /* RT_ASSERT((pageNums <= 4), ("Page numbers should not greater then 4\n")); */ 162 remainSize = size % MAX_DLFW_PAGE_SIZE; 163 164 for (page = 0; page < pageNums; page++) { 165 offset = page * MAX_DLFW_PAGE_SIZE; 166 ret = _PageWrite(padapter, page, bufferPtr+offset, MAX_DLFW_PAGE_SIZE); 167 168 if (ret == _FAIL) { 169 printk("====>%s %d\n", __func__, __LINE__); 170 goto exit; 171 } 172 } 173 174 if (remainSize) { 175 offset = pageNums * MAX_DLFW_PAGE_SIZE; 176 page = pageNums; 177 ret = _PageWrite(padapter, page, bufferPtr+offset, remainSize); 178 179 if (ret == _FAIL) { 180 printk("====>%s %d\n", __func__, __LINE__); 181 goto exit; 182 } 183 } 184 RT_TRACE(_module_hal_init_c_, _drv_info_, ("_WriteFW Done- for Normal chip.\n")); 185 186 exit: 187 return ret; 188 } 189 190 void _8051Reset8723(struct adapter *padapter) 191 { 192 u8 cpu_rst; 193 u8 io_rst; 194 195 196 /* Reset 8051(WLMCU) IO wrapper */ 197 /* 0x1c[8] = 0 */ 198 /* Suggested by Isaac@SD1 and Gimmy@SD1, coding by Lucas@20130624 */ 199 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1); 200 io_rst &= ~BIT(0); 201 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst); 202 203 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 204 cpu_rst &= ~BIT(2); 205 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst); 206 207 /* Enable 8051 IO wrapper */ 208 /* 0x1c[8] = 1 */ 209 io_rst = rtw_read8(padapter, REG_RSV_CTRL+1); 210 io_rst |= BIT(0); 211 rtw_write8(padapter, REG_RSV_CTRL+1, io_rst); 212 213 cpu_rst = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 214 cpu_rst |= BIT(2); 215 rtw_write8(padapter, REG_SYS_FUNC_EN+1, cpu_rst); 216 217 DBG_8192C("%s: Finish\n", __func__); 218 } 219 220 u8 g_fwdl_chksum_fail; 221 222 static s32 polling_fwdl_chksum( 223 struct adapter *adapter, u32 min_cnt, u32 timeout_ms 224 ) 225 { 226 s32 ret = _FAIL; 227 u32 value32; 228 unsigned long start = jiffies; 229 u32 cnt = 0; 230 231 /* polling CheckSum report */ 232 do { 233 cnt++; 234 value32 = rtw_read32(adapter, REG_MCUFWDL); 235 if (value32 & FWDL_ChkSum_rpt || adapter->bSurpriseRemoved || adapter->bDriverStopped) 236 break; 237 yield(); 238 } while (jiffies_to_msecs(jiffies-start) < timeout_ms || cnt < min_cnt); 239 240 if (!(value32 & FWDL_ChkSum_rpt)) { 241 goto exit; 242 } 243 244 if (g_fwdl_chksum_fail) { 245 DBG_871X("%s: fwdl test case: fwdl_chksum_fail\n", __func__); 246 g_fwdl_chksum_fail--; 247 goto exit; 248 } 249 250 ret = _SUCCESS; 251 252 exit: 253 DBG_871X( 254 "%s: Checksum report %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", 255 __func__, 256 (ret == _SUCCESS) ? "OK" : "Fail", 257 cnt, 258 jiffies_to_msecs(jiffies-start), 259 value32 260 ); 261 262 return ret; 263 } 264 265 u8 g_fwdl_wintint_rdy_fail; 266 267 static s32 _FWFreeToGo(struct adapter *adapter, u32 min_cnt, u32 timeout_ms) 268 { 269 s32 ret = _FAIL; 270 u32 value32; 271 unsigned long start = jiffies; 272 u32 cnt = 0; 273 274 value32 = rtw_read32(adapter, REG_MCUFWDL); 275 value32 |= MCUFWDL_RDY; 276 value32 &= ~WINTINI_RDY; 277 rtw_write32(adapter, REG_MCUFWDL, value32); 278 279 _8051Reset8723(adapter); 280 281 /* polling for FW ready */ 282 do { 283 cnt++; 284 value32 = rtw_read32(adapter, REG_MCUFWDL); 285 if (value32 & WINTINI_RDY || adapter->bSurpriseRemoved || adapter->bDriverStopped) 286 break; 287 yield(); 288 } while (jiffies_to_msecs(jiffies - start) < timeout_ms || cnt < min_cnt); 289 290 if (!(value32 & WINTINI_RDY)) { 291 goto exit; 292 } 293 294 if (g_fwdl_wintint_rdy_fail) { 295 DBG_871X("%s: fwdl test case: wintint_rdy_fail\n", __func__); 296 g_fwdl_wintint_rdy_fail--; 297 goto exit; 298 } 299 300 ret = _SUCCESS; 301 302 exit: 303 DBG_871X( 304 "%s: Polling FW ready %s! (%u, %dms), REG_MCUFWDL:0x%08x\n", 305 __func__, 306 (ret == _SUCCESS) ? "OK" : "Fail", 307 cnt, 308 jiffies_to_msecs(jiffies-start), 309 value32 310 ); 311 312 return ret; 313 } 314 315 #define IS_FW_81xxC(padapter) (((GET_HAL_DATA(padapter))->FirmwareSignature & 0xFFF0) == 0x88C0) 316 317 void rtl8723b_FirmwareSelfReset(struct adapter *padapter) 318 { 319 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 320 u8 u1bTmp; 321 u8 Delay = 100; 322 323 if ( 324 !(IS_FW_81xxC(padapter) && ((pHalData->FirmwareVersion < 0x21) || (pHalData->FirmwareVersion == 0x21 && pHalData->FirmwareSubVersion < 0x01))) 325 ) { /* after 88C Fw v33.1 */ 326 /* 0x1cf = 0x20. Inform 8051 to reset. 2009.12.25. tynli_test */ 327 rtw_write8(padapter, REG_HMETFR+3, 0x20); 328 329 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 330 while (u1bTmp & BIT2) { 331 Delay--; 332 if (Delay == 0) 333 break; 334 udelay(50); 335 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 336 } 337 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("-%s: 8051 reset success (%d)\n", __func__, Delay)); 338 339 if (Delay == 0) { 340 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("%s: Force 8051 reset!!!\n", __func__)); 341 /* force firmware reset */ 342 u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1); 343 rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2)); 344 } 345 } 346 } 347 348 /* */ 349 /* Description: */ 350 /* Download 8192C firmware code. */ 351 /* */ 352 /* */ 353 s32 rtl8723b_FirmwareDownload(struct adapter *padapter, bool bUsedWoWLANFw) 354 { 355 s32 rtStatus = _SUCCESS; 356 u8 write_fw = 0; 357 unsigned long fwdl_start_time; 358 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 359 struct rt_firmware *pFirmware; 360 struct rt_firmware *pBTFirmware; 361 struct rt_firmware_hdr *pFwHdr = NULL; 362 u8 *pFirmwareBuf; 363 u32 FirmwareLen; 364 const struct firmware *fw; 365 struct device *device = dvobj_to_dev(padapter->dvobj); 366 u8 *fwfilepath; 367 struct dvobj_priv *psdpriv = padapter->dvobj; 368 struct debug_priv *pdbgpriv = &psdpriv->drv_dbg; 369 u8 tmp_ps; 370 371 RT_TRACE(_module_hal_init_c_, _drv_info_, ("+%s\n", __func__)); 372 #ifdef CONFIG_WOWLAN 373 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("+%s, bUsedWoWLANFw:%d\n", __func__, bUsedWoWLANFw)); 374 #endif 375 pFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL); 376 if (!pFirmware) 377 return _FAIL; 378 pBTFirmware = kzalloc(sizeof(struct rt_firmware), GFP_KERNEL); 379 if (!pBTFirmware) { 380 kfree(pFirmware); 381 return _FAIL; 382 } 383 tmp_ps = rtw_read8(padapter, 0xa3); 384 tmp_ps &= 0xf8; 385 tmp_ps |= 0x02; 386 /* 1. write 0xA3[:2:0] = 3b'010 */ 387 rtw_write8(padapter, 0xa3, tmp_ps); 388 /* 2. read power_state = 0xA0[1:0] */ 389 tmp_ps = rtw_read8(padapter, 0xa0); 390 tmp_ps &= 0x03; 391 if (tmp_ps != 0x01) { 392 DBG_871X(FUNC_ADPT_FMT" tmp_ps =%x\n", FUNC_ADPT_ARG(padapter), tmp_ps); 393 pdbgpriv->dbg_downloadfw_pwr_state_cnt++; 394 } 395 396 #ifdef CONFIG_WOWLAN 397 if (bUsedWoWLANFw) 398 fwfilepath = "rtlwifi/rtl8723bs_wowlan.bin"; 399 else 400 #endif /* CONFIG_WOWLAN */ 401 fwfilepath = "rtlwifi/rtl8723bs_nic.bin"; 402 403 pr_info("rtl8723bs: acquire FW from file:%s\n", fwfilepath); 404 405 rtStatus = request_firmware(&fw, fwfilepath, device); 406 if (rtStatus) { 407 pr_err("Request firmware failed with error 0x%x\n", rtStatus); 408 rtStatus = _FAIL; 409 goto exit; 410 } 411 412 if (!fw) { 413 pr_err("Firmware %s not available\n", fwfilepath); 414 rtStatus = _FAIL; 415 goto exit; 416 } 417 418 if (fw->size > FW_8723B_SIZE) { 419 rtStatus = _FAIL; 420 RT_TRACE( 421 _module_hal_init_c_, 422 _drv_err_, 423 ("Firmware size exceed 0x%X. Check it.\n", FW_8188E_SIZE) 424 ); 425 goto exit; 426 } 427 428 pFirmware->fw_buffer_sz = kmemdup(fw->data, fw->size, GFP_KERNEL); 429 if (!pFirmware->fw_buffer_sz) { 430 rtStatus = _FAIL; 431 goto exit; 432 } 433 434 pFirmware->fw_length = fw->size; 435 release_firmware(fw); 436 if (pFirmware->fw_length > FW_8723B_SIZE) { 437 rtStatus = _FAIL; 438 DBG_871X_LEVEL(_drv_emerg_, "Firmware size:%u exceed %u\n", pFirmware->fw_length, FW_8723B_SIZE); 439 goto release_fw1; 440 } 441 442 pFirmwareBuf = pFirmware->fw_buffer_sz; 443 FirmwareLen = pFirmware->fw_length; 444 445 /* To Check Fw header. Added by tynli. 2009.12.04. */ 446 pFwHdr = (struct rt_firmware_hdr *)pFirmwareBuf; 447 448 pHalData->FirmwareVersion = le16_to_cpu(pFwHdr->version); 449 pHalData->FirmwareSubVersion = le16_to_cpu(pFwHdr->subversion); 450 pHalData->FirmwareSignature = le16_to_cpu(pFwHdr->signature); 451 452 DBG_871X( 453 "%s: fw_ver =%x fw_subver =%04x sig = 0x%x, Month =%02x, Date =%02x, Hour =%02x, Minute =%02x\n", 454 __func__, 455 pHalData->FirmwareVersion, 456 pHalData->FirmwareSubVersion, 457 pHalData->FirmwareSignature, 458 pFwHdr->month, 459 pFwHdr->date, 460 pFwHdr->hour, 461 pFwHdr->minute 462 ); 463 464 if (IS_FW_HEADER_EXIST_8723B(pFwHdr)) { 465 DBG_871X("%s(): Shift for fw header!\n", __func__); 466 /* Shift 32 bytes for FW header */ 467 pFirmwareBuf = pFirmwareBuf + 32; 468 FirmwareLen = FirmwareLen - 32; 469 } 470 471 /* Suggested by Filen. If 8051 is running in RAM code, driver should inform Fw to reset by itself, */ 472 /* or it will cause download Fw fail. 2010.02.01. by tynli. */ 473 if (rtw_read8(padapter, REG_MCUFWDL) & RAM_DL_SEL) { /* 8051 RAM code */ 474 rtw_write8(padapter, REG_MCUFWDL, 0x00); 475 rtl8723b_FirmwareSelfReset(padapter); 476 } 477 478 _FWDownloadEnable(padapter, true); 479 fwdl_start_time = jiffies; 480 while ( 481 !padapter->bDriverStopped && 482 !padapter->bSurpriseRemoved && 483 (write_fw++ < 3 || jiffies_to_msecs(jiffies - fwdl_start_time) < 500) 484 ) { 485 /* reset FWDL chksum */ 486 rtw_write8(padapter, REG_MCUFWDL, rtw_read8(padapter, REG_MCUFWDL)|FWDL_ChkSum_rpt); 487 488 rtStatus = _WriteFW(padapter, pFirmwareBuf, FirmwareLen); 489 if (rtStatus != _SUCCESS) 490 continue; 491 492 rtStatus = polling_fwdl_chksum(padapter, 5, 50); 493 if (rtStatus == _SUCCESS) 494 break; 495 } 496 _FWDownloadEnable(padapter, false); 497 if (_SUCCESS != rtStatus) 498 goto fwdl_stat; 499 500 rtStatus = _FWFreeToGo(padapter, 10, 200); 501 if (_SUCCESS != rtStatus) 502 goto fwdl_stat; 503 504 fwdl_stat: 505 DBG_871X( 506 "FWDL %s. write_fw:%u, %dms\n", 507 (rtStatus == _SUCCESS)?"success":"fail", 508 write_fw, 509 jiffies_to_msecs(jiffies - fwdl_start_time) 510 ); 511 512 exit: 513 kfree(pFirmware->fw_buffer_sz); 514 kfree(pFirmware); 515 release_fw1: 516 kfree(pBTFirmware); 517 DBG_871X(" <=== rtl8723b_FirmwareDownload()\n"); 518 return rtStatus; 519 } 520 521 void rtl8723b_InitializeFirmwareVars(struct adapter *padapter) 522 { 523 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 524 525 /* Init Fw LPS related. */ 526 adapter_to_pwrctl(padapter)->bFwCurrentInPSMode = false; 527 528 /* Init H2C cmd. */ 529 rtw_write8(padapter, REG_HMETFR, 0x0f); 530 531 /* Init H2C counter. by tynli. 2009.12.09. */ 532 pHalData->LastHMEBoxNum = 0; 533 /* pHalData->H2CQueueHead = 0; */ 534 /* pHalData->H2CQueueTail = 0; */ 535 /* pHalData->H2CStopInsertQueue = false; */ 536 } 537 538 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN) 539 /* */ 540 541 /* */ 542 /* Description: Prepare some information to Fw for WoWLAN. */ 543 /* (1) Download wowlan Fw. */ 544 /* (2) Download RSVD page packets. */ 545 /* (3) Enable AP offload if needed. */ 546 /* */ 547 /* 2011.04.12 by tynli. */ 548 /* */ 549 void SetFwRelatedForWoWLAN8723b( 550 struct adapter *padapter, u8 bHostIsGoingtoSleep 551 ) 552 { 553 int status = _FAIL; 554 /* */ 555 /* 1. Before WoWLAN we need to re-download WoWLAN Fw. */ 556 /* */ 557 status = rtl8723b_FirmwareDownload(padapter, bHostIsGoingtoSleep); 558 if (status != _SUCCESS) { 559 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware failed!!\n"); 560 return; 561 } else { 562 DBG_871X("SetFwRelatedForWoWLAN8723b(): Re-Download Firmware Success !!\n"); 563 } 564 /* */ 565 /* 2. Re-Init the variables about Fw related setting. */ 566 /* */ 567 rtl8723b_InitializeFirmwareVars(padapter); 568 } 569 #endif /* CONFIG_WOWLAN */ 570 571 static void rtl8723b_free_hal_data(struct adapter *padapter) 572 { 573 } 574 575 /* */ 576 /* Efuse related code */ 577 /* */ 578 static u8 hal_EfuseSwitchToBank( 579 struct adapter *padapter, u8 bank, bool bPseudoTest 580 ) 581 { 582 u8 bRet = false; 583 u32 value32 = 0; 584 #ifdef HAL_EFUSE_MEMORY 585 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 586 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 587 #endif 588 589 590 DBG_8192C("%s: Efuse switch bank to %d\n", __func__, bank); 591 if (bPseudoTest) { 592 #ifdef HAL_EFUSE_MEMORY 593 pEfuseHal->fakeEfuseBank = bank; 594 #else 595 fakeEfuseBank = bank; 596 #endif 597 bRet = true; 598 } else { 599 value32 = rtw_read32(padapter, EFUSE_TEST); 600 bRet = true; 601 switch (bank) { 602 case 0: 603 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 604 break; 605 case 1: 606 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_0); 607 break; 608 case 2: 609 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_1); 610 break; 611 case 3: 612 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_BT_SEL_2); 613 break; 614 default: 615 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0); 616 bRet = false; 617 break; 618 } 619 rtw_write32(padapter, EFUSE_TEST, value32); 620 } 621 622 return bRet; 623 } 624 625 static void Hal_GetEfuseDefinition( 626 struct adapter *padapter, 627 u8 efuseType, 628 u8 type, 629 void *pOut, 630 bool bPseudoTest 631 ) 632 { 633 switch (type) { 634 case TYPE_EFUSE_MAX_SECTION: 635 { 636 u8 *pMax_section; 637 pMax_section = pOut; 638 639 if (efuseType == EFUSE_WIFI) 640 *pMax_section = EFUSE_MAX_SECTION_8723B; 641 else 642 *pMax_section = EFUSE_BT_MAX_SECTION; 643 } 644 break; 645 646 case TYPE_EFUSE_REAL_CONTENT_LEN: 647 { 648 u16 *pu2Tmp; 649 pu2Tmp = pOut; 650 651 if (efuseType == EFUSE_WIFI) 652 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B; 653 else 654 *pu2Tmp = EFUSE_BT_REAL_CONTENT_LEN; 655 } 656 break; 657 658 case TYPE_AVAILABLE_EFUSE_BYTES_BANK: 659 { 660 u16 *pu2Tmp; 661 pu2Tmp = pOut; 662 663 if (efuseType == EFUSE_WIFI) 664 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES); 665 else 666 *pu2Tmp = (EFUSE_BT_REAL_BANK_CONTENT_LEN-EFUSE_PROTECT_BYTES_BANK); 667 } 668 break; 669 670 case TYPE_AVAILABLE_EFUSE_BYTES_TOTAL: 671 { 672 u16 *pu2Tmp; 673 pu2Tmp = pOut; 674 675 if (efuseType == EFUSE_WIFI) 676 *pu2Tmp = (EFUSE_REAL_CONTENT_LEN_8723B-EFUSE_OOB_PROTECT_BYTES); 677 else 678 *pu2Tmp = (EFUSE_BT_REAL_CONTENT_LEN-(EFUSE_PROTECT_BYTES_BANK*3)); 679 } 680 break; 681 682 case TYPE_EFUSE_MAP_LEN: 683 { 684 u16 *pu2Tmp; 685 pu2Tmp = pOut; 686 687 if (efuseType == EFUSE_WIFI) 688 *pu2Tmp = EFUSE_MAX_MAP_LEN; 689 else 690 *pu2Tmp = EFUSE_BT_MAP_LEN; 691 } 692 break; 693 694 case TYPE_EFUSE_PROTECT_BYTES_BANK: 695 { 696 u8 *pu1Tmp; 697 pu1Tmp = pOut; 698 699 if (efuseType == EFUSE_WIFI) 700 *pu1Tmp = EFUSE_OOB_PROTECT_BYTES; 701 else 702 *pu1Tmp = EFUSE_PROTECT_BYTES_BANK; 703 } 704 break; 705 706 case TYPE_EFUSE_CONTENT_LEN_BANK: 707 { 708 u16 *pu2Tmp; 709 pu2Tmp = pOut; 710 711 if (efuseType == EFUSE_WIFI) 712 *pu2Tmp = EFUSE_REAL_CONTENT_LEN_8723B; 713 else 714 *pu2Tmp = EFUSE_BT_REAL_BANK_CONTENT_LEN; 715 } 716 break; 717 718 default: 719 { 720 u8 *pu1Tmp; 721 pu1Tmp = pOut; 722 *pu1Tmp = 0; 723 } 724 break; 725 } 726 } 727 728 #define VOLTAGE_V25 0x03 729 #define LDOE25_SHIFT 28 730 731 /* */ 732 /* The following is for compile ok */ 733 /* That should be merged with the original in the future */ 734 /* */ 735 #define EFUSE_ACCESS_ON_8723 0x69 /* For RTL8723 only. */ 736 #define EFUSE_ACCESS_OFF_8723 0x00 /* For RTL8723 only. */ 737 #define REG_EFUSE_ACCESS_8723 0x00CF /* Efuse access protection for RTL8723 */ 738 739 /* */ 740 static void Hal_BT_EfusePowerSwitch( 741 struct adapter *padapter, u8 bWrite, u8 PwrState 742 ) 743 { 744 u8 tempval; 745 if (PwrState) { 746 /* enable BT power cut */ 747 /* 0x6A[14] = 1 */ 748 tempval = rtw_read8(padapter, 0x6B); 749 tempval |= BIT(6); 750 rtw_write8(padapter, 0x6B, tempval); 751 752 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ 753 /* So don't write 0x6A[14]= 1 and 0x6A[15]= 0 together! */ 754 msleep(1); 755 /* disable BT output isolation */ 756 /* 0x6A[15] = 0 */ 757 tempval = rtw_read8(padapter, 0x6B); 758 tempval &= ~BIT(7); 759 rtw_write8(padapter, 0x6B, tempval); 760 } else { 761 /* enable BT output isolation */ 762 /* 0x6A[15] = 1 */ 763 tempval = rtw_read8(padapter, 0x6B); 764 tempval |= BIT(7); 765 rtw_write8(padapter, 0x6B, tempval); 766 767 /* Attention!! Between 0x6A[14] and 0x6A[15] setting need 100us delay */ 768 /* So don't write 0x6A[14]= 1 and 0x6A[15]= 0 together! */ 769 770 /* disable BT power cut */ 771 /* 0x6A[14] = 1 */ 772 tempval = rtw_read8(padapter, 0x6B); 773 tempval &= ~BIT(6); 774 rtw_write8(padapter, 0x6B, tempval); 775 } 776 777 } 778 static void Hal_EfusePowerSwitch( 779 struct adapter *padapter, u8 bWrite, u8 PwrState 780 ) 781 { 782 u8 tempval; 783 u16 tmpV16; 784 785 786 if (PwrState) { 787 /* To avoid cannot access efuse regsiters after disable/enable several times during DTM test. */ 788 /* Suggested by SD1 IsaacHsu. 2013.07.08, added by tynli. */ 789 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL); 790 if (tempval & BIT(0)) { /* SDIO local register is suspend */ 791 u8 count = 0; 792 793 794 tempval &= ~BIT(0); 795 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL, tempval); 796 797 /* check 0x86[1:0]= 10'2h, wait power state to leave suspend */ 798 do { 799 tempval = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HSUS_CTRL); 800 tempval &= 0x3; 801 if (tempval == 0x02) 802 break; 803 804 count++; 805 if (count >= 100) 806 break; 807 808 mdelay(10); 809 } while (1); 810 811 if (count >= 100) { 812 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend fail! Local 0x86 =%#X\n", 813 FUNC_ADPT_ARG(padapter), tempval); 814 } else { 815 DBG_8192C(FUNC_ADPT_FMT ": Leave SDIO local register suspend OK! Local 0x86 =%#X\n", 816 FUNC_ADPT_ARG(padapter), tempval); 817 } 818 } 819 820 rtw_write8(padapter, REG_EFUSE_ACCESS_8723, EFUSE_ACCESS_ON_8723); 821 822 /* Reset: 0x0000h[28], default valid */ 823 tmpV16 = rtw_read16(padapter, REG_SYS_FUNC_EN); 824 if (!(tmpV16 & FEN_ELDR)) { 825 tmpV16 |= FEN_ELDR; 826 rtw_write16(padapter, REG_SYS_FUNC_EN, tmpV16); 827 } 828 829 /* Clock: Gated(0x0008h[5]) 8M(0x0008h[1]) clock from ANA, default valid */ 830 tmpV16 = rtw_read16(padapter, REG_SYS_CLKR); 831 if ((!(tmpV16 & LOADER_CLK_EN)) || (!(tmpV16 & ANA8M))) { 832 tmpV16 |= (LOADER_CLK_EN | ANA8M); 833 rtw_write16(padapter, REG_SYS_CLKR, tmpV16); 834 } 835 836 if (bWrite) { 837 /* Enable LDO 2.5V before read/write action */ 838 tempval = rtw_read8(padapter, EFUSE_TEST+3); 839 tempval &= 0x0F; 840 tempval |= (VOLTAGE_V25 << 4); 841 rtw_write8(padapter, EFUSE_TEST+3, (tempval | 0x80)); 842 843 /* rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON); */ 844 } 845 } else { 846 rtw_write8(padapter, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF); 847 848 if (bWrite) { 849 /* Disable LDO 2.5V after read/write action */ 850 tempval = rtw_read8(padapter, EFUSE_TEST+3); 851 rtw_write8(padapter, EFUSE_TEST+3, (tempval & 0x7F)); 852 } 853 854 } 855 } 856 857 static void hal_ReadEFuse_WiFi( 858 struct adapter *padapter, 859 u16 _offset, 860 u16 _size_byte, 861 u8 *pbuf, 862 bool bPseudoTest 863 ) 864 { 865 #ifdef HAL_EFUSE_MEMORY 866 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 867 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 868 #endif 869 u8 *efuseTbl = NULL; 870 u16 eFuse_Addr = 0; 871 u8 offset, wden; 872 u8 efuseHeader, efuseExtHdr, efuseData; 873 u16 i, total, used; 874 u8 efuse_usage = 0; 875 876 /* DBG_871X("YJ: ====>%s():_offset =%d _size_byte =%d bPseudoTest =%d\n", __func__, _offset, _size_byte, bPseudoTest); */ 877 /* */ 878 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ 879 /* */ 880 if ((_offset+_size_byte) > EFUSE_MAX_MAP_LEN) { 881 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); 882 return; 883 } 884 885 efuseTbl = rtw_malloc(EFUSE_MAX_MAP_LEN); 886 if (!efuseTbl) { 887 DBG_8192C("%s: alloc efuseTbl fail!\n", __func__); 888 return; 889 } 890 /* 0xff will be efuse default value instead of 0x00. */ 891 memset(efuseTbl, 0xFF, EFUSE_MAX_MAP_LEN); 892 893 894 #ifdef DEBUG 895 if (0) { 896 for (i = 0; i < 256; i++) 897 efuse_OneByteRead(padapter, i, &efuseTbl[i], false); 898 DBG_871X("Efuse Content:\n"); 899 for (i = 0; i < 256; i++) { 900 if (i % 16 == 0) 901 printk("\n"); 902 printk("%02X ", efuseTbl[i]); 903 } 904 printk("\n"); 905 } 906 #endif 907 908 909 /* switch bank back to bank 0 for later BT and wifi use. */ 910 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 911 912 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { 913 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); 914 if (efuseHeader == 0xFF) { 915 DBG_8192C("%s: data end at address =%#x\n", __func__, eFuse_Addr-1); 916 break; 917 } 918 /* DBG_8192C("%s: efuse[0x%X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseHeader); */ 919 920 /* Check PG header for section num. */ 921 if (EXT_HEADER(efuseHeader)) { /* extended header */ 922 offset = GET_HDR_OFFSET_2_0(efuseHeader); 923 /* DBG_8192C("%s: extended header offset = 0x%X\n", __func__, offset); */ 924 925 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); 926 /* DBG_8192C("%s: efuse[0x%X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseExtHdr); */ 927 if (ALL_WORDS_DISABLED(efuseExtHdr)) 928 continue; 929 930 offset |= ((efuseExtHdr & 0xF0) >> 1); 931 wden = (efuseExtHdr & 0x0F); 932 } else { 933 offset = ((efuseHeader >> 4) & 0x0f); 934 wden = (efuseHeader & 0x0f); 935 } 936 /* DBG_8192C("%s: Offset =%d Worden = 0x%X\n", __func__, offset, wden); */ 937 938 if (offset < EFUSE_MAX_SECTION_8723B) { 939 u16 addr; 940 /* Get word enable value from PG header */ 941 /* DBG_8192C("%s: Offset =%d Worden = 0x%X\n", __func__, offset, wden); */ 942 943 addr = offset * PGPKT_DATA_SIZE; 944 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 945 /* Check word enable condition in the section */ 946 if (!(wden & (0x01<<i))) { 947 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 948 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ 949 efuseTbl[addr] = efuseData; 950 951 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 952 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); */ 953 efuseTbl[addr+1] = efuseData; 954 } 955 addr += 2; 956 } 957 } else { 958 DBG_8192C(KERN_ERR "%s: offset(%d) is illegal!!\n", __func__, offset); 959 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2; 960 } 961 } 962 963 /* Copy from Efuse map to output pointer memory!!! */ 964 for (i = 0; i < _size_byte; i++) 965 pbuf[i] = efuseTbl[_offset+i]; 966 967 #ifdef DEBUG 968 if (1) { 969 DBG_871X("Efuse Realmap:\n"); 970 for (i = 0; i < _size_byte; i++) { 971 if (i % 16 == 0) 972 printk("\n"); 973 printk("%02X ", pbuf[i]); 974 } 975 printk("\n"); 976 } 977 #endif 978 /* Calculate Efuse utilization */ 979 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); 980 used = eFuse_Addr - 1; 981 efuse_usage = (u8)((used*100)/total); 982 if (bPseudoTest) { 983 #ifdef HAL_EFUSE_MEMORY 984 pEfuseHal->fakeEfuseUsedBytes = used; 985 #else 986 fakeEfuseUsedBytes = used; 987 #endif 988 } else { 989 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&used); 990 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_USAGE, (u8 *)&efuse_usage); 991 } 992 993 kfree(efuseTbl); 994 } 995 996 static void hal_ReadEFuse_BT( 997 struct adapter *padapter, 998 u16 _offset, 999 u16 _size_byte, 1000 u8 *pbuf, 1001 bool bPseudoTest 1002 ) 1003 { 1004 #ifdef HAL_EFUSE_MEMORY 1005 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1006 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1007 #endif 1008 u8 *efuseTbl; 1009 u8 bank; 1010 u16 eFuse_Addr; 1011 u8 efuseHeader, efuseExtHdr, efuseData; 1012 u8 offset, wden; 1013 u16 i, total, used; 1014 u8 efuse_usage; 1015 1016 1017 /* */ 1018 /* Do NOT excess total size of EFuse table. Added by Roger, 2008.11.10. */ 1019 /* */ 1020 if ((_offset+_size_byte) > EFUSE_BT_MAP_LEN) { 1021 DBG_8192C("%s: Invalid offset(%#x) with read bytes(%#x)!!\n", __func__, _offset, _size_byte); 1022 return; 1023 } 1024 1025 efuseTbl = rtw_malloc(EFUSE_BT_MAP_LEN); 1026 if (!efuseTbl) { 1027 DBG_8192C("%s: efuseTbl malloc fail!\n", __func__); 1028 return; 1029 } 1030 /* 0xff will be efuse default value instead of 0x00. */ 1031 memset(efuseTbl, 0xFF, EFUSE_BT_MAP_LEN); 1032 1033 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &total, bPseudoTest); 1034 1035 for (bank = 1; bank < 3; bank++) { /* 8723b Max bake 0~2 */ 1036 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { 1037 DBG_8192C("%s: hal_EfuseSwitchToBank Fail!!\n", __func__); 1038 goto exit; 1039 } 1040 1041 eFuse_Addr = 0; 1042 1043 while (AVAILABLE_EFUSE_ADDR(eFuse_Addr)) { 1044 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseHeader, bPseudoTest); 1045 if (efuseHeader == 0xFF) 1046 break; 1047 DBG_8192C("%s: efuse[%#X]= 0x%02x (header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseHeader); 1048 1049 /* Check PG header for section num. */ 1050 if (EXT_HEADER(efuseHeader)) { /* extended header */ 1051 offset = GET_HDR_OFFSET_2_0(efuseHeader); 1052 DBG_8192C("%s: extended header offset_2_0 = 0x%X\n", __func__, offset); 1053 1054 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseExtHdr, bPseudoTest); 1055 DBG_8192C("%s: efuse[%#X]= 0x%02x (ext header)\n", __func__, (((bank-1)*EFUSE_REAL_CONTENT_LEN_8723B)+eFuse_Addr-1), efuseExtHdr); 1056 if (ALL_WORDS_DISABLED(efuseExtHdr)) 1057 continue; 1058 1059 1060 offset |= ((efuseExtHdr & 0xF0) >> 1); 1061 wden = (efuseExtHdr & 0x0F); 1062 } else { 1063 offset = ((efuseHeader >> 4) & 0x0f); 1064 wden = (efuseHeader & 0x0f); 1065 } 1066 1067 if (offset < EFUSE_BT_MAX_SECTION) { 1068 u16 addr; 1069 1070 /* Get word enable value from PG header */ 1071 DBG_8192C("%s: Offset =%d Worden =%#X\n", __func__, offset, wden); 1072 1073 addr = offset * PGPKT_DATA_SIZE; 1074 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1075 /* Check word enable condition in the section */ 1076 if (!(wden & (0x01<<i))) { 1077 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 1078 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); 1079 efuseTbl[addr] = efuseData; 1080 1081 efuse_OneByteRead(padapter, eFuse_Addr++, &efuseData, bPseudoTest); 1082 DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, eFuse_Addr-1, efuseData); 1083 efuseTbl[addr+1] = efuseData; 1084 } 1085 addr += 2; 1086 } 1087 } else { 1088 DBG_8192C("%s: offset(%d) is illegal!!\n", __func__, offset); 1089 eFuse_Addr += Efuse_CalculateWordCnts(wden)*2; 1090 } 1091 } 1092 1093 if ((eFuse_Addr-1) < total) { 1094 DBG_8192C("%s: bank(%d) data end at %#x\n", __func__, bank, eFuse_Addr-1); 1095 break; 1096 } 1097 } 1098 1099 /* switch bank back to bank 0 for later BT and wifi use. */ 1100 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 1101 1102 /* Copy from Efuse map to output pointer memory!!! */ 1103 for (i = 0; i < _size_byte; i++) 1104 pbuf[i] = efuseTbl[_offset+i]; 1105 1106 /* */ 1107 /* Calculate Efuse utilization. */ 1108 /* */ 1109 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &total, bPseudoTest); 1110 used = (EFUSE_BT_REAL_BANK_CONTENT_LEN*(bank-1)) + eFuse_Addr - 1; 1111 DBG_8192C("%s: bank(%d) data end at %#x , used =%d\n", __func__, bank, eFuse_Addr-1, used); 1112 efuse_usage = (u8)((used*100)/total); 1113 if (bPseudoTest) { 1114 #ifdef HAL_EFUSE_MEMORY 1115 pEfuseHal->fakeBTEfuseUsedBytes = used; 1116 #else 1117 fakeBTEfuseUsedBytes = used; 1118 #endif 1119 } else { 1120 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&used); 1121 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BT_USAGE, (u8 *)&efuse_usage); 1122 } 1123 1124 exit: 1125 kfree(efuseTbl); 1126 } 1127 1128 static void Hal_ReadEFuse( 1129 struct adapter *padapter, 1130 u8 efuseType, 1131 u16 _offset, 1132 u16 _size_byte, 1133 u8 *pbuf, 1134 bool bPseudoTest 1135 ) 1136 { 1137 if (efuseType == EFUSE_WIFI) 1138 hal_ReadEFuse_WiFi(padapter, _offset, _size_byte, pbuf, bPseudoTest); 1139 else 1140 hal_ReadEFuse_BT(padapter, _offset, _size_byte, pbuf, bPseudoTest); 1141 } 1142 1143 static u16 hal_EfuseGetCurrentSize_WiFi( 1144 struct adapter *padapter, bool bPseudoTest 1145 ) 1146 { 1147 #ifdef HAL_EFUSE_MEMORY 1148 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1149 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1150 #endif 1151 u16 efuse_addr = 0; 1152 u16 start_addr = 0; /* for debug */ 1153 u8 hoffset = 0, hworden = 0; 1154 u8 efuse_data, word_cnts = 0; 1155 u32 count = 0; /* for debug */ 1156 1157 1158 if (bPseudoTest) { 1159 #ifdef HAL_EFUSE_MEMORY 1160 efuse_addr = (u16)pEfuseHal->fakeEfuseUsedBytes; 1161 #else 1162 efuse_addr = (u16)fakeEfuseUsedBytes; 1163 #endif 1164 } else 1165 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); 1166 1167 start_addr = efuse_addr; 1168 DBG_8192C("%s: start_efuse_addr = 0x%X\n", __func__, efuse_addr); 1169 1170 /* switch bank back to bank 0 for later BT and wifi use. */ 1171 hal_EfuseSwitchToBank(padapter, 0, bPseudoTest); 1172 1173 count = 0; 1174 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1175 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) { 1176 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr); 1177 goto error; 1178 } 1179 1180 if (efuse_data == 0xFF) 1181 break; 1182 1183 if ((start_addr != 0) && (efuse_addr == start_addr)) { 1184 count++; 1185 DBG_8192C(FUNC_ADPT_FMT ": [WARNING] efuse raw 0x%X = 0x%02X not 0xFF!!(%d times)\n", 1186 FUNC_ADPT_ARG(padapter), efuse_addr, efuse_data, count); 1187 1188 efuse_data = 0xFF; 1189 if (count < 4) { 1190 /* try again! */ 1191 1192 if (count > 2) { 1193 /* try again form address 0 */ 1194 efuse_addr = 0; 1195 start_addr = 0; 1196 } 1197 1198 continue; 1199 } 1200 1201 goto error; 1202 } 1203 1204 if (EXT_HEADER(efuse_data)) { 1205 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1206 efuse_addr++; 1207 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1208 if (ALL_WORDS_DISABLED(efuse_data)) 1209 continue; 1210 1211 hoffset |= ((efuse_data & 0xF0) >> 1); 1212 hworden = efuse_data & 0x0F; 1213 } else { 1214 hoffset = (efuse_data>>4) & 0x0F; 1215 hworden = efuse_data & 0x0F; 1216 } 1217 1218 word_cnts = Efuse_CalculateWordCnts(hworden); 1219 efuse_addr += (word_cnts*2)+1; 1220 } 1221 1222 if (bPseudoTest) { 1223 #ifdef HAL_EFUSE_MEMORY 1224 pEfuseHal->fakeEfuseUsedBytes = efuse_addr; 1225 #else 1226 fakeEfuseUsedBytes = efuse_addr; 1227 #endif 1228 } else 1229 rtw_hal_set_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&efuse_addr); 1230 1231 goto exit; 1232 1233 error: 1234 /* report max size to prevent write efuse */ 1235 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_addr, bPseudoTest); 1236 1237 exit: 1238 DBG_8192C("%s: CurrentSize =%d\n", __func__, efuse_addr); 1239 1240 return efuse_addr; 1241 } 1242 1243 static u16 hal_EfuseGetCurrentSize_BT(struct adapter *padapter, u8 bPseudoTest) 1244 { 1245 #ifdef HAL_EFUSE_MEMORY 1246 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1247 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1248 #endif 1249 u16 btusedbytes; 1250 u16 efuse_addr; 1251 u8 bank, startBank; 1252 u8 hoffset = 0, hworden = 0; 1253 u8 efuse_data, word_cnts = 0; 1254 u16 retU2 = 0; 1255 1256 if (bPseudoTest) { 1257 #ifdef HAL_EFUSE_MEMORY 1258 btusedbytes = pEfuseHal->fakeBTEfuseUsedBytes; 1259 #else 1260 btusedbytes = fakeBTEfuseUsedBytes; 1261 #endif 1262 } else 1263 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&btusedbytes); 1264 1265 efuse_addr = (u16)((btusedbytes%EFUSE_BT_REAL_BANK_CONTENT_LEN)); 1266 startBank = (u8)(1+(btusedbytes/EFUSE_BT_REAL_BANK_CONTENT_LEN)); 1267 1268 DBG_8192C("%s: start from bank =%d addr = 0x%X\n", __func__, startBank, efuse_addr); 1269 1270 EFUSE_GetEfuseDefinition(padapter, EFUSE_BT, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &retU2, bPseudoTest); 1271 1272 for (bank = startBank; bank < 3; bank++) { 1273 if (hal_EfuseSwitchToBank(padapter, bank, bPseudoTest) == false) { 1274 DBG_8192C(KERN_ERR "%s: switch bank(%d) Fail!!\n", __func__, bank); 1275 /* bank = EFUSE_MAX_BANK; */ 1276 break; 1277 } 1278 1279 /* only when bank is switched we have to reset the efuse_addr. */ 1280 if (bank != startBank) 1281 efuse_addr = 0; 1282 #if 1 1283 1284 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1285 if (efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) == false) { 1286 DBG_8192C(KERN_ERR "%s: efuse_OneByteRead Fail! addr = 0x%X !!\n", __func__, efuse_addr); 1287 /* bank = EFUSE_MAX_BANK; */ 1288 break; 1289 } 1290 DBG_8192C("%s: efuse_OneByteRead ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); 1291 1292 if (efuse_data == 0xFF) 1293 break; 1294 1295 if (EXT_HEADER(efuse_data)) { 1296 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1297 efuse_addr++; 1298 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1299 DBG_8192C("%s: efuse_OneByteRead EXT_HEADER ! addr = 0x%X !efuse_data = 0x%X! bank =%d\n", __func__, efuse_addr, efuse_data, bank); 1300 1301 if (ALL_WORDS_DISABLED(efuse_data)) { 1302 efuse_addr++; 1303 continue; 1304 } 1305 1306 /* hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); */ 1307 hoffset |= ((efuse_data & 0xF0) >> 1); 1308 hworden = efuse_data & 0x0F; 1309 } else { 1310 hoffset = (efuse_data>>4) & 0x0F; 1311 hworden = efuse_data & 0x0F; 1312 } 1313 1314 DBG_8192C(FUNC_ADPT_FMT": Offset =%d Worden =%#X\n", 1315 FUNC_ADPT_ARG(padapter), hoffset, hworden); 1316 1317 word_cnts = Efuse_CalculateWordCnts(hworden); 1318 /* read next header */ 1319 efuse_addr += (word_cnts*2)+1; 1320 } 1321 #else 1322 while ( 1323 bContinual && 1324 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest) && 1325 AVAILABLE_EFUSE_ADDR(efuse_addr) 1326 ) { 1327 if (efuse_data != 0xFF) { 1328 if ((efuse_data&0x1F) == 0x0F) { /* extended header */ 1329 hoffset = efuse_data; 1330 efuse_addr++; 1331 efuse_OneByteRead(padapter, efuse_addr, &efuse_data, bPseudoTest); 1332 if ((efuse_data & 0x0F) == 0x0F) { 1333 efuse_addr++; 1334 continue; 1335 } else { 1336 hoffset = ((hoffset & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); 1337 hworden = efuse_data & 0x0F; 1338 } 1339 } else { 1340 hoffset = (efuse_data>>4) & 0x0F; 1341 hworden = efuse_data & 0x0F; 1342 } 1343 word_cnts = Efuse_CalculateWordCnts(hworden); 1344 /* read next header */ 1345 efuse_addr = efuse_addr + (word_cnts*2)+1; 1346 } else 1347 bContinual = false; 1348 } 1349 #endif 1350 1351 1352 /* Check if we need to check next bank efuse */ 1353 if (efuse_addr < retU2) 1354 break; /* don't need to check next bank. */ 1355 } 1356 1357 retU2 = ((bank-1)*EFUSE_BT_REAL_BANK_CONTENT_LEN)+efuse_addr; 1358 if (bPseudoTest) { 1359 pEfuseHal->fakeBTEfuseUsedBytes = retU2; 1360 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->fakeBTEfuseUsedBytes)); */ 1361 } else { 1362 pEfuseHal->BTEfuseUsedBytes = retU2; 1363 /* RT_DISP(FEEPROM, EFUSE_PG, ("Hal_EfuseGetCurrentSize_BT92C(), already use %u bytes\n", pEfuseHal->BTEfuseUsedBytes)); */ 1364 } 1365 1366 DBG_8192C("%s: CurrentSize =%d\n", __func__, retU2); 1367 return retU2; 1368 } 1369 1370 static u16 Hal_EfuseGetCurrentSize( 1371 struct adapter *padapter, u8 efuseType, bool bPseudoTest 1372 ) 1373 { 1374 u16 ret = 0; 1375 1376 if (efuseType == EFUSE_WIFI) 1377 ret = hal_EfuseGetCurrentSize_WiFi(padapter, bPseudoTest); 1378 else 1379 ret = hal_EfuseGetCurrentSize_BT(padapter, bPseudoTest); 1380 1381 return ret; 1382 } 1383 1384 static u8 Hal_EfuseWordEnableDataWrite( 1385 struct adapter *padapter, 1386 u16 efuse_addr, 1387 u8 word_en, 1388 u8 *data, 1389 bool bPseudoTest 1390 ) 1391 { 1392 u16 tmpaddr = 0; 1393 u16 start_addr = efuse_addr; 1394 u8 badworden = 0x0F; 1395 u8 tmpdata[PGPKT_DATA_SIZE]; 1396 1397 1398 /* DBG_8192C("%s: efuse_addr =%#x word_en =%#x\n", __func__, efuse_addr, word_en); */ 1399 memset(tmpdata, 0xFF, PGPKT_DATA_SIZE); 1400 1401 if (!(word_en & BIT(0))) { 1402 tmpaddr = start_addr; 1403 efuse_OneByteWrite(padapter, start_addr++, data[0], bPseudoTest); 1404 efuse_OneByteWrite(padapter, start_addr++, data[1], bPseudoTest); 1405 1406 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[0], bPseudoTest); 1407 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[1], bPseudoTest); 1408 if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1])) { 1409 badworden &= (~BIT(0)); 1410 } 1411 } 1412 if (!(word_en & BIT(1))) { 1413 tmpaddr = start_addr; 1414 efuse_OneByteWrite(padapter, start_addr++, data[2], bPseudoTest); 1415 efuse_OneByteWrite(padapter, start_addr++, data[3], bPseudoTest); 1416 1417 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[2], bPseudoTest); 1418 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[3], bPseudoTest); 1419 if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3])) { 1420 badworden &= (~BIT(1)); 1421 } 1422 } 1423 1424 if (!(word_en & BIT(2))) { 1425 tmpaddr = start_addr; 1426 efuse_OneByteWrite(padapter, start_addr++, data[4], bPseudoTest); 1427 efuse_OneByteWrite(padapter, start_addr++, data[5], bPseudoTest); 1428 1429 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[4], bPseudoTest); 1430 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[5], bPseudoTest); 1431 if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5])) { 1432 badworden &= (~BIT(2)); 1433 } 1434 } 1435 1436 if (!(word_en & BIT(3))) { 1437 tmpaddr = start_addr; 1438 efuse_OneByteWrite(padapter, start_addr++, data[6], bPseudoTest); 1439 efuse_OneByteWrite(padapter, start_addr++, data[7], bPseudoTest); 1440 1441 efuse_OneByteRead(padapter, tmpaddr, &tmpdata[6], bPseudoTest); 1442 efuse_OneByteRead(padapter, tmpaddr+1, &tmpdata[7], bPseudoTest); 1443 if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7])) { 1444 badworden &= (~BIT(3)); 1445 } 1446 } 1447 1448 return badworden; 1449 } 1450 1451 static s32 Hal_EfusePgPacketRead( 1452 struct adapter *padapter, 1453 u8 offset, 1454 u8 *data, 1455 bool bPseudoTest 1456 ) 1457 { 1458 u8 efuse_data, word_cnts = 0; 1459 u16 efuse_addr = 0; 1460 u8 hoffset = 0, hworden = 0; 1461 u8 i; 1462 u8 max_section = 0; 1463 s32 ret; 1464 1465 1466 if (!data) 1467 return false; 1468 1469 EFUSE_GetEfuseDefinition(padapter, EFUSE_WIFI, TYPE_EFUSE_MAX_SECTION, &max_section, bPseudoTest); 1470 if (offset > max_section) { 1471 DBG_8192C("%s: Packet offset(%d) is illegal(>%d)!\n", __func__, offset, max_section); 1472 return false; 1473 } 1474 1475 memset(data, 0xFF, PGPKT_DATA_SIZE); 1476 ret = true; 1477 1478 /* */ 1479 /* <Roger_TODO> Efuse has been pre-programmed dummy 5Bytes at the end of Efuse by CP. */ 1480 /* Skip dummy parts to prevent unexpected data read from Efuse. */ 1481 /* By pass right now. 2009.02.19. */ 1482 /* */ 1483 while (AVAILABLE_EFUSE_ADDR(efuse_addr)) { 1484 if (efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest) == false) { 1485 ret = false; 1486 break; 1487 } 1488 1489 if (efuse_data == 0xFF) 1490 break; 1491 1492 if (EXT_HEADER(efuse_data)) { 1493 hoffset = GET_HDR_OFFSET_2_0(efuse_data); 1494 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1495 if (ALL_WORDS_DISABLED(efuse_data)) { 1496 DBG_8192C("%s: Error!! All words disabled!\n", __func__); 1497 continue; 1498 } 1499 1500 hoffset |= ((efuse_data & 0xF0) >> 1); 1501 hworden = efuse_data & 0x0F; 1502 } else { 1503 hoffset = (efuse_data>>4) & 0x0F; 1504 hworden = efuse_data & 0x0F; 1505 } 1506 1507 if (hoffset == offset) { 1508 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { 1509 /* Check word enable condition in the section */ 1510 if (!(hworden & (0x01<<i))) { 1511 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1512 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ 1513 data[i*2] = efuse_data; 1514 1515 efuse_OneByteRead(padapter, efuse_addr++, &efuse_data, bPseudoTest); 1516 /* DBG_8192C("%s: efuse[%#X]= 0x%02X\n", __func__, efuse_addr+tmpidx, efuse_data); */ 1517 data[(i*2)+1] = efuse_data; 1518 } 1519 } 1520 } else { 1521 word_cnts = Efuse_CalculateWordCnts(hworden); 1522 efuse_addr += word_cnts*2; 1523 } 1524 } 1525 1526 return ret; 1527 } 1528 1529 static u8 hal_EfusePgCheckAvailableAddr( 1530 struct adapter *padapter, u8 efuseType, u8 bPseudoTest 1531 ) 1532 { 1533 u16 max_available = 0; 1534 u16 current_size; 1535 1536 1537 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &max_available, bPseudoTest); 1538 /* DBG_8192C("%s: max_available =%d\n", __func__, max_available); */ 1539 1540 current_size = Efuse_GetCurrentSize(padapter, efuseType, bPseudoTest); 1541 if (current_size >= max_available) { 1542 DBG_8192C("%s: Error!! current_size(%d)>max_available(%d)\n", __func__, current_size, max_available); 1543 return false; 1544 } 1545 return true; 1546 } 1547 1548 static void hal_EfuseConstructPGPkt( 1549 u8 offset, 1550 u8 word_en, 1551 u8 *pData, 1552 PPGPKT_STRUCT pTargetPkt 1553 ) 1554 { 1555 memset(pTargetPkt->data, 0xFF, PGPKT_DATA_SIZE); 1556 pTargetPkt->offset = offset; 1557 pTargetPkt->word_en = word_en; 1558 efuse_WordEnableDataRead(word_en, pData, pTargetPkt->data); 1559 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); 1560 } 1561 1562 static u8 hal_EfusePartialWriteCheck( 1563 struct adapter *padapter, 1564 u8 efuseType, 1565 u16 *pAddr, 1566 PPGPKT_STRUCT pTargetPkt, 1567 u8 bPseudoTest 1568 ) 1569 { 1570 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1571 PEFUSE_HAL pEfuseHal = &pHalData->EfuseHal; 1572 u8 bRet = false; 1573 u16 startAddr = 0, efuse_max_available_len = 0, efuse_max = 0; 1574 u8 efuse_data = 0; 1575 1576 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_TOTAL, &efuse_max_available_len, bPseudoTest); 1577 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_EFUSE_CONTENT_LEN_BANK, &efuse_max, bPseudoTest); 1578 1579 if (efuseType == EFUSE_WIFI) { 1580 if (bPseudoTest) { 1581 #ifdef HAL_EFUSE_MEMORY 1582 startAddr = (u16)pEfuseHal->fakeEfuseUsedBytes; 1583 #else 1584 startAddr = (u16)fakeEfuseUsedBytes; 1585 #endif 1586 } else 1587 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BYTES, (u8 *)&startAddr); 1588 } else { 1589 if (bPseudoTest) { 1590 #ifdef HAL_EFUSE_MEMORY 1591 startAddr = (u16)pEfuseHal->fakeBTEfuseUsedBytes; 1592 #else 1593 startAddr = (u16)fakeBTEfuseUsedBytes; 1594 #endif 1595 } else 1596 rtw_hal_get_hwreg(padapter, HW_VAR_EFUSE_BT_BYTES, (u8 *)&startAddr); 1597 } 1598 startAddr %= efuse_max; 1599 DBG_8192C("%s: startAddr =%#X\n", __func__, startAddr); 1600 1601 while (1) { 1602 if (startAddr >= efuse_max_available_len) { 1603 bRet = false; 1604 DBG_8192C("%s: startAddr(%d) >= efuse_max_available_len(%d)\n", __func__, startAddr, efuse_max_available_len); 1605 break; 1606 } 1607 1608 if (efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest) && (efuse_data != 0xFF)) { 1609 #if 1 1610 bRet = false; 1611 DBG_8192C("%s: Something Wrong! last bytes(%#X = 0x%02X) is not 0xFF\n", 1612 __func__, startAddr, efuse_data); 1613 break; 1614 #else 1615 if (EXT_HEADER(efuse_data)) { 1616 cur_header = efuse_data; 1617 startAddr++; 1618 efuse_OneByteRead(padapter, startAddr, &efuse_data, bPseudoTest); 1619 if (ALL_WORDS_DISABLED(efuse_data)) { 1620 DBG_8192C("%s: Error condition, all words disabled!", __func__); 1621 bRet = false; 1622 break; 1623 } else { 1624 curPkt.offset = ((cur_header & 0xE0) >> 5) | ((efuse_data & 0xF0) >> 1); 1625 curPkt.word_en = efuse_data & 0x0F; 1626 } 1627 } else { 1628 cur_header = efuse_data; 1629 curPkt.offset = (cur_header>>4) & 0x0F; 1630 curPkt.word_en = cur_header & 0x0F; 1631 } 1632 1633 curPkt.word_cnts = Efuse_CalculateWordCnts(curPkt.word_en); 1634 /* if same header is found but no data followed */ 1635 /* write some part of data followed by the header. */ 1636 if ( 1637 (curPkt.offset == pTargetPkt->offset) && 1638 (hal_EfuseCheckIfDatafollowed(padapter, curPkt.word_cnts, startAddr+1, bPseudoTest) == false) && 1639 wordEnMatched(pTargetPkt, &curPkt, &matched_wden) == true 1640 ) { 1641 DBG_8192C("%s: Need to partial write data by the previous wrote header\n", __func__); 1642 /* Here to write partial data */ 1643 badworden = Efuse_WordEnableDataWrite(padapter, startAddr+1, matched_wden, pTargetPkt->data, bPseudoTest); 1644 if (badworden != 0x0F) { 1645 u32 PgWriteSuccess = 0; 1646 /* if write fail on some words, write these bad words again */ 1647 if (efuseType == EFUSE_WIFI) 1648 PgWriteSuccess = Efuse_PgPacketWrite(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); 1649 else 1650 PgWriteSuccess = Efuse_PgPacketWrite_BT(padapter, pTargetPkt->offset, badworden, pTargetPkt->data, bPseudoTest); 1651 1652 if (!PgWriteSuccess) { 1653 bRet = false; /* write fail, return */ 1654 break; 1655 } 1656 } 1657 /* partial write ok, update the target packet for later use */ 1658 for (i = 0; i < 4; i++) { 1659 if ((matched_wden & (0x1<<i)) == 0) { /* this word has been written */ 1660 pTargetPkt->word_en |= (0x1<<i); /* disable the word */ 1661 } 1662 } 1663 pTargetPkt->word_cnts = Efuse_CalculateWordCnts(pTargetPkt->word_en); 1664 } 1665 /* read from next header */ 1666 startAddr = startAddr + (curPkt.word_cnts*2) + 1; 1667 #endif 1668 } else { 1669 /* not used header, 0xff */ 1670 *pAddr = startAddr; 1671 /* DBG_8192C("%s: Started from unused header offset =%d\n", __func__, startAddr)); */ 1672 bRet = true; 1673 break; 1674 } 1675 } 1676 1677 return bRet; 1678 } 1679 1680 static u8 hal_EfusePgPacketWrite1ByteHeader( 1681 struct adapter *padapter, 1682 u8 efuseType, 1683 u16 *pAddr, 1684 PPGPKT_STRUCT pTargetPkt, 1685 u8 bPseudoTest 1686 ) 1687 { 1688 u8 pg_header = 0, tmp_header = 0; 1689 u16 efuse_addr = *pAddr; 1690 u8 repeatcnt = 0; 1691 1692 1693 /* DBG_8192C("%s\n", __func__); */ 1694 pg_header = ((pTargetPkt->offset << 4) & 0xf0) | pTargetPkt->word_en; 1695 1696 do { 1697 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1698 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1699 if (tmp_header != 0xFF) 1700 break; 1701 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1702 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__); 1703 return false; 1704 } 1705 } while (1); 1706 1707 if (tmp_header != pg_header) { 1708 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1709 return false; 1710 } 1711 1712 *pAddr = efuse_addr; 1713 1714 return true; 1715 } 1716 1717 static u8 hal_EfusePgPacketWrite2ByteHeader( 1718 struct adapter *padapter, 1719 u8 efuseType, 1720 u16 *pAddr, 1721 PPGPKT_STRUCT pTargetPkt, 1722 u8 bPseudoTest 1723 ) 1724 { 1725 u16 efuse_addr, efuse_max_available_len = 0; 1726 u8 pg_header = 0, tmp_header = 0; 1727 u8 repeatcnt = 0; 1728 1729 1730 /* DBG_8192C("%s\n", __func__); */ 1731 EFUSE_GetEfuseDefinition(padapter, efuseType, TYPE_AVAILABLE_EFUSE_BYTES_BANK, &efuse_max_available_len, bPseudoTest); 1732 1733 efuse_addr = *pAddr; 1734 if (efuse_addr >= efuse_max_available_len) { 1735 DBG_8192C("%s: addr(%d) over available (%d)!!\n", __func__, 1736 efuse_addr, efuse_max_available_len); 1737 return false; 1738 } 1739 1740 pg_header = ((pTargetPkt->offset & 0x07) << 5) | 0x0F; 1741 /* DBG_8192C("%s: pg_header = 0x%x\n", __func__, pg_header); */ 1742 1743 do { 1744 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1745 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1746 if (tmp_header != 0xFF) 1747 break; 1748 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1749 DBG_8192C("%s: Repeat over limit for pg_header!!\n", __func__); 1750 return false; 1751 } 1752 } while (1); 1753 1754 if (tmp_header != pg_header) { 1755 DBG_8192C(KERN_ERR "%s: PG Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1756 return false; 1757 } 1758 1759 /* to write ext_header */ 1760 efuse_addr++; 1761 pg_header = ((pTargetPkt->offset & 0x78) << 1) | pTargetPkt->word_en; 1762 1763 do { 1764 efuse_OneByteWrite(padapter, efuse_addr, pg_header, bPseudoTest); 1765 efuse_OneByteRead(padapter, efuse_addr, &tmp_header, bPseudoTest); 1766 if (tmp_header != 0xFF) 1767 break; 1768 if (repeatcnt++ > EFUSE_REPEAT_THRESHOLD_) { 1769 DBG_8192C("%s: Repeat over limit for ext_header!!\n", __func__); 1770 return false; 1771 } 1772 } while (1); 1773 1774 if (tmp_header != pg_header) { /* offset PG fail */ 1775 DBG_8192C(KERN_ERR "%s: PG EXT Header Fail!!(pg = 0x%02X read = 0x%02X)\n", __func__, pg_header, tmp_header); 1776 return false; 1777 } 1778 1779 *pAddr = efuse_addr; 1780 1781 return true; 1782 } 1783 1784 static u8 hal_EfusePgPacketWriteHeader( 1785 struct adapter *padapter, 1786 u8 efuseType, 1787 u16 *pAddr, 1788 PPGPKT_STRUCT pTargetPkt, 1789 u8 bPseudoTest 1790 ) 1791 { 1792 u8 bRet = false; 1793 1794 if (pTargetPkt->offset >= EFUSE_MAX_SECTION_BASE) 1795 bRet = hal_EfusePgPacketWrite2ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); 1796 else 1797 bRet = hal_EfusePgPacketWrite1ByteHeader(padapter, efuseType, pAddr, pTargetPkt, bPseudoTest); 1798 1799 return bRet; 1800 } 1801 1802 static u8 hal_EfusePgPacketWriteData( 1803 struct adapter *padapter, 1804 u8 efuseType, 1805 u16 *pAddr, 1806 PPGPKT_STRUCT pTargetPkt, 1807 u8 bPseudoTest 1808 ) 1809 { 1810 u16 efuse_addr; 1811 u8 badworden; 1812 1813 1814 efuse_addr = *pAddr; 1815 badworden = Efuse_WordEnableDataWrite(padapter, efuse_addr+1, pTargetPkt->word_en, pTargetPkt->data, bPseudoTest); 1816 if (badworden != 0x0F) { 1817 DBG_8192C("%s: Fail!!\n", __func__); 1818 return false; 1819 } 1820 1821 /* DBG_8192C("%s: ok\n", __func__); */ 1822 return true; 1823 } 1824 1825 static s32 Hal_EfusePgPacketWrite( 1826 struct adapter *padapter, 1827 u8 offset, 1828 u8 word_en, 1829 u8 *pData, 1830 bool bPseudoTest 1831 ) 1832 { 1833 PGPKT_STRUCT targetPkt; 1834 u16 startAddr = 0; 1835 u8 efuseType = EFUSE_WIFI; 1836 1837 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest)) 1838 return false; 1839 1840 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); 1841 1842 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1843 return false; 1844 1845 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1846 return false; 1847 1848 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1849 return false; 1850 1851 return true; 1852 } 1853 1854 static bool Hal_EfusePgPacketWrite_BT( 1855 struct adapter *padapter, 1856 u8 offset, 1857 u8 word_en, 1858 u8 *pData, 1859 bool bPseudoTest 1860 ) 1861 { 1862 PGPKT_STRUCT targetPkt; 1863 u16 startAddr = 0; 1864 u8 efuseType = EFUSE_BT; 1865 1866 if (!hal_EfusePgCheckAvailableAddr(padapter, efuseType, bPseudoTest)) 1867 return false; 1868 1869 hal_EfuseConstructPGPkt(offset, word_en, pData, &targetPkt); 1870 1871 if (!hal_EfusePartialWriteCheck(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1872 return false; 1873 1874 if (!hal_EfusePgPacketWriteHeader(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1875 return false; 1876 1877 if (!hal_EfusePgPacketWriteData(padapter, efuseType, &startAddr, &targetPkt, bPseudoTest)) 1878 return false; 1879 1880 return true; 1881 } 1882 1883 static HAL_VERSION ReadChipVersion8723B(struct adapter *padapter) 1884 { 1885 u32 value32; 1886 HAL_VERSION ChipVersion; 1887 struct hal_com_data *pHalData; 1888 1889 /* YJ, TODO, move read chip type here */ 1890 pHalData = GET_HAL_DATA(padapter); 1891 1892 value32 = rtw_read32(padapter, REG_SYS_CFG); 1893 ChipVersion.ICType = CHIP_8723B; 1894 ChipVersion.ChipType = ((value32 & RTL_ID) ? TEST_CHIP : NORMAL_CHIP); 1895 ChipVersion.RFType = RF_TYPE_1T1R; 1896 ChipVersion.VendorType = ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : CHIP_VENDOR_TSMC); 1897 ChipVersion.CUTVersion = (value32 & CHIP_VER_RTL_MASK)>>CHIP_VER_RTL_SHIFT; /* IC version (CUT) */ 1898 1899 /* For regulator mode. by tynli. 2011.01.14 */ 1900 pHalData->RegulatorMode = ((value32 & SPS_SEL) ? RT_LDO_REGULATOR : RT_SWITCHING_REGULATOR); 1901 1902 value32 = rtw_read32(padapter, REG_GPIO_OUTSTS); 1903 ChipVersion.ROMVer = ((value32 & RF_RL_ID) >> 20); /* ROM code version. */ 1904 1905 /* For multi-function consideration. Added by Roger, 2010.10.06. */ 1906 pHalData->MultiFunc = RT_MULTI_FUNC_NONE; 1907 value32 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL); 1908 pHalData->MultiFunc |= ((value32 & WL_FUNC_EN) ? RT_MULTI_FUNC_WIFI : 0); 1909 pHalData->MultiFunc |= ((value32 & BT_FUNC_EN) ? RT_MULTI_FUNC_BT : 0); 1910 pHalData->MultiFunc |= ((value32 & GPS_FUNC_EN) ? RT_MULTI_FUNC_GPS : 0); 1911 pHalData->PolarityCtl = ((value32 & WL_HWPDN_SL) ? RT_POLARITY_HIGH_ACT : RT_POLARITY_LOW_ACT); 1912 #if 1 1913 dump_chip_info(ChipVersion); 1914 #endif 1915 pHalData->VersionID = ChipVersion; 1916 if (IS_1T2R(ChipVersion)) 1917 pHalData->rf_type = RF_1T2R; 1918 else if (IS_2T2R(ChipVersion)) 1919 pHalData->rf_type = RF_2T2R; 1920 else 1921 pHalData->rf_type = RF_1T1R; 1922 1923 MSG_8192C("RF_Type is %x!!\n", pHalData->rf_type); 1924 1925 return ChipVersion; 1926 } 1927 1928 static void rtl8723b_read_chip_version(struct adapter *padapter) 1929 { 1930 ReadChipVersion8723B(padapter); 1931 } 1932 1933 void rtl8723b_InitBeaconParameters(struct adapter *padapter) 1934 { 1935 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1936 u16 val16; 1937 u8 val8; 1938 1939 1940 val8 = DIS_TSF_UDT; 1941 val16 = val8 | (val8 << 8); /* port0 and port1 */ 1942 1943 /* Enable prot0 beacon function for PSTDMA */ 1944 val16 |= EN_BCN_FUNCTION; 1945 1946 rtw_write16(padapter, REG_BCN_CTRL, val16); 1947 1948 /* TODO: Remove these magic number */ 1949 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0x6404);/* ms */ 1950 /* Firmware will control REG_DRVERLYINT when power saving is enable, */ 1951 /* so don't set this register on STA mode. */ 1952 if (check_fwstate(&padapter->mlmepriv, WIFI_STATION_STATE) == false) 1953 rtw_write8(padapter, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME_8723B); /* 5ms */ 1954 rtw_write8(padapter, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME_8723B); /* 2ms */ 1955 1956 /* Suggested by designer timchen. Change beacon AIFS to the largest number */ 1957 /* beacause test chip does not contension before sending beacon. by tynli. 2009.11.03 */ 1958 rtw_write16(padapter, REG_BCNTCFG, 0x660F); 1959 1960 pHalData->RegBcnCtrlVal = rtw_read8(padapter, REG_BCN_CTRL); 1961 pHalData->RegTxPause = rtw_read8(padapter, REG_TXPAUSE); 1962 pHalData->RegFwHwTxQCtrl = rtw_read8(padapter, REG_FWHW_TXQ_CTRL+2); 1963 pHalData->RegReg542 = rtw_read8(padapter, REG_TBTT_PROHIBIT+2); 1964 pHalData->RegCR_1 = rtw_read8(padapter, REG_CR+1); 1965 } 1966 1967 void _InitBurstPktLen_8723BS(struct adapter *Adapter) 1968 { 1969 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1970 1971 rtw_write8(Adapter, 0x4c7, rtw_read8(Adapter, 0x4c7)|BIT(7)); /* enable single pkt ampdu */ 1972 rtw_write8(Adapter, REG_RX_PKT_LIMIT_8723B, 0x18); /* for VHT packet length 11K */ 1973 rtw_write8(Adapter, REG_MAX_AGGR_NUM_8723B, 0x1F); 1974 rtw_write8(Adapter, REG_PIFS_8723B, 0x00); 1975 rtw_write8(Adapter, REG_FWHW_TXQ_CTRL_8723B, rtw_read8(Adapter, REG_FWHW_TXQ_CTRL)&(~BIT(7))); 1976 if (pHalData->AMPDUBurstMode) 1977 rtw_write8(Adapter, REG_AMPDU_BURST_MODE_8723B, 0x5F); 1978 rtw_write8(Adapter, REG_AMPDU_MAX_TIME_8723B, 0x70); 1979 1980 /* ARFB table 9 for 11ac 5G 2SS */ 1981 rtw_write32(Adapter, REG_ARFR0_8723B, 0x00000010); 1982 if (IS_NORMAL_CHIP(pHalData->VersionID)) 1983 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0xfffff000); 1984 else 1985 rtw_write32(Adapter, REG_ARFR0_8723B+4, 0x3e0ff000); 1986 1987 /* ARFB table 10 for 11ac 5G 1SS */ 1988 rtw_write32(Adapter, REG_ARFR1_8723B, 0x00000010); 1989 rtw_write32(Adapter, REG_ARFR1_8723B+4, 0x003ff000); 1990 } 1991 1992 static void ResumeTxBeacon(struct adapter *padapter) 1993 { 1994 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1995 1996 1997 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ 1998 /* which should be read from register to a global variable. */ 1999 2000 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+ResumeTxBeacon\n")); 2001 2002 pHalData->RegFwHwTxQCtrl |= BIT(6); 2003 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); 2004 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0xff); 2005 pHalData->RegReg542 |= BIT(0); 2006 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); 2007 } 2008 2009 static void StopTxBeacon(struct adapter *padapter) 2010 { 2011 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2012 2013 2014 /* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */ 2015 /* which should be read from register to a global variable. */ 2016 2017 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+StopTxBeacon\n")); 2018 2019 pHalData->RegFwHwTxQCtrl &= ~BIT(6); 2020 rtw_write8(padapter, REG_FWHW_TXQ_CTRL+2, pHalData->RegFwHwTxQCtrl); 2021 rtw_write8(padapter, REG_TBTT_PROHIBIT+1, 0x64); 2022 pHalData->RegReg542 &= ~BIT(0); 2023 rtw_write8(padapter, REG_TBTT_PROHIBIT+2, pHalData->RegReg542); 2024 2025 CheckFwRsvdPageContent(padapter); /* 2010.06.23. Added by tynli. */ 2026 } 2027 2028 static void _BeaconFunctionEnable(struct adapter *padapter, u8 Enable, u8 Linked) 2029 { 2030 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT | EN_BCN_FUNCTION | DIS_BCNQ_SUB); 2031 rtw_write8(padapter, REG_RD_CTRL+1, 0x6F); 2032 } 2033 2034 static void rtl8723b_SetBeaconRelatedRegisters(struct adapter *padapter) 2035 { 2036 u8 val8; 2037 u32 value32; 2038 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; 2039 struct mlme_ext_info *pmlmeinfo = &pmlmeext->mlmext_info; 2040 u32 bcn_ctrl_reg; 2041 2042 /* reset TSF, enable update TSF, correcting TSF On Beacon */ 2043 2044 /* REG_BCN_INTERVAL */ 2045 /* REG_BCNDMATIM */ 2046 /* REG_ATIMWND */ 2047 /* REG_TBTT_PROHIBIT */ 2048 /* REG_DRVERLYINT */ 2049 /* REG_BCN_MAX_ERR */ 2050 /* REG_BCNTCFG (0x510) */ 2051 /* REG_DUAL_TSF_RST */ 2052 /* REG_BCN_CTRL (0x550) */ 2053 2054 2055 bcn_ctrl_reg = REG_BCN_CTRL; 2056 2057 /* */ 2058 /* ATIM window */ 2059 /* */ 2060 rtw_write16(padapter, REG_ATIMWND, 2); 2061 2062 /* */ 2063 /* Beacon interval (in unit of TU). */ 2064 /* */ 2065 rtw_write16(padapter, REG_BCN_INTERVAL, pmlmeinfo->bcn_interval); 2066 2067 rtl8723b_InitBeaconParameters(padapter); 2068 2069 rtw_write8(padapter, REG_SLOT, 0x09); 2070 2071 /* */ 2072 /* Reset TSF Timer to zero, added by Roger. 2008.06.24 */ 2073 /* */ 2074 value32 = rtw_read32(padapter, REG_TCR); 2075 value32 &= ~TSFRST; 2076 rtw_write32(padapter, REG_TCR, value32); 2077 2078 value32 |= TSFRST; 2079 rtw_write32(padapter, REG_TCR, value32); 2080 2081 /* NOTE: Fix test chip's bug (about contention windows's randomness) */ 2082 if (check_fwstate(&padapter->mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE|WIFI_AP_STATE) == true) { 2083 rtw_write8(padapter, REG_RXTSF_OFFSET_CCK, 0x50); 2084 rtw_write8(padapter, REG_RXTSF_OFFSET_OFDM, 0x50); 2085 } 2086 2087 _BeaconFunctionEnable(padapter, true, true); 2088 2089 ResumeTxBeacon(padapter); 2090 val8 = rtw_read8(padapter, bcn_ctrl_reg); 2091 val8 |= DIS_BCNQ_SUB; 2092 rtw_write8(padapter, bcn_ctrl_reg, val8); 2093 } 2094 2095 static void rtl8723b_GetHalODMVar( 2096 struct adapter *Adapter, 2097 enum HAL_ODM_VARIABLE eVariable, 2098 void *pValue1, 2099 void *pValue2 2100 ) 2101 { 2102 GetHalODMVar(Adapter, eVariable, pValue1, pValue2); 2103 } 2104 2105 static void rtl8723b_SetHalODMVar( 2106 struct adapter *Adapter, 2107 enum HAL_ODM_VARIABLE eVariable, 2108 void *pValue1, 2109 bool bSet 2110 ) 2111 { 2112 SetHalODMVar(Adapter, eVariable, pValue1, bSet); 2113 } 2114 2115 static void hal_notch_filter_8723b(struct adapter *adapter, bool enable) 2116 { 2117 if (enable) { 2118 DBG_871X("Enable notch filter\n"); 2119 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) | BIT1); 2120 } else { 2121 DBG_871X("Disable notch filter\n"); 2122 rtw_write8(adapter, rOFDM0_RxDSP+1, rtw_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1); 2123 } 2124 } 2125 2126 static void UpdateHalRAMask8723B(struct adapter *padapter, u32 mac_id, u8 rssi_level) 2127 { 2128 u32 mask, rate_bitmap; 2129 u8 shortGIrate = false; 2130 struct sta_info *psta; 2131 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2132 struct dm_priv *pdmpriv = &pHalData->dmpriv; 2133 struct mlme_ext_priv *pmlmeext = &padapter->mlmeextpriv; 2134 struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info); 2135 2136 DBG_871X("%s(): mac_id =%d rssi_level =%d\n", __func__, mac_id, rssi_level); 2137 2138 if (mac_id >= NUM_STA) /* CAM_SIZE */ 2139 return; 2140 2141 psta = pmlmeinfo->FW_sta_info[mac_id].psta; 2142 if (!psta) 2143 return; 2144 2145 shortGIrate = query_ra_short_GI(psta); 2146 2147 mask = psta->ra_mask; 2148 2149 rate_bitmap = 0xffffffff; 2150 rate_bitmap = ODM_Get_Rate_Bitmap(&pHalData->odmpriv, mac_id, mask, rssi_level); 2151 DBG_871X("%s => mac_id:%d, networkType:0x%02x, mask:0x%08x\n\t ==> rssi_level:%d, rate_bitmap:0x%08x\n", 2152 __func__, mac_id, psta->wireless_mode, mask, rssi_level, rate_bitmap); 2153 2154 mask &= rate_bitmap; 2155 2156 rate_bitmap = hal_btcoex_GetRaMask(padapter); 2157 mask &= ~rate_bitmap; 2158 2159 #ifdef CONFIG_CMCC_TEST 2160 if (pmlmeext->cur_wireless_mode & WIRELESS_11G) { 2161 if (mac_id == 0) { 2162 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); 2163 mask &= 0xffffff00; /* disable CCK & <24M OFDM rate for 11G mode for CMCC */ 2164 DBG_871X("CMCC_BT update raid entry, mask = 0x%x\n", mask); 2165 } 2166 } 2167 #endif 2168 2169 if (pHalData->fw_ractrl) { 2170 rtl8723b_set_FwMacIdConfig_cmd(padapter, mac_id, psta->raid, psta->bw_mode, shortGIrate, mask); 2171 } 2172 2173 /* set correct initial date rate for each mac_id */ 2174 pdmpriv->INIDATA_RATE[mac_id] = psta->init_rate; 2175 DBG_871X("%s(): mac_id =%d raid = 0x%x bw =%d mask = 0x%x init_rate = 0x%x\n", __func__, mac_id, psta->raid, psta->bw_mode, mask, psta->init_rate); 2176 } 2177 2178 2179 void rtl8723b_set_hal_ops(struct hal_ops *pHalFunc) 2180 { 2181 pHalFunc->free_hal_data = &rtl8723b_free_hal_data; 2182 2183 pHalFunc->dm_init = &rtl8723b_init_dm_priv; 2184 2185 pHalFunc->read_chip_version = &rtl8723b_read_chip_version; 2186 2187 pHalFunc->UpdateRAMaskHandler = &UpdateHalRAMask8723B; 2188 2189 pHalFunc->set_bwmode_handler = &PHY_SetBWMode8723B; 2190 pHalFunc->set_channel_handler = &PHY_SwChnl8723B; 2191 pHalFunc->set_chnl_bw_handler = &PHY_SetSwChnlBWMode8723B; 2192 2193 pHalFunc->set_tx_power_level_handler = &PHY_SetTxPowerLevel8723B; 2194 pHalFunc->get_tx_power_level_handler = &PHY_GetTxPowerLevel8723B; 2195 2196 pHalFunc->hal_dm_watchdog = &rtl8723b_HalDmWatchDog; 2197 pHalFunc->hal_dm_watchdog_in_lps = &rtl8723b_HalDmWatchDog_in_LPS; 2198 2199 2200 pHalFunc->SetBeaconRelatedRegistersHandler = &rtl8723b_SetBeaconRelatedRegisters; 2201 2202 pHalFunc->Add_RateATid = &rtl8723b_Add_RateATid; 2203 2204 pHalFunc->run_thread = &rtl8723b_start_thread; 2205 pHalFunc->cancel_thread = &rtl8723b_stop_thread; 2206 2207 pHalFunc->read_bbreg = &PHY_QueryBBReg_8723B; 2208 pHalFunc->write_bbreg = &PHY_SetBBReg_8723B; 2209 pHalFunc->read_rfreg = &PHY_QueryRFReg_8723B; 2210 pHalFunc->write_rfreg = &PHY_SetRFReg_8723B; 2211 2212 /* Efuse related function */ 2213 pHalFunc->BTEfusePowerSwitch = &Hal_BT_EfusePowerSwitch; 2214 pHalFunc->EfusePowerSwitch = &Hal_EfusePowerSwitch; 2215 pHalFunc->ReadEFuse = &Hal_ReadEFuse; 2216 pHalFunc->EFUSEGetEfuseDefinition = &Hal_GetEfuseDefinition; 2217 pHalFunc->EfuseGetCurrentSize = &Hal_EfuseGetCurrentSize; 2218 pHalFunc->Efuse_PgPacketRead = &Hal_EfusePgPacketRead; 2219 pHalFunc->Efuse_PgPacketWrite = &Hal_EfusePgPacketWrite; 2220 pHalFunc->Efuse_WordEnableDataWrite = &Hal_EfuseWordEnableDataWrite; 2221 pHalFunc->Efuse_PgPacketWrite_BT = &Hal_EfusePgPacketWrite_BT; 2222 2223 pHalFunc->GetHalODMVarHandler = &rtl8723b_GetHalODMVar; 2224 pHalFunc->SetHalODMVarHandler = &rtl8723b_SetHalODMVar; 2225 2226 pHalFunc->xmit_thread_handler = &hal_xmit_handler; 2227 pHalFunc->hal_notch_filter = &hal_notch_filter_8723b; 2228 2229 pHalFunc->c2h_handler = c2h_handler_8723b; 2230 pHalFunc->c2h_id_filter_ccx = c2h_id_filter_ccx_8723b; 2231 2232 pHalFunc->fill_h2c_cmd = &FillH2CCmd8723B; 2233 } 2234 2235 void rtl8723b_InitAntenna_Selection(struct adapter *padapter) 2236 { 2237 u8 val; 2238 2239 val = rtw_read8(padapter, REG_LEDCFG2); 2240 /* Let 8051 take control antenna setting */ 2241 val |= BIT(7); /* DPDT_SEL_EN, 0x4C[23] */ 2242 rtw_write8(padapter, REG_LEDCFG2, val); 2243 } 2244 2245 void rtl8723b_init_default_value(struct adapter *padapter) 2246 { 2247 struct hal_com_data *pHalData; 2248 struct dm_priv *pdmpriv; 2249 u8 i; 2250 2251 2252 pHalData = GET_HAL_DATA(padapter); 2253 pdmpriv = &pHalData->dmpriv; 2254 2255 padapter->registrypriv.wireless_mode = WIRELESS_11BG_24N; 2256 2257 /* init default value */ 2258 pHalData->fw_ractrl = false; 2259 pHalData->bIQKInitialized = false; 2260 if (!adapter_to_pwrctl(padapter)->bkeepfwalive) 2261 pHalData->LastHMEBoxNum = 0; 2262 2263 pHalData->bIQKInitialized = false; 2264 2265 /* init dm default value */ 2266 pdmpriv->TM_Trigger = 0;/* for IQK */ 2267 /* pdmpriv->binitialized = false; */ 2268 /* pdmpriv->prv_traffic_idx = 3; */ 2269 /* pdmpriv->initialize = 0; */ 2270 2271 pdmpriv->ThermalValue_HP_index = 0; 2272 for (i = 0; i < HP_THERMAL_NUM; i++) 2273 pdmpriv->ThermalValue_HP[i] = 0; 2274 2275 /* init Efuse variables */ 2276 pHalData->EfuseUsedBytes = 0; 2277 pHalData->EfuseUsedPercentage = 0; 2278 #ifdef HAL_EFUSE_MEMORY 2279 pHalData->EfuseHal.fakeEfuseBank = 0; 2280 pHalData->EfuseHal.fakeEfuseUsedBytes = 0; 2281 memset(pHalData->EfuseHal.fakeEfuseContent, 0xFF, EFUSE_MAX_HW_SIZE); 2282 memset(pHalData->EfuseHal.fakeEfuseInitMap, 0xFF, EFUSE_MAX_MAP_LEN); 2283 memset(pHalData->EfuseHal.fakeEfuseModifiedMap, 0xFF, EFUSE_MAX_MAP_LEN); 2284 pHalData->EfuseHal.BTEfuseUsedBytes = 0; 2285 pHalData->EfuseHal.BTEfuseUsedPercentage = 0; 2286 memset(pHalData->EfuseHal.BTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE); 2287 memset(pHalData->EfuseHal.BTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2288 memset(pHalData->EfuseHal.BTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2289 pHalData->EfuseHal.fakeBTEfuseUsedBytes = 0; 2290 memset(pHalData->EfuseHal.fakeBTEfuseContent, 0xFF, EFUSE_MAX_BT_BANK*EFUSE_MAX_HW_SIZE); 2291 memset(pHalData->EfuseHal.fakeBTEfuseInitMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2292 memset(pHalData->EfuseHal.fakeBTEfuseModifiedMap, 0xFF, EFUSE_BT_MAX_MAP_LEN); 2293 #endif 2294 } 2295 2296 u8 GetEEPROMSize8723B(struct adapter *padapter) 2297 { 2298 u8 size = 0; 2299 u32 cr; 2300 2301 cr = rtw_read16(padapter, REG_9346CR); 2302 /* 6: EEPROM used is 93C46, 4: boot from E-Fuse. */ 2303 size = (cr & BOOT_FROM_EEPROM) ? 6 : 4; 2304 2305 MSG_8192C("EEPROM type is %s\n", size == 4 ? "E-FUSE" : "93C46"); 2306 2307 return size; 2308 } 2309 2310 /* */ 2311 /* */ 2312 /* LLT R/W/Init function */ 2313 /* */ 2314 /* */ 2315 s32 rtl8723b_InitLLTTable(struct adapter *padapter) 2316 { 2317 unsigned long start, passing_time; 2318 u32 val32; 2319 s32 ret; 2320 2321 2322 ret = _FAIL; 2323 2324 val32 = rtw_read32(padapter, REG_AUTO_LLT); 2325 val32 |= BIT_AUTO_INIT_LLT; 2326 rtw_write32(padapter, REG_AUTO_LLT, val32); 2327 2328 start = jiffies; 2329 2330 do { 2331 val32 = rtw_read32(padapter, REG_AUTO_LLT); 2332 if (!(val32 & BIT_AUTO_INIT_LLT)) { 2333 ret = _SUCCESS; 2334 break; 2335 } 2336 2337 passing_time = jiffies_to_msecs(jiffies - start); 2338 if (passing_time > 1000) { 2339 DBG_8192C( 2340 "%s: FAIL!! REG_AUTO_LLT(0x%X) =%08x\n", 2341 __func__, 2342 REG_AUTO_LLT, 2343 val32 2344 ); 2345 break; 2346 } 2347 2348 msleep(1); 2349 } while (1); 2350 2351 return ret; 2352 } 2353 2354 static bool Hal_GetChnlGroup8723B(u8 Channel, u8 *pGroup) 2355 { 2356 bool bIn24G = true; 2357 2358 if (Channel <= 14) { 2359 bIn24G = true; 2360 2361 if (1 <= Channel && Channel <= 2) 2362 *pGroup = 0; 2363 else if (3 <= Channel && Channel <= 5) 2364 *pGroup = 1; 2365 else if (6 <= Channel && Channel <= 8) 2366 *pGroup = 2; 2367 else if (9 <= Channel && Channel <= 11) 2368 *pGroup = 3; 2369 else if (12 <= Channel && Channel <= 14) 2370 *pGroup = 4; 2371 else { 2372 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 2.4 G, but Channel %d in Group not found\n", Channel)); 2373 } 2374 } else { 2375 bIn24G = false; 2376 2377 if (36 <= Channel && Channel <= 42) 2378 *pGroup = 0; 2379 else if (44 <= Channel && Channel <= 48) 2380 *pGroup = 1; 2381 else if (50 <= Channel && Channel <= 58) 2382 *pGroup = 2; 2383 else if (60 <= Channel && Channel <= 64) 2384 *pGroup = 3; 2385 else if (100 <= Channel && Channel <= 106) 2386 *pGroup = 4; 2387 else if (108 <= Channel && Channel <= 114) 2388 *pGroup = 5; 2389 else if (116 <= Channel && Channel <= 122) 2390 *pGroup = 6; 2391 else if (124 <= Channel && Channel <= 130) 2392 *pGroup = 7; 2393 else if (132 <= Channel && Channel <= 138) 2394 *pGroup = 8; 2395 else if (140 <= Channel && Channel <= 144) 2396 *pGroup = 9; 2397 else if (149 <= Channel && Channel <= 155) 2398 *pGroup = 10; 2399 else if (157 <= Channel && Channel <= 161) 2400 *pGroup = 11; 2401 else if (165 <= Channel && Channel <= 171) 2402 *pGroup = 12; 2403 else if (173 <= Channel && Channel <= 177) 2404 *pGroup = 13; 2405 else { 2406 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("==>Hal_GetChnlGroup8723B in 5G, but Channel %d in Group not found\n", Channel)); 2407 } 2408 2409 } 2410 RT_TRACE( 2411 _module_hci_hal_init_c_, 2412 _drv_info_, 2413 ( 2414 "<==Hal_GetChnlGroup8723B, (%s) Channel = %d, Group =%d,\n", 2415 bIn24G ? "2.4G" : "5G", 2416 Channel, 2417 *pGroup 2418 ) 2419 ); 2420 return bIn24G; 2421 } 2422 2423 void Hal_InitPGData(struct adapter *padapter, u8 *PROMContent) 2424 { 2425 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2426 2427 if (!pEEPROM->bautoload_fail_flag) { /* autoload OK. */ 2428 if (!pEEPROM->EepromOrEfuse) { 2429 /* Read EFUSE real map to shadow. */ 2430 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); 2431 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B); 2432 } 2433 } else {/* autoload fail */ 2434 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("AutoLoad Fail reported from CR9346!!\n")); 2435 if (!pEEPROM->EepromOrEfuse) 2436 EFUSE_ShadowMapUpdate(padapter, EFUSE_WIFI, false); 2437 memcpy((void *)PROMContent, (void *)pEEPROM->efuse_eeprom_data, HWSET_MAX_SIZE_8723B); 2438 } 2439 } 2440 2441 void Hal_EfuseParseIDCode(struct adapter *padapter, u8 *hwinfo) 2442 { 2443 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2444 /* struct hal_com_data *pHalData = GET_HAL_DATA(padapter); */ 2445 u16 EEPROMId; 2446 2447 2448 /* Checl 0x8129 again for making sure autoload status!! */ 2449 EEPROMId = le16_to_cpu(*((__le16 *)hwinfo)); 2450 if (EEPROMId != RTL_EEPROM_ID) { 2451 DBG_8192C("EEPROM ID(%#x) is invalid!!\n", EEPROMId); 2452 pEEPROM->bautoload_fail_flag = true; 2453 } else 2454 pEEPROM->bautoload_fail_flag = false; 2455 2456 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("EEPROM ID = 0x%04x\n", EEPROMId)); 2457 } 2458 2459 static void Hal_ReadPowerValueFromPROM_8723B( 2460 struct adapter *Adapter, 2461 struct TxPowerInfo24G *pwrInfo24G, 2462 u8 *PROMContent, 2463 bool AutoLoadFail 2464 ) 2465 { 2466 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2467 u32 rfPath, eeAddr = EEPROM_TX_PWR_INX_8723B, group, TxCount = 0; 2468 2469 memset(pwrInfo24G, 0, sizeof(struct TxPowerInfo24G)); 2470 2471 if (0xFF == PROMContent[eeAddr+1]) 2472 AutoLoadFail = true; 2473 2474 if (AutoLoadFail) { 2475 DBG_871X("%s(): Use Default value!\n", __func__); 2476 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { 2477 /* 2.4G default value */ 2478 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 2479 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2480 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2481 } 2482 2483 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2484 if (TxCount == 0) { 2485 pwrInfo24G->BW20_Diff[rfPath][0] = EEPROM_DEFAULT_24G_HT20_DIFF; 2486 pwrInfo24G->OFDM_Diff[rfPath][0] = EEPROM_DEFAULT_24G_OFDM_DIFF; 2487 } else { 2488 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2489 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2490 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2491 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2492 } 2493 } 2494 } 2495 2496 return; 2497 } 2498 2499 pHalData->bTXPowerDataReadFromEEPORM = true; /* YJ, move, 120316 */ 2500 2501 for (rfPath = 0; rfPath < MAX_RF_PATH; rfPath++) { 2502 /* 2 2.4G default value */ 2503 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) { 2504 pwrInfo24G->IndexCCK_Base[rfPath][group] = PROMContent[eeAddr++]; 2505 if (pwrInfo24G->IndexCCK_Base[rfPath][group] == 0xFF) 2506 pwrInfo24G->IndexCCK_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2507 } 2508 2509 for (group = 0; group < MAX_CHNL_GROUP_24G-1; group++) { 2510 pwrInfo24G->IndexBW40_Base[rfPath][group] = PROMContent[eeAddr++]; 2511 if (pwrInfo24G->IndexBW40_Base[rfPath][group] == 0xFF) 2512 pwrInfo24G->IndexBW40_Base[rfPath][group] = EEPROM_DEFAULT_24G_INDEX; 2513 } 2514 2515 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2516 if (TxCount == 0) { 2517 pwrInfo24G->BW40_Diff[rfPath][TxCount] = 0; 2518 if (PROMContent[eeAddr] == 0xFF) 2519 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF; 2520 else { 2521 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2522 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2523 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; 2524 } 2525 2526 if (PROMContent[eeAddr] == 0xFF) 2527 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF; 2528 else { 2529 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2530 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2531 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; 2532 } 2533 pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0; 2534 eeAddr++; 2535 } else { 2536 if (PROMContent[eeAddr] == 0xFF) 2537 pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2538 else { 2539 pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2540 if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2541 pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0; 2542 } 2543 2544 if (PROMContent[eeAddr] == 0xFF) 2545 pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2546 else { 2547 pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2548 if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2549 pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0; 2550 } 2551 eeAddr++; 2552 2553 if (PROMContent[eeAddr] == 0xFF) 2554 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2555 else { 2556 pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4; 2557 if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2558 pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0; 2559 } 2560 2561 if (PROMContent[eeAddr] == 0xFF) 2562 pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF; 2563 else { 2564 pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f); 2565 if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */ 2566 pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0; 2567 } 2568 eeAddr++; 2569 } 2570 } 2571 } 2572 } 2573 2574 2575 void Hal_EfuseParseTxPowerInfo_8723B( 2576 struct adapter *padapter, u8 *PROMContent, bool AutoLoadFail 2577 ) 2578 { 2579 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2580 struct TxPowerInfo24G pwrInfo24G; 2581 u8 rfPath, ch, TxCount = 1; 2582 2583 Hal_ReadPowerValueFromPROM_8723B(padapter, &pwrInfo24G, PROMContent, AutoLoadFail); 2584 for (rfPath = 0 ; rfPath < MAX_RF_PATH ; rfPath++) { 2585 for (ch = 0 ; ch < CHANNEL_MAX_NUMBER; ch++) { 2586 u8 group = 0; 2587 2588 Hal_GetChnlGroup8723B(ch+1, &group); 2589 2590 if (ch == 14-1) { 2591 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][5]; 2592 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; 2593 } else { 2594 pHalData->Index24G_CCK_Base[rfPath][ch] = pwrInfo24G.IndexCCK_Base[rfPath][group]; 2595 pHalData->Index24G_BW40_Base[rfPath][ch] = pwrInfo24G.IndexBW40_Base[rfPath][group]; 2596 } 2597 #ifdef DEBUG 2598 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("======= Path %d, ChannelIndex %d, Group %d =======\n", rfPath, ch, group)); 2599 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_CCK_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_CCK_Base[rfPath][ch])); 2600 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Index24G_BW40_Base[%d][%d] = 0x%x\n", rfPath, ch, pHalData->Index24G_BW40_Base[rfPath][ch])); 2601 #endif 2602 } 2603 2604 for (TxCount = 0; TxCount < MAX_TX_COUNT; TxCount++) { 2605 pHalData->CCK_24G_Diff[rfPath][TxCount] = pwrInfo24G.CCK_Diff[rfPath][TxCount]; 2606 pHalData->OFDM_24G_Diff[rfPath][TxCount] = pwrInfo24G.OFDM_Diff[rfPath][TxCount]; 2607 pHalData->BW20_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW20_Diff[rfPath][TxCount]; 2608 pHalData->BW40_24G_Diff[rfPath][TxCount] = pwrInfo24G.BW40_Diff[rfPath][TxCount]; 2609 2610 #ifdef DEBUG 2611 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("--------------------------------------- 2.4G ---------------------------------------\n")); 2612 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("CCK_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->CCK_24G_Diff[rfPath][TxCount])); 2613 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("OFDM_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->OFDM_24G_Diff[rfPath][TxCount])); 2614 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW20_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW20_24G_Diff[rfPath][TxCount])); 2615 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("BW40_24G_Diff[%d][%d]= %d\n", rfPath, TxCount, pHalData->BW40_24G_Diff[rfPath][TxCount])); 2616 #endif 2617 } 2618 } 2619 2620 /* 2010/10/19 MH Add Regulator recognize for CU. */ 2621 if (!AutoLoadFail) { 2622 pHalData->EEPROMRegulatory = (PROMContent[EEPROM_RF_BOARD_OPTION_8723B]&0x7); /* bit0~2 */ 2623 if (PROMContent[EEPROM_RF_BOARD_OPTION_8723B] == 0xFF) 2624 pHalData->EEPROMRegulatory = (EEPROM_DEFAULT_BOARD_OPTION&0x7); /* bit0~2 */ 2625 } else 2626 pHalData->EEPROMRegulatory = 0; 2627 2628 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROMRegulatory = 0x%x\n", pHalData->EEPROMRegulatory)); 2629 } 2630 2631 void Hal_EfuseParseBTCoexistInfo_8723B( 2632 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2633 ) 2634 { 2635 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2636 u8 tempval; 2637 u32 tmpu4; 2638 2639 if (!AutoLoadFail) { 2640 tmpu4 = rtw_read32(padapter, REG_MULTI_FUNC_CTRL); 2641 if (tmpu4 & BT_FUNC_EN) 2642 pHalData->EEPROMBluetoothCoexist = true; 2643 else 2644 pHalData->EEPROMBluetoothCoexist = false; 2645 2646 pHalData->EEPROMBluetoothType = BT_RTL8723B; 2647 2648 tempval = hwinfo[EEPROM_RF_BT_SETTING_8723B]; 2649 if (tempval != 0xFF) { 2650 pHalData->EEPROMBluetoothAntNum = tempval & BIT(0); 2651 /* EFUSE_0xC3[6] == 0, S1(Main)-ODM_RF_PATH_A; */ 2652 /* EFUSE_0xC3[6] == 1, S0(Aux)-ODM_RF_PATH_B */ 2653 pHalData->ant_path = (tempval & BIT(6))?ODM_RF_PATH_B:ODM_RF_PATH_A; 2654 } else { 2655 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2656 if (pHalData->PackageType == PACKAGE_QFN68) 2657 pHalData->ant_path = ODM_RF_PATH_B; 2658 else 2659 pHalData->ant_path = ODM_RF_PATH_A; 2660 } 2661 } else { 2662 pHalData->EEPROMBluetoothCoexist = false; 2663 pHalData->EEPROMBluetoothType = BT_RTL8723B; 2664 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2665 pHalData->ant_path = ODM_RF_PATH_A; 2666 } 2667 2668 if (padapter->registrypriv.ant_num > 0) { 2669 DBG_8192C( 2670 "%s: Apply driver defined antenna number(%d) to replace origin(%d)\n", 2671 __func__, 2672 padapter->registrypriv.ant_num, 2673 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1 2674 ); 2675 2676 switch (padapter->registrypriv.ant_num) { 2677 case 1: 2678 pHalData->EEPROMBluetoothAntNum = Ant_x1; 2679 break; 2680 case 2: 2681 pHalData->EEPROMBluetoothAntNum = Ant_x2; 2682 break; 2683 default: 2684 DBG_8192C( 2685 "%s: Discard invalid driver defined antenna number(%d)!\n", 2686 __func__, 2687 padapter->registrypriv.ant_num 2688 ); 2689 break; 2690 } 2691 } 2692 2693 hal_btcoex_SetBTCoexist(padapter, pHalData->EEPROMBluetoothCoexist); 2694 hal_btcoex_SetChipType(padapter, pHalData->EEPROMBluetoothType); 2695 hal_btcoex_SetPgAntNum(padapter, pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1); 2696 if (pHalData->EEPROMBluetoothAntNum == Ant_x1) 2697 hal_btcoex_SetSingleAntPath(padapter, pHalData->ant_path); 2698 2699 DBG_8192C( 2700 "%s: %s BT-coex, ant_num =%d\n", 2701 __func__, 2702 pHalData->EEPROMBluetoothCoexist == true ? "Enable" : "Disable", 2703 pHalData->EEPROMBluetoothAntNum == Ant_x2 ? 2 : 1 2704 ); 2705 } 2706 2707 void Hal_EfuseParseEEPROMVer_8723B( 2708 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2709 ) 2710 { 2711 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2712 2713 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2714 if (!AutoLoadFail) 2715 pHalData->EEPROMVersion = hwinfo[EEPROM_VERSION_8723B]; 2716 else 2717 pHalData->EEPROMVersion = 1; 2718 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("Hal_EfuseParseEEPROMVer(), EEVer = %d\n", 2719 pHalData->EEPROMVersion)); 2720 } 2721 2722 2723 2724 void Hal_EfuseParsePackageType_8723B( 2725 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2726 ) 2727 { 2728 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2729 u8 package; 2730 u8 efuseContent; 2731 2732 Efuse_PowerSwitch(padapter, false, true); 2733 efuse_OneByteRead(padapter, 0x1FB, &efuseContent, false); 2734 DBG_871X("%s phy efuse read 0x1FB =%x\n", __func__, efuseContent); 2735 Efuse_PowerSwitch(padapter, false, false); 2736 2737 package = efuseContent & 0x7; 2738 switch (package) { 2739 case 0x4: 2740 pHalData->PackageType = PACKAGE_TFBGA79; 2741 break; 2742 case 0x5: 2743 pHalData->PackageType = PACKAGE_TFBGA90; 2744 break; 2745 case 0x6: 2746 pHalData->PackageType = PACKAGE_QFN68; 2747 break; 2748 case 0x7: 2749 pHalData->PackageType = PACKAGE_TFBGA80; 2750 break; 2751 2752 default: 2753 pHalData->PackageType = PACKAGE_DEFAULT; 2754 break; 2755 } 2756 2757 DBG_871X("PackageType = 0x%X\n", pHalData->PackageType); 2758 } 2759 2760 2761 void Hal_EfuseParseVoltage_8723B( 2762 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2763 ) 2764 { 2765 struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 2766 2767 /* memcpy(pEEPROM->adjuseVoltageVal, &hwinfo[EEPROM_Voltage_ADDR_8723B], 1); */ 2768 DBG_871X("%s hwinfo[EEPROM_Voltage_ADDR_8723B] =%02x\n", __func__, hwinfo[EEPROM_Voltage_ADDR_8723B]); 2769 pEEPROM->adjuseVoltageVal = (hwinfo[EEPROM_Voltage_ADDR_8723B] & 0xf0) >> 4; 2770 DBG_871X("%s pEEPROM->adjuseVoltageVal =%x\n", __func__, pEEPROM->adjuseVoltageVal); 2771 } 2772 2773 void Hal_EfuseParseChnlPlan_8723B( 2774 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2775 ) 2776 { 2777 padapter->mlmepriv.ChannelPlan = hal_com_config_channel_plan( 2778 padapter, 2779 hwinfo ? hwinfo[EEPROM_ChannelPlan_8723B] : 0xFF, 2780 padapter->registrypriv.channel_plan, 2781 RT_CHANNEL_DOMAIN_WORLD_NULL, 2782 AutoLoadFail 2783 ); 2784 2785 Hal_ChannelPlanToRegulation(padapter, padapter->mlmepriv.ChannelPlan); 2786 2787 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ChannelPlan = 0x%02x\n", padapter->mlmepriv.ChannelPlan)); 2788 } 2789 2790 void Hal_EfuseParseCustomerID_8723B( 2791 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2792 ) 2793 { 2794 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2795 2796 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2797 if (!AutoLoadFail) 2798 pHalData->EEPROMCustomerID = hwinfo[EEPROM_CustomID_8723B]; 2799 else 2800 pHalData->EEPROMCustomerID = 0; 2801 2802 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM Customer ID: 0x%2x\n", pHalData->EEPROMCustomerID)); 2803 } 2804 2805 void Hal_EfuseParseAntennaDiversity_8723B( 2806 struct adapter *padapter, 2807 u8 *hwinfo, 2808 bool AutoLoadFail 2809 ) 2810 { 2811 } 2812 2813 void Hal_EfuseParseXtal_8723B( 2814 struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail 2815 ) 2816 { 2817 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2818 2819 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2820 if (!AutoLoadFail) { 2821 pHalData->CrystalCap = hwinfo[EEPROM_XTAL_8723B]; 2822 if (pHalData->CrystalCap == 0xFF) 2823 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; /* what value should 8812 set? */ 2824 } else 2825 pHalData->CrystalCap = EEPROM_Default_CrystalCap_8723B; 2826 2827 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM CrystalCap: 0x%2x\n", pHalData->CrystalCap)); 2828 } 2829 2830 2831 void Hal_EfuseParseThermalMeter_8723B( 2832 struct adapter *padapter, u8 *PROMContent, u8 AutoLoadFail 2833 ) 2834 { 2835 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 2836 2837 /* RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("%s(): AutoLoadFail = %d\n", __func__, AutoLoadFail)); */ 2838 /* */ 2839 /* ThermalMeter from EEPROM */ 2840 /* */ 2841 if (!AutoLoadFail) 2842 pHalData->EEPROMThermalMeter = PROMContent[EEPROM_THERMAL_METER_8723B]; 2843 else 2844 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B; 2845 2846 if ((pHalData->EEPROMThermalMeter == 0xff) || AutoLoadFail) { 2847 pHalData->bAPKThermalMeterIgnore = true; 2848 pHalData->EEPROMThermalMeter = EEPROM_Default_ThermalMeter_8723B; 2849 } 2850 2851 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("EEPROM ThermalMeter = 0x%x\n", pHalData->EEPROMThermalMeter)); 2852 } 2853 2854 2855 void Hal_ReadRFGainOffset( 2856 struct adapter *Adapter, u8 *PROMContent, bool AutoloadFail 2857 ) 2858 { 2859 /* */ 2860 /* BB_RF Gain Offset from EEPROM */ 2861 /* */ 2862 2863 if (!AutoloadFail) { 2864 Adapter->eeprompriv.EEPROMRFGainOffset = PROMContent[EEPROM_RF_GAIN_OFFSET]; 2865 DBG_871X("AutoloadFail =%x,\n", AutoloadFail); 2866 Adapter->eeprompriv.EEPROMRFGainVal = EFUSE_Read1Byte(Adapter, EEPROM_RF_GAIN_VAL); 2867 DBG_871X("Adapter->eeprompriv.EEPROMRFGainVal =%x\n", Adapter->eeprompriv.EEPROMRFGainVal); 2868 } else { 2869 Adapter->eeprompriv.EEPROMRFGainOffset = 0; 2870 Adapter->eeprompriv.EEPROMRFGainVal = 0xFF; 2871 DBG_871X("else AutoloadFail =%x,\n", AutoloadFail); 2872 } 2873 DBG_871X("EEPRORFGainOffset = 0x%02x\n", Adapter->eeprompriv.EEPROMRFGainOffset); 2874 } 2875 2876 u8 BWMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib) 2877 { 2878 u8 BWSettingOfDesc = 0; 2879 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2880 2881 /* DBG_871X("BWMapping pHalData->CurrentChannelBW %d, pattrib->bwmode %d\n", pHalData->CurrentChannelBW, pattrib->bwmode); */ 2882 2883 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { 2884 if (pattrib->bwmode == CHANNEL_WIDTH_80) 2885 BWSettingOfDesc = 2; 2886 else if (pattrib->bwmode == CHANNEL_WIDTH_40) 2887 BWSettingOfDesc = 1; 2888 else 2889 BWSettingOfDesc = 0; 2890 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { 2891 if ((pattrib->bwmode == CHANNEL_WIDTH_40) || (pattrib->bwmode == CHANNEL_WIDTH_80)) 2892 BWSettingOfDesc = 1; 2893 else 2894 BWSettingOfDesc = 0; 2895 } else 2896 BWSettingOfDesc = 0; 2897 2898 /* if (pTcb->bBTTxPacket) */ 2899 /* BWSettingOfDesc = 0; */ 2900 2901 return BWSettingOfDesc; 2902 } 2903 2904 u8 SCMapping_8723B(struct adapter *Adapter, struct pkt_attrib *pattrib) 2905 { 2906 u8 SCSettingOfDesc = 0; 2907 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 2908 2909 /* DBG_871X("SCMapping: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur80MhzPrimeSC, pHalData->nCur40MhzPrimeSC); */ 2910 2911 if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) { 2912 if (pattrib->bwmode == CHANNEL_WIDTH_80) { 2913 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2914 } else if (pattrib->bwmode == CHANNEL_WIDTH_40) { 2915 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) 2916 SCSettingOfDesc = VHT_DATA_SC_40_LOWER_OF_80MHZ; 2917 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) 2918 SCSettingOfDesc = VHT_DATA_SC_40_UPPER_OF_80MHZ; 2919 else 2920 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n"); 2921 } else { 2922 if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) 2923 SCSettingOfDesc = VHT_DATA_SC_20_LOWEST_OF_80MHZ; 2924 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)) 2925 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; 2926 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) 2927 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; 2928 else if ((pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) && (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)) 2929 SCSettingOfDesc = VHT_DATA_SC_20_UPPERST_OF_80MHZ; 2930 else 2931 DBG_871X("SCMapping: Not Correct Primary40MHz Setting\n"); 2932 } 2933 } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) { 2934 /* DBG_871X("SCMapping: HT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n", pHalData->CurrentChannelBW, pHalData->nCur40MhzPrimeSC); */ 2935 2936 if (pattrib->bwmode == CHANNEL_WIDTH_40) { 2937 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2938 } else if (pattrib->bwmode == CHANNEL_WIDTH_20) { 2939 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) { 2940 SCSettingOfDesc = VHT_DATA_SC_20_UPPER_OF_80MHZ; 2941 } else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) { 2942 SCSettingOfDesc = VHT_DATA_SC_20_LOWER_OF_80MHZ; 2943 } else { 2944 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2945 } 2946 } 2947 } else { 2948 SCSettingOfDesc = VHT_DATA_SC_DONOT_CARE; 2949 } 2950 2951 return SCSettingOfDesc; 2952 } 2953 2954 static void rtl8723b_cal_txdesc_chksum(struct tx_desc *ptxdesc) 2955 { 2956 u16 *usPtr = (u16 *)ptxdesc; 2957 u32 count; 2958 u32 index; 2959 u16 checksum = 0; 2960 2961 2962 /* Clear first */ 2963 ptxdesc->txdw7 &= cpu_to_le32(0xffff0000); 2964 2965 /* checksume is always calculated by first 32 bytes, */ 2966 /* and it doesn't depend on TX DESC length. */ 2967 /* Thomas, Lucas@SD4, 20130515 */ 2968 count = 16; 2969 2970 for (index = 0; index < count; index++) { 2971 checksum |= le16_to_cpu(*(__le16 *)(usPtr + index)); 2972 } 2973 2974 ptxdesc->txdw7 |= cpu_to_le32(checksum & 0x0000ffff); 2975 } 2976 2977 static u8 fill_txdesc_sectype(struct pkt_attrib *pattrib) 2978 { 2979 u8 sectype = 0; 2980 if ((pattrib->encrypt > 0) && !pattrib->bswenc) { 2981 switch (pattrib->encrypt) { 2982 /* SEC_TYPE */ 2983 case _WEP40_: 2984 case _WEP104_: 2985 case _TKIP_: 2986 case _TKIP_WTMIC_: 2987 sectype = 1; 2988 break; 2989 2990 case _AES_: 2991 sectype = 3; 2992 break; 2993 2994 case _NO_PRIVACY_: 2995 default: 2996 break; 2997 } 2998 } 2999 return sectype; 3000 } 3001 3002 static void fill_txdesc_vcs_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc) 3003 { 3004 /* DBG_8192C("cvs_mode =%d\n", pattrib->vcs_mode); */ 3005 3006 if (pattrib->vcs_mode) { 3007 switch (pattrib->vcs_mode) { 3008 case RTS_CTS: 3009 ptxdesc->rtsen = 1; 3010 /* ENABLE HW RTS */ 3011 ptxdesc->hw_rts_en = 1; 3012 break; 3013 3014 case CTS_TO_SELF: 3015 ptxdesc->cts2self = 1; 3016 break; 3017 3018 case NONE_VCS: 3019 default: 3020 break; 3021 } 3022 3023 ptxdesc->rtsrate = 8; /* RTS Rate =24M */ 3024 ptxdesc->rts_ratefb_lmt = 0xF; 3025 3026 if (padapter->mlmeextpriv.mlmext_info.preamble_mode == PREAMBLE_SHORT) 3027 ptxdesc->rts_short = 1; 3028 3029 /* Set RTS BW */ 3030 if (pattrib->ht_en) 3031 ptxdesc->rts_sc = SCMapping_8723B(padapter, pattrib); 3032 } 3033 } 3034 3035 static void fill_txdesc_phy_8723b(struct adapter *padapter, struct pkt_attrib *pattrib, PTXDESC_8723B ptxdesc) 3036 { 3037 /* DBG_8192C("bwmode =%d, ch_off =%d\n", pattrib->bwmode, pattrib->ch_offset); */ 3038 3039 if (pattrib->ht_en) { 3040 ptxdesc->data_bw = BWMapping_8723B(padapter, pattrib); 3041 3042 ptxdesc->data_sc = SCMapping_8723B(padapter, pattrib); 3043 } 3044 } 3045 3046 static void rtl8723b_fill_default_txdesc( 3047 struct xmit_frame *pxmitframe, u8 *pbuf 3048 ) 3049 { 3050 struct adapter *padapter; 3051 struct hal_com_data *pHalData; 3052 struct mlme_ext_priv *pmlmeext; 3053 struct mlme_ext_info *pmlmeinfo; 3054 struct pkt_attrib *pattrib; 3055 PTXDESC_8723B ptxdesc; 3056 s32 bmcst; 3057 3058 memset(pbuf, 0, TXDESC_SIZE); 3059 3060 padapter = pxmitframe->padapter; 3061 pHalData = GET_HAL_DATA(padapter); 3062 pmlmeext = &padapter->mlmeextpriv; 3063 pmlmeinfo = &(pmlmeext->mlmext_info); 3064 3065 pattrib = &pxmitframe->attrib; 3066 bmcst = IS_MCAST(pattrib->ra); 3067 3068 ptxdesc = (PTXDESC_8723B)pbuf; 3069 3070 if (pxmitframe->frame_tag == DATA_FRAMETAG) { 3071 u8 drv_userate = 0; 3072 3073 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3074 ptxdesc->rate_id = pattrib->raid; 3075 ptxdesc->qsel = pattrib->qsel; 3076 ptxdesc->seq = pattrib->seqnum; 3077 3078 ptxdesc->sectype = fill_txdesc_sectype(pattrib); 3079 fill_txdesc_vcs_8723b(padapter, pattrib, ptxdesc); 3080 3081 if (pattrib->icmp_pkt == 1 && padapter->registrypriv.wifi_spec == 1) 3082 drv_userate = 1; 3083 3084 if ( 3085 (pattrib->ether_type != 0x888e) && 3086 (pattrib->ether_type != 0x0806) && 3087 (pattrib->ether_type != 0x88B4) && 3088 (pattrib->dhcp_pkt != 1) && 3089 (drv_userate != 1) 3090 #ifdef CONFIG_AUTO_AP_MODE 3091 && (!pattrib->pctrl) 3092 #endif 3093 ) { 3094 /* Non EAP & ARP & DHCP type data packet */ 3095 3096 if (pattrib->ampdu_en) { 3097 ptxdesc->agg_en = 1; /* AGG EN */ 3098 ptxdesc->max_agg_num = 0x1f; 3099 ptxdesc->ampdu_density = pattrib->ampdu_spacing; 3100 } else 3101 ptxdesc->bk = 1; /* AGG BK */ 3102 3103 fill_txdesc_phy_8723b(padapter, pattrib, ptxdesc); 3104 3105 ptxdesc->data_ratefb_lmt = 0x1F; 3106 3107 if (!pHalData->fw_ractrl) { 3108 ptxdesc->userate = 1; 3109 3110 if (pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & BIT(7)) 3111 ptxdesc->data_short = 1; 3112 3113 ptxdesc->datarate = pHalData->dmpriv.INIDATA_RATE[pattrib->mac_id] & 0x7F; 3114 } 3115 3116 if (padapter->fix_rate != 0xFF) { /* modify data rate by iwpriv */ 3117 ptxdesc->userate = 1; 3118 if (padapter->fix_rate & BIT(7)) 3119 ptxdesc->data_short = 1; 3120 3121 ptxdesc->datarate = (padapter->fix_rate & 0x7F); 3122 ptxdesc->disdatafb = 1; 3123 } 3124 3125 if (pattrib->ldpc) 3126 ptxdesc->data_ldpc = 1; 3127 if (pattrib->stbc) 3128 ptxdesc->data_stbc = 1; 3129 3130 #ifdef CONFIG_CMCC_TEST 3131 ptxdesc->data_short = 1; /* use cck short premble */ 3132 #endif 3133 } else { 3134 /* EAP data packet and ARP packet. */ 3135 /* Use the 1M data rate to send the EAP/ARP packet. */ 3136 /* This will maybe make the handshake smooth. */ 3137 3138 ptxdesc->bk = 1; /* AGG BK */ 3139 ptxdesc->userate = 1; /* driver uses rate */ 3140 if (pmlmeinfo->preamble_mode == PREAMBLE_SHORT) 3141 ptxdesc->data_short = 1;/* DATA_SHORT */ 3142 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3143 DBG_871X("YJ: %s(): ARP Data: userate =%d, datarate = 0x%x\n", __func__, ptxdesc->userate, ptxdesc->datarate); 3144 } 3145 3146 ptxdesc->usb_txagg_num = pxmitframe->agg_num; 3147 } else if (pxmitframe->frame_tag == MGNT_FRAMETAG) { 3148 /* RT_TRACE(_module_hal_xmit_c_, _drv_notice_, ("%s: MGNT_FRAMETAG\n", __func__)); */ 3149 3150 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3151 ptxdesc->qsel = pattrib->qsel; 3152 ptxdesc->rate_id = pattrib->raid; /* Rate ID */ 3153 ptxdesc->seq = pattrib->seqnum; 3154 ptxdesc->userate = 1; /* driver uses rate, 1M */ 3155 3156 ptxdesc->mbssid = pattrib->mbssid & 0xF; 3157 3158 ptxdesc->rty_lmt_en = 1; /* retry limit enable */ 3159 if (pattrib->retry_ctrl) { 3160 ptxdesc->data_rt_lmt = 6; 3161 } else { 3162 ptxdesc->data_rt_lmt = 12; 3163 } 3164 3165 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3166 3167 /* CCX-TXRPT ack for xmit mgmt frames. */ 3168 if (pxmitframe->ack_report) { 3169 #ifdef DBG_CCX 3170 DBG_8192C("%s set spe_rpt\n", __func__); 3171 #endif 3172 ptxdesc->spe_rpt = 1; 3173 ptxdesc->sw_define = (u8)(GET_PRIMARY_ADAPTER(padapter)->xmitpriv.seq_no); 3174 } 3175 } else if (pxmitframe->frame_tag == TXAGG_FRAMETAG) { 3176 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: TXAGG_FRAMETAG\n", __func__)); 3177 } else { 3178 RT_TRACE(_module_hal_xmit_c_, _drv_warning_, ("%s: frame_tag = 0x%x\n", __func__, pxmitframe->frame_tag)); 3179 3180 ptxdesc->macid = pattrib->mac_id; /* CAM_ID(MAC_ID) */ 3181 ptxdesc->rate_id = pattrib->raid; /* Rate ID */ 3182 ptxdesc->qsel = pattrib->qsel; 3183 ptxdesc->seq = pattrib->seqnum; 3184 ptxdesc->userate = 1; /* driver uses rate */ 3185 ptxdesc->datarate = MRateToHwRate(pmlmeext->tx_rate); 3186 } 3187 3188 ptxdesc->pktlen = pattrib->last_txcmdsz; 3189 ptxdesc->offset = TXDESC_SIZE + OFFSET_SZ; 3190 3191 if (bmcst) 3192 ptxdesc->bmc = 1; 3193 3194 /* 2009.11.05. tynli_test. Suggested by SD4 Filen for FW LPS. 3195 * (1) The sequence number of each non-Qos frame / broadcast / 3196 * multicast / mgnt frame should be controlled by Hw because Fw 3197 * will also send null data which we cannot control when Fw LPS 3198 * enable. 3199 * --> default enable non-Qos data sequense number. 2010.06.23. 3200 * by tynli. 3201 * (2) Enable HW SEQ control for beacon packet, because we use 3202 * Hw beacon. 3203 * (3) Use HW Qos SEQ to control the seq num of Ext port non-Qos 3204 * packets. 3205 * 2010.06.23. Added by tynli. 3206 */ 3207 if (!pattrib->qos_en) /* Hw set sequence number */ 3208 ptxdesc->en_hwseq = 1; /* HWSEQ_EN */ 3209 } 3210 3211 /* Description: 3212 * 3213 * Parameters: 3214 * pxmitframe xmitframe 3215 * pbuf where to fill tx desc 3216 */ 3217 void rtl8723b_update_txdesc(struct xmit_frame *pxmitframe, u8 *pbuf) 3218 { 3219 struct tx_desc *pdesc; 3220 3221 rtl8723b_fill_default_txdesc(pxmitframe, pbuf); 3222 3223 pdesc = (struct tx_desc *)pbuf; 3224 pdesc->txdw0 = pdesc->txdw0; 3225 pdesc->txdw1 = pdesc->txdw1; 3226 pdesc->txdw2 = pdesc->txdw2; 3227 pdesc->txdw3 = pdesc->txdw3; 3228 pdesc->txdw4 = pdesc->txdw4; 3229 pdesc->txdw5 = pdesc->txdw5; 3230 pdesc->txdw6 = pdesc->txdw6; 3231 pdesc->txdw7 = pdesc->txdw7; 3232 pdesc->txdw8 = pdesc->txdw8; 3233 pdesc->txdw9 = pdesc->txdw9; 3234 3235 rtl8723b_cal_txdesc_chksum(pdesc); 3236 } 3237 3238 /* */ 3239 /* Description: In normal chip, we should send some packet to Hw which will be used by Fw */ 3240 /* in FW LPS mode. The function is to fill the Tx descriptor of this packets, then */ 3241 /* Fw can tell Hw to send these packet derectly. */ 3242 /* Added by tynli. 2009.10.15. */ 3243 /* */ 3244 /* type1:pspoll, type2:null */ 3245 void rtl8723b_fill_fake_txdesc( 3246 struct adapter *padapter, 3247 u8 *pDesc, 3248 u32 BufferLen, 3249 u8 IsPsPoll, 3250 u8 IsBTQosNull, 3251 u8 bDataFrame 3252 ) 3253 { 3254 /* Clear all status */ 3255 memset(pDesc, 0, TXDESC_SIZE); 3256 3257 SET_TX_DESC_FIRST_SEG_8723B(pDesc, 1); /* bFirstSeg; */ 3258 SET_TX_DESC_LAST_SEG_8723B(pDesc, 1); /* bLastSeg; */ 3259 3260 SET_TX_DESC_OFFSET_8723B(pDesc, 0x28); /* Offset = 32 */ 3261 3262 SET_TX_DESC_PKT_SIZE_8723B(pDesc, BufferLen); /* Buffer size + command header */ 3263 SET_TX_DESC_QUEUE_SEL_8723B(pDesc, QSLT_MGNT); /* Fixed queue of Mgnt queue */ 3264 3265 /* Set NAVUSEHDR to prevent Ps-poll AId filed to be changed to error vlaue by Hw. */ 3266 if (IsPsPoll) { 3267 SET_TX_DESC_NAV_USE_HDR_8723B(pDesc, 1); 3268 } else { 3269 SET_TX_DESC_HWSEQ_EN_8723B(pDesc, 1); /* Hw set sequence number */ 3270 SET_TX_DESC_HWSEQ_SEL_8723B(pDesc, 0); 3271 } 3272 3273 if (IsBTQosNull) { 3274 SET_TX_DESC_BT_INT_8723B(pDesc, 1); 3275 } 3276 3277 SET_TX_DESC_USE_RATE_8723B(pDesc, 1); /* use data rate which is set by Sw */ 3278 SET_TX_DESC_OWN_8723B((u8 *)pDesc, 1); 3279 3280 SET_TX_DESC_TX_RATE_8723B(pDesc, DESC8723B_RATE1M); 3281 3282 /* */ 3283 /* Encrypt the data frame if under security mode excepct null data. Suggested by CCW. */ 3284 /* */ 3285 if (bDataFrame) { 3286 u32 EncAlg; 3287 3288 EncAlg = padapter->securitypriv.dot11PrivacyAlgrthm; 3289 switch (EncAlg) { 3290 case _NO_PRIVACY_: 3291 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0); 3292 break; 3293 case _WEP40_: 3294 case _WEP104_: 3295 case _TKIP_: 3296 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x1); 3297 break; 3298 case _SMS4_: 3299 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x2); 3300 break; 3301 case _AES_: 3302 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x3); 3303 break; 3304 default: 3305 SET_TX_DESC_SEC_TYPE_8723B(pDesc, 0x0); 3306 break; 3307 } 3308 } 3309 3310 /* USB interface drop packet if the checksum of descriptor isn't correct. */ 3311 /* Using this checksum can let hardware recovery from packet bulk out error (e.g. Cancel URC, Bulk out error.). */ 3312 rtl8723b_cal_txdesc_chksum((struct tx_desc *)pDesc); 3313 } 3314 3315 static void hw_var_set_opmode(struct adapter *padapter, u8 variable, u8 *val) 3316 { 3317 u8 val8; 3318 u8 mode = *((u8 *)val); 3319 3320 { 3321 /* disable Port0 TSF update */ 3322 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3323 val8 |= DIS_TSF_UDT; 3324 rtw_write8(padapter, REG_BCN_CTRL, val8); 3325 3326 /* set net_type */ 3327 Set_MSR(padapter, mode); 3328 DBG_871X("#### %s() -%d iface_type(0) mode = %d ####\n", __func__, __LINE__, mode); 3329 3330 if ((mode == _HW_STATE_STATION_) || (mode == _HW_STATE_NOLINK_)) { 3331 { 3332 StopTxBeacon(padapter); 3333 #ifdef CONFIG_INTERRUPT_BASED_TXBCN 3334 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT 3335 rtw_write8(padapter, REG_DRVERLYINT, 0x05); /* restore early int time to 5ms */ 3336 UpdateInterruptMask8812AU(padapter, true, 0, IMR_BCNDMAINT0_8723B); 3337 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ 3338 3339 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR 3340 UpdateInterruptMask8812AU(padapter, true, 0, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B)); 3341 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ 3342 3343 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ 3344 } 3345 3346 /* disable atim wnd */ 3347 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_ATIM); 3348 /* rtw_write8(padapter, REG_BCN_CTRL, 0x18); */ 3349 } else if (mode == _HW_STATE_ADHOC_) { 3350 ResumeTxBeacon(padapter); 3351 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|EN_BCN_FUNCTION|DIS_BCNQ_SUB); 3352 } else if (mode == _HW_STATE_AP_) { 3353 #ifdef CONFIG_INTERRUPT_BASED_TXBCN 3354 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT 3355 UpdateInterruptMask8723BU(padapter, true, IMR_BCNDMAINT0_8723B, 0); 3356 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_EARLY_INT */ 3357 3358 #ifdef CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR 3359 UpdateInterruptMask8723BU(padapter, true, (IMR_TXBCN0ERR_8723B|IMR_TXBCN0OK_8723B), 0); 3360 #endif /* CONFIG_INTERRUPT_BASED_TXBCN_BCN_OK_ERR */ 3361 3362 #endif /* CONFIG_INTERRUPT_BASED_TXBCN */ 3363 3364 ResumeTxBeacon(padapter); 3365 3366 rtw_write8(padapter, REG_BCN_CTRL, DIS_TSF_UDT|DIS_BCNQ_SUB); 3367 3368 /* Set RCR */ 3369 rtw_write32(padapter, REG_RCR, 0x7000208e);/* CBSSID_DATA must set to 0, reject ICV_ERR packet */ 3370 /* enable to rx data frame */ 3371 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3372 /* enable to rx ps-poll */ 3373 rtw_write16(padapter, REG_RXFLTMAP1, 0x0400); 3374 3375 /* Beacon Control related register for first time */ 3376 rtw_write8(padapter, REG_BCNDMATIM, 0x02); /* 2ms */ 3377 3378 /* rtw_write8(padapter, REG_BCN_MAX_ERR, 0xFF); */ 3379 rtw_write8(padapter, REG_ATIMWND, 0x0a); /* 10ms */ 3380 rtw_write16(padapter, REG_BCNTCFG, 0x00); 3381 rtw_write16(padapter, REG_TBTT_PROHIBIT, 0xff04); 3382 rtw_write16(padapter, REG_TSFTR_SYN_OFFSET, 0x7fff);/* +32767 (~32ms) */ 3383 3384 /* reset TSF */ 3385 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); 3386 3387 /* enable BCN0 Function for if1 */ 3388 /* don't enable update TSF0 for if1 (due to TSF update when beacon/probe rsp are received) */ 3389 rtw_write8(padapter, REG_BCN_CTRL, (DIS_TSF_UDT|EN_BCN_FUNCTION|EN_TXBCN_RPT|DIS_BCNQ_SUB)); 3390 3391 /* SW_BCN_SEL - Port0 */ 3392 /* rtw_write8(Adapter, REG_DWBCN1_CTRL_8192E+2, rtw_read8(Adapter, REG_DWBCN1_CTRL_8192E+2) & ~BIT4); */ 3393 rtw_hal_set_hwreg(padapter, HW_VAR_DL_BCN_SEL, NULL); 3394 3395 /* select BCN on port 0 */ 3396 rtw_write8( 3397 padapter, 3398 REG_CCK_CHECK_8723B, 3399 (rtw_read8(padapter, REG_CCK_CHECK_8723B)&~BIT_BCN_PORT_SEL) 3400 ); 3401 3402 /* dis BCN1 ATIM WND if if2 is station */ 3403 val8 = rtw_read8(padapter, REG_BCN_CTRL_1); 3404 val8 |= DIS_ATIM; 3405 rtw_write8(padapter, REG_BCN_CTRL_1, val8); 3406 } 3407 } 3408 } 3409 3410 static void hw_var_set_macaddr(struct adapter *padapter, u8 variable, u8 *val) 3411 { 3412 u8 idx = 0; 3413 u32 reg_macid; 3414 3415 reg_macid = REG_MACID; 3416 3417 for (idx = 0 ; idx < 6; idx++) 3418 rtw_write8(GET_PRIMARY_ADAPTER(padapter), (reg_macid+idx), val[idx]); 3419 } 3420 3421 static void hw_var_set_bssid(struct adapter *padapter, u8 variable, u8 *val) 3422 { 3423 u8 idx = 0; 3424 u32 reg_bssid; 3425 3426 reg_bssid = REG_BSSID; 3427 3428 for (idx = 0 ; idx < 6; idx++) 3429 rtw_write8(padapter, (reg_bssid+idx), val[idx]); 3430 } 3431 3432 static void hw_var_set_bcn_func(struct adapter *padapter, u8 variable, u8 *val) 3433 { 3434 u32 bcn_ctrl_reg; 3435 3436 bcn_ctrl_reg = REG_BCN_CTRL; 3437 3438 if (*(u8 *)val) 3439 rtw_write8(padapter, bcn_ctrl_reg, (EN_BCN_FUNCTION | EN_TXBCN_RPT)); 3440 else { 3441 u8 val8; 3442 val8 = rtw_read8(padapter, bcn_ctrl_reg); 3443 val8 &= ~(EN_BCN_FUNCTION | EN_TXBCN_RPT); 3444 3445 /* Always enable port0 beacon function for PSTDMA */ 3446 if (REG_BCN_CTRL == bcn_ctrl_reg) 3447 val8 |= EN_BCN_FUNCTION; 3448 3449 rtw_write8(padapter, bcn_ctrl_reg, val8); 3450 } 3451 } 3452 3453 static void hw_var_set_correct_tsf(struct adapter *padapter, u8 variable, u8 *val) 3454 { 3455 u8 val8; 3456 u64 tsf; 3457 struct mlme_ext_priv *pmlmeext; 3458 struct mlme_ext_info *pmlmeinfo; 3459 3460 3461 pmlmeext = &padapter->mlmeextpriv; 3462 pmlmeinfo = &pmlmeext->mlmext_info; 3463 3464 tsf = pmlmeext->TSFValue-do_div(pmlmeext->TSFValue, (pmlmeinfo->bcn_interval*1024))-1024; /* us */ 3465 3466 if ( 3467 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || 3468 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) 3469 ) 3470 StopTxBeacon(padapter); 3471 3472 { 3473 /* disable related TSF function */ 3474 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3475 val8 &= ~EN_BCN_FUNCTION; 3476 rtw_write8(padapter, REG_BCN_CTRL, val8); 3477 3478 rtw_write32(padapter, REG_TSFTR, tsf); 3479 rtw_write32(padapter, REG_TSFTR+4, tsf>>32); 3480 3481 /* enable related TSF function */ 3482 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3483 val8 |= EN_BCN_FUNCTION; 3484 rtw_write8(padapter, REG_BCN_CTRL, val8); 3485 } 3486 3487 if ( 3488 ((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || 3489 ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE) 3490 ) 3491 ResumeTxBeacon(padapter); 3492 } 3493 3494 static void hw_var_set_mlme_disconnect(struct adapter *padapter, u8 variable, u8 *val) 3495 { 3496 u8 val8; 3497 3498 /* Set RCR to not to receive data frame when NO LINK state */ 3499 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR) & ~RCR_ADF); */ 3500 /* reject all data frames */ 3501 rtw_write16(padapter, REG_RXFLTMAP2, 0); 3502 3503 /* reset TSF */ 3504 rtw_write8(padapter, REG_DUAL_TSF_RST, BIT(0)); 3505 3506 /* disable update TSF */ 3507 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3508 val8 |= DIS_TSF_UDT; 3509 rtw_write8(padapter, REG_BCN_CTRL, val8); 3510 } 3511 3512 static void hw_var_set_mlme_sitesurvey(struct adapter *padapter, u8 variable, u8 *val) 3513 { 3514 u32 value_rcr, rcr_clear_bit, reg_bcn_ctl; 3515 u16 value_rxfltmap2; 3516 u8 val8; 3517 struct hal_com_data *pHalData; 3518 struct mlme_priv *pmlmepriv; 3519 3520 3521 pHalData = GET_HAL_DATA(padapter); 3522 pmlmepriv = &padapter->mlmepriv; 3523 3524 reg_bcn_ctl = REG_BCN_CTRL; 3525 3526 rcr_clear_bit = RCR_CBSSID_BCN; 3527 3528 /* config RCR to receive different BSSID & not to receive data frame */ 3529 value_rxfltmap2 = 0; 3530 3531 if ((check_fwstate(pmlmepriv, WIFI_AP_STATE) == true)) 3532 rcr_clear_bit = RCR_CBSSID_BCN; 3533 3534 value_rcr = rtw_read32(padapter, REG_RCR); 3535 3536 if (*((u8 *)val)) { 3537 /* under sitesurvey */ 3538 value_rcr &= ~(rcr_clear_bit); 3539 rtw_write32(padapter, REG_RCR, value_rcr); 3540 3541 rtw_write16(padapter, REG_RXFLTMAP2, value_rxfltmap2); 3542 3543 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { 3544 /* disable update TSF */ 3545 val8 = rtw_read8(padapter, reg_bcn_ctl); 3546 val8 |= DIS_TSF_UDT; 3547 rtw_write8(padapter, reg_bcn_ctl, val8); 3548 } 3549 3550 /* Save original RRSR setting. */ 3551 pHalData->RegRRSR = rtw_read16(padapter, REG_RRSR); 3552 } else { 3553 /* sitesurvey done */ 3554 if (check_fwstate(pmlmepriv, (_FW_LINKED|WIFI_AP_STATE))) 3555 /* enable to rx data frame */ 3556 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3557 3558 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE | WIFI_ADHOC_STATE | WIFI_ADHOC_MASTER_STATE)) { 3559 /* enable update TSF */ 3560 val8 = rtw_read8(padapter, reg_bcn_ctl); 3561 val8 &= ~DIS_TSF_UDT; 3562 rtw_write8(padapter, reg_bcn_ctl, val8); 3563 } 3564 3565 value_rcr |= rcr_clear_bit; 3566 rtw_write32(padapter, REG_RCR, value_rcr); 3567 3568 /* Restore original RRSR setting. */ 3569 rtw_write16(padapter, REG_RRSR, pHalData->RegRRSR); 3570 } 3571 } 3572 3573 static void hw_var_set_mlme_join(struct adapter *padapter, u8 variable, u8 *val) 3574 { 3575 u8 val8; 3576 u16 val16; 3577 u32 val32; 3578 u8 RetryLimit; 3579 u8 type; 3580 struct mlme_priv *pmlmepriv; 3581 struct eeprom_priv *pEEPROM; 3582 3583 3584 RetryLimit = 0x30; 3585 type = *(u8 *)val; 3586 pmlmepriv = &padapter->mlmepriv; 3587 pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter); 3588 3589 if (type == 0) { /* prepare to join */ 3590 /* enable to rx data frame.Accept all data frame */ 3591 /* rtw_write32(padapter, REG_RCR, rtw_read32(padapter, REG_RCR)|RCR_ADF); */ 3592 rtw_write16(padapter, REG_RXFLTMAP2, 0xFFFF); 3593 3594 val32 = rtw_read32(padapter, REG_RCR); 3595 if (padapter->in_cta_test) 3596 val32 &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);/* RCR_ADF */ 3597 else 3598 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN; 3599 rtw_write32(padapter, REG_RCR, val32); 3600 3601 if (check_fwstate(pmlmepriv, WIFI_STATION_STATE) == true) 3602 RetryLimit = (pEEPROM->CustomerID == RT_CID_CCX) ? 7 : 48; 3603 else /* Ad-hoc Mode */ 3604 RetryLimit = 0x7; 3605 } else if (type == 1) /* joinbss_event call back when join res < 0 */ 3606 rtw_write16(padapter, REG_RXFLTMAP2, 0x00); 3607 else if (type == 2) { /* sta add event call back */ 3608 /* enable update TSF */ 3609 val8 = rtw_read8(padapter, REG_BCN_CTRL); 3610 val8 &= ~DIS_TSF_UDT; 3611 rtw_write8(padapter, REG_BCN_CTRL, val8); 3612 3613 if (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE)) 3614 RetryLimit = 0x7; 3615 } 3616 3617 val16 = (RetryLimit << RETRY_LIMIT_SHORT_SHIFT) | (RetryLimit << RETRY_LIMIT_LONG_SHIFT); 3618 rtw_write16(padapter, REG_RL, val16); 3619 } 3620 3621 void CCX_FwC2HTxRpt_8723b(struct adapter *padapter, u8 *pdata, u8 len) 3622 { 3623 u8 seq_no; 3624 3625 #define GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 6, 1) 3626 #define GET_8723B_C2H_TX_RPT_RETRY_OVER(_Header) LE_BITS_TO_1BYTE((_Header + 0), 7, 1) 3627 3628 /* DBG_871X("%s, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", __func__, */ 3629 /* *pdata, *(pdata+1), *(pdata+2), *(pdata+3), *(pdata+4), *(pdata+5), *(pdata+6), *(pdata+7)); */ 3630 3631 seq_no = *(pdata+6); 3632 3633 if (GET_8723B_C2H_TX_RPT_RETRY_OVER(pdata) | GET_8723B_C2H_TX_RPT_LIFE_TIME_OVER(pdata)) { 3634 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); 3635 } 3636 /* 3637 else if (seq_no != padapter->xmitpriv.seq_no) { 3638 DBG_871X("tx_seq_no =%d, rpt_seq_no =%d\n", padapter->xmitpriv.seq_no, seq_no); 3639 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_CCX_PKT_FAIL); 3640 } 3641 */ 3642 else 3643 rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_SUCCESS); 3644 } 3645 3646 s32 c2h_id_filter_ccx_8723b(u8 *buf) 3647 { 3648 struct c2h_evt_hdr_88xx *c2h_evt = (struct c2h_evt_hdr_88xx *)buf; 3649 s32 ret = false; 3650 if (c2h_evt->id == C2H_CCX_TX_RPT) 3651 ret = true; 3652 3653 return ret; 3654 } 3655 3656 3657 s32 c2h_handler_8723b(struct adapter *padapter, u8 *buf) 3658 { 3659 struct c2h_evt_hdr_88xx *pC2hEvent = (struct c2h_evt_hdr_88xx *)buf; 3660 s32 ret = _SUCCESS; 3661 u8 index = 0; 3662 3663 if (!pC2hEvent) { 3664 DBG_8192C("%s(): pC2hEventis NULL\n", __func__); 3665 ret = _FAIL; 3666 goto exit; 3667 } 3668 3669 switch (pC2hEvent->id) { 3670 case C2H_AP_RPT_RSP: 3671 break; 3672 case C2H_DBG: 3673 { 3674 RT_TRACE(_module_hal_init_c_, _drv_info_, ("c2h_handler_8723b: %s\n", pC2hEvent->payload)); 3675 } 3676 break; 3677 3678 case C2H_CCX_TX_RPT: 3679 /* CCX_FwC2HTxRpt(padapter, QueueID, pC2hEvent->payload); */ 3680 break; 3681 3682 case C2H_EXT_RA_RPT: 3683 /* C2HExtRaRptHandler(padapter, pC2hEvent->payload, C2hEvent.CmdLen); */ 3684 break; 3685 3686 case C2H_HW_INFO_EXCH: 3687 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n")); 3688 for (index = 0; index < pC2hEvent->plen; index++) { 3689 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, pC2hEvent->payload[index])); 3690 } 3691 break; 3692 3693 case C2H_8723B_BT_INFO: 3694 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->plen, pC2hEvent->payload); 3695 break; 3696 3697 default: 3698 break; 3699 } 3700 3701 /* Clear event to notify FW we have read the command. */ 3702 /* Note: */ 3703 /* If this field isn't clear, the FW won't update the next command message. */ 3704 /* rtw_write8(padapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE); */ 3705 exit: 3706 return ret; 3707 } 3708 3709 static void process_c2h_event(struct adapter *padapter, PC2H_EVT_HDR pC2hEvent, u8 *c2hBuf) 3710 { 3711 u8 index = 0; 3712 3713 if (!c2hBuf) { 3714 DBG_8192C("%s c2hbuff is NULL\n", __func__); 3715 return; 3716 } 3717 3718 switch (pC2hEvent->CmdID) { 3719 case C2H_AP_RPT_RSP: 3720 break; 3721 case C2H_DBG: 3722 { 3723 RT_TRACE(_module_hal_init_c_, _drv_info_, ("C2HCommandHandler: %s\n", c2hBuf)); 3724 } 3725 break; 3726 3727 case C2H_CCX_TX_RPT: 3728 /* CCX_FwC2HTxRpt(padapter, QueueID, tmpBuf); */ 3729 break; 3730 3731 case C2H_EXT_RA_RPT: 3732 /* C2HExtRaRptHandler(padapter, tmpBuf, C2hEvent.CmdLen); */ 3733 break; 3734 3735 case C2H_HW_INFO_EXCH: 3736 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], C2H_HW_INFO_EXCH\n")); 3737 for (index = 0; index < pC2hEvent->CmdLen; index++) { 3738 RT_TRACE(_module_hal_init_c_, _drv_info_, ("[BT], tmpBuf[%d]= 0x%x\n", index, c2hBuf[index])); 3739 } 3740 break; 3741 3742 case C2H_8723B_BT_INFO: 3743 hal_btcoex_BtInfoNotify(padapter, pC2hEvent->CmdLen, c2hBuf); 3744 break; 3745 3746 default: 3747 break; 3748 } 3749 } 3750 3751 void C2HPacketHandler_8723B(struct adapter *padapter, u8 *pbuffer, u16 length) 3752 { 3753 C2H_EVT_HDR C2hEvent; 3754 u8 *tmpBuf = NULL; 3755 #ifdef CONFIG_WOWLAN 3756 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); 3757 3758 if (pwrpriv->wowlan_mode) { 3759 DBG_871X("%s(): return because wowolan_mode ==true! CMDID =%d\n", __func__, pbuffer[0]); 3760 return; 3761 } 3762 #endif 3763 C2hEvent.CmdID = pbuffer[0]; 3764 C2hEvent.CmdSeq = pbuffer[1]; 3765 C2hEvent.CmdLen = length-2; 3766 tmpBuf = pbuffer+2; 3767 3768 /* DBG_871X("%s C2hEvent.CmdID:%x C2hEvent.CmdLen:%x C2hEvent.CmdSeq:%x\n", */ 3769 /* __func__, C2hEvent.CmdID, C2hEvent.CmdLen, C2hEvent.CmdSeq); */ 3770 RT_PRINT_DATA(_module_hal_init_c_, _drv_notice_, "C2HPacketHandler_8723B(): Command Content:\n", tmpBuf, C2hEvent.CmdLen); 3771 3772 process_c2h_event(padapter, &C2hEvent, tmpBuf); 3773 /* c2h_handler_8723b(padapter,&C2hEvent); */ 3774 } 3775 3776 void SetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) 3777 { 3778 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 3779 u8 val8; 3780 u32 val32; 3781 3782 switch (variable) { 3783 case HW_VAR_MEDIA_STATUS: 3784 val8 = rtw_read8(padapter, MSR) & 0x0c; 3785 val8 |= *val; 3786 rtw_write8(padapter, MSR, val8); 3787 break; 3788 3789 case HW_VAR_MEDIA_STATUS1: 3790 val8 = rtw_read8(padapter, MSR) & 0x03; 3791 val8 |= *val << 2; 3792 rtw_write8(padapter, MSR, val8); 3793 break; 3794 3795 case HW_VAR_SET_OPMODE: 3796 hw_var_set_opmode(padapter, variable, val); 3797 break; 3798 3799 case HW_VAR_MAC_ADDR: 3800 hw_var_set_macaddr(padapter, variable, val); 3801 break; 3802 3803 case HW_VAR_BSSID: 3804 hw_var_set_bssid(padapter, variable, val); 3805 break; 3806 3807 case HW_VAR_BASIC_RATE: 3808 { 3809 struct mlme_ext_info *mlmext_info = &padapter->mlmeextpriv.mlmext_info; 3810 u16 input_b = 0, masked = 0, ioted = 0, BrateCfg = 0; 3811 u16 rrsr_2g_force_mask = (RRSR_11M|RRSR_5_5M|RRSR_1M); 3812 u16 rrsr_2g_allow_mask = (RRSR_24M|RRSR_12M|RRSR_6M|RRSR_CCK_RATES); 3813 3814 HalSetBrateCfg(padapter, val, &BrateCfg); 3815 input_b = BrateCfg; 3816 3817 /* apply force and allow mask */ 3818 BrateCfg |= rrsr_2g_force_mask; 3819 BrateCfg &= rrsr_2g_allow_mask; 3820 masked = BrateCfg; 3821 3822 #ifdef CONFIG_CMCC_TEST 3823 BrateCfg |= (RRSR_11M|RRSR_5_5M|RRSR_1M); /* use 11M to send ACK */ 3824 BrateCfg |= (RRSR_24M|RRSR_18M|RRSR_12M); /* CMCC_OFDM_ACK 12/18/24M */ 3825 #endif 3826 3827 /* IOT consideration */ 3828 if (mlmext_info->assoc_AP_vendor == HT_IOT_PEER_CISCO) { 3829 /* if peer is cisco and didn't use ofdm rate, we enable 6M ack */ 3830 if ((BrateCfg & (RRSR_24M|RRSR_12M|RRSR_6M)) == 0) 3831 BrateCfg |= RRSR_6M; 3832 } 3833 ioted = BrateCfg; 3834 3835 pHalData->BasicRateSet = BrateCfg; 3836 3837 DBG_8192C("HW_VAR_BASIC_RATE: %#x -> %#x -> %#x\n", input_b, masked, ioted); 3838 3839 /* Set RRSR rate table. */ 3840 rtw_write16(padapter, REG_RRSR, BrateCfg); 3841 rtw_write8(padapter, REG_RRSR+2, rtw_read8(padapter, REG_RRSR+2)&0xf0); 3842 } 3843 break; 3844 3845 case HW_VAR_TXPAUSE: 3846 rtw_write8(padapter, REG_TXPAUSE, *val); 3847 break; 3848 3849 case HW_VAR_BCN_FUNC: 3850 hw_var_set_bcn_func(padapter, variable, val); 3851 break; 3852 3853 case HW_VAR_CORRECT_TSF: 3854 hw_var_set_correct_tsf(padapter, variable, val); 3855 break; 3856 3857 case HW_VAR_CHECK_BSSID: 3858 { 3859 u32 val32; 3860 val32 = rtw_read32(padapter, REG_RCR); 3861 if (*val) 3862 val32 |= RCR_CBSSID_DATA|RCR_CBSSID_BCN; 3863 else 3864 val32 &= ~(RCR_CBSSID_DATA|RCR_CBSSID_BCN); 3865 rtw_write32(padapter, REG_RCR, val32); 3866 } 3867 break; 3868 3869 case HW_VAR_MLME_DISCONNECT: 3870 hw_var_set_mlme_disconnect(padapter, variable, val); 3871 break; 3872 3873 case HW_VAR_MLME_SITESURVEY: 3874 hw_var_set_mlme_sitesurvey(padapter, variable, val); 3875 3876 hal_btcoex_ScanNotify(padapter, *val?true:false); 3877 break; 3878 3879 case HW_VAR_MLME_JOIN: 3880 hw_var_set_mlme_join(padapter, variable, val); 3881 3882 switch (*val) { 3883 case 0: 3884 /* prepare to join */ 3885 hal_btcoex_ConnectNotify(padapter, true); 3886 break; 3887 case 1: 3888 /* joinbss_event callback when join res < 0 */ 3889 hal_btcoex_ConnectNotify(padapter, false); 3890 break; 3891 case 2: 3892 /* sta add event callback */ 3893 /* rtw_btcoex_MediaStatusNotify(padapter, RT_MEDIA_CONNECT); */ 3894 break; 3895 } 3896 break; 3897 3898 case HW_VAR_ON_RCR_AM: 3899 val32 = rtw_read32(padapter, REG_RCR); 3900 val32 |= RCR_AM; 3901 rtw_write32(padapter, REG_RCR, val32); 3902 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); 3903 break; 3904 3905 case HW_VAR_OFF_RCR_AM: 3906 val32 = rtw_read32(padapter, REG_RCR); 3907 val32 &= ~RCR_AM; 3908 rtw_write32(padapter, REG_RCR, val32); 3909 DBG_8192C("%s, %d, RCR = %x\n", __func__, __LINE__, rtw_read32(padapter, REG_RCR)); 3910 break; 3911 3912 case HW_VAR_BEACON_INTERVAL: 3913 rtw_write16(padapter, REG_BCN_INTERVAL, *((u16 *)val)); 3914 break; 3915 3916 case HW_VAR_SLOT_TIME: 3917 rtw_write8(padapter, REG_SLOT, *val); 3918 break; 3919 3920 case HW_VAR_RESP_SIFS: 3921 /* SIFS_Timer = 0x0a0a0808; */ 3922 /* RESP_SIFS for CCK */ 3923 rtw_write8(padapter, REG_RESP_SIFS_CCK, val[0]); /* SIFS_T2T_CCK (0x08) */ 3924 rtw_write8(padapter, REG_RESP_SIFS_CCK+1, val[1]); /* SIFS_R2T_CCK(0x08) */ 3925 /* RESP_SIFS for OFDM */ 3926 rtw_write8(padapter, REG_RESP_SIFS_OFDM, val[2]); /* SIFS_T2T_OFDM (0x0a) */ 3927 rtw_write8(padapter, REG_RESP_SIFS_OFDM+1, val[3]); /* SIFS_R2T_OFDM(0x0a) */ 3928 break; 3929 3930 case HW_VAR_ACK_PREAMBLE: 3931 { 3932 u8 regTmp; 3933 u8 bShortPreamble = *val; 3934 3935 /* Joseph marked out for Netgear 3500 TKIP channel 7 issue.(Temporarily) */ 3936 /* regTmp = (pHalData->nCur40MhzPrimeSC)<<5; */ 3937 regTmp = 0; 3938 if (bShortPreamble) 3939 regTmp |= 0x80; 3940 rtw_write8(padapter, REG_RRSR+2, regTmp); 3941 } 3942 break; 3943 3944 case HW_VAR_CAM_EMPTY_ENTRY: 3945 { 3946 u8 ucIndex = *val; 3947 u8 i; 3948 u32 ulCommand = 0; 3949 u32 ulContent = 0; 3950 u32 ulEncAlgo = CAM_AES; 3951 3952 for (i = 0; i < CAM_CONTENT_COUNT; i++) { 3953 /* filled id in CAM config 2 byte */ 3954 if (i == 0) { 3955 ulContent |= (ucIndex & 0x03) | ((u16)(ulEncAlgo)<<2); 3956 /* ulContent |= CAM_VALID; */ 3957 } else 3958 ulContent = 0; 3959 3960 /* polling bit, and No Write enable, and address */ 3961 ulCommand = CAM_CONTENT_COUNT*ucIndex+i; 3962 ulCommand = ulCommand | CAM_POLLINIG | CAM_WRITE; 3963 /* write content 0 is equall to mark invalid */ 3964 rtw_write32(padapter, WCAMI, ulContent); /* mdelay(40); */ 3965 /* RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A4: %lx\n", ulContent)); */ 3966 rtw_write32(padapter, RWCAM, ulCommand); /* mdelay(40); */ 3967 /* RT_TRACE(COMP_SEC, DBG_LOUD, ("CAM_empty_entry(): WRITE A0: %lx\n", ulCommand)); */ 3968 } 3969 } 3970 break; 3971 3972 case HW_VAR_CAM_INVALID_ALL: 3973 rtw_write32(padapter, RWCAM, BIT(31)|BIT(30)); 3974 break; 3975 3976 case HW_VAR_CAM_WRITE: 3977 { 3978 u32 cmd; 3979 u32 *cam_val = (u32 *)val; 3980 3981 rtw_write32(padapter, WCAMI, cam_val[0]); 3982 3983 cmd = CAM_POLLINIG | CAM_WRITE | cam_val[1]; 3984 rtw_write32(padapter, RWCAM, cmd); 3985 } 3986 break; 3987 3988 case HW_VAR_AC_PARAM_VO: 3989 rtw_write32(padapter, REG_EDCA_VO_PARAM, *((u32 *)val)); 3990 break; 3991 3992 case HW_VAR_AC_PARAM_VI: 3993 rtw_write32(padapter, REG_EDCA_VI_PARAM, *((u32 *)val)); 3994 break; 3995 3996 case HW_VAR_AC_PARAM_BE: 3997 pHalData->AcParam_BE = ((u32 *)(val))[0]; 3998 rtw_write32(padapter, REG_EDCA_BE_PARAM, *((u32 *)val)); 3999 break; 4000 4001 case HW_VAR_AC_PARAM_BK: 4002 rtw_write32(padapter, REG_EDCA_BK_PARAM, *((u32 *)val)); 4003 break; 4004 4005 case HW_VAR_ACM_CTRL: 4006 { 4007 u8 ctrl = *((u8 *)val); 4008 u8 hwctrl = 0; 4009 4010 if (ctrl != 0) { 4011 hwctrl |= AcmHw_HwEn; 4012 4013 if (ctrl & BIT(1)) /* BE */ 4014 hwctrl |= AcmHw_BeqEn; 4015 4016 if (ctrl & BIT(2)) /* VI */ 4017 hwctrl |= AcmHw_ViqEn; 4018 4019 if (ctrl & BIT(3)) /* VO */ 4020 hwctrl |= AcmHw_VoqEn; 4021 } 4022 4023 DBG_8192C("[HW_VAR_ACM_CTRL] Write 0x%02X\n", hwctrl); 4024 rtw_write8(padapter, REG_ACMHWCTRL, hwctrl); 4025 } 4026 break; 4027 4028 case HW_VAR_AMPDU_FACTOR: 4029 { 4030 u32 AMPDULen = (*((u8 *)val)); 4031 4032 if (AMPDULen < HT_AGG_SIZE_32K) 4033 AMPDULen = (0x2000 << (*((u8 *)val)))-1; 4034 else 4035 AMPDULen = 0x7fff; 4036 4037 rtw_write32(padapter, REG_AMPDU_MAX_LENGTH_8723B, AMPDULen); 4038 } 4039 break; 4040 4041 case HW_VAR_H2C_FW_PWRMODE: 4042 { 4043 u8 psmode = *val; 4044 4045 /* Forece leave RF low power mode for 1T1R to prevent conficting setting in Fw power */ 4046 /* saving sequence. 2010.06.07. Added by tynli. Suggested by SD3 yschang. */ 4047 if (psmode != PS_MODE_ACTIVE) { 4048 ODM_RF_Saving(&pHalData->odmpriv, true); 4049 } 4050 4051 /* if (psmode != PS_MODE_ACTIVE) { */ 4052 /* rtl8723b_set_lowpwr_lps_cmd(padapter, true); */ 4053 /* else { */ 4054 /* rtl8723b_set_lowpwr_lps_cmd(padapter, false); */ 4055 /* */ 4056 rtl8723b_set_FwPwrMode_cmd(padapter, psmode); 4057 } 4058 break; 4059 case HW_VAR_H2C_PS_TUNE_PARAM: 4060 rtl8723b_set_FwPsTuneParam_cmd(padapter); 4061 break; 4062 4063 case HW_VAR_H2C_FW_JOINBSSRPT: 4064 rtl8723b_set_FwJoinBssRpt_cmd(padapter, *val); 4065 break; 4066 4067 case HW_VAR_INITIAL_GAIN: 4068 { 4069 DIG_T *pDigTable = &pHalData->odmpriv.DM_DigTable; 4070 u32 rx_gain = *(u32 *)val; 4071 4072 if (rx_gain == 0xff) {/* restore rx gain */ 4073 ODM_Write_DIG(&pHalData->odmpriv, pDigTable->BackupIGValue); 4074 } else { 4075 pDigTable->BackupIGValue = pDigTable->CurIGValue; 4076 ODM_Write_DIG(&pHalData->odmpriv, rx_gain); 4077 } 4078 } 4079 break; 4080 4081 case HW_VAR_EFUSE_USAGE: 4082 pHalData->EfuseUsedPercentage = *val; 4083 break; 4084 4085 case HW_VAR_EFUSE_BYTES: 4086 pHalData->EfuseUsedBytes = *((u16 *)val); 4087 break; 4088 4089 case HW_VAR_EFUSE_BT_USAGE: 4090 #ifdef HAL_EFUSE_MEMORY 4091 pHalData->EfuseHal.BTEfuseUsedPercentage = *val; 4092 #endif 4093 break; 4094 4095 case HW_VAR_EFUSE_BT_BYTES: 4096 #ifdef HAL_EFUSE_MEMORY 4097 pHalData->EfuseHal.BTEfuseUsedBytes = *((u16 *)val); 4098 #else 4099 BTEfuseUsedBytes = *((u16 *)val); 4100 #endif 4101 break; 4102 4103 case HW_VAR_FIFO_CLEARN_UP: 4104 { 4105 #define RW_RELEASE_EN BIT(18) 4106 #define RXDMA_IDLE BIT(17) 4107 4108 struct pwrctrl_priv *pwrpriv = adapter_to_pwrctl(padapter); 4109 u8 trycnt = 100; 4110 4111 /* pause tx */ 4112 rtw_write8(padapter, REG_TXPAUSE, 0xff); 4113 4114 /* keep sn */ 4115 padapter->xmitpriv.nqos_ssn = rtw_read16(padapter, REG_NQOS_SEQ); 4116 4117 if (!pwrpriv->bkeepfwalive) { 4118 /* RX DMA stop */ 4119 val32 = rtw_read32(padapter, REG_RXPKT_NUM); 4120 val32 |= RW_RELEASE_EN; 4121 rtw_write32(padapter, REG_RXPKT_NUM, val32); 4122 do { 4123 val32 = rtw_read32(padapter, REG_RXPKT_NUM); 4124 val32 &= RXDMA_IDLE; 4125 if (val32) 4126 break; 4127 4128 DBG_871X("%s: [HW_VAR_FIFO_CLEARN_UP] val =%x times:%d\n", __func__, val32, trycnt); 4129 } while (--trycnt); 4130 4131 if (trycnt == 0) { 4132 DBG_8192C("[HW_VAR_FIFO_CLEARN_UP] Stop RX DMA failed......\n"); 4133 } 4134 4135 /* RQPN Load 0 */ 4136 rtw_write16(padapter, REG_RQPN_NPQ, 0); 4137 rtw_write32(padapter, REG_RQPN, 0x80000000); 4138 mdelay(2); 4139 } 4140 } 4141 break; 4142 4143 case HW_VAR_APFM_ON_MAC: 4144 pHalData->bMacPwrCtrlOn = *val; 4145 DBG_8192C("%s: bMacPwrCtrlOn =%d\n", __func__, pHalData->bMacPwrCtrlOn); 4146 break; 4147 4148 case HW_VAR_NAV_UPPER: 4149 { 4150 u32 usNavUpper = *((u32 *)val); 4151 4152 if (usNavUpper > HAL_NAV_UPPER_UNIT_8723B * 0xFF) { 4153 RT_TRACE(_module_hal_init_c_, _drv_notice_, ("The setting value (0x%08X us) of NAV_UPPER is larger than (%d * 0xFF)!!!\n", usNavUpper, HAL_NAV_UPPER_UNIT_8723B)); 4154 break; 4155 } 4156 4157 usNavUpper = DIV_ROUND_UP(usNavUpper, 4158 HAL_NAV_UPPER_UNIT_8723B); 4159 rtw_write8(padapter, REG_NAV_UPPER, (u8)usNavUpper); 4160 } 4161 break; 4162 4163 case HW_VAR_H2C_MEDIA_STATUS_RPT: 4164 { 4165 u16 mstatus_rpt = (*(u16 *)val); 4166 u8 mstatus, macId; 4167 4168 mstatus = (u8) (mstatus_rpt & 0xFF); 4169 macId = (u8)(mstatus_rpt >> 8); 4170 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, mstatus, macId); 4171 } 4172 break; 4173 case HW_VAR_BCN_VALID: 4174 { 4175 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */ 4176 val8 = rtw_read8(padapter, REG_TDECTRL+2); 4177 val8 |= BIT(0); 4178 rtw_write8(padapter, REG_TDECTRL+2, val8); 4179 } 4180 break; 4181 4182 case HW_VAR_DL_BCN_SEL: 4183 { 4184 /* SW_BCN_SEL - Port0 */ 4185 val8 = rtw_read8(padapter, REG_DWBCN1_CTRL_8723B+2); 4186 val8 &= ~BIT(4); 4187 rtw_write8(padapter, REG_DWBCN1_CTRL_8723B+2, val8); 4188 } 4189 break; 4190 4191 case HW_VAR_DO_IQK: 4192 pHalData->bNeedIQK = true; 4193 break; 4194 4195 case HW_VAR_DL_RSVD_PAGE: 4196 if (check_fwstate(&padapter->mlmepriv, WIFI_AP_STATE) == true) 4197 rtl8723b_download_BTCoex_AP_mode_rsvd_page(padapter); 4198 else 4199 rtl8723b_download_rsvd_page(padapter, RT_MEDIA_CONNECT); 4200 break; 4201 4202 case HW_VAR_MACID_SLEEP: 4203 /* Input is MACID */ 4204 val32 = *(u32 *)val; 4205 if (val32 > 31) { 4206 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] Invalid macid(%d)\n", 4207 FUNC_ADPT_ARG(padapter), val32); 4208 break; 4209 } 4210 val8 = (u8)val32; /* macid is between 0~31 */ 4211 4212 val32 = rtw_read32(padapter, REG_MACID_SLEEP); 4213 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_SLEEP] macid =%d, org MACID_SLEEP = 0x%08X\n", 4214 FUNC_ADPT_ARG(padapter), val8, val32); 4215 if (val32 & BIT(val8)) 4216 break; 4217 val32 |= BIT(val8); 4218 rtw_write32(padapter, REG_MACID_SLEEP, val32); 4219 break; 4220 4221 case HW_VAR_MACID_WAKEUP: 4222 /* Input is MACID */ 4223 val32 = *(u32 *)val; 4224 if (val32 > 31) { 4225 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] Invalid macid(%d)\n", 4226 FUNC_ADPT_ARG(padapter), val32); 4227 break; 4228 } 4229 val8 = (u8)val32; /* macid is between 0~31 */ 4230 4231 val32 = rtw_read32(padapter, REG_MACID_SLEEP); 4232 DBG_8192C(FUNC_ADPT_FMT ": [HW_VAR_MACID_WAKEUP] macid =%d, org MACID_SLEEP = 0x%08X\n", 4233 FUNC_ADPT_ARG(padapter), val8, val32); 4234 if (!(val32 & BIT(val8))) 4235 break; 4236 val32 &= ~BIT(val8); 4237 rtw_write32(padapter, REG_MACID_SLEEP, val32); 4238 break; 4239 4240 default: 4241 SetHwReg(padapter, variable, val); 4242 break; 4243 } 4244 } 4245 4246 void GetHwReg8723B(struct adapter *padapter, u8 variable, u8 *val) 4247 { 4248 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 4249 u8 val8; 4250 u16 val16; 4251 4252 switch (variable) { 4253 case HW_VAR_TXPAUSE: 4254 *val = rtw_read8(padapter, REG_TXPAUSE); 4255 break; 4256 4257 case HW_VAR_BCN_VALID: 4258 { 4259 /* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */ 4260 val8 = rtw_read8(padapter, REG_TDECTRL+2); 4261 *val = (BIT(0) & val8) ? true : false; 4262 } 4263 break; 4264 4265 case HW_VAR_FWLPS_RF_ON: 4266 { 4267 /* When we halt NIC, we should check if FW LPS is leave. */ 4268 u32 valRCR; 4269 4270 if ( 4271 padapter->bSurpriseRemoved || 4272 (adapter_to_pwrctl(padapter)->rf_pwrstate == rf_off) 4273 ) { 4274 /* If it is in HW/SW Radio OFF or IPS state, we do not check Fw LPS Leave, */ 4275 /* because Fw is unload. */ 4276 *val = true; 4277 } else { 4278 valRCR = rtw_read32(padapter, REG_RCR); 4279 valRCR &= 0x00070000; 4280 if (valRCR) 4281 *val = false; 4282 else 4283 *val = true; 4284 } 4285 } 4286 break; 4287 4288 case HW_VAR_EFUSE_USAGE: 4289 *val = pHalData->EfuseUsedPercentage; 4290 break; 4291 4292 case HW_VAR_EFUSE_BYTES: 4293 *((u16 *)val) = pHalData->EfuseUsedBytes; 4294 break; 4295 4296 case HW_VAR_EFUSE_BT_USAGE: 4297 #ifdef HAL_EFUSE_MEMORY 4298 *val = pHalData->EfuseHal.BTEfuseUsedPercentage; 4299 #endif 4300 break; 4301 4302 case HW_VAR_EFUSE_BT_BYTES: 4303 #ifdef HAL_EFUSE_MEMORY 4304 *((u16 *)val) = pHalData->EfuseHal.BTEfuseUsedBytes; 4305 #else 4306 *((u16 *)val) = BTEfuseUsedBytes; 4307 #endif 4308 break; 4309 4310 case HW_VAR_APFM_ON_MAC: 4311 *val = pHalData->bMacPwrCtrlOn; 4312 break; 4313 case HW_VAR_CHK_HI_QUEUE_EMPTY: 4314 val16 = rtw_read16(padapter, REG_TXPKT_EMPTY); 4315 *val = (val16 & BIT(10)) ? true:false; 4316 break; 4317 #ifdef CONFIG_WOWLAN 4318 case HW_VAR_RPWM_TOG: 4319 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1) & BIT7; 4320 break; 4321 case HW_VAR_WAKEUP_REASON: 4322 *val = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON); 4323 if (*val == 0xEA) 4324 *val = 0; 4325 break; 4326 case HW_VAR_SYS_CLKR: 4327 *val = rtw_read8(padapter, REG_SYS_CLKR); 4328 break; 4329 #endif 4330 default: 4331 GetHwReg(padapter, variable, val); 4332 break; 4333 } 4334 } 4335 4336 /* Description: 4337 * Change default setting of specified variable. 4338 */ 4339 u8 SetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval) 4340 { 4341 u8 bResult; 4342 4343 bResult = _SUCCESS; 4344 4345 switch (variable) { 4346 default: 4347 bResult = SetHalDefVar(padapter, variable, pval); 4348 break; 4349 } 4350 4351 return bResult; 4352 } 4353 4354 /* Description: 4355 * Query setting of specified variable. 4356 */ 4357 u8 GetHalDefVar8723B(struct adapter *padapter, enum HAL_DEF_VARIABLE variable, void *pval) 4358 { 4359 u8 bResult; 4360 4361 bResult = _SUCCESS; 4362 4363 switch (variable) { 4364 case HAL_DEF_MAX_RECVBUF_SZ: 4365 *((u32 *)pval) = MAX_RECVBUF_SZ; 4366 break; 4367 4368 case HAL_DEF_RX_PACKET_OFFSET: 4369 *((u32 *)pval) = RXDESC_SIZE + DRVINFO_SZ*8; 4370 break; 4371 4372 case HW_VAR_MAX_RX_AMPDU_FACTOR: 4373 /* Stanley@BB.SD3 suggests 16K can get stable performance */ 4374 /* The experiment was done on SDIO interface */ 4375 /* coding by Lucas@20130730 */ 4376 *(u32 *)pval = IEEE80211_HT_MAX_AMPDU_16K; 4377 break; 4378 case HAL_DEF_TX_LDPC: 4379 case HAL_DEF_RX_LDPC: 4380 *((u8 *)pval) = false; 4381 break; 4382 case HAL_DEF_TX_STBC: 4383 *((u8 *)pval) = 0; 4384 break; 4385 case HAL_DEF_RX_STBC: 4386 *((u8 *)pval) = 1; 4387 break; 4388 case HAL_DEF_EXPLICIT_BEAMFORMER: 4389 case HAL_DEF_EXPLICIT_BEAMFORMEE: 4390 *((u8 *)pval) = false; 4391 break; 4392 4393 case HW_DEF_RA_INFO_DUMP: 4394 { 4395 u8 mac_id = *(u8 *)pval; 4396 u32 cmd; 4397 u32 ra_info1, ra_info2; 4398 u32 rate_mask1, rate_mask2; 4399 u8 curr_tx_rate, curr_tx_sgi, hight_rate, lowest_rate; 4400 4401 DBG_8192C("============ RA status check Mac_id:%d ===================\n", mac_id); 4402 4403 cmd = 0x40000100 | mac_id; 4404 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd); 4405 msleep(10); 4406 ra_info1 = rtw_read32(padapter, 0x2F0); 4407 curr_tx_rate = ra_info1&0x7F; 4408 curr_tx_sgi = (ra_info1>>7)&0x01; 4409 DBG_8192C("[ ra_info1:0x%08x ] =>cur_tx_rate = %s, cur_sgi:%d, PWRSTS = 0x%02x \n", 4410 ra_info1, 4411 HDATA_RATE(curr_tx_rate), 4412 curr_tx_sgi, 4413 (ra_info1>>8) & 0x07); 4414 4415 cmd = 0x40000400 | mac_id; 4416 rtw_write32(padapter, REG_HMEBOX_DBG_2_8723B, cmd); 4417 msleep(10); 4418 ra_info1 = rtw_read32(padapter, 0x2F0); 4419 ra_info2 = rtw_read32(padapter, 0x2F4); 4420 rate_mask1 = rtw_read32(padapter, 0x2F8); 4421 rate_mask2 = rtw_read32(padapter, 0x2FC); 4422 hight_rate = ra_info2&0xFF; 4423 lowest_rate = (ra_info2>>8) & 0xFF; 4424 4425 DBG_8192C("[ ra_info1:0x%08x ] =>RSSI =%d, BW_setting = 0x%02x, DISRA = 0x%02x, VHT_EN = 0x%02x\n", 4426 ra_info1, 4427 ra_info1&0xFF, 4428 (ra_info1>>8) & 0xFF, 4429 (ra_info1>>16) & 0xFF, 4430 (ra_info1>>24) & 0xFF); 4431 4432 DBG_8192C("[ ra_info2:0x%08x ] =>hight_rate =%s, lowest_rate =%s, SGI = 0x%02x, RateID =%d\n", 4433 ra_info2, 4434 HDATA_RATE(hight_rate), 4435 HDATA_RATE(lowest_rate), 4436 (ra_info2>>16) & 0xFF, 4437 (ra_info2>>24) & 0xFF); 4438 4439 DBG_8192C("rate_mask2 = 0x%08x, rate_mask1 = 0x%08x\n", rate_mask2, rate_mask1); 4440 4441 } 4442 break; 4443 4444 case HAL_DEF_TX_PAGE_BOUNDARY: 4445 if (!padapter->registrypriv.wifi_spec) { 4446 *(u8 *)pval = TX_PAGE_BOUNDARY_8723B; 4447 } else { 4448 *(u8 *)pval = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B; 4449 } 4450 break; 4451 4452 case HAL_DEF_MACID_SLEEP: 4453 *(u8 *)pval = true; /* support macid sleep */ 4454 break; 4455 4456 default: 4457 bResult = GetHalDefVar(padapter, variable, pval); 4458 break; 4459 } 4460 4461 return bResult; 4462 } 4463 4464 #ifdef CONFIG_WOWLAN 4465 void Hal_DetectWoWMode(struct adapter *padapter) 4466 { 4467 adapter_to_pwrctl(padapter)->bSupportRemoteWakeup = true; 4468 DBG_871X("%s\n", __func__); 4469 } 4470 #endif /* CONFIG_WOWLAN */ 4471 4472 void rtl8723b_start_thread(struct adapter *padapter) 4473 { 4474 #ifndef CONFIG_SDIO_TX_TASKLET 4475 struct xmit_priv *xmitpriv = &padapter->xmitpriv; 4476 4477 xmitpriv->SdioXmitThread = kthread_run(rtl8723bs_xmit_thread, padapter, "RTWHALXT"); 4478 if (IS_ERR(xmitpriv->SdioXmitThread)) { 4479 RT_TRACE(_module_hal_xmit_c_, _drv_err_, ("%s: start rtl8723bs_xmit_thread FAIL!!\n", __func__)); 4480 } 4481 #endif 4482 } 4483 4484 void rtl8723b_stop_thread(struct adapter *padapter) 4485 { 4486 #ifndef CONFIG_SDIO_TX_TASKLET 4487 struct xmit_priv *xmitpriv = &padapter->xmitpriv; 4488 4489 /* stop xmit_buf_thread */ 4490 if (xmitpriv->SdioXmitThread) { 4491 complete(&xmitpriv->SdioXmitStart); 4492 wait_for_completion(&xmitpriv->SdioXmitTerminate); 4493 xmitpriv->SdioXmitThread = NULL; 4494 } 4495 #endif 4496 } 4497 4498 #if defined(CONFIG_CHECK_BT_HANG) 4499 extern void check_bt_status_work(void *data); 4500 void rtl8723bs_init_checkbthang_workqueue(struct adapter *adapter) 4501 { 4502 adapter->priv_checkbt_wq = alloc_workqueue("sdio_wq", 0, 0); 4503 INIT_DELAYED_WORK(&adapter->checkbt_work, (void *)check_bt_status_work); 4504 } 4505 4506 void rtl8723bs_free_checkbthang_workqueue(struct adapter *adapter) 4507 { 4508 if (adapter->priv_checkbt_wq) { 4509 cancel_delayed_work_sync(&adapter->checkbt_work); 4510 flush_workqueue(adapter->priv_checkbt_wq); 4511 destroy_workqueue(adapter->priv_checkbt_wq); 4512 adapter->priv_checkbt_wq = NULL; 4513 } 4514 } 4515 4516 void rtl8723bs_cancle_checkbthang_workqueue(struct adapter *adapter) 4517 { 4518 if (adapter->priv_checkbt_wq) 4519 cancel_delayed_work_sync(&adapter->checkbt_work); 4520 } 4521 4522 void rtl8723bs_hal_check_bt_hang(struct adapter *adapter) 4523 { 4524 if (adapter->priv_checkbt_wq) 4525 queue_delayed_work(adapter->priv_checkbt_wq, &(adapter->checkbt_work), 0); 4526 } 4527 #endif 4528