1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5  *
6  ******************************************************************************/
7 
8 
9 #ifndef __HALHWOUTSRC_H__
10 #define __HALHWOUTSRC_H__
11 
12 
13 /*--------------------------Define -------------------------------------------*/
14 /* define READ_NEXT_PAIR(v1, v2, i) do { i += 2; v1 = Array[i]; v2 = Array[i+1]; } while (0) */
15 #define AGC_DIFF_CONFIG_MP(ic, band) (ODM_ReadAndConfig_MP_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_MP_##ic##_AGC_TAB_DIFF_##band, \
16 	sizeof(Array_MP_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
17 #define AGC_DIFF_CONFIG_TC(ic, band) (ODM_ReadAndConfig_TC_##ic##_AGC_TAB_DIFF(pDM_Odm, Array_TC_##ic##_AGC_TAB_DIFF_##band, \
18 	sizeof(Array_TC_##ic##_AGC_TAB_DIFF_##band)/sizeof(u32)))
19 
20 #define AGC_DIFF_CONFIG(ic, band)\
21 	do {\
22 		if (pDM_Odm->bIsMPChip)\
23 			AGC_DIFF_CONFIG_MP(ic, band);\
24 		else\
25 			AGC_DIFF_CONFIG_TC(ic, band);\
26 	} while (0)
27 
28 
29 /*  */
30 /*  structure and define */
31 /*  */
32 
33 struct phy_rx_agc_info_t {
34 	#if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
35 		u8 gain:7, trsw:1;
36 	#else
37 		u8 trsw:1, gain:7;
38 	#endif
39 };
40 
41 struct phy_status_rpt_8192cd_t {
42 	struct phy_rx_agc_info_t path_agc[2];
43 	u8 ch_corr[2];
44 	u8 cck_sig_qual_ofdm_pwdb_all;
45 	u8 cck_agc_rpt_ofdm_cfosho_a;
46 	u8 cck_rpt_b_ofdm_cfosho_b;
47 	u8 rsvd_1;/* ch_corr_msb; */
48 	u8 noise_power_db_msb;
49 	s8 path_cfotail[2];
50 	u8 pcts_mask[2];
51 	s8 stream_rxevm[2];
52 	u8 path_rxsnr[2];
53 	u8 noise_power_db_lsb;
54 	u8 rsvd_2[3];
55 	u8 stream_csi[2];
56 	u8 stream_target_csi[2];
57 	s8	sig_evm;
58 	u8 rsvd_3;
59 
60 #if (ODM_ENDIAN_TYPE == ODM_ENDIAN_LITTLE)
61 	u8 antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
62 	u8 sgi_en:1;
63 	u8 rxsc:2;
64 	u8 idle_long:1;
65 	u8 r_ant_train_en:1;
66 	u8 ant_sel_b:1;
67 	u8 ant_sel:1;
68 #else	/*  _BIG_ENDIAN_ */
69 	u8 ant_sel:1;
70 	u8 ant_sel_b:1;
71 	u8 r_ant_train_en:1;
72 	u8 idle_long:1;
73 	u8 rxsc:2;
74 	u8 sgi_en:1;
75 	u8 antsel_rx_keep_2:1;	/* ex_intf_flg:1; */
76 #endif
77 };
78 
79 void ODM_PhyStatusQuery(
80 	struct dm_odm_t *pDM_Odm,
81 	struct odm_phy_info *pPhyInfo,
82 	u8 *pPhyStatus,
83 	struct odm_packet_info *pPktinfo
84 );
85 
86 enum hal_status ODM_ConfigRFWithTxPwrTrackHeaderFile(struct dm_odm_t *pDM_Odm);
87 
88 enum hal_status ODM_ConfigRFWithHeaderFile(
89 	struct dm_odm_t *pDM_Odm,
90 	enum ODM_RF_Config_Type ConfigType,
91 	enum odm_rf_radio_path_e eRFPath
92 );
93 
94 enum hal_status ODM_ConfigBBWithHeaderFile(
95 	struct dm_odm_t *pDM_Odm, enum ODM_BB_Config_Type ConfigType
96 );
97 
98 enum hal_status ODM_ConfigFWWithHeaderFile(
99 	struct dm_odm_t *pDM_Odm,
100 	enum ODM_FW_Config_Type ConfigType,
101 	u8 *pFirmware,
102 	u32 *pSize
103 );
104 
105 s32 odm_SignalScaleMapping(struct dm_odm_t *pDM_Odm, s32 CurrSig);
106 
107 #endif
108