1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17 #ifndef __HALDMOUTSRC_H__ 18 #define __HALDMOUTSRC_H__ 19 20 21 #include "odm_EdcaTurboCheck.h" 22 #include "odm_DIG.h" 23 #include "odm_PathDiv.h" 24 #include "odm_DynamicBBPowerSaving.h" 25 #include "odm_DynamicTxPower.h" 26 #include "odm_CfoTracking.h" 27 #include "odm_NoiseMonitor.h" 28 29 #define TP_MODE 0 30 #define RSSI_MODE 1 31 #define TRAFFIC_LOW 0 32 #define TRAFFIC_HIGH 1 33 #define NONE 0 34 35 36 /* 3 Tx Power Tracking */ 37 /* 3 ============================================================ */ 38 #define DPK_DELTA_MAPPING_NUM 13 39 #define index_mapping_HP_NUM 15 40 #define OFDM_TABLE_SIZE 43 41 #define CCK_TABLE_SIZE 33 42 #define TXSCALE_TABLE_SIZE 37 43 #define TXPWR_TRACK_TABLE_SIZE 30 44 #define DELTA_SWINGIDX_SIZE 30 45 #define BAND_NUM 4 46 47 /* 3 PSD Handler */ 48 /* 3 ============================================================ */ 49 50 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 51 #define MODE_40M 0 /* 0:20M, 1:40M */ 52 #define PSD_TH2 3 53 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 54 #define SIR_STEP_SIZE 3 55 #define Smooth_Size_1 5 56 #define Smooth_TH_1 3 57 #define Smooth_Size_2 10 58 #define Smooth_TH_2 4 59 #define Smooth_Size_3 20 60 #define Smooth_TH_3 4 61 #define Smooth_Step_Size 5 62 #define Adaptive_SIR 1 63 #define PSD_RESCAN 4 64 #define PSD_SCAN_INTERVAL 700 /* ms */ 65 66 /* 8723A High Power IGI Setting */ 67 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 68 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 69 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 70 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 71 72 /* ANT Test */ 73 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 74 #define ANTTESTA 0x01 /* Ant A will be Testing */ 75 #define ANTTESTB 0x02 /* Ant B will be testing */ 76 77 #define PS_MODE_ACTIVE 0x01 78 79 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 80 #define MAIN_ANT 1 /* Ant A or Ant Main */ 81 #define AUX_ANT 2 /* AntB or Ant Aux */ 82 #define MAX_ANT 3 /* 3 for AP using */ 83 84 85 /* Antenna Diversity Type */ 86 #define SW_ANTDIV 0 87 #define HW_ANTDIV 1 88 /* structure and define */ 89 90 /* Remove DIG by Yuchen */ 91 92 /* Remoce BB power saving by Yuchn */ 93 94 /* Remove DIG by yuchen */ 95 96 typedef struct _Dynamic_Primary_CCA { 97 u8 PriCCA_flag; 98 u8 intf_flag; 99 u8 intf_type; 100 u8 DupRTS_flag; 101 u8 Monitor_flag; 102 u8 CH_offset; 103 u8 MF_state; 104 } Pri_CCA_T, *pPri_CCA_T; 105 106 typedef struct _Rate_Adaptive_Table_ { 107 u8 firstconnect; 108 } RA_T, *pRA_T; 109 110 typedef struct _RX_High_Power_ { 111 u8 RXHP_flag; 112 u8 PSD_func_trigger; 113 u8 PSD_bitmap_RXHP[80]; 114 u8 Pre_IGI; 115 u8 Cur_IGI; 116 u8 Pre_pw_th; 117 u8 Cur_pw_th; 118 bool First_time_enter; 119 bool RXHP_enable; 120 u8 TP_Mode; 121 RT_TIMER PSDTimer; 122 } RXHP_T, *pRXHP_T; 123 124 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 125 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 126 127 /* This indicates two different the steps. */ 128 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 129 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 130 /* with original RSSI to determine if it is necessary to switch antenna. */ 131 #define SWAW_STEP_PEAK 0 132 #define SWAW_STEP_DETERMINE 1 133 134 #define TP_MODE 0 135 #define RSSI_MODE 1 136 #define TRAFFIC_LOW 0 137 #define TRAFFIC_HIGH 1 138 #define TRAFFIC_UltraLOW 2 139 140 typedef struct _SW_Antenna_Switch_ { 141 u8 Double_chk_flag; 142 u8 try_flag; 143 s32 PreRSSI; 144 u8 CurAntenna; 145 u8 PreAntenna; 146 u8 RSSI_Trying; 147 u8 TestMode; 148 u8 bTriggerAntennaSwitch; 149 u8 SelectAntennaMap; 150 u8 RSSI_target; 151 u8 reset_idx; 152 u16 Single_Ant_Counter; 153 u16 Dual_Ant_Counter; 154 u16 Aux_FailDetec_Counter; 155 u16 Retry_Counter; 156 157 /* Before link Antenna Switch check */ 158 u8 SWAS_NoLink_State; 159 u32 SWAS_NoLink_BK_Reg860; 160 u32 SWAS_NoLink_BK_Reg92c; 161 u32 SWAS_NoLink_BK_Reg948; 162 bool ANTA_ON; /* To indicate Ant A is or not */ 163 bool ANTB_ON; /* To indicate Ant B is on or not */ 164 bool Pre_Aux_FailDetec; 165 bool RSSI_AntDect_bResult; 166 u8 Ant5G; 167 u8 Ant2G; 168 169 s32 RSSI_sum_A; 170 s32 RSSI_sum_B; 171 s32 RSSI_cnt_A; 172 s32 RSSI_cnt_B; 173 174 u64 lastTxOkCnt; 175 u64 lastRxOkCnt; 176 u64 TXByteCnt_A; 177 u64 TXByteCnt_B; 178 u64 RXByteCnt_A; 179 u64 RXByteCnt_B; 180 u8 TrafficLoad; 181 u8 Train_time; 182 u8 Train_time_flag; 183 RT_TIMER SwAntennaSwitchTimer; 184 RT_TIMER SwAntennaSwitchTimer_8723B; 185 u32 PktCnt_SWAntDivByCtrlFrame; 186 bool bSWAntDivByCtrlFrame; 187 } SWAT_T, *pSWAT_T; 188 189 /* Remove Edca by YuChen */ 190 191 192 typedef struct _ODM_RATE_ADAPTIVE { 193 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 194 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 195 bool bUseLdpc; 196 bool bLowerRtsRate; 197 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 198 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 199 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 200 201 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; 202 203 204 #define IQK_MAC_REG_NUM 4 205 #define IQK_ADDA_REG_NUM 16 206 #define IQK_BB_REG_NUM_MAX 10 207 #define IQK_BB_REG_NUM 9 208 #define HP_THERMAL_NUM 8 209 210 #define AVG_THERMAL_NUM 8 211 #define IQK_Matrix_REG_NUM 8 212 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 213 * + Channels_5G_20M_NUM 214 * + Channels_5G 215 */ 216 217 #define DM_Type_ByFW 0 218 #define DM_Type_ByDriver 1 219 220 /* */ 221 /* Declare for common info */ 222 /* */ 223 #define MAX_PATH_NUM_92CS 2 224 #define MAX_PATH_NUM_8188E 1 225 #define MAX_PATH_NUM_8192E 2 226 #define MAX_PATH_NUM_8723B 1 227 #define MAX_PATH_NUM_8812A 2 228 #define MAX_PATH_NUM_8821A 1 229 #define MAX_PATH_NUM_8814A 4 230 #define MAX_PATH_NUM_8822B 2 231 232 233 #define IQK_THRESHOLD 8 234 #define DPK_THRESHOLD 4 235 236 struct odm_phy_info { 237 /* 238 * Be care, if you want to add any element, please insert it between 239 * rx_pwd_ball and signal_strength. 240 */ 241 u8 rx_pwd_ba11; 242 243 u8 signal_quality; /* in 0-100 index. */ 244 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 245 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 246 247 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 248 249 u16 cfo_short[4]; /* per-path's Cfo_short */ 250 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 251 252 s8 rx_power; /* in dBm Translate from PWdB */ 253 254 /* 255 * Real power in dBm for this packet, no beautification and 256 * aggregation. Keep this raw info to be used for the other procedures. 257 */ 258 s8 recv_signal_power; 259 u8 bt_rx_rssi_percentage; 260 u8 signal_strength; /* in 0-100 index. */ 261 262 s8 rx_pwr[4]; /* per-path's pwdb */ 263 264 u8 rx_snr[4]; /* per-path's SNR */ 265 u8 band_width; 266 u8 bt_coex_pwr_adjust; 267 }; 268 269 270 struct odm_packet_info { 271 u8 data_rate; 272 u8 station_id; 273 bool bssid_match; 274 bool to_self; 275 bool is_beacon; 276 }; 277 278 279 typedef struct _ODM_Phy_Dbg_Info_ { 280 /* ODM Write, debug info */ 281 s8 RxSNRdB[4]; 282 u32 NumQryPhyStatus; 283 u32 NumQryPhyStatusCCK; 284 u32 NumQryPhyStatusOFDM; 285 u8 NumQryBeaconPkt; 286 /* Others */ 287 s32 RxEVM[4]; 288 289 } ODM_PHY_DBG_INFO_T; 290 291 292 typedef struct _ODM_Mac_Status_Info_ { 293 u8 test; 294 } ODM_MAC_INFO; 295 296 297 typedef enum tag_Dynamic_ODM_Support_Ability_Type { 298 /* BB Team */ 299 ODM_DIG = 0x00000001, 300 ODM_HIGH_POWER = 0x00000002, 301 ODM_CCK_CCA_TH = 0x00000004, 302 ODM_FA_STATISTICS = 0x00000008, 303 ODM_RAMASK = 0x00000010, 304 ODM_RSSI_MONITOR = 0x00000020, 305 ODM_SW_ANTDIV = 0x00000040, 306 ODM_HW_ANTDIV = 0x00000080, 307 ODM_BB_PWRSV = 0x00000100, 308 ODM_2TPATHDIV = 0x00000200, 309 ODM_1TPATHDIV = 0x00000400, 310 ODM_PSD2AFH = 0x00000800 311 } ODM_Ability_E; 312 313 /* */ 314 /* 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T */ 315 /* Please declare below ODM relative info in your STA info structure. */ 316 /* */ 317 typedef struct _ODM_STA_INFO { 318 /* Driver Write */ 319 bool bUsed; /* record the sta status link or not? */ 320 /* u8 WirelessMode; */ 321 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 322 323 /* ODM Write */ 324 /* 1 PHY_STATUS_INFO */ 325 u8 RSSI_Path[4]; /* */ 326 u8 RSSI_Ave; 327 u8 RXEVM[4]; 328 u8 RXSNR[4]; 329 330 /* ODM Write */ 331 /* 1 TX_INFO (may changed by IC) */ 332 /* TX_INFO_T pTxInfo; Define in IC folder. Move lower layer. */ 333 334 /* */ 335 /* Please use compile flag to disabe the strcutrue for other IC except 88E. */ 336 /* Move To lower layer. */ 337 /* */ 338 /* ODM Write Wilson will handle this part(said by Luke.Lee) */ 339 /* TX_RPT_T pTxRpt; Define in IC folder. Move lower layer. */ 340 } ODM_STA_INFO_T, *PODM_STA_INFO_T; 341 342 /* */ 343 /* 2011/10/20 MH Define Common info enum for all team. */ 344 /* */ 345 typedef enum _ODM_Common_Info_Definition { 346 /* Fixed value: */ 347 348 /* HOOK BEFORE REG INIT----------- */ 349 ODM_CMNINFO_PLATFORM = 0, 350 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 351 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 352 ODM_CMNINFO_MP_TEST_CHIP, 353 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 354 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 355 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 356 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 357 ODM_CMNINFO_RFE_TYPE, 358 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 359 ODM_CMNINFO_PACKAGE_TYPE, 360 ODM_CMNINFO_EXT_LNA, /* true */ 361 ODM_CMNINFO_5G_EXT_LNA, 362 ODM_CMNINFO_EXT_PA, 363 ODM_CMNINFO_5G_EXT_PA, 364 ODM_CMNINFO_GPA, 365 ODM_CMNINFO_APA, 366 ODM_CMNINFO_GLNA, 367 ODM_CMNINFO_ALNA, 368 ODM_CMNINFO_EXT_TRSW, 369 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 370 ODM_CMNINFO_BINHCT_TEST, 371 ODM_CMNINFO_BWIFI_TEST, 372 ODM_CMNINFO_SMART_CONCURRENT, 373 /* HOOK BEFORE REG INIT----------- */ 374 375 376 /* Dynamic value: */ 377 /* POINTER REFERENCE----------- */ 378 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 379 ODM_CMNINFO_TX_UNI, 380 ODM_CMNINFO_RX_UNI, 381 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 382 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 383 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 384 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 385 ODM_CMNINFO_BW, /* ODM_BW_E */ 386 ODM_CMNINFO_CHNL, 387 ODM_CMNINFO_FORCED_RATE, 388 389 ODM_CMNINFO_DMSP_GET_VALUE, 390 ODM_CMNINFO_BUDDY_ADAPTOR, 391 ODM_CMNINFO_DMSP_IS_MASTER, 392 ODM_CMNINFO_SCAN, 393 ODM_CMNINFO_POWER_SAVING, 394 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 395 ODM_CMNINFO_DRV_STOP, 396 ODM_CMNINFO_PNP_IN, 397 ODM_CMNINFO_INIT_ON, 398 ODM_CMNINFO_ANT_TEST, 399 ODM_CMNINFO_NET_CLOSED, 400 ODM_CMNINFO_MP_MODE, 401 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 402 ODM_CMNINFO_FORCED_IGI_LB, 403 ODM_CMNINFO_IS1ANTENNA, 404 ODM_CMNINFO_RFDEFAULTPATH, 405 /* POINTER REFERENCE----------- */ 406 407 /* CALL BY VALUE------------- */ 408 ODM_CMNINFO_WIFI_DIRECT, 409 ODM_CMNINFO_WIFI_DISPLAY, 410 ODM_CMNINFO_LINK_IN_PROGRESS, 411 ODM_CMNINFO_LINK, 412 ODM_CMNINFO_STATION_STATE, 413 ODM_CMNINFO_RSSI_MIN, 414 ODM_CMNINFO_DBG_COMP, /* u64 */ 415 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 416 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 417 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 418 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 419 ODM_CMNINFO_BT_ENABLED, 420 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 421 ODM_CMNINFO_BT_HS_RSSI, 422 ODM_CMNINFO_BT_OPERATION, 423 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 424 ODM_CMNINFO_BT_DISABLE_EDCA, 425 /* CALL BY VALUE------------- */ 426 427 /* Dynamic ptr array hook itms. */ 428 ODM_CMNINFO_STA_STATUS, 429 ODM_CMNINFO_PHY_STATUS, 430 ODM_CMNINFO_MAC_STATUS, 431 432 ODM_CMNINFO_MAX, 433 434 435 } ODM_CMNINFO_E; 436 437 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 438 typedef enum _ODM_Support_Ability_Definition { 439 /* */ 440 /* BB ODM section BIT 0-15 */ 441 /* */ 442 ODM_BB_DIG = BIT0, 443 ODM_BB_RA_MASK = BIT1, 444 ODM_BB_DYNAMIC_TXPWR = BIT2, 445 ODM_BB_FA_CNT = BIT3, 446 ODM_BB_RSSI_MONITOR = BIT4, 447 ODM_BB_CCK_PD = BIT5, 448 ODM_BB_ANT_DIV = BIT6, 449 ODM_BB_PWR_SAVE = BIT7, 450 ODM_BB_PWR_TRAIN = BIT8, 451 ODM_BB_RATE_ADAPTIVE = BIT9, 452 ODM_BB_PATH_DIV = BIT10, 453 ODM_BB_PSD = BIT11, 454 ODM_BB_RXHP = BIT12, 455 ODM_BB_ADAPTIVITY = BIT13, 456 ODM_BB_CFO_TRACKING = BIT14, 457 458 /* MAC DM section BIT 16-23 */ 459 ODM_MAC_EDCA_TURBO = BIT16, 460 ODM_MAC_EARLY_MODE = BIT17, 461 462 /* RF ODM section BIT 24-31 */ 463 ODM_RF_TX_PWR_TRACK = BIT24, 464 ODM_RF_RX_GAIN_TRACK = BIT25, 465 ODM_RF_CALIBRATION = BIT26, 466 } ODM_ABILITY_E; 467 468 /* ODM_CMNINFO_INTERFACE */ 469 typedef enum tag_ODM_Support_Interface_Definition { 470 ODM_ITRF_SDIO = 0x4, 471 ODM_ITRF_ALL = 0x7, 472 } ODM_INTERFACE_E; 473 474 /* ODM_CMNINFO_IC_TYPE */ 475 typedef enum tag_ODM_Support_IC_Type_Definition { 476 ODM_RTL8723B = BIT8, 477 } ODM_IC_TYPE_E; 478 479 /* ODM_CMNINFO_CUT_VER */ 480 typedef enum tag_ODM_Cut_Version_Definition { 481 ODM_CUT_A = 0, 482 ODM_CUT_B = 1, 483 ODM_CUT_C = 2, 484 ODM_CUT_D = 3, 485 ODM_CUT_E = 4, 486 ODM_CUT_F = 5, 487 488 ODM_CUT_I = 8, 489 ODM_CUT_J = 9, 490 ODM_CUT_K = 10, 491 ODM_CUT_TEST = 15, 492 } ODM_CUT_VERSION_E; 493 494 /* ODM_CMNINFO_FAB_VER */ 495 typedef enum tag_ODM_Fab_Version_Definition { 496 ODM_TSMC = 0, 497 ODM_UMC = 1, 498 } ODM_FAB_E; 499 500 /* ODM_CMNINFO_RF_TYPE */ 501 /* */ 502 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 503 /* */ 504 typedef enum tag_ODM_RF_Path_Bit_Definition { 505 ODM_RF_TX_A = BIT0, 506 ODM_RF_TX_B = BIT1, 507 ODM_RF_TX_C = BIT2, 508 ODM_RF_TX_D = BIT3, 509 ODM_RF_RX_A = BIT4, 510 ODM_RF_RX_B = BIT5, 511 ODM_RF_RX_C = BIT6, 512 ODM_RF_RX_D = BIT7, 513 } ODM_RF_PATH_E; 514 515 516 typedef enum tag_ODM_RF_Type_Definition { 517 ODM_1T1R = 0, 518 ODM_1T2R = 1, 519 ODM_2T2R = 2, 520 ODM_2T3R = 3, 521 ODM_2T4R = 4, 522 ODM_3T3R = 5, 523 ODM_3T4R = 6, 524 ODM_4T4R = 7, 525 } ODM_RF_TYPE_E; 526 527 528 /* */ 529 /* ODM Dynamic common info value definition */ 530 /* */ 531 532 /* typedef enum _MACPHY_MODE_8192D{ */ 533 /* SINGLEMAC_SINGLEPHY, */ 534 /* DUALMAC_DUALPHY, */ 535 /* DUALMAC_SINGLEPHY, */ 536 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */ 537 /* Above is the original define in MP driver. Please use the same define. THX. */ 538 typedef enum tag_ODM_MAC_PHY_Mode_Definition { 539 ODM_SMSP = 0, 540 ODM_DMSP = 1, 541 ODM_DMDP = 2, 542 } ODM_MAC_PHY_MODE_E; 543 544 545 typedef enum tag_BT_Coexist_Definition { 546 ODM_BT_BUSY = 1, 547 ODM_BT_ON = 2, 548 ODM_BT_OFF = 3, 549 ODM_BT_NONE = 4, 550 } ODM_BT_COEXIST_E; 551 552 /* ODM_CMNINFO_OP_MODE */ 553 typedef enum tag_Operation_Mode_Definition { 554 ODM_NO_LINK = BIT0, 555 ODM_LINK = BIT1, 556 ODM_SCAN = BIT2, 557 ODM_POWERSAVE = BIT3, 558 ODM_AP_MODE = BIT4, 559 ODM_CLIENT_MODE = BIT5, 560 ODM_AD_HOC = BIT6, 561 ODM_WIFI_DIRECT = BIT7, 562 ODM_WIFI_DISPLAY = BIT8, 563 } ODM_OPERATION_MODE_E; 564 565 /* ODM_CMNINFO_WM_MODE */ 566 typedef enum tag_Wireless_Mode_Definition { 567 ODM_WM_UNKNOW = 0x0, 568 ODM_WM_B = BIT0, 569 ODM_WM_G = BIT1, 570 ODM_WM_A = BIT2, 571 ODM_WM_N24G = BIT3, 572 ODM_WM_N5G = BIT4, 573 ODM_WM_AUTO = BIT5, 574 ODM_WM_AC = BIT6, 575 } ODM_WIRELESS_MODE_E; 576 577 /* ODM_CMNINFO_BAND */ 578 typedef enum tag_Band_Type_Definition { 579 ODM_BAND_2_4G = 0, 580 ODM_BAND_5G, 581 ODM_BAND_ON_BOTH, 582 ODM_BANDMAX 583 } ODM_BAND_TYPE_E; 584 585 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 586 typedef enum tag_Secondary_Channel_Offset_Definition { 587 ODM_DONT_CARE = 0, 588 ODM_BELOW = 1, 589 ODM_ABOVE = 2 590 } ODM_SEC_CHNL_OFFSET_E; 591 592 /* ODM_CMNINFO_SEC_MODE */ 593 typedef enum tag_Security_Definition { 594 ODM_SEC_OPEN = 0, 595 ODM_SEC_WEP40 = 1, 596 ODM_SEC_TKIP = 2, 597 ODM_SEC_RESERVE = 3, 598 ODM_SEC_AESCCMP = 4, 599 ODM_SEC_WEP104 = 5, 600 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 601 ODM_SEC_SMS4 = 7, 602 } ODM_SECURITY_E; 603 604 /* ODM_CMNINFO_BW */ 605 typedef enum tag_Bandwidth_Definition { 606 ODM_BW20M = 0, 607 ODM_BW40M = 1, 608 ODM_BW80M = 2, 609 ODM_BW160M = 3, 610 ODM_BW10M = 4, 611 } ODM_BW_E; 612 613 614 /* ODM_CMNINFO_BOARD_TYPE */ 615 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 616 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 617 typedef enum tag_Board_Definition { 618 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 619 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ 620 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ 621 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ 622 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 623 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 624 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ 625 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 626 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 627 } ODM_BOARD_TYPE_E; 628 629 typedef enum tag_ODM_Package_Definition { 630 ODM_PACKAGE_DEFAULT = 0, 631 ODM_PACKAGE_QFN68 = BIT(0), 632 ODM_PACKAGE_TFBGA90 = BIT(1), 633 ODM_PACKAGE_TFBGA79 = BIT(2), 634 } ODM_Package_TYPE_E; 635 636 typedef enum tag_ODM_TYPE_GPA_Definition { 637 TYPE_GPA0 = 0, 638 TYPE_GPA1 = BIT(1)|BIT(0) 639 } ODM_TYPE_GPA_E; 640 641 typedef enum tag_ODM_TYPE_APA_Definition { 642 TYPE_APA0 = 0, 643 TYPE_APA1 = BIT(1)|BIT(0) 644 } ODM_TYPE_APA_E; 645 646 typedef enum tag_ODM_TYPE_GLNA_Definition { 647 TYPE_GLNA0 = 0, 648 TYPE_GLNA1 = BIT(2)|BIT(0), 649 TYPE_GLNA2 = BIT(3)|BIT(1), 650 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 651 } ODM_TYPE_GLNA_E; 652 653 typedef enum tag_ODM_TYPE_ALNA_Definition { 654 TYPE_ALNA0 = 0, 655 TYPE_ALNA1 = BIT(2)|BIT(0), 656 TYPE_ALNA2 = BIT(3)|BIT(1), 657 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 658 } ODM_TYPE_ALNA_E; 659 660 /* ODM_CMNINFO_ONE_PATH_CCA */ 661 typedef enum tag_CCA_Path { 662 ODM_CCA_2R = 0, 663 ODM_CCA_1R_A = 1, 664 ODM_CCA_1R_B = 2, 665 } ODM_CCA_PATH_E; 666 667 668 typedef struct _ODM_RA_Info_ { 669 u8 RateID; 670 u32 RateMask; 671 u32 RAUseRate; 672 u8 RateSGI; 673 u8 RssiStaRA; 674 u8 PreRssiStaRA; 675 u8 SGIEnable; 676 u8 DecisionRate; 677 u8 PreRate; 678 u8 HighestRate; 679 u8 LowestRate; 680 u32 NscUp; 681 u32 NscDown; 682 u16 RTY[5]; 683 u32 TOTAL; 684 u16 DROP; 685 u8 Active; 686 u16 RptTime; 687 u8 RAWaitingCounter; 688 u8 RAPendingCounter; 689 u8 PTActive; /* on or off */ 690 u8 PTTryState; /* 0 trying state, 1 for decision state */ 691 u8 PTStage; /* 0~6 */ 692 u8 PTStopCount; /* Stop PT counter */ 693 u8 PTPreRate; /* if rate change do PT */ 694 u8 PTPreRssi; /* if RSSI change 5% do PT */ 695 u8 PTModeSS; /* decide whitch rate should do PT */ 696 u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ 697 u8 PTSmoothFactor; 698 } ODM_RA_INFO_T, *PODM_RA_INFO_T; 699 700 typedef struct _IQK_MATRIX_REGS_SETTING { 701 bool bIQKDone; 702 s32 Value[3][IQK_Matrix_REG_NUM]; 703 bool bBWIqkResultSaved[3]; 704 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING; 705 706 707 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 708 709 typedef struct ODM_RF_Calibration_Structure { 710 /* for tx power tracking */ 711 712 u32 RegA24; /* for TempCCK */ 713 s32 RegE94; 714 s32 RegE9C; 715 s32 RegEB4; 716 s32 RegEBC; 717 718 u8 TXPowercount; 719 bool bTXPowerTrackingInit; 720 bool bTXPowerTracking; 721 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 722 u8 TM_Trigger; 723 u8 InternalPA5G[2]; /* pathA / pathB */ 724 725 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 726 u8 ThermalValue; 727 u8 ThermalValue_LCK; 728 u8 ThermalValue_IQK; 729 u8 ThermalValue_DPK; 730 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 731 u8 ThermalValue_AVG_index; 732 u8 ThermalValue_RxGain; 733 u8 ThermalValue_Crystal; 734 u8 ThermalValue_DPKstore; 735 u8 ThermalValue_DPKtrack; 736 bool TxPowerTrackingInProgress; 737 738 bool bReloadtxpowerindex; 739 u8 bRfPiEnable; 740 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 741 742 743 /* Tx power Tracking ------------------------- */ 744 u8 bCCKinCH14; 745 u8 CCK_index; 746 u8 OFDM_index[MAX_RF_PATH]; 747 s8 PowerIndexOffset[MAX_RF_PATH]; 748 s8 DeltaPowerIndex[MAX_RF_PATH]; 749 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 750 bool bTxPowerChanged; 751 752 u8 ThermalValue_HP[HP_THERMAL_NUM]; 753 u8 ThermalValue_HP_index; 754 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 755 bool bNeedIQK; 756 bool bIQKInProgress; 757 u8 Delta_IQK; 758 u8 Delta_LCK; 759 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 760 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 761 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 762 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 763 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 764 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 765 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 766 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 767 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 768 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 769 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 770 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 771 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 772 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 773 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 774 775 /* */ 776 777 /* for IQK */ 778 u32 RegC04; 779 u32 Reg874; 780 u32 RegC08; 781 u32 RegB68; 782 u32 RegB6C; 783 u32 Reg870; 784 u32 Reg860; 785 u32 Reg864; 786 787 bool bIQKInitialized; 788 bool bLCKInProgress; 789 bool bAntennaDetected; 790 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 791 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 792 u32 IQK_BB_backup_recover[9]; 793 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 794 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 795 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 796 797 798 /* for APK */ 799 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 800 u8 bAPKdone; 801 u8 bAPKThermalMeterIgnore; 802 803 /* DPK */ 804 bool bDPKFail; 805 u8 bDPdone; 806 u8 bDPPathAOK; 807 u8 bDPPathBOK; 808 809 u32 TxLOK[2]; 810 811 } ODM_RF_CAL_T, *PODM_RF_CAL_T; 812 /* */ 813 /* ODM Dynamic common info value definition */ 814 /* */ 815 816 typedef struct _FAST_ANTENNA_TRAINNING_ { 817 u8 Bssid[6]; 818 u8 antsel_rx_keep_0; 819 u8 antsel_rx_keep_1; 820 u8 antsel_rx_keep_2; 821 u8 antsel_rx_keep_3; 822 u32 antSumRSSI[7]; 823 u32 antRSSIcnt[7]; 824 u32 antAveRSSI[7]; 825 u8 FAT_State; 826 u32 TrainIdx; 827 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 828 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 829 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 830 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 831 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 832 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 833 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 834 u8 RxIdleAnt; 835 bool bBecomeLinked; 836 u32 MinMaxRSSI; 837 u8 idx_AntDiv_counter_2G; 838 u8 idx_AntDiv_counter_5G; 839 u32 AntDiv_2G_5G; 840 u32 CCK_counter_main; 841 u32 CCK_counter_aux; 842 u32 OFDM_counter_main; 843 u32 OFDM_counter_aux; 844 845 846 u32 CCK_CtrlFrame_Cnt_main; 847 u32 CCK_CtrlFrame_Cnt_aux; 848 u32 OFDM_CtrlFrame_Cnt_main; 849 u32 OFDM_CtrlFrame_Cnt_aux; 850 u32 MainAnt_CtrlFrame_Sum; 851 u32 AuxAnt_CtrlFrame_Sum; 852 u32 MainAnt_CtrlFrame_Cnt; 853 u32 AuxAnt_CtrlFrame_Cnt; 854 855 } FAT_T, *pFAT_T; 856 857 typedef enum _FAT_STATE { 858 FAT_NORMAL_STATE = 0, 859 FAT_TRAINING_STATE = 1, 860 } FAT_STATE_E, *PFAT_STATE_E; 861 862 typedef enum _ANT_DIV_TYPE { 863 NO_ANTDIV = 0xFF, 864 CG_TRX_HW_ANTDIV = 0x01, 865 CGCS_RX_HW_ANTDIV = 0x02, 866 FIXED_HW_ANTDIV = 0x03, 867 CG_TRX_SMART_ANTDIV = 0x04, 868 CGCS_RX_SW_ANTDIV = 0x05, 869 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 870 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; 871 872 typedef struct _ODM_PATH_DIVERSITY_ { 873 u8 RespTxPath; 874 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 875 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 876 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 877 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 878 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 879 } PATHDIV_T, *pPATHDIV_T; 880 881 882 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ 883 PHY_REG_PG_RELATIVE_VALUE = 0, 884 PHY_REG_PG_EXACT_VALUE = 1 885 } PHY_REG_PG_TYPE; 886 887 888 /* */ 889 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 890 /* */ 891 typedef struct _ANT_DETECTED_INFO { 892 bool bAntDetected; 893 u32 dBForAntA; 894 u32 dBForAntB; 895 u32 dBForAntO; 896 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO; 897 898 /* */ 899 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 900 /* */ 901 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure { 902 /* RT_TIMER FastAntTrainingTimer; */ 903 /* */ 904 /* Add for different team use temporarily */ 905 /* */ 906 struct adapter *Adapter; /* For CE/NIC team */ 907 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 908 bool odm_ready; 909 910 PHY_REG_PG_TYPE PhyRegPgValueType; 911 u8 PhyRegPgVersion; 912 913 u64 DebugComponents; 914 u32 DebugLevel; 915 916 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 917 u32 LastNumQryPhyStatusAll; 918 u32 RxPWDBAve; 919 bool MPDIG_2G; /* off MPDIG */ 920 u8 Times_2G; 921 922 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 923 bool bCckHighPower; 924 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 925 u8 ControlChannel; 926 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 927 928 /* REMOVED COMMON INFO---------- */ 929 /* u8 PseudoMacPhyMode; */ 930 /* bool *BTCoexist; */ 931 /* bool PseudoBtCoexist; */ 932 /* u8 OPMode; */ 933 /* bool bAPMode; */ 934 /* bool bClientMode; */ 935 /* bool bAdHocMode; */ 936 /* bool bSlaveOfDMSP; */ 937 /* REMOVED COMMON INFO---------- */ 938 939 940 /* 1 COMMON INFORMATION */ 941 942 /* */ 943 /* Init Value */ 944 /* */ 945 /* HOOK BEFORE REG INIT----------- */ 946 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 947 u8 SupportPlatform; 948 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ?K?K = 1/2/3/?K */ 949 u32 SupportAbility; 950 /* ODM PCIE/USB/SDIO = 1/2/3 */ 951 u8 SupportInterface; 952 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 953 u32 SupportICType; 954 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 955 u8 CutVersion; 956 /* Fab Version TSMC/UMC = 0/1 */ 957 u8 FabVersion; 958 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 959 u8 RFType; 960 u8 RFEType; 961 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 962 u8 BoardType; 963 u8 PackageType; 964 u8 TypeGLNA; 965 u8 TypeGPA; 966 u8 TypeALNA; 967 u8 TypeAPA; 968 /* with external LNA NO/Yes = 0/1 */ 969 u8 ExtLNA; 970 u8 ExtLNA5G; 971 /* with external PA NO/Yes = 0/1 */ 972 u8 ExtPA; 973 u8 ExtPA5G; 974 /* with external TRSW NO/Yes = 0/1 */ 975 u8 ExtTRSW; 976 u8 PatchID; /* Customer ID */ 977 bool bInHctTest; 978 bool bWIFITest; 979 980 bool bDualMacSmartConcurrent; 981 u32 BK_SupportAbility; 982 u8 AntDivType; 983 /* HOOK BEFORE REG INIT----------- */ 984 985 /* */ 986 /* Dynamic Value */ 987 /* */ 988 /* POINTER REFERENCE----------- */ 989 990 u8 u8_temp; 991 bool bool_temp; 992 struct adapter *adapter_temp; 993 994 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 995 u8 *pMacPhyMode; 996 /* TX Unicast byte count */ 997 u64 *pNumTxBytesUnicast; 998 /* RX Unicast byte count */ 999 u64 *pNumRxBytesUnicast; 1000 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 1001 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 1002 /* Frequence band 2.4G/5G = 0/1 */ 1003 u8 *pBandType; 1004 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 1005 u8 *pSecChOffset; 1006 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 1007 u8 *pSecurity; 1008 /* BW info 20M/40M/80M = 0/1/2 */ 1009 u8 *pBandWidth; 1010 /* Central channel location Ch1/Ch2/.... */ 1011 u8 *pChannel; /* central channel number */ 1012 bool DPK_Done; 1013 /* Common info for 92D DMSP */ 1014 1015 bool *pbGetValueFromOtherMac; 1016 struct adapter **pBuddyAdapter; 1017 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 1018 /* Common info for Status */ 1019 bool *pbScanInProcess; 1020 bool *pbPowerSaving; 1021 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 1022 u8 *pOnePathCCA; 1023 /* pMgntInfo->AntennaTest */ 1024 u8 *pAntennaTest; 1025 bool *pbNet_closed; 1026 u8 *mp_mode; 1027 /* u8 *pAidMap; */ 1028 u8 *pu1ForcedIgiLb; 1029 /* For 8723B IQK----------- */ 1030 bool *pIs1Antenna; 1031 u8 *pRFDefaultPath; 1032 /* 0:S1, 1:S0 */ 1033 1034 /* POINTER REFERENCE----------- */ 1035 u16 *pForcedDataRate; 1036 /* CALL BY VALUE------------- */ 1037 bool bLinkInProcess; 1038 bool bWIFI_Direct; 1039 bool bWIFI_Display; 1040 bool bLinked; 1041 1042 bool bsta_state; 1043 u8 RSSI_Min; 1044 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 1045 bool bIsMPChip; 1046 bool bOneEntryOnly; 1047 /* Common info for BTDM */ 1048 bool bBtEnabled; /* BT is disabled */ 1049 bool bBtConnectProcess; /* BT HS is under connection progress. */ 1050 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 1051 bool bBtHsOperation; /* BT HS mode is under progress */ 1052 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 1053 bool bBtLimitedDig; /* BT is busy. */ 1054 /* CALL BY VALUE------------- */ 1055 u8 RSSI_A; 1056 u8 RSSI_B; 1057 u64 RSSI_TRSW; 1058 u64 RSSI_TRSW_H; 1059 u64 RSSI_TRSW_L; 1060 u64 RSSI_TRSW_iso; 1061 1062 u8 RxRate; 1063 bool bNoisyState; 1064 u8 TxRate; 1065 u8 LinkedInterval; 1066 u8 preChannel; 1067 u32 TxagcOffsetValueA; 1068 bool IsTxagcOffsetPositiveA; 1069 u32 TxagcOffsetValueB; 1070 bool IsTxagcOffsetPositiveB; 1071 u64 lastTxOkCnt; 1072 u64 lastRxOkCnt; 1073 u32 BbSwingOffsetA; 1074 bool IsBbSwingOffsetPositiveA; 1075 u32 BbSwingOffsetB; 1076 bool IsBbSwingOffsetPositiveB; 1077 s8 TH_L2H_ini; 1078 s8 TH_EDCCA_HL_diff; 1079 s8 IGI_Base; 1080 u8 IGI_target; 1081 bool ForceEDCCA; 1082 u8 AdapEn_RSSI; 1083 s8 Force_TH_H; 1084 s8 Force_TH_L; 1085 u8 IGI_LowerBound; 1086 u8 antdiv_rssi; 1087 u8 AntType; 1088 u8 pre_AntType; 1089 u8 antdiv_period; 1090 u8 antdiv_select; 1091 u8 NdpaPeriod; 1092 bool H2C_RARpt_connect; 1093 1094 /* add by Yu Cehn for adaptivtiy */ 1095 bool adaptivity_flag; 1096 bool NHM_disable; 1097 bool TxHangFlg; 1098 bool Carrier_Sense_enable; 1099 u8 tolerance_cnt; 1100 u64 NHMCurTxOkcnt; 1101 u64 NHMCurRxOkcnt; 1102 u64 NHMLastTxOkcnt; 1103 u64 NHMLastRxOkcnt; 1104 u8 txEdcca1; 1105 u8 txEdcca0; 1106 s8 H2L_lb; 1107 s8 L2H_lb; 1108 u8 Adaptivity_IGI_upper; 1109 u8 NHM_cnt_0; 1110 1111 1112 ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 1113 /* */ 1114 /* 2 Define STA info. */ 1115 /* _ODM_STA_INFO */ 1116 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 1117 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 1118 1119 /* */ 1120 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 1121 /* We need to colelct all support abilit to a proper area. */ 1122 /* */ 1123 bool RaSupport88E; 1124 1125 /* Define ........... */ 1126 1127 /* Latest packet phy info (ODM write) */ 1128 ODM_PHY_DBG_INFO_T PhyDbgInfo; 1129 /* PHY_INFO_88E PhyInfo; */ 1130 1131 /* Latest packet phy info (ODM write) */ 1132 ODM_MAC_INFO *pMacInfo; 1133 /* MAC_INFO_88E MacInfo; */ 1134 1135 /* Different Team independt structure?? */ 1136 1137 /* */ 1138 /* TX_RTP_CMN TX_retrpo; */ 1139 /* TX_RTP_88E TX_retrpo; */ 1140 /* TX_RTP_8195 TX_retrpo; */ 1141 1142 /* */ 1143 /* ODM Structure */ 1144 /* */ 1145 FAT_T DM_FatTable; 1146 DIG_T DM_DigTable; 1147 PS_T DM_PSTable; 1148 Pri_CCA_T DM_PriCCA; 1149 RXHP_T DM_RXHP_Table; 1150 RA_T DM_RA_Table; 1151 false_ALARM_STATISTICS FalseAlmCnt; 1152 false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 1153 SWAT_T DM_SWAT_Table; 1154 bool RSSI_test; 1155 CFO_TRACKING DM_CfoTrack; 1156 1157 EDCA_T DM_EDCA_Table; 1158 u32 WMMEDCA_BE; 1159 PATHDIV_T DM_PathDiv; 1160 /* Copy from SD4 structure */ 1161 /* */ 1162 /* ================================================== */ 1163 /* */ 1164 1165 /* common */ 1166 /* u8 DM_Type; */ 1167 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 1168 /* u8 PSD_func_flag; Add By Gary */ 1169 /* for DIG */ 1170 /* u8 bDMInitialGainEnable; */ 1171 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 1172 /* for Antenna diversity */ 1173 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 1174 /* PSTA_INFO_T RSSI_target; */ 1175 1176 bool *pbDriverStopped; 1177 bool *pbDriverIsGoingToPnpSetPowerSleep; 1178 bool *pinit_adpt_in_progress; 1179 1180 /* PSD */ 1181 bool bUserAssignLevel; 1182 RT_TIMER PSDTimer; 1183 u8 RSSI_BT; /* come from BT */ 1184 bool bPSDinProcess; 1185 bool bPSDactive; 1186 bool bDMInitialGainEnable; 1187 1188 /* MPT DIG */ 1189 RT_TIMER MPT_DIGTimer; 1190 1191 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 1192 u8 bUseRAMask; 1193 1194 ODM_RATE_ADAPTIVE RateAdaptive; 1195 1196 ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool */ 1197 1198 ODM_RF_CAL_T RFCalibrateInfo; 1199 1200 /* */ 1201 /* TX power tracking */ 1202 /* */ 1203 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 1204 u8 BbSwingIdxOfdmCurrent; 1205 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 1206 bool BbSwingFlagOfdm; 1207 u8 BbSwingIdxCck; 1208 u8 BbSwingIdxCckCurrent; 1209 u8 BbSwingIdxCckBase; 1210 u8 DefaultOfdmIndex; 1211 u8 DefaultCckIndex; 1212 bool BbSwingFlagCck; 1213 1214 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 1215 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 1216 s8 Remnant_CCKSwingIdx; 1217 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 1218 bool Modify_TxAGC_Flag_PathA; 1219 bool Modify_TxAGC_Flag_PathB; 1220 bool Modify_TxAGC_Flag_PathC; 1221 bool Modify_TxAGC_Flag_PathD; 1222 bool Modify_TxAGC_Flag_PathA_CCK; 1223 1224 s8 KfreeOffset[MAX_RF_PATH]; 1225 /* */ 1226 /* ODM system resource. */ 1227 /* */ 1228 1229 /* ODM relative time. */ 1230 RT_TIMER PathDivSwitchTimer; 1231 /* 2011.09.27 add for Path Diversity */ 1232 RT_TIMER CCKPathDiversityTimer; 1233 RT_TIMER FastAntTrainingTimer; 1234 1235 /* ODM relative workitem. */ 1236 1237 #if (BEAMFORMING_SUPPORT == 1) 1238 RT_BEAMFORMING_INFO BeamformingInfo; 1239 #endif 1240 } DM_ODM_T, *PDM_ODM_T; /* DM_Dynamic_Mechanism_Structure */ 1241 1242 #define ODM_RF_PATH_MAX 2 1243 1244 typedef enum _ODM_RF_RADIO_PATH { 1245 ODM_RF_PATH_A = 0, /* Radio Path A */ 1246 ODM_RF_PATH_B = 1, /* Radio Path B */ 1247 ODM_RF_PATH_C = 2, /* Radio Path C */ 1248 ODM_RF_PATH_D = 3, /* Radio Path D */ 1249 ODM_RF_PATH_AB, 1250 ODM_RF_PATH_AC, 1251 ODM_RF_PATH_AD, 1252 ODM_RF_PATH_BC, 1253 ODM_RF_PATH_BD, 1254 ODM_RF_PATH_CD, 1255 ODM_RF_PATH_ABC, 1256 ODM_RF_PATH_ACD, 1257 ODM_RF_PATH_BCD, 1258 ODM_RF_PATH_ABCD, 1259 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1260 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; 1261 1262 typedef enum _ODM_RF_CONTENT { 1263 odm_radioa_txt = 0x1000, 1264 odm_radiob_txt = 0x1001, 1265 odm_radioc_txt = 0x1002, 1266 odm_radiod_txt = 0x1003 1267 } ODM_RF_CONTENT; 1268 1269 typedef enum _ODM_BB_Config_Type { 1270 CONFIG_BB_PHY_REG, 1271 CONFIG_BB_AGC_TAB, 1272 CONFIG_BB_AGC_TAB_2G, 1273 CONFIG_BB_AGC_TAB_5G, 1274 CONFIG_BB_PHY_REG_PG, 1275 CONFIG_BB_PHY_REG_MP, 1276 CONFIG_BB_AGC_TAB_DIFF, 1277 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1278 1279 typedef enum _ODM_RF_Config_Type { 1280 CONFIG_RF_RADIO, 1281 CONFIG_RF_TXPWR_LMT, 1282 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1283 1284 typedef enum _ODM_FW_Config_Type { 1285 CONFIG_FW_NIC, 1286 CONFIG_FW_NIC_2, 1287 CONFIG_FW_AP, 1288 CONFIG_FW_WoWLAN, 1289 CONFIG_FW_WoWLAN_2, 1290 CONFIG_FW_AP_WoWLAN, 1291 CONFIG_FW_BT, 1292 } ODM_FW_Config_Type; 1293 1294 /* Status code */ 1295 typedef enum _RT_STATUS { 1296 RT_STATUS_SUCCESS, 1297 RT_STATUS_FAILURE, 1298 RT_STATUS_PENDING, 1299 RT_STATUS_RESOURCE, 1300 RT_STATUS_INVALID_CONTEXT, 1301 RT_STATUS_INVALID_PARAMETER, 1302 RT_STATUS_NOT_SUPPORT, 1303 RT_STATUS_OS_API_FAILED, 1304 } RT_STATUS, *PRT_STATUS; 1305 1306 #ifdef REMOVE_PACK 1307 #pragma pack() 1308 #endif 1309 1310 /* include "odm_function.h" */ 1311 1312 /* 3 =========================================================== */ 1313 /* 3 DIG */ 1314 /* 3 =========================================================== */ 1315 1316 /* Remove DIG by Yuchen */ 1317 1318 /* 3 =========================================================== */ 1319 /* 3 AGC RX High Power Mode */ 1320 /* 3 =========================================================== */ 1321 #define LNA_Low_Gain_1 0x64 1322 #define LNA_Low_Gain_2 0x5A 1323 #define LNA_Low_Gain_3 0x58 1324 1325 #define FA_RXHP_TH1 5000 1326 #define FA_RXHP_TH2 1500 1327 #define FA_RXHP_TH3 800 1328 #define FA_RXHP_TH4 600 1329 #define FA_RXHP_TH5 500 1330 1331 /* 3 =========================================================== */ 1332 /* 3 EDCA */ 1333 /* 3 =========================================================== */ 1334 1335 /* 3 =========================================================== */ 1336 /* 3 Dynamic Tx Power */ 1337 /* 3 =========================================================== */ 1338 /* Dynamic Tx Power Control Threshold */ 1339 1340 /* 3 =========================================================== */ 1341 /* 3 Rate Adaptive */ 1342 /* 3 =========================================================== */ 1343 #define DM_RATR_STA_INIT 0 1344 #define DM_RATR_STA_HIGH 1 1345 #define DM_RATR_STA_MIDDLE 2 1346 #define DM_RATR_STA_LOW 3 1347 1348 /* 3 =========================================================== */ 1349 /* 3 BB Power Save */ 1350 /* 3 =========================================================== */ 1351 1352 typedef enum tag_1R_CCA_Type_Definition { 1353 CCA_1R = 0, 1354 CCA_2R = 1, 1355 CCA_MAX = 2, 1356 } DM_1R_CCA_E; 1357 1358 typedef enum tag_RF_Type_Definition { 1359 RF_Save = 0, 1360 RF_Normal = 1, 1361 RF_MAX = 2, 1362 } DM_RF_E; 1363 1364 /* 3 =========================================================== */ 1365 /* 3 Antenna Diversity */ 1366 /* 3 =========================================================== */ 1367 typedef enum tag_SW_Antenna_Switch_Definition { 1368 Antenna_A = 1, 1369 Antenna_B = 2, 1370 Antenna_MAX = 3, 1371 } DM_SWAS_E; 1372 1373 1374 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1375 #define MAX_ANTENNA_DETECTION_CNT 10 1376 1377 /* */ 1378 /* Extern Global Variables. */ 1379 /* */ 1380 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1381 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1382 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1383 1384 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1385 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1386 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1387 1388 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1389 1390 /* */ 1391 /* check Sta pointer valid or not */ 1392 /* */ 1393 #define IS_STA_VALID(pSta) (pSta) 1394 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1395 /* This indicates two different the steps. */ 1396 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1397 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1398 /* with original RSSI to determine if it is necessary to switch antenna. */ 1399 #define SWAW_STEP_PEAK 0 1400 #define SWAW_STEP_DETERMINE 1 1401 1402 /* Remove DIG by yuchen */ 1403 1404 void ODM_SetAntenna(PDM_ODM_T pDM_Odm, u8 Antenna); 1405 1406 1407 /* Remove BB power saving by Yuchen */ 1408 1409 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1410 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm); 1411 1412 bool ODM_RAStateCheck( 1413 PDM_ODM_T pDM_Odm, 1414 s32 RSSI, 1415 bool bForceUpdate, 1416 u8 *pRATRState 1417 ); 1418 1419 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1420 void ODM_SwAntDivChkPerPktRssi( 1421 PDM_ODM_T pDM_Odm, 1422 u8 StationID, 1423 struct odm_phy_info *pPhyInfo 1424 ); 1425 1426 u32 ODM_Get_Rate_Bitmap( 1427 PDM_ODM_T pDM_Odm, 1428 u32 macid, 1429 u32 ra_mask, 1430 u8 rssi_level 1431 ); 1432 1433 #if (BEAMFORMING_SUPPORT == 1) 1434 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1435 #endif 1436 1437 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm); 1438 1439 void ODM_DMInit(PDM_ODM_T pDM_Odm); 1440 1441 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /* For common use in the future */ 1442 1443 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value); 1444 1445 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue); 1446 1447 void ODM_CmnInfoPtrArrayHook( 1448 PDM_ODM_T pDM_Odm, 1449 ODM_CMNINFO_E CmnInfo, 1450 u16 Index, 1451 void *pValue 1452 ); 1453 1454 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value); 1455 1456 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm); 1457 1458 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm); 1459 1460 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm); 1461 1462 void ODM_AntselStatistics_88C( 1463 PDM_ODM_T pDM_Odm, 1464 u8 MacId, 1465 u32 PWDBAll, 1466 bool isCCKrate 1467 ); 1468 1469 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State); 1470 1471 #endif 1472