1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_DynamicBBPowerSaving.h" 15 #include "odm_DynamicTxPower.h" 16 #include "odm_CfoTracking.h" 17 #include "odm_NoiseMonitor.h" 18 19 #define TP_MODE 0 20 #define RSSI_MODE 1 21 #define TRAFFIC_LOW 0 22 #define TRAFFIC_HIGH 1 23 #define NONE 0 24 25 /* 3 Tx Power Tracking */ 26 /* 3 ============================================================ */ 27 #define DPK_DELTA_MAPPING_NUM 13 28 #define index_mapping_HP_NUM 15 29 #define OFDM_TABLE_SIZE 43 30 #define CCK_TABLE_SIZE 33 31 #define TXSCALE_TABLE_SIZE 37 32 #define TXPWR_TRACK_TABLE_SIZE 30 33 #define DELTA_SWINGIDX_SIZE 30 34 #define BAND_NUM 4 35 36 /* 3 PSD Handler */ 37 /* 3 ============================================================ */ 38 39 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 40 #define MODE_40M 0 /* 0:20M, 1:40M */ 41 #define PSD_TH2 3 42 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 43 #define SIR_STEP_SIZE 3 44 #define Smooth_Size_1 5 45 #define Smooth_TH_1 3 46 #define Smooth_Size_2 10 47 #define Smooth_TH_2 4 48 #define Smooth_Size_3 20 49 #define Smooth_TH_3 4 50 #define Smooth_Step_Size 5 51 #define Adaptive_SIR 1 52 #define PSD_RESCAN 4 53 #define PSD_SCAN_INTERVAL 700 /* ms */ 54 55 /* 8723A High Power IGI Setting */ 56 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 57 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 58 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 59 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 60 61 /* ANT Test */ 62 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 63 #define ANTTESTA 0x01 /* Ant A will be Testing */ 64 #define ANTTESTB 0x02 /* Ant B will be testing */ 65 66 #define PS_MODE_ACTIVE 0x01 67 68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 69 #define MAIN_ANT 1 /* Ant A or Ant Main */ 70 #define AUX_ANT 2 /* AntB or Ant Aux */ 71 #define MAX_ANT 3 /* 3 for AP using */ 72 73 /* Antenna Diversity Type */ 74 #define SW_ANTDIV 0 75 #define HW_ANTDIV 1 76 /* structure and define */ 77 78 /* Remove DIG by Yuchen */ 79 80 /* Remoce BB power saving by Yuchn */ 81 82 /* Remove DIG by yuchen */ 83 84 struct dynamic_primary_CCA { 85 u8 PriCCA_flag; 86 u8 intf_flag; 87 u8 intf_type; 88 u8 DupRTS_flag; 89 u8 Monitor_flag; 90 u8 CH_offset; 91 u8 MF_state; 92 }; 93 94 struct ra_t { 95 u8 firstconnect; 96 }; 97 98 struct rxhp_t { 99 u8 RXHP_flag; 100 u8 PSD_func_trigger; 101 u8 PSD_bitmap_RXHP[80]; 102 u8 Pre_IGI; 103 u8 Cur_IGI; 104 u8 Pre_pw_th; 105 u8 Cur_pw_th; 106 bool First_time_enter; 107 bool RXHP_enable; 108 u8 TP_Mode; 109 struct timer_list PSDTimer; 110 }; 111 112 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 113 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 114 115 /* This indicates two different the steps. */ 116 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 117 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 118 /* with original RSSI to determine if it is necessary to switch antenna. */ 119 #define SWAW_STEP_PEAK 0 120 #define SWAW_STEP_DETERMINE 1 121 122 #define TP_MODE 0 123 #define RSSI_MODE 1 124 #define TRAFFIC_LOW 0 125 #define TRAFFIC_HIGH 1 126 #define TRAFFIC_UltraLOW 2 127 128 struct swat_t { /* _SW_Antenna_Switch_ */ 129 u8 Double_chk_flag; 130 u8 try_flag; 131 s32 PreRSSI; 132 u8 CurAntenna; 133 u8 PreAntenna; 134 u8 RSSI_Trying; 135 u8 TestMode; 136 u8 bTriggerAntennaSwitch; 137 u8 SelectAntennaMap; 138 u8 RSSI_target; 139 u8 reset_idx; 140 u16 Single_Ant_Counter; 141 u16 Dual_Ant_Counter; 142 u16 Aux_FailDetec_Counter; 143 u16 Retry_Counter; 144 145 /* Before link Antenna Switch check */ 146 u8 SWAS_NoLink_State; 147 u32 SWAS_NoLink_BK_Reg860; 148 u32 SWAS_NoLink_BK_Reg92c; 149 u32 SWAS_NoLink_BK_Reg948; 150 bool ANTA_ON; /* To indicate Ant A is or not */ 151 bool ANTB_ON; /* To indicate Ant B is on or not */ 152 bool Pre_Aux_FailDetec; 153 bool RSSI_AntDect_bResult; 154 u8 Ant5G; 155 u8 Ant2G; 156 157 s32 RSSI_sum_A; 158 s32 RSSI_sum_B; 159 s32 RSSI_cnt_A; 160 s32 RSSI_cnt_B; 161 162 u64 lastTxOkCnt; 163 u64 lastRxOkCnt; 164 u64 TXByteCnt_A; 165 u64 TXByteCnt_B; 166 u64 RXByteCnt_A; 167 u64 RXByteCnt_B; 168 u8 TrafficLoad; 169 u8 Train_time; 170 u8 Train_time_flag; 171 struct timer_list SwAntennaSwitchTimer; 172 struct timer_list SwAntennaSwitchTimer_8723B; 173 u32 PktCnt_SWAntDivByCtrlFrame; 174 bool bSWAntDivByCtrlFrame; 175 }; 176 177 /* Remove Edca by YuChen */ 178 179 180 struct odm_rate_adaptive { 181 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 182 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 183 bool bUseLdpc; 184 bool bLowerRtsRate; 185 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 186 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 187 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 188 189 }; 190 191 #define IQK_MAC_REG_NUM 4 192 #define IQK_ADDA_REG_NUM 16 193 #define IQK_BB_REG_NUM_MAX 10 194 #define IQK_BB_REG_NUM 9 195 #define HP_THERMAL_NUM 8 196 197 #define AVG_THERMAL_NUM 8 198 #define IQK_Matrix_REG_NUM 8 199 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 200 * + Channels_5G_20M_NUM 201 * + Channels_5G 202 */ 203 204 #define DM_Type_ByFW 0 205 #define DM_Type_ByDriver 1 206 207 /* */ 208 /* Declare for common info */ 209 /* */ 210 #define MAX_PATH_NUM_92CS 2 211 #define MAX_PATH_NUM_8188E 1 212 #define MAX_PATH_NUM_8192E 2 213 #define MAX_PATH_NUM_8723B 1 214 #define MAX_PATH_NUM_8812A 2 215 #define MAX_PATH_NUM_8821A 1 216 #define MAX_PATH_NUM_8814A 4 217 #define MAX_PATH_NUM_8822B 2 218 219 #define IQK_THRESHOLD 8 220 #define DPK_THRESHOLD 4 221 222 struct odm_phy_info { 223 /* 224 * Be care, if you want to add any element, please insert it between 225 * rx_pwd_ball and signal_strength. 226 */ 227 u8 rx_pwd_ba11; 228 229 u8 signal_quality; /* in 0-100 index. */ 230 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 231 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 232 233 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 234 235 u16 cfo_short[4]; /* per-path's Cfo_short */ 236 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 237 238 s8 rx_power; /* in dBm Translate from PWdB */ 239 240 /* 241 * Real power in dBm for this packet, no beautification and 242 * aggregation. Keep this raw info to be used for the other procedures. 243 */ 244 s8 recv_signal_power; 245 u8 bt_rx_rssi_percentage; 246 u8 signal_strength; /* in 0-100 index. */ 247 248 s8 rx_pwr[4]; /* per-path's pwdb */ 249 250 u8 rx_snr[4]; /* per-path's SNR */ 251 u8 band_width; 252 u8 bt_coex_pwr_adjust; 253 }; 254 255 struct odm_packet_info { 256 u8 data_rate; 257 u8 station_id; 258 bool bssid_match; 259 bool to_self; 260 bool is_beacon; 261 }; 262 263 struct odm_phy_dbg_info { 264 /* ODM Write, debug info */ 265 s8 RxSNRdB[4]; 266 u32 NumQryPhyStatus; 267 u32 NumQryPhyStatusCCK; 268 u32 NumQryPhyStatusOFDM; 269 u8 NumQryBeaconPkt; 270 /* Others */ 271 s32 RxEVM[4]; 272 273 }; 274 275 struct odm_mac_status_info { 276 u8 test; 277 }; 278 279 /* */ 280 /* 2011/10/20 MH Define Common info enum for all team. */ 281 /* */ 282 enum odm_cmninfo_e { 283 /* Fixed value: */ 284 285 /* HOOK BEFORE REG INIT----------- */ 286 ODM_CMNINFO_PLATFORM = 0, 287 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 288 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 289 ODM_CMNINFO_MP_TEST_CHIP, 290 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 291 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 292 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 293 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 294 ODM_CMNINFO_RFE_TYPE, 295 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 296 ODM_CMNINFO_PACKAGE_TYPE, 297 ODM_CMNINFO_EXT_LNA, /* true */ 298 ODM_CMNINFO_5G_EXT_LNA, 299 ODM_CMNINFO_EXT_PA, 300 ODM_CMNINFO_5G_EXT_PA, 301 ODM_CMNINFO_GPA, 302 ODM_CMNINFO_APA, 303 ODM_CMNINFO_GLNA, 304 ODM_CMNINFO_ALNA, 305 ODM_CMNINFO_EXT_TRSW, 306 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 307 ODM_CMNINFO_BINHCT_TEST, 308 ODM_CMNINFO_BWIFI_TEST, 309 ODM_CMNINFO_SMART_CONCURRENT, 310 /* HOOK BEFORE REG INIT----------- */ 311 312 /* Dynamic value: */ 313 /* POINTER REFERENCE----------- */ 314 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 315 ODM_CMNINFO_TX_UNI, 316 ODM_CMNINFO_RX_UNI, 317 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 318 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 319 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 320 ODM_CMNINFO_BW, /* ODM_BW_E */ 321 ODM_CMNINFO_CHNL, 322 ODM_CMNINFO_FORCED_RATE, 323 324 ODM_CMNINFO_DMSP_GET_VALUE, 325 ODM_CMNINFO_BUDDY_ADAPTOR, 326 ODM_CMNINFO_DMSP_IS_MASTER, 327 ODM_CMNINFO_SCAN, 328 ODM_CMNINFO_POWER_SAVING, 329 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 330 ODM_CMNINFO_DRV_STOP, 331 ODM_CMNINFO_PNP_IN, 332 ODM_CMNINFO_INIT_ON, 333 ODM_CMNINFO_ANT_TEST, 334 ODM_CMNINFO_NET_CLOSED, 335 ODM_CMNINFO_MP_MODE, 336 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 337 ODM_CMNINFO_FORCED_IGI_LB, 338 ODM_CMNINFO_IS1ANTENNA, 339 ODM_CMNINFO_RFDEFAULTPATH, 340 /* POINTER REFERENCE----------- */ 341 342 /* CALL BY VALUE------------- */ 343 ODM_CMNINFO_WIFI_DIRECT, 344 ODM_CMNINFO_WIFI_DISPLAY, 345 ODM_CMNINFO_LINK_IN_PROGRESS, 346 ODM_CMNINFO_LINK, 347 ODM_CMNINFO_STATION_STATE, 348 ODM_CMNINFO_RSSI_MIN, 349 ODM_CMNINFO_DBG_COMP, /* u64 */ 350 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 351 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 352 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 353 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 354 ODM_CMNINFO_BT_ENABLED, 355 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 356 ODM_CMNINFO_BT_HS_RSSI, 357 ODM_CMNINFO_BT_OPERATION, 358 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 359 ODM_CMNINFO_BT_DISABLE_EDCA, 360 /* CALL BY VALUE------------- */ 361 362 /* Dynamic ptr array hook itms. */ 363 ODM_CMNINFO_STA_STATUS, 364 ODM_CMNINFO_PHY_STATUS, 365 ODM_CMNINFO_MAC_STATUS, 366 367 ODM_CMNINFO_MAX, 368 }; 369 370 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 371 enum { /* _ODM_Support_Ability_Definition */ 372 /* */ 373 /* BB ODM section BIT 0-15 */ 374 /* */ 375 ODM_BB_DIG = BIT0, 376 ODM_BB_RA_MASK = BIT1, 377 ODM_BB_DYNAMIC_TXPWR = BIT2, 378 ODM_BB_FA_CNT = BIT3, 379 ODM_BB_RSSI_MONITOR = BIT4, 380 ODM_BB_CCK_PD = BIT5, 381 ODM_BB_ANT_DIV = BIT6, 382 ODM_BB_PWR_SAVE = BIT7, 383 ODM_BB_PWR_TRAIN = BIT8, 384 ODM_BB_RATE_ADAPTIVE = BIT9, 385 ODM_BB_PATH_DIV = BIT10, 386 ODM_BB_PSD = BIT11, 387 ODM_BB_RXHP = BIT12, 388 ODM_BB_ADAPTIVITY = BIT13, 389 ODM_BB_CFO_TRACKING = BIT14, 390 391 /* MAC DM section BIT 16-23 */ 392 ODM_MAC_EDCA_TURBO = BIT16, 393 ODM_MAC_EARLY_MODE = BIT17, 394 395 /* RF ODM section BIT 24-31 */ 396 ODM_RF_TX_PWR_TRACK = BIT24, 397 ODM_RF_RX_GAIN_TRACK = BIT25, 398 ODM_RF_CALIBRATION = BIT26, 399 }; 400 401 /* ODM_CMNINFO_INTERFACE */ 402 enum { /* tag_ODM_Support_Interface_Definition */ 403 ODM_ITRF_SDIO = 0x4, 404 ODM_ITRF_ALL = 0x7, 405 }; 406 407 /* ODM_CMNINFO_IC_TYPE */ 408 enum { /* tag_ODM_Support_IC_Type_Definition */ 409 ODM_RTL8723B = BIT8, 410 }; 411 412 /* ODM_CMNINFO_CUT_VER */ 413 enum { /* tag_ODM_Cut_Version_Definition */ 414 ODM_CUT_A = 0, 415 ODM_CUT_B = 1, 416 ODM_CUT_C = 2, 417 ODM_CUT_D = 3, 418 ODM_CUT_E = 4, 419 ODM_CUT_F = 5, 420 421 ODM_CUT_I = 8, 422 ODM_CUT_J = 9, 423 ODM_CUT_K = 10, 424 ODM_CUT_TEST = 15, 425 }; 426 427 /* ODM_CMNINFO_FAB_VER */ 428 enum { /* tag_ODM_Fab_Version_Definition */ 429 ODM_TSMC = 0, 430 ODM_UMC = 1, 431 }; 432 433 /* ODM_CMNINFO_RF_TYPE */ 434 /* */ 435 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 436 /* */ 437 enum { /* tag_ODM_RF_Type_Definition */ 438 ODM_1T1R = 0, 439 ODM_1T2R = 1, 440 ODM_2T2R = 2, 441 ODM_2T3R = 3, 442 ODM_2T4R = 4, 443 ODM_3T3R = 5, 444 ODM_3T4R = 6, 445 ODM_4T4R = 7, 446 }; 447 448 /* */ 449 /* ODM Dynamic common info value definition */ 450 /* */ 451 452 /* ODM_CMNINFO_WM_MODE */ 453 enum { /* tag_Wireless_Mode_Definition */ 454 ODM_WM_UNKNOWN = 0x0, 455 ODM_WM_B = BIT0, 456 ODM_WM_G = BIT1, 457 ODM_WM_N24G = BIT3, 458 ODM_WM_AUTO = BIT5, 459 }; 460 461 /* ODM_CMNINFO_BW */ 462 enum { /* tag_Bandwidth_Definition */ 463 ODM_BW20M = 0, 464 ODM_BW40M = 1, 465 }; 466 467 /* ODM_CMNINFO_BOARD_TYPE */ 468 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 469 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 470 471 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 472 TYPE_GPA0 = 0, 473 TYPE_GPA1 = BIT(1)|BIT(0) 474 }; 475 476 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 477 TYPE_APA0 = 0, 478 TYPE_APA1 = BIT(1)|BIT(0) 479 }; 480 481 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 482 TYPE_GLNA0 = 0, 483 TYPE_GLNA1 = BIT(2)|BIT(0), 484 TYPE_GLNA2 = BIT(3)|BIT(1), 485 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 486 }; 487 488 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 489 TYPE_ALNA0 = 0, 490 TYPE_ALNA1 = BIT(2)|BIT(0), 491 TYPE_ALNA2 = BIT(3)|BIT(1), 492 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 493 }; 494 495 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 496 bool bIQKDone; 497 s32 Value[3][IQK_Matrix_REG_NUM]; 498 bool bBWIqkResultSaved[3]; 499 }; 500 501 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 502 503 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 504 /* for tx power tracking */ 505 506 u32 RegA24; /* for TempCCK */ 507 s32 RegE94; 508 s32 RegE9C; 509 s32 RegEB4; 510 s32 RegEBC; 511 512 u8 TXPowercount; 513 bool bTXPowerTrackingInit; 514 bool bTXPowerTracking; 515 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 516 u8 TM_Trigger; 517 u8 InternalPA5G[2]; /* pathA / pathB */ 518 519 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 520 u8 ThermalValue; 521 u8 ThermalValue_LCK; 522 u8 ThermalValue_IQK; 523 u8 ThermalValue_DPK; 524 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 525 u8 ThermalValue_AVG_index; 526 u8 ThermalValue_RxGain; 527 u8 ThermalValue_Crystal; 528 u8 ThermalValue_DPKstore; 529 u8 ThermalValue_DPKtrack; 530 bool TxPowerTrackingInProgress; 531 532 bool bReloadtxpowerindex; 533 u8 bRfPiEnable; 534 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 535 536 /* Tx power Tracking ------------------------- */ 537 u8 bCCKinCH14; 538 u8 CCK_index; 539 u8 OFDM_index[MAX_RF_PATH]; 540 s8 PowerIndexOffset[MAX_RF_PATH]; 541 s8 DeltaPowerIndex[MAX_RF_PATH]; 542 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 543 bool bTxPowerChanged; 544 545 u8 ThermalValue_HP[HP_THERMAL_NUM]; 546 u8 ThermalValue_HP_index; 547 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 548 bool bNeedIQK; 549 bool bIQKInProgress; 550 u8 Delta_IQK; 551 u8 Delta_LCK; 552 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 553 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 554 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 555 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 556 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 557 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 558 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 559 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 560 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 561 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 562 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 563 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 564 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 565 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 566 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 567 568 /* */ 569 570 /* for IQK */ 571 u32 RegC04; 572 u32 Reg874; 573 u32 RegC08; 574 u32 RegB68; 575 u32 RegB6C; 576 u32 Reg870; 577 u32 Reg860; 578 u32 Reg864; 579 580 bool bIQKInitialized; 581 bool bLCKInProgress; 582 bool bAntennaDetected; 583 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 584 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 585 u32 IQK_BB_backup_recover[9]; 586 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 587 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 588 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 589 590 /* for APK */ 591 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 592 u8 bAPKdone; 593 u8 bAPKThermalMeterIgnore; 594 595 /* DPK */ 596 bool bDPKFail; 597 u8 bDPdone; 598 u8 bDPPathAOK; 599 u8 bDPPathBOK; 600 601 u32 TxLOK[2]; 602 603 }; 604 /* */ 605 /* ODM Dynamic common info value definition */ 606 /* */ 607 608 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 609 u8 Bssid[6]; 610 u8 antsel_rx_keep_0; 611 u8 antsel_rx_keep_1; 612 u8 antsel_rx_keep_2; 613 u8 antsel_rx_keep_3; 614 u32 antSumRSSI[7]; 615 u32 antRSSIcnt[7]; 616 u32 antAveRSSI[7]; 617 u8 FAT_State; 618 u32 TrainIdx; 619 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 620 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 621 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 622 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 623 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 624 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 625 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 626 u8 RxIdleAnt; 627 bool bBecomeLinked; 628 u32 MinMaxRSSI; 629 u8 idx_AntDiv_counter_2G; 630 u8 idx_AntDiv_counter_5G; 631 u32 CCK_counter_main; 632 u32 CCK_counter_aux; 633 u32 OFDM_counter_main; 634 u32 OFDM_counter_aux; 635 636 u32 CCK_CtrlFrame_Cnt_main; 637 u32 CCK_CtrlFrame_Cnt_aux; 638 u32 OFDM_CtrlFrame_Cnt_main; 639 u32 OFDM_CtrlFrame_Cnt_aux; 640 u32 MainAnt_CtrlFrame_Sum; 641 u32 AuxAnt_CtrlFrame_Sum; 642 u32 MainAnt_CtrlFrame_Cnt; 643 u32 AuxAnt_CtrlFrame_Cnt; 644 645 }; 646 647 enum { 648 NO_ANTDIV = 0xFF, 649 CG_TRX_HW_ANTDIV = 0x01, 650 CGCS_RX_HW_ANTDIV = 0x02, 651 FIXED_HW_ANTDIV = 0x03, 652 CG_TRX_SMART_ANTDIV = 0x04, 653 CGCS_RX_SW_ANTDIV = 0x05, 654 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 655 }; 656 657 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 658 u8 RespTxPath; 659 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 660 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 661 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 662 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 663 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 664 }; 665 666 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 667 PHY_REG_PG_RELATIVE_VALUE = 0, 668 PHY_REG_PG_EXACT_VALUE = 1 669 }; 670 671 /* */ 672 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 673 /* */ 674 struct ant_detected_info { 675 bool bAntDetected; 676 u32 dBForAntA; 677 u32 dBForAntB; 678 u32 dBForAntO; 679 }; 680 681 /* */ 682 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 683 /* */ 684 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 685 /* struct timer_list FastAntTrainingTimer; */ 686 /* */ 687 /* Add for different team use temporarily */ 688 /* */ 689 struct adapter *Adapter; /* For CE/NIC team */ 690 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 691 bool odm_ready; 692 693 enum phy_reg_pg_type PhyRegPgValueType; 694 u8 PhyRegPgVersion; 695 696 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 697 u32 LastNumQryPhyStatusAll; 698 u32 RxPWDBAve; 699 bool MPDIG_2G; /* off MPDIG */ 700 u8 Times_2G; 701 702 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 703 bool bCckHighPower; 704 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 705 u8 ControlChannel; 706 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 707 708 /* REMOVED COMMON INFO---------- */ 709 /* u8 PseudoMacPhyMode; */ 710 /* bool *BTCoexist; */ 711 /* bool PseudoBtCoexist; */ 712 /* u8 OPMode; */ 713 /* bool bAPMode; */ 714 /* bool bClientMode; */ 715 /* bool bAdHocMode; */ 716 /* bool bSlaveOfDMSP; */ 717 /* REMOVED COMMON INFO---------- */ 718 719 /* 1 COMMON INFORMATION */ 720 721 /* */ 722 /* Init Value */ 723 /* */ 724 /* HOOK BEFORE REG INIT----------- */ 725 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 726 u8 SupportPlatform; 727 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 728 u32 SupportAbility; 729 /* ODM PCIE/USB/SDIO = 1/2/3 */ 730 u8 SupportInterface; 731 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 732 u32 SupportICType; 733 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 734 u8 CutVersion; 735 /* Fab Version TSMC/UMC = 0/1 */ 736 u8 FabVersion; 737 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 738 u8 RFType; 739 u8 RFEType; 740 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 741 u8 BoardType; 742 u8 PackageType; 743 u8 TypeGLNA; 744 u8 TypeGPA; 745 u8 TypeALNA; 746 u8 TypeAPA; 747 /* with external LNA NO/Yes = 0/1 */ 748 u8 ExtLNA; 749 u8 ExtLNA5G; 750 /* with external PA NO/Yes = 0/1 */ 751 u8 ExtPA; 752 u8 ExtPA5G; 753 /* with external TRSW NO/Yes = 0/1 */ 754 u8 ExtTRSW; 755 u8 PatchID; /* Customer ID */ 756 bool bInHctTest; 757 bool bWIFITest; 758 759 bool bDualMacSmartConcurrent; 760 u32 BK_SupportAbility; 761 u8 AntDivType; 762 /* HOOK BEFORE REG INIT----------- */ 763 764 /* */ 765 /* Dynamic Value */ 766 /* */ 767 /* POINTER REFERENCE----------- */ 768 769 u8 u8_temp; 770 bool bool_temp; 771 struct adapter *adapter_temp; 772 773 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 774 u8 *pMacPhyMode; 775 /* TX Unicast byte count */ 776 u64 *pNumTxBytesUnicast; 777 /* RX Unicast byte count */ 778 u64 *pNumRxBytesUnicast; 779 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 780 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 781 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 782 u8 *pSecChOffset; 783 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 784 u8 *pSecurity; 785 /* BW info 20M/40M/80M = 0/1/2 */ 786 u8 *pBandWidth; 787 /* Central channel location Ch1/Ch2/.... */ 788 u8 *pChannel; /* central channel number */ 789 bool DPK_Done; 790 /* Common info for 92D DMSP */ 791 792 bool *pbGetValueFromOtherMac; 793 struct adapter **pBuddyAdapter; 794 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 795 /* Common info for Status */ 796 bool *pbScanInProcess; 797 bool *pbPowerSaving; 798 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 799 u8 *pOnePathCCA; 800 /* pMgntInfo->AntennaTest */ 801 u8 *pAntennaTest; 802 bool *pbNet_closed; 803 u8 *mp_mode; 804 /* u8 *pAidMap; */ 805 u8 *pu1ForcedIgiLb; 806 /* For 8723B IQK----------- */ 807 bool *pIs1Antenna; 808 u8 *pRFDefaultPath; 809 /* 0:S1, 1:S0 */ 810 811 /* POINTER REFERENCE----------- */ 812 u16 *pForcedDataRate; 813 /* CALL BY VALUE------------- */ 814 bool bLinkInProcess; 815 bool bWIFI_Direct; 816 bool bWIFI_Display; 817 bool bLinked; 818 819 bool bsta_state; 820 u8 RSSI_Min; 821 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 822 bool bIsMPChip; 823 bool bOneEntryOnly; 824 /* Common info for BTDM */ 825 bool bBtEnabled; /* BT is disabled */ 826 bool bBtConnectProcess; /* BT HS is under connection progress. */ 827 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 828 bool bBtHsOperation; /* BT HS mode is under progress */ 829 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 830 bool bBtLimitedDig; /* BT is busy. */ 831 /* CALL BY VALUE------------- */ 832 u8 RSSI_A; 833 u8 RSSI_B; 834 u64 RSSI_TRSW; 835 u64 RSSI_TRSW_H; 836 u64 RSSI_TRSW_L; 837 u64 RSSI_TRSW_iso; 838 839 u8 RxRate; 840 bool bNoisyState; 841 u8 TxRate; 842 u8 LinkedInterval; 843 u8 preChannel; 844 u32 TxagcOffsetValueA; 845 bool IsTxagcOffsetPositiveA; 846 u32 TxagcOffsetValueB; 847 bool IsTxagcOffsetPositiveB; 848 u64 lastTxOkCnt; 849 u64 lastRxOkCnt; 850 u32 BbSwingOffsetA; 851 bool IsBbSwingOffsetPositiveA; 852 u32 BbSwingOffsetB; 853 bool IsBbSwingOffsetPositiveB; 854 s8 TH_L2H_ini; 855 s8 TH_EDCCA_HL_diff; 856 s8 IGI_Base; 857 u8 IGI_target; 858 bool ForceEDCCA; 859 u8 AdapEn_RSSI; 860 s8 Force_TH_H; 861 s8 Force_TH_L; 862 u8 IGI_LowerBound; 863 u8 antdiv_rssi; 864 u8 AntType; 865 u8 pre_AntType; 866 u8 antdiv_period; 867 u8 antdiv_select; 868 u8 NdpaPeriod; 869 bool H2C_RARpt_connect; 870 871 /* add by Yu Cehn for adaptivtiy */ 872 bool adaptivity_flag; 873 bool NHM_disable; 874 bool TxHangFlg; 875 bool Carrier_Sense_enable; 876 u8 tolerance_cnt; 877 u64 NHMCurTxOkcnt; 878 u64 NHMCurRxOkcnt; 879 u64 NHMLastTxOkcnt; 880 u64 NHMLastRxOkcnt; 881 u8 txEdcca1; 882 u8 txEdcca0; 883 s8 H2L_lb; 884 s8 L2H_lb; 885 u8 Adaptivity_IGI_upper; 886 u8 NHM_cnt_0; 887 888 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 889 /* */ 890 /* 2 Define STA info. */ 891 /* _ODM_STA_INFO */ 892 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 893 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 894 895 /* */ 896 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 897 /* We need to colelct all support abilit to a proper area. */ 898 /* */ 899 bool RaSupport88E; 900 901 /* Define ........... */ 902 903 /* Latest packet phy info (ODM write) */ 904 struct odm_phy_dbg_info PhyDbgInfo; 905 /* PHY_INFO_88E PhyInfo; */ 906 907 /* Latest packet phy info (ODM write) */ 908 struct odm_mac_status_info *pMacInfo; 909 /* MAC_INFO_88E MacInfo; */ 910 911 /* Different Team independt structure?? */ 912 913 /* */ 914 /* TX_RTP_CMN TX_retrpo; */ 915 /* TX_RTP_88E TX_retrpo; */ 916 /* TX_RTP_8195 TX_retrpo; */ 917 918 /* */ 919 /* ODM Structure */ 920 /* */ 921 struct fat_t DM_FatTable; 922 struct dig_t DM_DigTable; 923 struct ps_t DM_PSTable; 924 struct dynamic_primary_CCA DM_PriCCA; 925 struct rxhp_t dM_RXHP_Table; 926 struct ra_t DM_RA_Table; 927 struct false_ALARM_STATISTICS FalseAlmCnt; 928 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 929 struct swat_t DM_SWAT_Table; 930 bool RSSI_test; 931 struct cfo_tracking DM_CfoTrack; 932 933 struct edca_t DM_EDCA_Table; 934 u32 WMMEDCA_BE; 935 struct pathdiv_t DM_PathDiv; 936 /* Copy from SD4 structure */ 937 /* */ 938 /* ================================================== */ 939 /* */ 940 941 /* common */ 942 /* u8 DM_Type; */ 943 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 944 /* u8 PSD_func_flag; Add By Gary */ 945 /* for DIG */ 946 /* u8 bDMInitialGainEnable; */ 947 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 948 /* for Antenna diversity */ 949 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 950 /* PSTA_INFO_T RSSI_target; */ 951 952 bool *pbDriverStopped; 953 bool *pbDriverIsGoingToPnpSetPowerSleep; 954 bool *pinit_adpt_in_progress; 955 956 /* PSD */ 957 bool bUserAssignLevel; 958 struct timer_list PSDTimer; 959 u8 RSSI_BT; /* come from BT */ 960 bool bPSDinProcess; 961 bool bPSDactive; 962 bool bDMInitialGainEnable; 963 964 /* MPT DIG */ 965 struct timer_list MPT_DIGTimer; 966 967 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 968 u8 bUseRAMask; 969 970 struct odm_rate_adaptive RateAdaptive; 971 972 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 973 974 struct odm_rf_cal_t RFCalibrateInfo; 975 976 /* */ 977 /* TX power tracking */ 978 /* */ 979 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 980 u8 BbSwingIdxOfdmCurrent; 981 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 982 bool BbSwingFlagOfdm; 983 u8 BbSwingIdxCck; 984 u8 BbSwingIdxCckCurrent; 985 u8 BbSwingIdxCckBase; 986 u8 DefaultOfdmIndex; 987 u8 DefaultCckIndex; 988 bool BbSwingFlagCck; 989 990 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 991 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 992 s8 Remnant_CCKSwingIdx; 993 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 994 bool Modify_TxAGC_Flag_PathA; 995 bool Modify_TxAGC_Flag_PathB; 996 bool Modify_TxAGC_Flag_PathC; 997 bool Modify_TxAGC_Flag_PathD; 998 bool Modify_TxAGC_Flag_PathA_CCK; 999 1000 s8 KfreeOffset[MAX_RF_PATH]; 1001 /* */ 1002 /* ODM system resource. */ 1003 /* */ 1004 1005 /* ODM relative time. */ 1006 struct timer_list PathDivSwitchTimer; 1007 /* 2011.09.27 add for Path Diversity */ 1008 struct timer_list CCKPathDiversityTimer; 1009 struct timer_list FastAntTrainingTimer; 1010 1011 /* ODM relative workitem. */ 1012 1013 #if (BEAMFORMING_SUPPORT == 1) 1014 RT_BEAMFORMING_INFO BeamformingInfo; 1015 #endif 1016 }; 1017 1018 #define ODM_RF_PATH_MAX 2 1019 1020 enum odm_rf_radio_path_e { 1021 ODM_RF_PATH_A = 0, /* Radio Path A */ 1022 ODM_RF_PATH_B = 1, /* Radio Path B */ 1023 ODM_RF_PATH_C = 2, /* Radio Path C */ 1024 ODM_RF_PATH_D = 3, /* Radio Path D */ 1025 ODM_RF_PATH_AB, 1026 ODM_RF_PATH_AC, 1027 ODM_RF_PATH_AD, 1028 ODM_RF_PATH_BC, 1029 ODM_RF_PATH_BD, 1030 ODM_RF_PATH_CD, 1031 ODM_RF_PATH_ABC, 1032 ODM_RF_PATH_ACD, 1033 ODM_RF_PATH_BCD, 1034 ODM_RF_PATH_ABCD, 1035 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1036 }; 1037 1038 enum odm_rf_content { 1039 odm_radioa_txt = 0x1000, 1040 odm_radiob_txt = 0x1001, 1041 odm_radioc_txt = 0x1002, 1042 odm_radiod_txt = 0x1003 1043 }; 1044 1045 enum ODM_BB_Config_Type { 1046 CONFIG_BB_PHY_REG, 1047 CONFIG_BB_AGC_TAB, 1048 CONFIG_BB_AGC_TAB_2G, 1049 CONFIG_BB_AGC_TAB_5G, 1050 CONFIG_BB_PHY_REG_PG, 1051 CONFIG_BB_PHY_REG_MP, 1052 CONFIG_BB_AGC_TAB_DIFF, 1053 }; 1054 1055 enum ODM_RF_Config_Type { 1056 CONFIG_RF_RADIO, 1057 CONFIG_RF_TXPWR_LMT, 1058 }; 1059 1060 enum ODM_FW_Config_Type { 1061 CONFIG_FW_NIC, 1062 CONFIG_FW_NIC_2, 1063 CONFIG_FW_AP, 1064 CONFIG_FW_WoWLAN, 1065 CONFIG_FW_WoWLAN_2, 1066 CONFIG_FW_AP_WoWLAN, 1067 CONFIG_FW_BT, 1068 }; 1069 1070 #ifdef REMOVE_PACK 1071 #pragma pack() 1072 #endif 1073 1074 /* include "odm_function.h" */ 1075 1076 /* 3 =========================================================== */ 1077 /* 3 DIG */ 1078 /* 3 =========================================================== */ 1079 1080 /* Remove DIG by Yuchen */ 1081 1082 /* 3 =========================================================== */ 1083 /* 3 AGC RX High Power Mode */ 1084 /* 3 =========================================================== */ 1085 #define LNA_Low_Gain_1 0x64 1086 #define LNA_Low_Gain_2 0x5A 1087 #define LNA_Low_Gain_3 0x58 1088 1089 #define FA_RXHP_TH1 5000 1090 #define FA_RXHP_TH2 1500 1091 #define FA_RXHP_TH3 800 1092 #define FA_RXHP_TH4 600 1093 #define FA_RXHP_TH5 500 1094 1095 /* 3 =========================================================== */ 1096 /* 3 EDCA */ 1097 /* 3 =========================================================== */ 1098 1099 /* 3 =========================================================== */ 1100 /* 3 Dynamic Tx Power */ 1101 /* 3 =========================================================== */ 1102 /* Dynamic Tx Power Control Threshold */ 1103 1104 /* 3 =========================================================== */ 1105 /* 3 Rate Adaptive */ 1106 /* 3 =========================================================== */ 1107 #define DM_RATR_STA_INIT 0 1108 #define DM_RATR_STA_HIGH 1 1109 #define DM_RATR_STA_MIDDLE 2 1110 #define DM_RATR_STA_LOW 3 1111 1112 /* 3 =========================================================== */ 1113 /* 3 BB Power Save */ 1114 /* 3 =========================================================== */ 1115 1116 enum { /* tag_1R_CCA_Type_Definition */ 1117 CCA_1R = 0, 1118 CCA_2R = 1, 1119 CCA_MAX = 2, 1120 }; 1121 1122 enum { /* tag_RF_Type_Definition */ 1123 RF_Save = 0, 1124 RF_Normal = 1, 1125 RF_MAX = 2, 1126 }; 1127 1128 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1129 #define MAX_ANTENNA_DETECTION_CNT 10 1130 1131 /* */ 1132 /* Extern Global Variables. */ 1133 /* */ 1134 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1135 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1136 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1137 1138 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1139 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1140 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1141 1142 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1143 1144 /* */ 1145 /* check Sta pointer valid or not */ 1146 /* */ 1147 #define IS_STA_VALID(pSta) (pSta) 1148 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1149 /* This indicates two different the steps. */ 1150 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1151 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1152 /* with original RSSI to determine if it is necessary to switch antenna. */ 1153 #define SWAW_STEP_PEAK 0 1154 #define SWAW_STEP_DETERMINE 1 1155 1156 /* Remove BB power saving by Yuchen */ 1157 1158 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1159 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1160 1161 bool ODM_RAStateCheck( 1162 struct dm_odm_t *pDM_Odm, 1163 s32 RSSI, 1164 bool bForceUpdate, 1165 u8 *pRATRState 1166 ); 1167 1168 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1169 void ODM_SwAntDivChkPerPktRssi( 1170 struct dm_odm_t *pDM_Odm, 1171 u8 StationID, 1172 struct odm_phy_info *pPhyInfo 1173 ); 1174 1175 u32 ODM_Get_Rate_Bitmap( 1176 struct dm_odm_t *pDM_Odm, 1177 u32 macid, 1178 u32 ra_mask, 1179 u8 rssi_level 1180 ); 1181 1182 #if (BEAMFORMING_SUPPORT == 1) 1183 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1184 #endif 1185 1186 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1187 1188 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1189 1190 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1191 1192 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1193 1194 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1195 1196 void ODM_CmnInfoPtrArrayHook( 1197 struct dm_odm_t *pDM_Odm, 1198 enum odm_cmninfo_e CmnInfo, 1199 u16 Index, 1200 void *pValue 1201 ); 1202 1203 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1204 1205 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1206 1207 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1208 1209 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1210 1211 void ODM_AntselStatistics_88C( 1212 struct dm_odm_t *pDM_Odm, 1213 u8 MacId, 1214 u32 PWDBAll, 1215 bool isCCKrate 1216 ); 1217 1218 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1219 1220 #endif 1221