1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5  *
6  ******************************************************************************/
7 
8 
9 #ifndef	__HALDMOUTSRC_H__
10 #define __HALDMOUTSRC_H__
11 
12 #include "odm_EdcaTurboCheck.h"
13 #include "odm_DIG.h"
14 #include "odm_DynamicBBPowerSaving.h"
15 #include "odm_DynamicTxPower.h"
16 #include "odm_CfoTracking.h"
17 #include "odm_NoiseMonitor.h"
18 
19 #define	TP_MODE		0
20 #define	RSSI_MODE		1
21 #define	TRAFFIC_LOW	0
22 #define	TRAFFIC_HIGH	1
23 #define	NONE			0
24 
25 /* 3 Tx Power Tracking */
26 /* 3 ============================================================ */
27 #define		DPK_DELTA_MAPPING_NUM	13
28 #define		index_mapping_HP_NUM	15
29 #define	OFDM_TABLE_SIZE		43
30 #define	CCK_TABLE_SIZE			33
31 #define TXSCALE_TABLE_SIZE		37
32 #define TXPWR_TRACK_TABLE_SIZE	30
33 #define DELTA_SWINGIDX_SIZE     30
34 #define BAND_NUM				4
35 
36 /* 3 PSD Handler */
37 /* 3 ============================================================ */
38 
39 #define	AFH_PSD		1	/* 0:normal PSD scan, 1: only do 20 pts PSD */
40 #define	MODE_40M		0	/* 0:20M, 1:40M */
41 #define	PSD_TH2		3
42 #define	PSD_CHMIN		20   /*  Minimum channel number for BT AFH */
43 #define	SIR_STEP_SIZE	3
44 #define   Smooth_Size_1		5
45 #define	Smooth_TH_1	3
46 #define   Smooth_Size_2		10
47 #define	Smooth_TH_2	4
48 #define   Smooth_Size_3		20
49 #define	Smooth_TH_3	4
50 #define   Smooth_Step_Size 5
51 #define	Adaptive_SIR	1
52 #define	PSD_RESCAN		4
53 #define	PSD_SCAN_INTERVAL	700 /* ms */
54 
55 /* 8723A High Power IGI Setting */
56 #define		DM_DIG_HIGH_PWR_IGI_LOWER_BOUND	0x22
57 #define			DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
58 #define		DM_DIG_HIGH_PWR_THRESHOLD	0x3a
59 #define		DM_DIG_LOW_PWR_THRESHOLD	0x14
60 
61 /* ANT Test */
62 #define			ANTTESTALL		0x00		/* Ant A or B will be Testing */
63 #define		ANTTESTA		0x01		/* Ant A will be Testing */
64 #define		ANTTESTB		0x02		/* Ant B will be testing */
65 
66 #define	PS_MODE_ACTIVE 0x01
67 
68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
69 #define		MAIN_ANT		1		/* Ant A or Ant Main */
70 #define		AUX_ANT		2		/* AntB or Ant Aux */
71 #define		MAX_ANT		3		/*  3 for AP using */
72 
73 /* Antenna Diversity Type */
74 #define	SW_ANTDIV	0
75 #define	HW_ANTDIV	1
76 /*  structure and define */
77 
78 /* Remove DIG by Yuchen */
79 
80 /* Remoce BB power saving by Yuchn */
81 
82 /* Remove DIG by yuchen */
83 
84 struct dynamic_primary_CCA {
85 	u8 PriCCA_flag;
86 	u8 intf_flag;
87 	u8 intf_type;
88 	u8 DupRTS_flag;
89 	u8 Monitor_flag;
90 	u8 CH_offset;
91 	u8 MF_state;
92 };
93 
94 struct ra_t {
95 	u8 firstconnect;
96 };
97 
98 struct rxhp_t {
99 	u8 RXHP_flag;
100 	u8 PSD_func_trigger;
101 	u8 PSD_bitmap_RXHP[80];
102 	u8 Pre_IGI;
103 	u8 Cur_IGI;
104 	u8 Pre_pw_th;
105 	u8 Cur_pw_th;
106 	bool First_time_enter;
107 	bool RXHP_enable;
108 	u8 TP_Mode;
109 	struct timer_list PSDTimer;
110 };
111 
112 #define ASSOCIATE_ENTRY_NUM					32 /*  Max size of AsocEntry[]. */
113 #define	ODM_ASSOCIATE_ENTRY_NUM				ASSOCIATE_ENTRY_NUM
114 
115 /*  This indicates two different the steps. */
116 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
117 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
118 /*  with original RSSI to determine if it is necessary to switch antenna. */
119 #define SWAW_STEP_PEAK		0
120 #define SWAW_STEP_DETERMINE	1
121 
122 #define	TP_MODE		0
123 #define	RSSI_MODE		1
124 #define	TRAFFIC_LOW	0
125 #define	TRAFFIC_HIGH	1
126 #define	TRAFFIC_UltraLOW	2
127 
128 struct swat_t { /* _SW_Antenna_Switch_ */
129 	u8 Double_chk_flag;
130 	u8 try_flag;
131 	s32 PreRSSI;
132 	u8 CurAntenna;
133 	u8 PreAntenna;
134 	u8 RSSI_Trying;
135 	u8 TestMode;
136 	u8 bTriggerAntennaSwitch;
137 	u8 SelectAntennaMap;
138 	u8 RSSI_target;
139 	u8 reset_idx;
140 	u16 Single_Ant_Counter;
141 	u16 Dual_Ant_Counter;
142 	u16 Aux_FailDetec_Counter;
143 	u16 Retry_Counter;
144 
145 	/*  Before link Antenna Switch check */
146 	u8 SWAS_NoLink_State;
147 	u32 SWAS_NoLink_BK_Reg860;
148 	u32 SWAS_NoLink_BK_Reg92c;
149 	u32 SWAS_NoLink_BK_Reg948;
150 	bool ANTA_ON;	/* To indicate Ant A is or not */
151 	bool ANTB_ON;	/* To indicate Ant B is on or not */
152 	bool Pre_Aux_FailDetec;
153 	bool RSSI_AntDect_bResult;
154 	u8 Ant2G;
155 
156 	s32 RSSI_sum_A;
157 	s32 RSSI_sum_B;
158 	s32 RSSI_cnt_A;
159 	s32 RSSI_cnt_B;
160 
161 	u64 lastTxOkCnt;
162 	u64 lastRxOkCnt;
163 	u64 TXByteCnt_A;
164 	u64 TXByteCnt_B;
165 	u64 RXByteCnt_A;
166 	u64 RXByteCnt_B;
167 	u8 TrafficLoad;
168 	u8 Train_time;
169 	u8 Train_time_flag;
170 	struct timer_list SwAntennaSwitchTimer;
171 	struct timer_list SwAntennaSwitchTimer_8723B;
172 	u32 PktCnt_SWAntDivByCtrlFrame;
173 	bool bSWAntDivByCtrlFrame;
174 };
175 
176 /* Remove Edca by YuChen */
177 
178 
179 struct odm_rate_adaptive {
180 	u8 Type;				/*  DM_Type_ByFW/DM_Type_ByDriver */
181 	u8 LdpcThres;			/*  if RSSI > LdpcThres => switch from LPDC to BCC */
182 	bool bUseLdpc;
183 	bool bLowerRtsRate;
184 	u8 HighRSSIThresh;		/*  if RSSI > HighRSSIThresh	=> RATRState is DM_RATR_STA_HIGH */
185 	u8 LowRSSIThresh;		/*  if RSSI <= LowRSSIThresh	=> RATRState is DM_RATR_STA_LOW */
186 	u8 RATRState;			/*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
187 
188 };
189 
190 #define IQK_MAC_REG_NUM		4
191 #define IQK_ADDA_REG_NUM		16
192 #define IQK_BB_REG_NUM_MAX	10
193 #define IQK_BB_REG_NUM		9
194 #define HP_THERMAL_NUM		8
195 
196 #define AVG_THERMAL_NUM		8
197 #define IQK_Matrix_REG_NUM	8
198 #define IQK_Matrix_Settings_NUM	14 /* Channels_2_4G_NUM */
199 
200 #define		DM_Type_ByFW			0
201 #define		DM_Type_ByDriver		1
202 
203 /*  */
204 /*  Declare for common info */
205 /*  */
206 #define MAX_PATH_NUM_92CS		2
207 #define MAX_PATH_NUM_8188E		1
208 #define MAX_PATH_NUM_8192E		2
209 #define MAX_PATH_NUM_8723B		1
210 #define MAX_PATH_NUM_8812A		2
211 #define MAX_PATH_NUM_8821A		1
212 #define MAX_PATH_NUM_8814A		4
213 #define MAX_PATH_NUM_8822B		2
214 
215 #define IQK_THRESHOLD			8
216 #define DPK_THRESHOLD			4
217 
218 struct odm_phy_info {
219 	/*
220 	 *  Be care, if you want to add any element, please insert it between
221 	 *  rx_pwd_ball and signal_strength.
222 	 */
223 	u8 rx_pwd_ba11;
224 
225 	u8 signal_quality;             /* in 0-100 index. */
226 	s8 rx_mimo_signal_quality[4];  /* per-path's EVM */
227 	u8 rx_mimo_evm_dbm[4];         /* per-path's EVM dbm */
228 
229 	u8 rx_mimo_signal_strength[4]; /* in 0~100 index */
230 
231 	u16 cfo_short[4];              /* per-path's Cfo_short */
232 	u16 cfo_tail[4];               /* per-path's Cfo_tail */
233 
234 	s8 rx_power;                   /* in dBm Translate from PWdB */
235 
236 	/*
237 	 * Real power in dBm for this packet, no beautification and
238 	 * aggregation. Keep this raw info to be used for the other procedures.
239 	 */
240 	s8 recv_signal_power;
241 	u8 bt_rx_rssi_percentage;
242 	u8 signal_strength;	       /* in 0-100 index. */
243 
244 	s8 rx_pwr[4];                  /* per-path's pwdb */
245 
246 	u8 rx_snr[4];                  /* per-path's SNR */
247 	u8 band_width;
248 	u8 bt_coex_pwr_adjust;
249 };
250 
251 struct odm_packet_info {
252 	u8 data_rate;
253 	u8 station_id;
254 	bool bssid_match;
255 	bool to_self;
256 	bool is_beacon;
257 };
258 
259 struct odm_phy_dbg_info {
260 	/* ODM Write, debug info */
261 	s8 RxSNRdB[4];
262 	u32 NumQryPhyStatus;
263 	u32 NumQryPhyStatusCCK;
264 	u32 NumQryPhyStatusOFDM;
265 	u8 NumQryBeaconPkt;
266 	/* Others */
267 	s32 RxEVM[4];
268 
269 };
270 
271 struct odm_mac_status_info {
272 	u8 test;
273 };
274 
275 /*  */
276 /*  2011/10/20 MH Define Common info enum for all team. */
277 /*  */
278 enum odm_cmninfo_e {
279 	/*  Fixed value: */
280 
281 	/* HOOK BEFORE REG INIT----------- */
282 	ODM_CMNINFO_PLATFORM = 0,
283 	ODM_CMNINFO_ABILITY,					/*  ODM_ABILITY_E */
284 	ODM_CMNINFO_INTERFACE,				/*  ODM_INTERFACE_E */
285 	ODM_CMNINFO_IC_TYPE,					/*  ODM_IC_TYPE_E */
286 	ODM_CMNINFO_CUT_VER,					/*  ODM_CUT_VERSION_E */
287 	ODM_CMNINFO_FAB_VER,					/*  ODM_FAB_E */
288 	ODM_CMNINFO_RFE_TYPE,
289 	ODM_CMNINFO_PACKAGE_TYPE,
290 	ODM_CMNINFO_EXT_LNA,					/*  true */
291 	ODM_CMNINFO_EXT_PA,
292 	ODM_CMNINFO_GPA,
293 	ODM_CMNINFO_APA,
294 	ODM_CMNINFO_GLNA,
295 	ODM_CMNINFO_ALNA,
296 	ODM_CMNINFO_EXT_TRSW,
297 	ODM_CMNINFO_PATCH_ID,				/* CUSTOMER ID */
298 	ODM_CMNINFO_BINHCT_TEST,
299 	ODM_CMNINFO_BWIFI_TEST,
300 	ODM_CMNINFO_SMART_CONCURRENT,
301 	/* HOOK BEFORE REG INIT----------- */
302 
303 	/*  Dynamic value: */
304 /*  POINTER REFERENCE----------- */
305 	ODM_CMNINFO_MAC_PHY_MODE,	/*  ODM_MAC_PHY_MODE_E */
306 	ODM_CMNINFO_TX_UNI,
307 	ODM_CMNINFO_RX_UNI,
308 	ODM_CMNINFO_WM_MODE,		/*  ODM_WIRELESS_MODE_E */
309 	ODM_CMNINFO_SEC_CHNL_OFFSET,	/*  ODM_SEC_CHNL_OFFSET_E */
310 	ODM_CMNINFO_SEC_MODE,		/*  ODM_SECURITY_E */
311 	ODM_CMNINFO_BW,			/*  ODM_BW_E */
312 	ODM_CMNINFO_CHNL,
313 	ODM_CMNINFO_FORCED_RATE,
314 
315 	ODM_CMNINFO_DMSP_GET_VALUE,
316 	ODM_CMNINFO_BUDDY_ADAPTOR,
317 	ODM_CMNINFO_DMSP_IS_MASTER,
318 	ODM_CMNINFO_SCAN,
319 	ODM_CMNINFO_POWER_SAVING,
320 	ODM_CMNINFO_ONE_PATH_CCA,	/*  ODM_CCA_PATH_E */
321 	ODM_CMNINFO_DRV_STOP,
322 	ODM_CMNINFO_PNP_IN,
323 	ODM_CMNINFO_INIT_ON,
324 	ODM_CMNINFO_ANT_TEST,
325 	ODM_CMNINFO_NET_CLOSED,
326 	ODM_CMNINFO_MP_MODE,
327 	/* ODM_CMNINFO_RTSTA_AID,	 For win driver only? */
328 	ODM_CMNINFO_FORCED_IGI_LB,
329 	ODM_CMNINFO_IS1ANTENNA,
330 	ODM_CMNINFO_RFDEFAULTPATH,
331 /*  POINTER REFERENCE----------- */
332 
333 /* CALL BY VALUE------------- */
334 	ODM_CMNINFO_WIFI_DIRECT,
335 	ODM_CMNINFO_WIFI_DISPLAY,
336 	ODM_CMNINFO_LINK_IN_PROGRESS,
337 	ODM_CMNINFO_LINK,
338 	ODM_CMNINFO_STATION_STATE,
339 	ODM_CMNINFO_RSSI_MIN,
340 	ODM_CMNINFO_DBG_COMP,			/*  u64 */
341 	ODM_CMNINFO_DBG_LEVEL,			/*  u32 */
342 	ODM_CMNINFO_RA_THRESHOLD_HIGH,		/*  u8 */
343 	ODM_CMNINFO_RA_THRESHOLD_LOW,		/*  u8 */
344 	ODM_CMNINFO_RF_ANTENNA_TYPE,		/*  u8 */
345 	ODM_CMNINFO_BT_ENABLED,
346 	ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
347 	ODM_CMNINFO_BT_HS_RSSI,
348 	ODM_CMNINFO_BT_OPERATION,
349 	ODM_CMNINFO_BT_LIMITED_DIG,		/* Need to Limited Dig or not */
350 	ODM_CMNINFO_BT_DISABLE_EDCA,
351 /* CALL BY VALUE------------- */
352 
353 	/*  Dynamic ptr array hook itms. */
354 	ODM_CMNINFO_STA_STATUS,
355 	ODM_CMNINFO_PHY_STATUS,
356 	ODM_CMNINFO_MAC_STATUS,
357 
358 	ODM_CMNINFO_MAX,
359 };
360 
361 /*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
362 enum { /* _ODM_Support_Ability_Definition */
363 	/*  */
364 	/*  BB ODM section BIT 0-15 */
365 	/*  */
366 	ODM_BB_DIG			= BIT0,
367 	ODM_BB_RA_MASK			= BIT1,
368 	ODM_BB_DYNAMIC_TXPWR		= BIT2,
369 	ODM_BB_FA_CNT			= BIT3,
370 	ODM_BB_RSSI_MONITOR		= BIT4,
371 	ODM_BB_CCK_PD			= BIT5,
372 	ODM_BB_ANT_DIV			= BIT6,
373 	ODM_BB_PWR_SAVE			= BIT7,
374 	ODM_BB_PWR_TRAIN		= BIT8,
375 	ODM_BB_RATE_ADAPTIVE		= BIT9,
376 	ODM_BB_PATH_DIV			= BIT10,
377 	ODM_BB_PSD			= BIT11,
378 	ODM_BB_RXHP			= BIT12,
379 	ODM_BB_ADAPTIVITY		= BIT13,
380 	ODM_BB_CFO_TRACKING		= BIT14,
381 
382 	/*  MAC DM section BIT 16-23 */
383 	ODM_MAC_EDCA_TURBO		= BIT16,
384 	ODM_MAC_EARLY_MODE		= BIT17,
385 
386 	/*  RF ODM section BIT 24-31 */
387 	ODM_RF_TX_PWR_TRACK		= BIT24,
388 	ODM_RF_RX_GAIN_TRACK	= BIT25,
389 	ODM_RF_CALIBRATION		= BIT26,
390 };
391 
392 /* 	ODM_CMNINFO_INTERFACE */
393 enum { /* tag_ODM_Support_Interface_Definition */
394 	ODM_ITRF_SDIO	=	0x4,
395 	ODM_ITRF_ALL	=	0x7,
396 };
397 
398 /*  ODM_CMNINFO_IC_TYPE */
399 enum { /* tag_ODM_Support_IC_Type_Definition */
400 	ODM_RTL8723B	=	BIT8,
401 };
402 
403 /* ODM_CMNINFO_CUT_VER */
404 enum { /* tag_ODM_Cut_Version_Definition */
405 	ODM_CUT_A		=	0,
406 	ODM_CUT_B		=	1,
407 	ODM_CUT_C		=	2,
408 	ODM_CUT_D		=	3,
409 	ODM_CUT_E		=	4,
410 	ODM_CUT_F		=	5,
411 
412 	ODM_CUT_I		=	8,
413 	ODM_CUT_J		=	9,
414 	ODM_CUT_K		=	10,
415 	ODM_CUT_TEST	=	15,
416 };
417 
418 /*  ODM_CMNINFO_FAB_VER */
419 enum { /* tag_ODM_Fab_Version_Definition */
420 	ODM_TSMC	=	0,
421 	ODM_UMC		=	1,
422 };
423 
424 /*  */
425 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
426 /*  */
427 enum { /* tag_ODM_RF_Type_Definition */
428 	ODM_1T1R	=	0,
429 	ODM_1T2R	=	1,
430 	ODM_2T2R	=	2,
431 	ODM_2T3R	=	3,
432 	ODM_2T4R	=	4,
433 	ODM_3T3R	=	5,
434 	ODM_3T4R	=	6,
435 	ODM_4T4R	=	7,
436 };
437 
438 /*  */
439 /*  ODM Dynamic common info value definition */
440 /*  */
441 
442 /*  ODM_CMNINFO_WM_MODE */
443 enum { /* tag_Wireless_Mode_Definition */
444 	ODM_WM_UNKNOWN    = 0x0,
445 	ODM_WM_B          = BIT0,
446 	ODM_WM_G          = BIT1,
447 	ODM_WM_N24G       = BIT3,
448 	ODM_WM_AUTO       = BIT5,
449 };
450 
451 /*  ODM_CMNINFO_BW */
452 enum { /* tag_Bandwidth_Definition */
453 	ODM_BW20M		= 0,
454 	ODM_BW40M		= 1,
455 };
456 
457 /*  For AC-series IC, external PA & LNA can be individually added on 2.4G */
458 
459 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */
460 	TYPE_GPA0 = 0,
461 	TYPE_GPA1 = BIT(1)|BIT(0)
462 };
463 
464 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */
465 	TYPE_APA0 = 0,
466 	TYPE_APA1 = BIT(1)|BIT(0)
467 };
468 
469 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */
470 	TYPE_GLNA0 = 0,
471 	TYPE_GLNA1 = BIT(2)|BIT(0),
472 	TYPE_GLNA2 = BIT(3)|BIT(1),
473 	TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
474 };
475 
476 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */
477 	TYPE_ALNA0 = 0,
478 	TYPE_ALNA1 = BIT(2)|BIT(0),
479 	TYPE_ALNA2 = BIT(3)|BIT(1),
480 	TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
481 };
482 
483 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */
484 	bool bIQKDone;
485 	s32 Value[3][IQK_Matrix_REG_NUM];
486 	bool bBWIqkResultSaved[3];
487 };
488 
489 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
490 
491 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */
492 	/* for tx power tracking */
493 
494 	u32 RegA24; /*  for TempCCK */
495 	s32 RegE94;
496 	s32 RegE9C;
497 	s32 RegEB4;
498 	s32 RegEBC;
499 
500 	u8 TXPowercount;
501 	bool bTXPowerTrackingInit;
502 	bool bTXPowerTracking;
503 	u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
504 	u8 TM_Trigger;
505 
506 	u8 ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
507 	u8 ThermalValue;
508 	u8 ThermalValue_LCK;
509 	u8 ThermalValue_IQK;
510 	u8 ThermalValue_DPK;
511 	u8 ThermalValue_AVG[AVG_THERMAL_NUM];
512 	u8 ThermalValue_AVG_index;
513 	u8 ThermalValue_RxGain;
514 	u8 ThermalValue_Crystal;
515 	u8 ThermalValue_DPKstore;
516 	u8 ThermalValue_DPKtrack;
517 	bool TxPowerTrackingInProgress;
518 
519 	bool bReloadtxpowerindex;
520 	u8 bRfPiEnable;
521 	u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
522 
523 	/*  Tx power Tracking ------------------------- */
524 	u8 bCCKinCH14;
525 	u8 CCK_index;
526 	u8 OFDM_index[MAX_RF_PATH];
527 	s8 PowerIndexOffset[MAX_RF_PATH];
528 	s8 DeltaPowerIndex[MAX_RF_PATH];
529 	s8 DeltaPowerIndexLast[MAX_RF_PATH];
530 	bool bTxPowerChanged;
531 
532 	u8 ThermalValue_HP[HP_THERMAL_NUM];
533 	u8 ThermalValue_HP_index;
534 	struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
535 	bool bNeedIQK;
536 	bool bIQKInProgress;
537 	u8 Delta_IQK;
538 	u8 Delta_LCK;
539 	s8 BBSwingDiff2G; /*  Unit: dB */
540 	u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
541 	u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
542 	u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
543 	u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
544 	u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
545 	u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
546 	u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
547 	u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
548 	u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
549 	u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
550 
551 	/*  */
552 
553 	/* for IQK */
554 	u32 RegC04;
555 	u32 Reg874;
556 	u32 RegC08;
557 	u32 RegB68;
558 	u32 RegB6C;
559 	u32 Reg870;
560 	u32 Reg860;
561 	u32 Reg864;
562 
563 	bool bIQKInitialized;
564 	bool bLCKInProgress;
565 	bool bAntennaDetected;
566 	u32 ADDA_backup[IQK_ADDA_REG_NUM];
567 	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
568 	u32 IQK_BB_backup_recover[9];
569 	u32 IQK_BB_backup[IQK_BB_REG_NUM];
570 	u32 TxIQC_8723B[2][3][2]; /*  { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
571 	u32 RxIQC_8723B[2][2][2]; /*  { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
572 
573 	/* for APK */
574 	u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
575 	u8 bAPKdone;
576 	u8 bAPKThermalMeterIgnore;
577 
578 	/*  DPK */
579 	bool bDPKFail;
580 	u8 bDPdone;
581 	u8 bDPPathAOK;
582 	u8 bDPPathBOK;
583 
584 	u32 TxLOK[2];
585 
586 };
587 /*  */
588 /*  ODM Dynamic common info value definition */
589 /*  */
590 
591 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */
592 	u8 Bssid[6];
593 	u8 antsel_rx_keep_0;
594 	u8 antsel_rx_keep_1;
595 	u8 antsel_rx_keep_2;
596 	u8 antsel_rx_keep_3;
597 	u32 antSumRSSI[7];
598 	u32 antRSSIcnt[7];
599 	u32 antAveRSSI[7];
600 	u8 FAT_State;
601 	u32 TrainIdx;
602 	u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
603 	u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
604 	u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
605 	u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
606 	u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
607 	u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
608 	u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
609 	u8 RxIdleAnt;
610 	bool	bBecomeLinked;
611 	u32 MinMaxRSSI;
612 	u8 idx_AntDiv_counter_2G;
613 	u32 CCK_counter_main;
614 	u32 CCK_counter_aux;
615 	u32 OFDM_counter_main;
616 	u32 OFDM_counter_aux;
617 
618 	u32 CCK_CtrlFrame_Cnt_main;
619 	u32 CCK_CtrlFrame_Cnt_aux;
620 	u32 OFDM_CtrlFrame_Cnt_main;
621 	u32 OFDM_CtrlFrame_Cnt_aux;
622 	u32 MainAnt_CtrlFrame_Sum;
623 	u32 AuxAnt_CtrlFrame_Sum;
624 	u32 MainAnt_CtrlFrame_Cnt;
625 	u32 AuxAnt_CtrlFrame_Cnt;
626 
627 };
628 
629 enum {
630 	NO_ANTDIV			= 0xFF,
631 	CG_TRX_HW_ANTDIV		= 0x01,
632 	CGCS_RX_HW_ANTDIV	= 0x02,
633 	FIXED_HW_ANTDIV		= 0x03,
634 	CG_TRX_SMART_ANTDIV	= 0x04,
635 	CGCS_RX_SW_ANTDIV	= 0x05,
636 	S0S1_SW_ANTDIV          = 0x06 /* 8723B intrnal switch S0 S1 */
637 };
638 
639 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */
640 	u8 RespTxPath;
641 	u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
642 	u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
643 	u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
644 	u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
645 	u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
646 };
647 
648 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */
649 	PHY_REG_PG_RELATIVE_VALUE = 0,
650 	PHY_REG_PG_EXACT_VALUE = 1
651 };
652 
653 /*  */
654 /*  Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
655 /*  */
656 struct ant_detected_info {
657 	bool bAntDetected;
658 	u32 dBForAntA;
659 	u32 dBForAntB;
660 	u32 dBForAntO;
661 };
662 
663 /*  */
664 /*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
665 /*  */
666 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */
667 	/* struct timer_list	FastAntTrainingTimer; */
668 	/*  */
669 	/* 	Add for different team use temporarily */
670 	/*  */
671 	struct adapter *Adapter;		/*  For CE/NIC team */
672 	/*  WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
673 	bool odm_ready;
674 
675 	enum phy_reg_pg_type PhyRegPgValueType;
676 	u8 PhyRegPgVersion;
677 
678 	u32 NumQryPhyStatusAll;	/* CCK + OFDM */
679 	u32 LastNumQryPhyStatusAll;
680 	u32 RxPWDBAve;
681 	bool MPDIG_2G;		/* off MPDIG */
682 	u8 Times_2G;
683 
684 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
685 	bool bCckHighPower;
686 	u8 RFPathRxEnable;		/*  ODM_CMNINFO_RFPATH_ENABLE */
687 	u8 ControlChannel;
688 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
689 
690 /* REMOVED COMMON INFO---------- */
691 	/* u8 		PseudoMacPhyMode; */
692 	/* bool			*BTCoexist; */
693 	/* bool			PseudoBtCoexist; */
694 	/* u8 		OPMode; */
695 	/* bool			bAPMode; */
696 	/* bool			bClientMode; */
697 	/* bool			bAdHocMode; */
698 	/* bool			bSlaveOfDMSP; */
699 /* REMOVED COMMON INFO---------- */
700 
701 /* 1  COMMON INFORMATION */
702 
703 	/*  */
704 	/*  Init Value */
705 	/*  */
706 /* HOOK BEFORE REG INIT----------- */
707 	/*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
708 	u8 SupportPlatform;
709 	/*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */
710 	u32 SupportAbility;
711 	/*  ODM PCIE/USB/SDIO = 1/2/3 */
712 	u8 SupportInterface;
713 	/*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
714 	u32 SupportICType;
715 	/*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
716 	u8 CutVersion;
717 	/*  Fab Version TSMC/UMC = 0/1 */
718 	u8 FabVersion;
719 	/*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
720 	u8 RFEType;
721 	/*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
722 	u8 BoardType;
723 	u8 PackageType;
724 	u8 TypeGLNA;
725 	u8 TypeGPA;
726 	u8 TypeALNA;
727 	u8 TypeAPA;
728 	/*  with external LNA  NO/Yes = 0/1 */
729 	u8 ExtLNA;
730 	/*  with external PA  NO/Yes = 0/1 */
731 	u8 ExtPA;
732 	/*  with external TRSW  NO/Yes = 0/1 */
733 	u8 ExtTRSW;
734 	u8 PatchID; /* Customer ID */
735 	bool bInHctTest;
736 	bool bWIFITest;
737 
738 	bool bDualMacSmartConcurrent;
739 	u32 BK_SupportAbility;
740 	u8 AntDivType;
741 /* HOOK BEFORE REG INIT----------- */
742 
743 	/*  */
744 	/*  Dynamic Value */
745 	/*  */
746 /*  POINTER REFERENCE----------- */
747 
748 	u8 u8_temp;
749 	bool bool_temp;
750 	struct adapter *adapter_temp;
751 
752 	/*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
753 	u8 *pMacPhyMode;
754 	/* TX Unicast byte count */
755 	u64 *pNumTxBytesUnicast;
756 	/* RX Unicast byte count */
757 	u64 *pNumRxBytesUnicast;
758 	/*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
759 	u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
760 	/*  Secondary channel offset don't_care/below/above = 0/1/2 */
761 	u8 *pSecChOffset;
762 	/*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
763 	u8 *pSecurity;
764 	/*  BW info 20M/40M/80M = 0/1/2 */
765 	u8 *pBandWidth;
766 	/*  Central channel location Ch1/Ch2/.... */
767 	u8 *pChannel; /* central channel number */
768 	bool DPK_Done;
769 	/*  Common info for 92D DMSP */
770 
771 	bool *pbGetValueFromOtherMac;
772 	struct adapter **pBuddyAdapter;
773 	bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
774 	/*  Common info for Status */
775 	bool *pbScanInProcess;
776 	bool *pbPowerSaving;
777 	/*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
778 	u8 *pOnePathCCA;
779 	/* pMgntInfo->AntennaTest */
780 	u8 *pAntennaTest;
781 	bool *pbNet_closed;
782 	u8 *mp_mode;
783 	/* u8 	*pAidMap; */
784 	u8 *pu1ForcedIgiLb;
785 /*  For 8723B IQK----------- */
786 	bool *pIs1Antenna;
787 	u8 *pRFDefaultPath;
788 	/*  0:S1, 1:S0 */
789 
790 /*  POINTER REFERENCE----------- */
791 	u16 *pForcedDataRate;
792 /* CALL BY VALUE------------- */
793 	bool bLinkInProcess;
794 	bool bWIFI_Direct;
795 	bool bWIFI_Display;
796 	bool bLinked;
797 
798 	bool bsta_state;
799 	u8 RSSI_Min;
800 	u8 InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
801 	bool bOneEntryOnly;
802 	/*  Common info for BTDM */
803 	bool bBtEnabled;			/*  BT is disabled */
804 	bool bBtConnectProcess;	/*  BT HS is under connection progress. */
805 	u8 btHsRssi;				/*  BT HS mode wifi rssi value. */
806 	bool bBtHsOperation;		/*  BT HS mode is under progress */
807 	bool bBtDisableEdcaTurbo;	/*  Under some condition, don't enable the EDCA Turbo */
808 	bool bBtLimitedDig;			/*  BT is busy. */
809 /* CALL BY VALUE------------- */
810 	u8 RSSI_A;
811 	u8 RSSI_B;
812 	u64 RSSI_TRSW;
813 	u64 RSSI_TRSW_H;
814 	u64 RSSI_TRSW_L;
815 	u64 RSSI_TRSW_iso;
816 
817 	u8 RxRate;
818 	bool bNoisyState;
819 	u8 TxRate;
820 	u8 LinkedInterval;
821 	u8 preChannel;
822 	u32 TxagcOffsetValueA;
823 	bool IsTxagcOffsetPositiveA;
824 	u32 TxagcOffsetValueB;
825 	bool IsTxagcOffsetPositiveB;
826 	u64	lastTxOkCnt;
827 	u64	lastRxOkCnt;
828 	u32 BbSwingOffsetA;
829 	bool IsBbSwingOffsetPositiveA;
830 	u32 BbSwingOffsetB;
831 	bool IsBbSwingOffsetPositiveB;
832 	s8 TH_L2H_ini;
833 	s8 TH_EDCCA_HL_diff;
834 	s8 IGI_Base;
835 	u8 IGI_target;
836 	bool ForceEDCCA;
837 	u8 AdapEn_RSSI;
838 	s8 Force_TH_H;
839 	s8 Force_TH_L;
840 	u8 IGI_LowerBound;
841 	u8 antdiv_rssi;
842 	u8 AntType;
843 	u8 pre_AntType;
844 	u8 antdiv_period;
845 	u8 antdiv_select;
846 	u8 NdpaPeriod;
847 	bool H2C_RARpt_connect;
848 
849 	/*  add by Yu Cehn for adaptivtiy */
850 	bool adaptivity_flag;
851 	bool NHM_disable;
852 	bool TxHangFlg;
853 	bool Carrier_Sense_enable;
854 	u8 tolerance_cnt;
855 	u64 NHMCurTxOkcnt;
856 	u64 NHMCurRxOkcnt;
857 	u64 NHMLastTxOkcnt;
858 	u64 NHMLastRxOkcnt;
859 	u8 txEdcca1;
860 	u8 txEdcca0;
861 	s8 H2L_lb;
862 	s8 L2H_lb;
863 	u8 Adaptivity_IGI_upper;
864 	u8 NHM_cnt_0;
865 
866 	struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */
867 	/*  */
868 	/* 2 Define STA info. */
869 	/*  _ODM_STA_INFO */
870 	/*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
871 	PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
872 
873 	/*  */
874 	/*  2012/02/14 MH Add to share 88E ra with other SW team. */
875 	/*  We need to colelct all support abilit to a proper area. */
876 	/*  */
877 	bool RaSupport88E;
878 
879 	/*  Define ........... */
880 
881 	/*  Latest packet phy info (ODM write) */
882 	struct odm_phy_dbg_info PhyDbgInfo;
883 	/* PHY_INFO_88E		PhyInfo; */
884 
885 	/*  Latest packet phy info (ODM write) */
886 	struct odm_mac_status_info *pMacInfo;
887 	/* MAC_INFO_88E		MacInfo; */
888 
889 	/*  Different Team independt structure?? */
890 
891 	/*  */
892 	/* TX_RTP_CMN		TX_retrpo; */
893 	/* TX_RTP_88E		TX_retrpo; */
894 	/* TX_RTP_8195		TX_retrpo; */
895 
896 	/*  */
897 	/* ODM Structure */
898 	/*  */
899 	struct fat_t DM_FatTable;
900 	struct dig_t DM_DigTable;
901 	struct ps_t DM_PSTable;
902 	struct dynamic_primary_CCA DM_PriCCA;
903 	struct rxhp_t dM_RXHP_Table;
904 	struct ra_t DM_RA_Table;
905 	struct false_ALARM_STATISTICS FalseAlmCnt;
906 	struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
907 	struct swat_t DM_SWAT_Table;
908 	bool RSSI_test;
909 	struct cfo_tracking DM_CfoTrack;
910 
911 	struct edca_t DM_EDCA_Table;
912 	u32 WMMEDCA_BE;
913 	struct pathdiv_t DM_PathDiv;
914 	/*  Copy from SD4 structure */
915 	/*  */
916 	/*  ================================================== */
917 	/*  */
918 
919 	/* common */
920 	/* u8 DM_Type; */
921 	/* u8    PSD_Report_RXHP[80];    Add By Gary */
922 	/* u8    PSD_func_flag;                Add By Gary */
923 	/* for DIG */
924 	/* u8 bDMInitialGainEnable; */
925 	/* u8 binitialized;  for dm_initial_gain_Multi_STA use. */
926 	/* for Antenna diversity */
927 	/* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
928 	/* PSTA_INFO_T RSSI_target; */
929 
930 	bool *pbDriverStopped;
931 	bool *pbDriverIsGoingToPnpSetPowerSleep;
932 	bool *pinit_adpt_in_progress;
933 
934 	/* PSD */
935 	bool bUserAssignLevel;
936 	struct timer_list PSDTimer;
937 	u8 RSSI_BT;			/* come from BT */
938 	bool bPSDinProcess;
939 	bool bPSDactive;
940 	bool bDMInitialGainEnable;
941 
942 	/* MPT DIG */
943 	struct timer_list MPT_DIGTimer;
944 
945 	/* for rate adaptive, in fact,  88c/92c fw will handle this */
946 	u8 bUseRAMask;
947 
948 	struct odm_rate_adaptive RateAdaptive;
949 
950 	struct ant_detected_info AntDetectedInfo; /*  Antenna detected information for RSSI tool */
951 
952 	struct odm_rf_cal_t RFCalibrateInfo;
953 
954 	/*  */
955 	/*  TX power tracking */
956 	/*  */
957 	u8 BbSwingIdxOfdm[MAX_RF_PATH];
958 	u8 BbSwingIdxOfdmCurrent;
959 	u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
960 	bool BbSwingFlagOfdm;
961 	u8 BbSwingIdxCck;
962 	u8 BbSwingIdxCckCurrent;
963 	u8 BbSwingIdxCckBase;
964 	u8 DefaultOfdmIndex;
965 	u8 DefaultCckIndex;
966 	bool BbSwingFlagCck;
967 
968 	s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
969 	s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
970 	s8 Remnant_CCKSwingIdx;
971 	s8 Modify_TxAGC_Value;       /* Remnat compensate value at TxAGC */
972 	bool Modify_TxAGC_Flag_PathA;
973 	bool Modify_TxAGC_Flag_PathB;
974 	bool Modify_TxAGC_Flag_PathC;
975 	bool Modify_TxAGC_Flag_PathD;
976 	bool Modify_TxAGC_Flag_PathA_CCK;
977 
978 	s8 KfreeOffset[MAX_RF_PATH];
979 	/*  */
980 	/*  ODM system resource. */
981 	/*  */
982 
983 	/*  ODM relative time. */
984 	struct timer_list PathDivSwitchTimer;
985 	/* 2011.09.27 add for Path Diversity */
986 	struct timer_list CCKPathDiversityTimer;
987 	struct timer_list FastAntTrainingTimer;
988 
989 	/*  ODM relative workitem. */
990 
991 	#if (BEAMFORMING_SUPPORT == 1)
992 	RT_BEAMFORMING_INFO BeamformingInfo;
993 	#endif
994 };
995 
996  enum odm_rf_content {
997 	odm_radioa_txt = 0x1000,
998 	odm_radiob_txt = 0x1001,
999 	odm_radioc_txt = 0x1002,
1000 	odm_radiod_txt = 0x1003
1001 };
1002 
1003 enum ODM_BB_Config_Type {
1004 	CONFIG_BB_PHY_REG,
1005 	CONFIG_BB_AGC_TAB,
1006 	CONFIG_BB_AGC_TAB_2G,
1007 	CONFIG_BB_PHY_REG_PG,
1008 	CONFIG_BB_PHY_REG_MP,
1009 	CONFIG_BB_AGC_TAB_DIFF,
1010 };
1011 
1012 enum ODM_RF_Config_Type {
1013 	CONFIG_RF_RADIO,
1014 	CONFIG_RF_TXPWR_LMT,
1015 };
1016 
1017 enum ODM_FW_Config_Type {
1018 	CONFIG_FW_NIC,
1019 	CONFIG_FW_NIC_2,
1020 	CONFIG_FW_AP,
1021 	CONFIG_FW_WoWLAN,
1022 	CONFIG_FW_WoWLAN_2,
1023 	CONFIG_FW_AP_WoWLAN,
1024 	CONFIG_FW_BT,
1025 };
1026 
1027 #ifdef REMOVE_PACK
1028 #pragma pack()
1029 #endif
1030 
1031 /* include "odm_function.h" */
1032 
1033 /* 3 =========================================================== */
1034 /* 3 DIG */
1035 /* 3 =========================================================== */
1036 
1037 /* Remove DIG by Yuchen */
1038 
1039 /* 3 =========================================================== */
1040 /* 3 AGC RX High Power Mode */
1041 /* 3 =========================================================== */
1042 #define          LNA_Low_Gain_1                      0x64
1043 #define          LNA_Low_Gain_2                      0x5A
1044 #define          LNA_Low_Gain_3                      0x58
1045 
1046 #define          FA_RXHP_TH1                           5000
1047 #define          FA_RXHP_TH2                           1500
1048 #define          FA_RXHP_TH3                             800
1049 #define          FA_RXHP_TH4                             600
1050 #define          FA_RXHP_TH5                             500
1051 
1052 /* 3 =========================================================== */
1053 /* 3 EDCA */
1054 /* 3 =========================================================== */
1055 
1056 /* 3 =========================================================== */
1057 /* 3 Dynamic Tx Power */
1058 /* 3 =========================================================== */
1059 /* Dynamic Tx Power Control Threshold */
1060 
1061 /* 3 =========================================================== */
1062 /* 3 Rate Adaptive */
1063 /* 3 =========================================================== */
1064 #define		DM_RATR_STA_INIT			0
1065 #define		DM_RATR_STA_HIGH			1
1066 #define		DM_RATR_STA_MIDDLE			2
1067 #define		DM_RATR_STA_LOW				3
1068 
1069 /* 3 =========================================================== */
1070 /* 3 BB Power Save */
1071 /* 3 =========================================================== */
1072 
1073 enum { /* tag_1R_CCA_Type_Definition */
1074 	CCA_1R = 0,
1075 	CCA_2R = 1,
1076 	CCA_MAX = 2,
1077 };
1078 
1079 enum { /* tag_RF_Type_Definition */
1080 	RF_Save = 0,
1081 	RF_Normal = 1,
1082 	RF_MAX = 2,
1083 };
1084 
1085 /*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1086 #define	MAX_ANTENNA_DETECTION_CNT	10
1087 
1088 /*  */
1089 /*  Extern Global Variables. */
1090 /*  */
1091 extern	u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1092 extern	u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1093 extern	u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1094 
1095 extern	u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1096 extern	u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1097 extern	u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1098 
1099 extern  u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1100 
1101 /*  */
1102 /*  check Sta pointer valid or not */
1103 /*  */
1104 #define IS_STA_VALID(pSta)		(pSta)
1105 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1106 /*  This indicates two different the steps. */
1107 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1108 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1109 /*  with original RSSI to determine if it is necessary to switch antenna. */
1110 #define SWAW_STEP_PEAK		0
1111 #define SWAW_STEP_DETERMINE	1
1112 
1113 /* Remove BB power saving by Yuchen */
1114 
1115 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1116 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm);
1117 
1118 bool ODM_RAStateCheck(
1119 	struct dm_odm_t *pDM_Odm,
1120 	s32	RSSI,
1121 	bool bForceUpdate,
1122 	u8 *pRATRState
1123 );
1124 
1125 #define dm_SWAW_RSSI_Check	ODM_SwAntDivChkPerPktRssi
1126 void ODM_SwAntDivChkPerPktRssi(
1127 	struct dm_odm_t *pDM_Odm,
1128 	u8 StationID,
1129 	struct odm_phy_info *pPhyInfo
1130 );
1131 
1132 u32 ODM_Get_Rate_Bitmap(
1133 	struct dm_odm_t *pDM_Odm,
1134 	u32 macid,
1135 	u32 ra_mask,
1136 	u8 rssi_level
1137 );
1138 
1139 #if (BEAMFORMING_SUPPORT == 1)
1140 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1141 #endif
1142 
1143 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm);
1144 
1145 void ODM_DMInit(struct dm_odm_t *pDM_Odm);
1146 
1147 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /*  For common use in the future */
1148 
1149 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value);
1150 
1151 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue);
1152 
1153 void ODM_CmnInfoPtrArrayHook(
1154 	struct dm_odm_t *pDM_Odm,
1155 	enum odm_cmninfo_e CmnInfo,
1156 	u16 Index,
1157 	void *pValue
1158 );
1159 
1160 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value);
1161 
1162 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm);
1163 
1164 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm);
1165 
1166 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm);
1167 
1168 void ODM_AntselStatistics_88C(
1169 	struct dm_odm_t *pDM_Odm,
1170 	u8 MacId,
1171 	u32 PWDBAll,
1172 	bool isCCKrate
1173 );
1174 
1175 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State);
1176 
1177 #endif
1178