1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_PathDiv.h" 15 #include "odm_DynamicBBPowerSaving.h" 16 #include "odm_DynamicTxPower.h" 17 #include "odm_CfoTracking.h" 18 #include "odm_NoiseMonitor.h" 19 20 #define TP_MODE 0 21 #define RSSI_MODE 1 22 #define TRAFFIC_LOW 0 23 #define TRAFFIC_HIGH 1 24 #define NONE 0 25 26 /* 3 Tx Power Tracking */ 27 /* 3 ============================================================ */ 28 #define DPK_DELTA_MAPPING_NUM 13 29 #define index_mapping_HP_NUM 15 30 #define OFDM_TABLE_SIZE 43 31 #define CCK_TABLE_SIZE 33 32 #define TXSCALE_TABLE_SIZE 37 33 #define TXPWR_TRACK_TABLE_SIZE 30 34 #define DELTA_SWINGIDX_SIZE 30 35 #define BAND_NUM 4 36 37 /* 3 PSD Handler */ 38 /* 3 ============================================================ */ 39 40 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 41 #define MODE_40M 0 /* 0:20M, 1:40M */ 42 #define PSD_TH2 3 43 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 44 #define SIR_STEP_SIZE 3 45 #define Smooth_Size_1 5 46 #define Smooth_TH_1 3 47 #define Smooth_Size_2 10 48 #define Smooth_TH_2 4 49 #define Smooth_Size_3 20 50 #define Smooth_TH_3 4 51 #define Smooth_Step_Size 5 52 #define Adaptive_SIR 1 53 #define PSD_RESCAN 4 54 #define PSD_SCAN_INTERVAL 700 /* ms */ 55 56 /* 8723A High Power IGI Setting */ 57 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 58 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 59 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 60 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 61 62 /* ANT Test */ 63 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 64 #define ANTTESTA 0x01 /* Ant A will be Testing */ 65 #define ANTTESTB 0x02 /* Ant B will be testing */ 66 67 #define PS_MODE_ACTIVE 0x01 68 69 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 70 #define MAIN_ANT 1 /* Ant A or Ant Main */ 71 #define AUX_ANT 2 /* AntB or Ant Aux */ 72 #define MAX_ANT 3 /* 3 for AP using */ 73 74 /* Antenna Diversity Type */ 75 #define SW_ANTDIV 0 76 #define HW_ANTDIV 1 77 /* structure and define */ 78 79 /* Remove DIG by Yuchen */ 80 81 /* Remoce BB power saving by Yuchn */ 82 83 /* Remove DIG by yuchen */ 84 85 struct dynamic_primary_CCA { 86 u8 PriCCA_flag; 87 u8 intf_flag; 88 u8 intf_type; 89 u8 DupRTS_flag; 90 u8 Monitor_flag; 91 u8 CH_offset; 92 u8 MF_state; 93 }; 94 95 struct ra_t { 96 u8 firstconnect; 97 }; 98 99 struct rxhp_t { 100 u8 RXHP_flag; 101 u8 PSD_func_trigger; 102 u8 PSD_bitmap_RXHP[80]; 103 u8 Pre_IGI; 104 u8 Cur_IGI; 105 u8 Pre_pw_th; 106 u8 Cur_pw_th; 107 bool First_time_enter; 108 bool RXHP_enable; 109 u8 TP_Mode; 110 struct timer_list PSDTimer; 111 }; 112 113 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 114 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 115 116 /* This indicates two different the steps. */ 117 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 118 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 119 /* with original RSSI to determine if it is necessary to switch antenna. */ 120 #define SWAW_STEP_PEAK 0 121 #define SWAW_STEP_DETERMINE 1 122 123 #define TP_MODE 0 124 #define RSSI_MODE 1 125 #define TRAFFIC_LOW 0 126 #define TRAFFIC_HIGH 1 127 #define TRAFFIC_UltraLOW 2 128 129 struct swat_t { /* _SW_Antenna_Switch_ */ 130 u8 Double_chk_flag; 131 u8 try_flag; 132 s32 PreRSSI; 133 u8 CurAntenna; 134 u8 PreAntenna; 135 u8 RSSI_Trying; 136 u8 TestMode; 137 u8 bTriggerAntennaSwitch; 138 u8 SelectAntennaMap; 139 u8 RSSI_target; 140 u8 reset_idx; 141 u16 Single_Ant_Counter; 142 u16 Dual_Ant_Counter; 143 u16 Aux_FailDetec_Counter; 144 u16 Retry_Counter; 145 146 /* Before link Antenna Switch check */ 147 u8 SWAS_NoLink_State; 148 u32 SWAS_NoLink_BK_Reg860; 149 u32 SWAS_NoLink_BK_Reg92c; 150 u32 SWAS_NoLink_BK_Reg948; 151 bool ANTA_ON; /* To indicate Ant A is or not */ 152 bool ANTB_ON; /* To indicate Ant B is on or not */ 153 bool Pre_Aux_FailDetec; 154 bool RSSI_AntDect_bResult; 155 u8 Ant5G; 156 u8 Ant2G; 157 158 s32 RSSI_sum_A; 159 s32 RSSI_sum_B; 160 s32 RSSI_cnt_A; 161 s32 RSSI_cnt_B; 162 163 u64 lastTxOkCnt; 164 u64 lastRxOkCnt; 165 u64 TXByteCnt_A; 166 u64 TXByteCnt_B; 167 u64 RXByteCnt_A; 168 u64 RXByteCnt_B; 169 u8 TrafficLoad; 170 u8 Train_time; 171 u8 Train_time_flag; 172 struct timer_list SwAntennaSwitchTimer; 173 struct timer_list SwAntennaSwitchTimer_8723B; 174 u32 PktCnt_SWAntDivByCtrlFrame; 175 bool bSWAntDivByCtrlFrame; 176 }; 177 178 /* Remove Edca by YuChen */ 179 180 181 struct odm_rate_adaptive { 182 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 183 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 184 bool bUseLdpc; 185 bool bLowerRtsRate; 186 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 187 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 188 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 189 190 }; 191 192 #define IQK_MAC_REG_NUM 4 193 #define IQK_ADDA_REG_NUM 16 194 #define IQK_BB_REG_NUM_MAX 10 195 #define IQK_BB_REG_NUM 9 196 #define HP_THERMAL_NUM 8 197 198 #define AVG_THERMAL_NUM 8 199 #define IQK_Matrix_REG_NUM 8 200 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 201 * + Channels_5G_20M_NUM 202 * + Channels_5G 203 */ 204 205 #define DM_Type_ByFW 0 206 #define DM_Type_ByDriver 1 207 208 /* */ 209 /* Declare for common info */ 210 /* */ 211 #define MAX_PATH_NUM_92CS 2 212 #define MAX_PATH_NUM_8188E 1 213 #define MAX_PATH_NUM_8192E 2 214 #define MAX_PATH_NUM_8723B 1 215 #define MAX_PATH_NUM_8812A 2 216 #define MAX_PATH_NUM_8821A 1 217 #define MAX_PATH_NUM_8814A 4 218 #define MAX_PATH_NUM_8822B 2 219 220 #define IQK_THRESHOLD 8 221 #define DPK_THRESHOLD 4 222 223 struct odm_phy_info { 224 /* 225 * Be care, if you want to add any element, please insert it between 226 * rx_pwd_ball and signal_strength. 227 */ 228 u8 rx_pwd_ba11; 229 230 u8 signal_quality; /* in 0-100 index. */ 231 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 232 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 233 234 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 235 236 u16 cfo_short[4]; /* per-path's Cfo_short */ 237 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 238 239 s8 rx_power; /* in dBm Translate from PWdB */ 240 241 /* 242 * Real power in dBm for this packet, no beautification and 243 * aggregation. Keep this raw info to be used for the other procedures. 244 */ 245 s8 recv_signal_power; 246 u8 bt_rx_rssi_percentage; 247 u8 signal_strength; /* in 0-100 index. */ 248 249 s8 rx_pwr[4]; /* per-path's pwdb */ 250 251 u8 rx_snr[4]; /* per-path's SNR */ 252 u8 band_width; 253 u8 bt_coex_pwr_adjust; 254 }; 255 256 struct odm_packet_info { 257 u8 data_rate; 258 u8 station_id; 259 bool bssid_match; 260 bool to_self; 261 bool is_beacon; 262 }; 263 264 struct odm_phy_dbg_info { 265 /* ODM Write, debug info */ 266 s8 RxSNRdB[4]; 267 u32 NumQryPhyStatus; 268 u32 NumQryPhyStatusCCK; 269 u32 NumQryPhyStatusOFDM; 270 u8 NumQryBeaconPkt; 271 /* Others */ 272 s32 RxEVM[4]; 273 274 }; 275 276 struct odm_mac_status_info { 277 u8 test; 278 }; 279 280 enum ODM_Ability_E { /* tag_Dynamic_ODM_Support_Ability_Type */ 281 /* BB Team */ 282 ODM_DIG = 0x00000001, 283 ODM_HIGH_POWER = 0x00000002, 284 ODM_CCK_CCA_TH = 0x00000004, 285 ODM_FA_STATISTICS = 0x00000008, 286 ODM_RAMASK = 0x00000010, 287 ODM_RSSI_MONITOR = 0x00000020, 288 ODM_SW_ANTDIV = 0x00000040, 289 ODM_HW_ANTDIV = 0x00000080, 290 ODM_BB_PWRSV = 0x00000100, 291 ODM_2TPATHDIV = 0x00000200, 292 ODM_1TPATHDIV = 0x00000400, 293 ODM_PSD2AFH = 0x00000800 294 }; 295 296 /* */ 297 /* 2011/10/20 MH Define Common info enum for all team. */ 298 /* */ 299 enum odm_cmninfo_e { 300 /* Fixed value: */ 301 302 /* HOOK BEFORE REG INIT----------- */ 303 ODM_CMNINFO_PLATFORM = 0, 304 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 305 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 306 ODM_CMNINFO_MP_TEST_CHIP, 307 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 308 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 309 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 310 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 311 ODM_CMNINFO_RFE_TYPE, 312 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 313 ODM_CMNINFO_PACKAGE_TYPE, 314 ODM_CMNINFO_EXT_LNA, /* true */ 315 ODM_CMNINFO_5G_EXT_LNA, 316 ODM_CMNINFO_EXT_PA, 317 ODM_CMNINFO_5G_EXT_PA, 318 ODM_CMNINFO_GPA, 319 ODM_CMNINFO_APA, 320 ODM_CMNINFO_GLNA, 321 ODM_CMNINFO_ALNA, 322 ODM_CMNINFO_EXT_TRSW, 323 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 324 ODM_CMNINFO_BINHCT_TEST, 325 ODM_CMNINFO_BWIFI_TEST, 326 ODM_CMNINFO_SMART_CONCURRENT, 327 /* HOOK BEFORE REG INIT----------- */ 328 329 /* Dynamic value: */ 330 /* POINTER REFERENCE----------- */ 331 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 332 ODM_CMNINFO_TX_UNI, 333 ODM_CMNINFO_RX_UNI, 334 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 335 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 336 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 337 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 338 ODM_CMNINFO_BW, /* ODM_BW_E */ 339 ODM_CMNINFO_CHNL, 340 ODM_CMNINFO_FORCED_RATE, 341 342 ODM_CMNINFO_DMSP_GET_VALUE, 343 ODM_CMNINFO_BUDDY_ADAPTOR, 344 ODM_CMNINFO_DMSP_IS_MASTER, 345 ODM_CMNINFO_SCAN, 346 ODM_CMNINFO_POWER_SAVING, 347 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 348 ODM_CMNINFO_DRV_STOP, 349 ODM_CMNINFO_PNP_IN, 350 ODM_CMNINFO_INIT_ON, 351 ODM_CMNINFO_ANT_TEST, 352 ODM_CMNINFO_NET_CLOSED, 353 ODM_CMNINFO_MP_MODE, 354 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 355 ODM_CMNINFO_FORCED_IGI_LB, 356 ODM_CMNINFO_IS1ANTENNA, 357 ODM_CMNINFO_RFDEFAULTPATH, 358 /* POINTER REFERENCE----------- */ 359 360 /* CALL BY VALUE------------- */ 361 ODM_CMNINFO_WIFI_DIRECT, 362 ODM_CMNINFO_WIFI_DISPLAY, 363 ODM_CMNINFO_LINK_IN_PROGRESS, 364 ODM_CMNINFO_LINK, 365 ODM_CMNINFO_STATION_STATE, 366 ODM_CMNINFO_RSSI_MIN, 367 ODM_CMNINFO_DBG_COMP, /* u64 */ 368 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 369 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 370 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 371 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 372 ODM_CMNINFO_BT_ENABLED, 373 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 374 ODM_CMNINFO_BT_HS_RSSI, 375 ODM_CMNINFO_BT_OPERATION, 376 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 377 ODM_CMNINFO_BT_DISABLE_EDCA, 378 /* CALL BY VALUE------------- */ 379 380 /* Dynamic ptr array hook itms. */ 381 ODM_CMNINFO_STA_STATUS, 382 ODM_CMNINFO_PHY_STATUS, 383 ODM_CMNINFO_MAC_STATUS, 384 385 ODM_CMNINFO_MAX, 386 }; 387 388 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 389 enum odm_ability_e { /* _ODM_Support_Ability_Definition */ 390 /* */ 391 /* BB ODM section BIT 0-15 */ 392 /* */ 393 ODM_BB_DIG = BIT0, 394 ODM_BB_RA_MASK = BIT1, 395 ODM_BB_DYNAMIC_TXPWR = BIT2, 396 ODM_BB_FA_CNT = BIT3, 397 ODM_BB_RSSI_MONITOR = BIT4, 398 ODM_BB_CCK_PD = BIT5, 399 ODM_BB_ANT_DIV = BIT6, 400 ODM_BB_PWR_SAVE = BIT7, 401 ODM_BB_PWR_TRAIN = BIT8, 402 ODM_BB_RATE_ADAPTIVE = BIT9, 403 ODM_BB_PATH_DIV = BIT10, 404 ODM_BB_PSD = BIT11, 405 ODM_BB_RXHP = BIT12, 406 ODM_BB_ADAPTIVITY = BIT13, 407 ODM_BB_CFO_TRACKING = BIT14, 408 409 /* MAC DM section BIT 16-23 */ 410 ODM_MAC_EDCA_TURBO = BIT16, 411 ODM_MAC_EARLY_MODE = BIT17, 412 413 /* RF ODM section BIT 24-31 */ 414 ODM_RF_TX_PWR_TRACK = BIT24, 415 ODM_RF_RX_GAIN_TRACK = BIT25, 416 ODM_RF_CALIBRATION = BIT26, 417 }; 418 419 /* ODM_CMNINFO_INTERFACE */ 420 enum odm_interface_e { /* tag_ODM_Support_Interface_Definition */ 421 ODM_ITRF_SDIO = 0x4, 422 ODM_ITRF_ALL = 0x7, 423 }; 424 425 /* ODM_CMNINFO_IC_TYPE */ 426 enum odm_ic_type_e { /* tag_ODM_Support_IC_Type_Definition */ 427 ODM_RTL8723B = BIT8, 428 }; 429 430 /* ODM_CMNINFO_CUT_VER */ 431 enum odm_cut_version_e { /* tag_ODM_Cut_Version_Definition */ 432 ODM_CUT_A = 0, 433 ODM_CUT_B = 1, 434 ODM_CUT_C = 2, 435 ODM_CUT_D = 3, 436 ODM_CUT_E = 4, 437 ODM_CUT_F = 5, 438 439 ODM_CUT_I = 8, 440 ODM_CUT_J = 9, 441 ODM_CUT_K = 10, 442 ODM_CUT_TEST = 15, 443 }; 444 445 /* ODM_CMNINFO_FAB_VER */ 446 enum odm_fab_e { /* tag_ODM_Fab_Version_Definition */ 447 ODM_TSMC = 0, 448 ODM_UMC = 1, 449 }; 450 451 /* ODM_CMNINFO_RF_TYPE */ 452 /* */ 453 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 454 /* */ 455 enum odm_rf_path_e { /* tag_ODM_RF_Path_Bit_Definition */ 456 ODM_RF_TX_A = BIT0, 457 ODM_RF_TX_B = BIT1, 458 ODM_RF_TX_C = BIT2, 459 ODM_RF_TX_D = BIT3, 460 ODM_RF_RX_A = BIT4, 461 ODM_RF_RX_B = BIT5, 462 ODM_RF_RX_C = BIT6, 463 ODM_RF_RX_D = BIT7, 464 }; 465 466 enum odm_rf_type_e { /* tag_ODM_RF_Type_Definition */ 467 ODM_1T1R = 0, 468 ODM_1T2R = 1, 469 ODM_2T2R = 2, 470 ODM_2T3R = 3, 471 ODM_2T4R = 4, 472 ODM_3T3R = 5, 473 ODM_3T4R = 6, 474 ODM_4T4R = 7, 475 }; 476 477 /* */ 478 /* ODM Dynamic common info value definition */ 479 /* */ 480 481 /* typedef enum _MACPHY_MODE_8192D{ */ 482 /* SINGLEMAC_SINGLEPHY, */ 483 /* DUALMAC_DUALPHY, */ 484 /* DUALMAC_SINGLEPHY, */ 485 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */ 486 /* Above is the original define in MP driver. Please use the same define. THX. */ 487 enum odm_mac_phy_mode_e { /* tag_ODM_MAC_PHY_Mode_Definition */ 488 ODM_SMSP = 0, 489 ODM_DMSP = 1, 490 ODM_DMDP = 2, 491 }; 492 493 enum odm_bt_coexist_e { /* tag_BT_Coexist_Definition */ 494 ODM_BT_BUSY = 1, 495 ODM_BT_ON = 2, 496 ODM_BT_OFF = 3, 497 ODM_BT_NONE = 4, 498 }; 499 500 /* ODM_CMNINFO_OP_MODE */ 501 enum odm_operation_mode_e { /* tag_Operation_Mode_Definition */ 502 ODM_NO_LINK = BIT0, 503 ODM_LINK = BIT1, 504 ODM_SCAN = BIT2, 505 ODM_POWERSAVE = BIT3, 506 ODM_AP_MODE = BIT4, 507 ODM_CLIENT_MODE = BIT5, 508 ODM_AD_HOC = BIT6, 509 ODM_WIFI_DIRECT = BIT7, 510 ODM_WIFI_DISPLAY = BIT8, 511 }; 512 513 /* ODM_CMNINFO_WM_MODE */ 514 enum odm_wireless_mode_e { /* tag_Wireless_Mode_Definition */ 515 ODM_WM_UNKNOWN = 0x0, 516 ODM_WM_B = BIT0, 517 ODM_WM_G = BIT1, 518 ODM_WM_A = BIT2, 519 ODM_WM_N24G = BIT3, 520 ODM_WM_N5G = BIT4, 521 ODM_WM_AUTO = BIT5, 522 ODM_WM_AC = BIT6, 523 }; 524 525 /* ODM_CMNINFO_BAND */ 526 enum odm_band_type_e { /* tag_Band_Type_Definition */ 527 ODM_BAND_2_4G = 0, 528 ODM_BAND_5G, 529 ODM_BAND_ON_BOTH, 530 ODM_BANDMAX 531 }; 532 533 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 534 enum odm_sec_chnl_offset_e { /* tag_Secondary_Channel_Offset_Definition */ 535 ODM_DONT_CARE = 0, 536 ODM_BELOW = 1, 537 ODM_ABOVE = 2 538 }; 539 540 /* ODM_CMNINFO_SEC_MODE */ 541 enum odm_security_e { /* tag_Security_Definition */ 542 ODM_SEC_OPEN = 0, 543 ODM_SEC_WEP40 = 1, 544 ODM_SEC_TKIP = 2, 545 ODM_SEC_RESERVE = 3, 546 ODM_SEC_AESCCMP = 4, 547 ODM_SEC_WEP104 = 5, 548 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 549 ODM_SEC_SMS4 = 7, 550 }; 551 552 /* ODM_CMNINFO_BW */ 553 enum odm_bw_e { /* tag_Bandwidth_Definition */ 554 ODM_BW20M = 0, 555 ODM_BW40M = 1, 556 ODM_BW80M = 2, 557 ODM_BW160M = 3, 558 ODM_BW10M = 4, 559 }; 560 561 /* ODM_CMNINFO_BOARD_TYPE */ 562 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 563 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 564 enum odm_board_type_e { /* tag_Board_Definition */ 565 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 566 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ 567 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ 568 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ 569 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 570 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 571 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ 572 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 573 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 574 }; 575 576 enum ODM_Package_TYPE_E { /* tag_ODM_Package_Definition */ 577 ODM_PACKAGE_DEFAULT = 0, 578 ODM_PACKAGE_QFN68 = BIT(0), 579 ODM_PACKAGE_TFBGA90 = BIT(1), 580 ODM_PACKAGE_TFBGA79 = BIT(2), 581 }; 582 583 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 584 TYPE_GPA0 = 0, 585 TYPE_GPA1 = BIT(1)|BIT(0) 586 }; 587 588 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 589 TYPE_APA0 = 0, 590 TYPE_APA1 = BIT(1)|BIT(0) 591 }; 592 593 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 594 TYPE_GLNA0 = 0, 595 TYPE_GLNA1 = BIT(2)|BIT(0), 596 TYPE_GLNA2 = BIT(3)|BIT(1), 597 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 598 }; 599 600 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 601 TYPE_ALNA0 = 0, 602 TYPE_ALNA1 = BIT(2)|BIT(0), 603 TYPE_ALNA2 = BIT(3)|BIT(1), 604 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 605 }; 606 607 /* ODM_CMNINFO_ONE_PATH_CCA */ 608 enum odm_cca_path_e { /* tag_CCA_Path */ 609 ODM_CCA_2R = 0, 610 ODM_CCA_1R_A = 1, 611 ODM_CCA_1R_B = 2, 612 }; 613 614 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 615 bool bIQKDone; 616 s32 Value[3][IQK_Matrix_REG_NUM]; 617 bool bBWIqkResultSaved[3]; 618 }; 619 620 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 621 622 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 623 /* for tx power tracking */ 624 625 u32 RegA24; /* for TempCCK */ 626 s32 RegE94; 627 s32 RegE9C; 628 s32 RegEB4; 629 s32 RegEBC; 630 631 u8 TXPowercount; 632 bool bTXPowerTrackingInit; 633 bool bTXPowerTracking; 634 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 635 u8 TM_Trigger; 636 u8 InternalPA5G[2]; /* pathA / pathB */ 637 638 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 639 u8 ThermalValue; 640 u8 ThermalValue_LCK; 641 u8 ThermalValue_IQK; 642 u8 ThermalValue_DPK; 643 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 644 u8 ThermalValue_AVG_index; 645 u8 ThermalValue_RxGain; 646 u8 ThermalValue_Crystal; 647 u8 ThermalValue_DPKstore; 648 u8 ThermalValue_DPKtrack; 649 bool TxPowerTrackingInProgress; 650 651 bool bReloadtxpowerindex; 652 u8 bRfPiEnable; 653 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 654 655 /* Tx power Tracking ------------------------- */ 656 u8 bCCKinCH14; 657 u8 CCK_index; 658 u8 OFDM_index[MAX_RF_PATH]; 659 s8 PowerIndexOffset[MAX_RF_PATH]; 660 s8 DeltaPowerIndex[MAX_RF_PATH]; 661 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 662 bool bTxPowerChanged; 663 664 u8 ThermalValue_HP[HP_THERMAL_NUM]; 665 u8 ThermalValue_HP_index; 666 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 667 bool bNeedIQK; 668 bool bIQKInProgress; 669 u8 Delta_IQK; 670 u8 Delta_LCK; 671 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 672 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 673 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 674 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 675 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 676 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 677 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 678 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 679 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 680 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 681 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 682 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 683 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 684 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 685 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 686 687 /* */ 688 689 /* for IQK */ 690 u32 RegC04; 691 u32 Reg874; 692 u32 RegC08; 693 u32 RegB68; 694 u32 RegB6C; 695 u32 Reg870; 696 u32 Reg860; 697 u32 Reg864; 698 699 bool bIQKInitialized; 700 bool bLCKInProgress; 701 bool bAntennaDetected; 702 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 703 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 704 u32 IQK_BB_backup_recover[9]; 705 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 706 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 707 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 708 709 /* for APK */ 710 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 711 u8 bAPKdone; 712 u8 bAPKThermalMeterIgnore; 713 714 /* DPK */ 715 bool bDPKFail; 716 u8 bDPdone; 717 u8 bDPPathAOK; 718 u8 bDPPathBOK; 719 720 u32 TxLOK[2]; 721 722 }; 723 /* */ 724 /* ODM Dynamic common info value definition */ 725 /* */ 726 727 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 728 u8 Bssid[6]; 729 u8 antsel_rx_keep_0; 730 u8 antsel_rx_keep_1; 731 u8 antsel_rx_keep_2; 732 u8 antsel_rx_keep_3; 733 u32 antSumRSSI[7]; 734 u32 antRSSIcnt[7]; 735 u32 antAveRSSI[7]; 736 u8 FAT_State; 737 u32 TrainIdx; 738 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 739 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 740 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 741 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 742 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 743 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 744 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 745 u8 RxIdleAnt; 746 bool bBecomeLinked; 747 u32 MinMaxRSSI; 748 u8 idx_AntDiv_counter_2G; 749 u8 idx_AntDiv_counter_5G; 750 u32 AntDiv_2G_5G; 751 u32 CCK_counter_main; 752 u32 CCK_counter_aux; 753 u32 OFDM_counter_main; 754 u32 OFDM_counter_aux; 755 756 u32 CCK_CtrlFrame_Cnt_main; 757 u32 CCK_CtrlFrame_Cnt_aux; 758 u32 OFDM_CtrlFrame_Cnt_main; 759 u32 OFDM_CtrlFrame_Cnt_aux; 760 u32 MainAnt_CtrlFrame_Sum; 761 u32 AuxAnt_CtrlFrame_Sum; 762 u32 MainAnt_CtrlFrame_Cnt; 763 u32 AuxAnt_CtrlFrame_Cnt; 764 765 }; 766 767 enum fat_state_e { 768 FAT_NORMAL_STATE = 0, 769 FAT_TRAINING_STATE = 1, 770 }; 771 772 enum ant_div_type_e { 773 NO_ANTDIV = 0xFF, 774 CG_TRX_HW_ANTDIV = 0x01, 775 CGCS_RX_HW_ANTDIV = 0x02, 776 FIXED_HW_ANTDIV = 0x03, 777 CG_TRX_SMART_ANTDIV = 0x04, 778 CGCS_RX_SW_ANTDIV = 0x05, 779 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 780 }; 781 782 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 783 u8 RespTxPath; 784 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 785 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 786 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 787 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 788 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 789 }; 790 791 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 792 PHY_REG_PG_RELATIVE_VALUE = 0, 793 PHY_REG_PG_EXACT_VALUE = 1 794 }; 795 796 /* */ 797 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 798 /* */ 799 struct ant_detected_info { 800 bool bAntDetected; 801 u32 dBForAntA; 802 u32 dBForAntB; 803 u32 dBForAntO; 804 }; 805 806 /* */ 807 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 808 /* */ 809 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 810 /* struct timer_list FastAntTrainingTimer; */ 811 /* */ 812 /* Add for different team use temporarily */ 813 /* */ 814 struct adapter *Adapter; /* For CE/NIC team */ 815 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 816 bool odm_ready; 817 818 enum phy_reg_pg_type PhyRegPgValueType; 819 u8 PhyRegPgVersion; 820 821 u64 DebugComponents; 822 u32 DebugLevel; 823 824 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 825 u32 LastNumQryPhyStatusAll; 826 u32 RxPWDBAve; 827 bool MPDIG_2G; /* off MPDIG */ 828 u8 Times_2G; 829 830 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 831 bool bCckHighPower; 832 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 833 u8 ControlChannel; 834 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 835 836 /* REMOVED COMMON INFO---------- */ 837 /* u8 PseudoMacPhyMode; */ 838 /* bool *BTCoexist; */ 839 /* bool PseudoBtCoexist; */ 840 /* u8 OPMode; */ 841 /* bool bAPMode; */ 842 /* bool bClientMode; */ 843 /* bool bAdHocMode; */ 844 /* bool bSlaveOfDMSP; */ 845 /* REMOVED COMMON INFO---------- */ 846 847 /* 1 COMMON INFORMATION */ 848 849 /* */ 850 /* Init Value */ 851 /* */ 852 /* HOOK BEFORE REG INIT----------- */ 853 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 854 u8 SupportPlatform; 855 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 856 u32 SupportAbility; 857 /* ODM PCIE/USB/SDIO = 1/2/3 */ 858 u8 SupportInterface; 859 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 860 u32 SupportICType; 861 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 862 u8 CutVersion; 863 /* Fab Version TSMC/UMC = 0/1 */ 864 u8 FabVersion; 865 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 866 u8 RFType; 867 u8 RFEType; 868 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 869 u8 BoardType; 870 u8 PackageType; 871 u8 TypeGLNA; 872 u8 TypeGPA; 873 u8 TypeALNA; 874 u8 TypeAPA; 875 /* with external LNA NO/Yes = 0/1 */ 876 u8 ExtLNA; 877 u8 ExtLNA5G; 878 /* with external PA NO/Yes = 0/1 */ 879 u8 ExtPA; 880 u8 ExtPA5G; 881 /* with external TRSW NO/Yes = 0/1 */ 882 u8 ExtTRSW; 883 u8 PatchID; /* Customer ID */ 884 bool bInHctTest; 885 bool bWIFITest; 886 887 bool bDualMacSmartConcurrent; 888 u32 BK_SupportAbility; 889 u8 AntDivType; 890 /* HOOK BEFORE REG INIT----------- */ 891 892 /* */ 893 /* Dynamic Value */ 894 /* */ 895 /* POINTER REFERENCE----------- */ 896 897 u8 u8_temp; 898 bool bool_temp; 899 struct adapter *adapter_temp; 900 901 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 902 u8 *pMacPhyMode; 903 /* TX Unicast byte count */ 904 u64 *pNumTxBytesUnicast; 905 /* RX Unicast byte count */ 906 u64 *pNumRxBytesUnicast; 907 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 908 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 909 /* Frequence band 2.4G/5G = 0/1 */ 910 u8 *pBandType; 911 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 912 u8 *pSecChOffset; 913 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 914 u8 *pSecurity; 915 /* BW info 20M/40M/80M = 0/1/2 */ 916 u8 *pBandWidth; 917 /* Central channel location Ch1/Ch2/.... */ 918 u8 *pChannel; /* central channel number */ 919 bool DPK_Done; 920 /* Common info for 92D DMSP */ 921 922 bool *pbGetValueFromOtherMac; 923 struct adapter **pBuddyAdapter; 924 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 925 /* Common info for Status */ 926 bool *pbScanInProcess; 927 bool *pbPowerSaving; 928 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 929 u8 *pOnePathCCA; 930 /* pMgntInfo->AntennaTest */ 931 u8 *pAntennaTest; 932 bool *pbNet_closed; 933 u8 *mp_mode; 934 /* u8 *pAidMap; */ 935 u8 *pu1ForcedIgiLb; 936 /* For 8723B IQK----------- */ 937 bool *pIs1Antenna; 938 u8 *pRFDefaultPath; 939 /* 0:S1, 1:S0 */ 940 941 /* POINTER REFERENCE----------- */ 942 u16 *pForcedDataRate; 943 /* CALL BY VALUE------------- */ 944 bool bLinkInProcess; 945 bool bWIFI_Direct; 946 bool bWIFI_Display; 947 bool bLinked; 948 949 bool bsta_state; 950 u8 RSSI_Min; 951 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 952 bool bIsMPChip; 953 bool bOneEntryOnly; 954 /* Common info for BTDM */ 955 bool bBtEnabled; /* BT is disabled */ 956 bool bBtConnectProcess; /* BT HS is under connection progress. */ 957 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 958 bool bBtHsOperation; /* BT HS mode is under progress */ 959 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 960 bool bBtLimitedDig; /* BT is busy. */ 961 /* CALL BY VALUE------------- */ 962 u8 RSSI_A; 963 u8 RSSI_B; 964 u64 RSSI_TRSW; 965 u64 RSSI_TRSW_H; 966 u64 RSSI_TRSW_L; 967 u64 RSSI_TRSW_iso; 968 969 u8 RxRate; 970 bool bNoisyState; 971 u8 TxRate; 972 u8 LinkedInterval; 973 u8 preChannel; 974 u32 TxagcOffsetValueA; 975 bool IsTxagcOffsetPositiveA; 976 u32 TxagcOffsetValueB; 977 bool IsTxagcOffsetPositiveB; 978 u64 lastTxOkCnt; 979 u64 lastRxOkCnt; 980 u32 BbSwingOffsetA; 981 bool IsBbSwingOffsetPositiveA; 982 u32 BbSwingOffsetB; 983 bool IsBbSwingOffsetPositiveB; 984 s8 TH_L2H_ini; 985 s8 TH_EDCCA_HL_diff; 986 s8 IGI_Base; 987 u8 IGI_target; 988 bool ForceEDCCA; 989 u8 AdapEn_RSSI; 990 s8 Force_TH_H; 991 s8 Force_TH_L; 992 u8 IGI_LowerBound; 993 u8 antdiv_rssi; 994 u8 AntType; 995 u8 pre_AntType; 996 u8 antdiv_period; 997 u8 antdiv_select; 998 u8 NdpaPeriod; 999 bool H2C_RARpt_connect; 1000 1001 /* add by Yu Cehn for adaptivtiy */ 1002 bool adaptivity_flag; 1003 bool NHM_disable; 1004 bool TxHangFlg; 1005 bool Carrier_Sense_enable; 1006 u8 tolerance_cnt; 1007 u64 NHMCurTxOkcnt; 1008 u64 NHMCurRxOkcnt; 1009 u64 NHMLastTxOkcnt; 1010 u64 NHMLastRxOkcnt; 1011 u8 txEdcca1; 1012 u8 txEdcca0; 1013 s8 H2L_lb; 1014 s8 L2H_lb; 1015 u8 Adaptivity_IGI_upper; 1016 u8 NHM_cnt_0; 1017 1018 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 1019 /* */ 1020 /* 2 Define STA info. */ 1021 /* _ODM_STA_INFO */ 1022 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 1023 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 1024 1025 /* */ 1026 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 1027 /* We need to colelct all support abilit to a proper area. */ 1028 /* */ 1029 bool RaSupport88E; 1030 1031 /* Define ........... */ 1032 1033 /* Latest packet phy info (ODM write) */ 1034 struct odm_phy_dbg_info PhyDbgInfo; 1035 /* PHY_INFO_88E PhyInfo; */ 1036 1037 /* Latest packet phy info (ODM write) */ 1038 struct odm_mac_status_info *pMacInfo; 1039 /* MAC_INFO_88E MacInfo; */ 1040 1041 /* Different Team independt structure?? */ 1042 1043 /* */ 1044 /* TX_RTP_CMN TX_retrpo; */ 1045 /* TX_RTP_88E TX_retrpo; */ 1046 /* TX_RTP_8195 TX_retrpo; */ 1047 1048 /* */ 1049 /* ODM Structure */ 1050 /* */ 1051 struct fat_t DM_FatTable; 1052 struct dig_t DM_DigTable; 1053 struct ps_t DM_PSTable; 1054 struct dynamic_primary_CCA DM_PriCCA; 1055 struct rxhp_t dM_RXHP_Table; 1056 struct ra_t DM_RA_Table; 1057 struct false_ALARM_STATISTICS FalseAlmCnt; 1058 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 1059 struct swat_t DM_SWAT_Table; 1060 bool RSSI_test; 1061 struct cfo_tracking DM_CfoTrack; 1062 1063 struct edca_t DM_EDCA_Table; 1064 u32 WMMEDCA_BE; 1065 struct pathdiv_t DM_PathDiv; 1066 /* Copy from SD4 structure */ 1067 /* */ 1068 /* ================================================== */ 1069 /* */ 1070 1071 /* common */ 1072 /* u8 DM_Type; */ 1073 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 1074 /* u8 PSD_func_flag; Add By Gary */ 1075 /* for DIG */ 1076 /* u8 bDMInitialGainEnable; */ 1077 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 1078 /* for Antenna diversity */ 1079 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 1080 /* PSTA_INFO_T RSSI_target; */ 1081 1082 bool *pbDriverStopped; 1083 bool *pbDriverIsGoingToPnpSetPowerSleep; 1084 bool *pinit_adpt_in_progress; 1085 1086 /* PSD */ 1087 bool bUserAssignLevel; 1088 struct timer_list PSDTimer; 1089 u8 RSSI_BT; /* come from BT */ 1090 bool bPSDinProcess; 1091 bool bPSDactive; 1092 bool bDMInitialGainEnable; 1093 1094 /* MPT DIG */ 1095 struct timer_list MPT_DIGTimer; 1096 1097 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 1098 u8 bUseRAMask; 1099 1100 struct odm_rate_adaptive RateAdaptive; 1101 1102 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 1103 1104 struct odm_rf_cal_t RFCalibrateInfo; 1105 1106 /* */ 1107 /* TX power tracking */ 1108 /* */ 1109 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 1110 u8 BbSwingIdxOfdmCurrent; 1111 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 1112 bool BbSwingFlagOfdm; 1113 u8 BbSwingIdxCck; 1114 u8 BbSwingIdxCckCurrent; 1115 u8 BbSwingIdxCckBase; 1116 u8 DefaultOfdmIndex; 1117 u8 DefaultCckIndex; 1118 bool BbSwingFlagCck; 1119 1120 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 1121 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 1122 s8 Remnant_CCKSwingIdx; 1123 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 1124 bool Modify_TxAGC_Flag_PathA; 1125 bool Modify_TxAGC_Flag_PathB; 1126 bool Modify_TxAGC_Flag_PathC; 1127 bool Modify_TxAGC_Flag_PathD; 1128 bool Modify_TxAGC_Flag_PathA_CCK; 1129 1130 s8 KfreeOffset[MAX_RF_PATH]; 1131 /* */ 1132 /* ODM system resource. */ 1133 /* */ 1134 1135 /* ODM relative time. */ 1136 struct timer_list PathDivSwitchTimer; 1137 /* 2011.09.27 add for Path Diversity */ 1138 struct timer_list CCKPathDiversityTimer; 1139 struct timer_list FastAntTrainingTimer; 1140 1141 /* ODM relative workitem. */ 1142 1143 #if (BEAMFORMING_SUPPORT == 1) 1144 RT_BEAMFORMING_INFO BeamformingInfo; 1145 #endif 1146 }; 1147 1148 #define ODM_RF_PATH_MAX 2 1149 1150 enum odm_rf_radio_path_e { 1151 ODM_RF_PATH_A = 0, /* Radio Path A */ 1152 ODM_RF_PATH_B = 1, /* Radio Path B */ 1153 ODM_RF_PATH_C = 2, /* Radio Path C */ 1154 ODM_RF_PATH_D = 3, /* Radio Path D */ 1155 ODM_RF_PATH_AB, 1156 ODM_RF_PATH_AC, 1157 ODM_RF_PATH_AD, 1158 ODM_RF_PATH_BC, 1159 ODM_RF_PATH_BD, 1160 ODM_RF_PATH_CD, 1161 ODM_RF_PATH_ABC, 1162 ODM_RF_PATH_ACD, 1163 ODM_RF_PATH_BCD, 1164 ODM_RF_PATH_ABCD, 1165 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1166 }; 1167 1168 enum odm_rf_content { 1169 odm_radioa_txt = 0x1000, 1170 odm_radiob_txt = 0x1001, 1171 odm_radioc_txt = 0x1002, 1172 odm_radiod_txt = 0x1003 1173 }; 1174 1175 enum ODM_BB_Config_Type { 1176 CONFIG_BB_PHY_REG, 1177 CONFIG_BB_AGC_TAB, 1178 CONFIG_BB_AGC_TAB_2G, 1179 CONFIG_BB_AGC_TAB_5G, 1180 CONFIG_BB_PHY_REG_PG, 1181 CONFIG_BB_PHY_REG_MP, 1182 CONFIG_BB_AGC_TAB_DIFF, 1183 }; 1184 1185 enum ODM_RF_Config_Type { 1186 CONFIG_RF_RADIO, 1187 CONFIG_RF_TXPWR_LMT, 1188 }; 1189 1190 enum ODM_FW_Config_Type { 1191 CONFIG_FW_NIC, 1192 CONFIG_FW_NIC_2, 1193 CONFIG_FW_AP, 1194 CONFIG_FW_WoWLAN, 1195 CONFIG_FW_WoWLAN_2, 1196 CONFIG_FW_AP_WoWLAN, 1197 CONFIG_FW_BT, 1198 }; 1199 1200 /* Status code */ 1201 enum rt_status { 1202 RT_STATUS_SUCCESS, 1203 RT_STATUS_FAILURE, 1204 RT_STATUS_PENDING, 1205 RT_STATUS_RESOURCE, 1206 RT_STATUS_INVALID_CONTEXT, 1207 RT_STATUS_INVALID_PARAMETER, 1208 RT_STATUS_NOT_SUPPORT, 1209 RT_STATUS_OS_API_FAILED, 1210 }; 1211 1212 #ifdef REMOVE_PACK 1213 #pragma pack() 1214 #endif 1215 1216 /* include "odm_function.h" */ 1217 1218 /* 3 =========================================================== */ 1219 /* 3 DIG */ 1220 /* 3 =========================================================== */ 1221 1222 /* Remove DIG by Yuchen */ 1223 1224 /* 3 =========================================================== */ 1225 /* 3 AGC RX High Power Mode */ 1226 /* 3 =========================================================== */ 1227 #define LNA_Low_Gain_1 0x64 1228 #define LNA_Low_Gain_2 0x5A 1229 #define LNA_Low_Gain_3 0x58 1230 1231 #define FA_RXHP_TH1 5000 1232 #define FA_RXHP_TH2 1500 1233 #define FA_RXHP_TH3 800 1234 #define FA_RXHP_TH4 600 1235 #define FA_RXHP_TH5 500 1236 1237 /* 3 =========================================================== */ 1238 /* 3 EDCA */ 1239 /* 3 =========================================================== */ 1240 1241 /* 3 =========================================================== */ 1242 /* 3 Dynamic Tx Power */ 1243 /* 3 =========================================================== */ 1244 /* Dynamic Tx Power Control Threshold */ 1245 1246 /* 3 =========================================================== */ 1247 /* 3 Rate Adaptive */ 1248 /* 3 =========================================================== */ 1249 #define DM_RATR_STA_INIT 0 1250 #define DM_RATR_STA_HIGH 1 1251 #define DM_RATR_STA_MIDDLE 2 1252 #define DM_RATR_STA_LOW 3 1253 1254 /* 3 =========================================================== */ 1255 /* 3 BB Power Save */ 1256 /* 3 =========================================================== */ 1257 1258 enum dm_1r_cca_e { /* tag_1R_CCA_Type_Definition */ 1259 CCA_1R = 0, 1260 CCA_2R = 1, 1261 CCA_MAX = 2, 1262 }; 1263 1264 enum dm_rf_e { /* tag_RF_Type_Definition */ 1265 RF_Save = 0, 1266 RF_Normal = 1, 1267 RF_MAX = 2, 1268 }; 1269 1270 /* 3 =========================================================== */ 1271 /* 3 Antenna Diversity */ 1272 /* 3 =========================================================== */ 1273 enum dm_swas_e { /* tag_SW_Antenna_Switch_Definition */ 1274 Antenna_A = 1, 1275 Antenna_B = 2, 1276 Antenna_MAX = 3, 1277 }; 1278 1279 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1280 #define MAX_ANTENNA_DETECTION_CNT 10 1281 1282 /* */ 1283 /* Extern Global Variables. */ 1284 /* */ 1285 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1286 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1287 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1288 1289 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1290 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1291 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1292 1293 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1294 1295 /* */ 1296 /* check Sta pointer valid or not */ 1297 /* */ 1298 #define IS_STA_VALID(pSta) (pSta) 1299 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1300 /* This indicates two different the steps. */ 1301 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1302 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1303 /* with original RSSI to determine if it is necessary to switch antenna. */ 1304 #define SWAW_STEP_PEAK 0 1305 #define SWAW_STEP_DETERMINE 1 1306 1307 /* Remove BB power saving by Yuchen */ 1308 1309 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1310 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1311 1312 bool ODM_RAStateCheck( 1313 struct dm_odm_t *pDM_Odm, 1314 s32 RSSI, 1315 bool bForceUpdate, 1316 u8 *pRATRState 1317 ); 1318 1319 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1320 void ODM_SwAntDivChkPerPktRssi( 1321 struct dm_odm_t *pDM_Odm, 1322 u8 StationID, 1323 struct odm_phy_info *pPhyInfo 1324 ); 1325 1326 u32 ODM_Get_Rate_Bitmap( 1327 struct dm_odm_t *pDM_Odm, 1328 u32 macid, 1329 u32 ra_mask, 1330 u8 rssi_level 1331 ); 1332 1333 #if (BEAMFORMING_SUPPORT == 1) 1334 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1335 #endif 1336 1337 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1338 1339 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1340 1341 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1342 1343 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1344 1345 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1346 1347 void ODM_CmnInfoPtrArrayHook( 1348 struct dm_odm_t *pDM_Odm, 1349 enum odm_cmninfo_e CmnInfo, 1350 u16 Index, 1351 void *pValue 1352 ); 1353 1354 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1355 1356 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1357 1358 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1359 1360 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1361 1362 void ODM_AntselStatistics_88C( 1363 struct dm_odm_t *pDM_Odm, 1364 u8 MacId, 1365 u32 PWDBAll, 1366 bool isCCKrate 1367 ); 1368 1369 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1370 1371 #endif 1372