1 /****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15 16 17 #ifndef __HALDMOUTSRC_H__ 18 #define __HALDMOUTSRC_H__ 19 20 21 #include "odm_EdcaTurboCheck.h" 22 #include "odm_DIG.h" 23 #include "odm_PathDiv.h" 24 #include "odm_DynamicBBPowerSaving.h" 25 #include "odm_DynamicTxPower.h" 26 #include "odm_CfoTracking.h" 27 #include "odm_NoiseMonitor.h" 28 29 #define TP_MODE 0 30 #define RSSI_MODE 1 31 #define TRAFFIC_LOW 0 32 #define TRAFFIC_HIGH 1 33 #define NONE 0 34 35 36 /* 3 Tx Power Tracking */ 37 /* 3 ============================================================ */ 38 #define DPK_DELTA_MAPPING_NUM 13 39 #define index_mapping_HP_NUM 15 40 #define OFDM_TABLE_SIZE 43 41 #define CCK_TABLE_SIZE 33 42 #define TXSCALE_TABLE_SIZE 37 43 #define TXPWR_TRACK_TABLE_SIZE 30 44 #define DELTA_SWINGIDX_SIZE 30 45 #define BAND_NUM 4 46 47 /* 3 PSD Handler */ 48 /* 3 ============================================================ */ 49 50 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 51 #define MODE_40M 0 /* 0:20M, 1:40M */ 52 #define PSD_TH2 3 53 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 54 #define SIR_STEP_SIZE 3 55 #define Smooth_Size_1 5 56 #define Smooth_TH_1 3 57 #define Smooth_Size_2 10 58 #define Smooth_TH_2 4 59 #define Smooth_Size_3 20 60 #define Smooth_TH_3 4 61 #define Smooth_Step_Size 5 62 #define Adaptive_SIR 1 63 #define PSD_RESCAN 4 64 #define PSD_SCAN_INTERVAL 700 /* ms */ 65 66 /* 8723A High Power IGI Setting */ 67 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 68 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 69 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 70 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 71 72 /* ANT Test */ 73 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 74 #define ANTTESTA 0x01 /* Ant A will be Testing */ 75 #define ANTTESTB 0x02 /* Ant B will be testing */ 76 77 #define PS_MODE_ACTIVE 0x01 78 79 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 80 #define MAIN_ANT 1 /* Ant A or Ant Main */ 81 #define AUX_ANT 2 /* AntB or Ant Aux */ 82 #define MAX_ANT 3 /* 3 for AP using */ 83 84 85 /* Antenna Diversity Type */ 86 #define SW_ANTDIV 0 87 #define HW_ANTDIV 1 88 /* structure and define */ 89 90 /* Remove DIG by Yuchen */ 91 92 /* Remoce BB power saving by Yuchn */ 93 94 /* Remove DIG by yuchen */ 95 96 typedef struct _Dynamic_Primary_CCA { 97 u8 PriCCA_flag; 98 u8 intf_flag; 99 u8 intf_type; 100 u8 DupRTS_flag; 101 u8 Monitor_flag; 102 u8 CH_offset; 103 u8 MF_state; 104 } Pri_CCA_T, *pPri_CCA_T; 105 106 typedef struct _Rate_Adaptive_Table_ { 107 u8 firstconnect; 108 } RA_T, *pRA_T; 109 110 typedef struct _RX_High_Power_ { 111 u8 RXHP_flag; 112 u8 PSD_func_trigger; 113 u8 PSD_bitmap_RXHP[80]; 114 u8 Pre_IGI; 115 u8 Cur_IGI; 116 u8 Pre_pw_th; 117 u8 Cur_pw_th; 118 bool First_time_enter; 119 bool RXHP_enable; 120 u8 TP_Mode; 121 RT_TIMER PSDTimer; 122 } RXHP_T, *pRXHP_T; 123 124 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 125 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 126 127 /* This indicates two different the steps. */ 128 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 129 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 130 /* with original RSSI to determine if it is necessary to switch antenna. */ 131 #define SWAW_STEP_PEAK 0 132 #define SWAW_STEP_DETERMINE 1 133 134 #define TP_MODE 0 135 #define RSSI_MODE 1 136 #define TRAFFIC_LOW 0 137 #define TRAFFIC_HIGH 1 138 #define TRAFFIC_UltraLOW 2 139 140 typedef struct _SW_Antenna_Switch_ { 141 u8 Double_chk_flag; 142 u8 try_flag; 143 s32 PreRSSI; 144 u8 CurAntenna; 145 u8 PreAntenna; 146 u8 RSSI_Trying; 147 u8 TestMode; 148 u8 bTriggerAntennaSwitch; 149 u8 SelectAntennaMap; 150 u8 RSSI_target; 151 u8 reset_idx; 152 u16 Single_Ant_Counter; 153 u16 Dual_Ant_Counter; 154 u16 Aux_FailDetec_Counter; 155 u16 Retry_Counter; 156 157 /* Before link Antenna Switch check */ 158 u8 SWAS_NoLink_State; 159 u32 SWAS_NoLink_BK_Reg860; 160 u32 SWAS_NoLink_BK_Reg92c; 161 u32 SWAS_NoLink_BK_Reg948; 162 bool ANTA_ON; /* To indicate Ant A is or not */ 163 bool ANTB_ON; /* To indicate Ant B is on or not */ 164 bool Pre_Aux_FailDetec; 165 bool RSSI_AntDect_bResult; 166 u8 Ant5G; 167 u8 Ant2G; 168 169 s32 RSSI_sum_A; 170 s32 RSSI_sum_B; 171 s32 RSSI_cnt_A; 172 s32 RSSI_cnt_B; 173 174 u64 lastTxOkCnt; 175 u64 lastRxOkCnt; 176 u64 TXByteCnt_A; 177 u64 TXByteCnt_B; 178 u64 RXByteCnt_A; 179 u64 RXByteCnt_B; 180 u8 TrafficLoad; 181 u8 Train_time; 182 u8 Train_time_flag; 183 RT_TIMER SwAntennaSwitchTimer; 184 RT_TIMER SwAntennaSwitchTimer_8723B; 185 u32 PktCnt_SWAntDivByCtrlFrame; 186 bool bSWAntDivByCtrlFrame; 187 } SWAT_T, *pSWAT_T; 188 189 /* Remove Edca by YuChen */ 190 191 192 typedef struct _ODM_RATE_ADAPTIVE { 193 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 194 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 195 bool bUseLdpc; 196 bool bLowerRtsRate; 197 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 198 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 199 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 200 201 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE; 202 203 204 #define IQK_MAC_REG_NUM 4 205 #define IQK_ADDA_REG_NUM 16 206 #define IQK_BB_REG_NUM_MAX 10 207 #define IQK_BB_REG_NUM 9 208 #define HP_THERMAL_NUM 8 209 210 #define AVG_THERMAL_NUM 8 211 #define IQK_Matrix_REG_NUM 8 212 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 213 * + Channels_5G_20M_NUM 214 * + Channels_5G 215 */ 216 217 #define DM_Type_ByFW 0 218 #define DM_Type_ByDriver 1 219 220 /* */ 221 /* Declare for common info */ 222 /* */ 223 #define MAX_PATH_NUM_92CS 2 224 #define MAX_PATH_NUM_8188E 1 225 #define MAX_PATH_NUM_8192E 2 226 #define MAX_PATH_NUM_8723B 1 227 #define MAX_PATH_NUM_8812A 2 228 #define MAX_PATH_NUM_8821A 1 229 #define MAX_PATH_NUM_8814A 4 230 #define MAX_PATH_NUM_8822B 2 231 232 233 #define IQK_THRESHOLD 8 234 #define DPK_THRESHOLD 4 235 236 typedef struct _ODM_Phy_Status_Info_ { 237 /* */ 238 /* Be care, if you want to add any element please insert between */ 239 /* RxPWDBAll & SignalStrength. */ 240 /* */ 241 u8 RxPWDBAll; 242 243 u8 SignalQuality; /* in 0-100 index. */ 244 s8 RxMIMOSignalQuality[4]; /* per-path's EVM */ 245 u8 RxMIMOEVMdbm[4]; /* per-path's EVM dbm */ 246 247 u8 RxMIMOSignalStrength[4];/* in 0~100 index */ 248 249 u16 Cfo_short[4]; /* per-path's Cfo_short */ 250 u16 Cfo_tail[4]; /* per-path's Cfo_tail */ 251 252 s8 RxPower; /* in dBm Translate from PWdB */ 253 s8 RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */ 254 u8 BTRxRSSIPercentage; 255 u8 SignalStrength; /* in 0-100 index. */ 256 257 s8 RxPwr[4]; /* per-path's pwdb */ 258 259 u8 RxSNR[4]; /* per-path's SNR */ 260 u8 BandWidth; 261 u8 btCoexPwrAdjust; 262 } ODM_PHY_INFO_T, *PODM_PHY_INFO_T; 263 264 265 typedef struct _ODM_Per_Pkt_Info_ { 266 /* u8 Rate; */ 267 u8 DataRate; 268 u8 StationID; 269 bool bPacketMatchBSSID; 270 bool bPacketToSelf; 271 bool bPacketBeacon; 272 bool bToSelf; 273 } ODM_PACKET_INFO_T, *PODM_PACKET_INFO_T; 274 275 276 typedef struct _ODM_Phy_Dbg_Info_ { 277 /* ODM Write, debug info */ 278 s8 RxSNRdB[4]; 279 u32 NumQryPhyStatus; 280 u32 NumQryPhyStatusCCK; 281 u32 NumQryPhyStatusOFDM; 282 u8 NumQryBeaconPkt; 283 /* Others */ 284 s32 RxEVM[4]; 285 286 } ODM_PHY_DBG_INFO_T; 287 288 289 typedef struct _ODM_Mac_Status_Info_ { 290 u8 test; 291 } ODM_MAC_INFO; 292 293 294 typedef enum tag_Dynamic_ODM_Support_Ability_Type { 295 /* BB Team */ 296 ODM_DIG = 0x00000001, 297 ODM_HIGH_POWER = 0x00000002, 298 ODM_CCK_CCA_TH = 0x00000004, 299 ODM_FA_STATISTICS = 0x00000008, 300 ODM_RAMASK = 0x00000010, 301 ODM_RSSI_MONITOR = 0x00000020, 302 ODM_SW_ANTDIV = 0x00000040, 303 ODM_HW_ANTDIV = 0x00000080, 304 ODM_BB_PWRSV = 0x00000100, 305 ODM_2TPATHDIV = 0x00000200, 306 ODM_1TPATHDIV = 0x00000400, 307 ODM_PSD2AFH = 0x00000800 308 } ODM_Ability_E; 309 310 /* */ 311 /* 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T */ 312 /* Please declare below ODM relative info in your STA info structure. */ 313 /* */ 314 typedef struct _ODM_STA_INFO { 315 /* Driver Write */ 316 bool bUsed; /* record the sta status link or not? */ 317 /* u8 WirelessMode; */ 318 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */ 319 320 /* ODM Write */ 321 /* 1 PHY_STATUS_INFO */ 322 u8 RSSI_Path[4]; /* */ 323 u8 RSSI_Ave; 324 u8 RXEVM[4]; 325 u8 RXSNR[4]; 326 327 /* ODM Write */ 328 /* 1 TX_INFO (may changed by IC) */ 329 /* TX_INFO_T pTxInfo; Define in IC folder. Move lower layer. */ 330 331 /* */ 332 /* Please use compile flag to disabe the strcutrue for other IC except 88E. */ 333 /* Move To lower layer. */ 334 /* */ 335 /* ODM Write Wilson will handle this part(said by Luke.Lee) */ 336 /* TX_RPT_T pTxRpt; Define in IC folder. Move lower layer. */ 337 } ODM_STA_INFO_T, *PODM_STA_INFO_T; 338 339 /* */ 340 /* 2011/10/20 MH Define Common info enum for all team. */ 341 /* */ 342 typedef enum _ODM_Common_Info_Definition { 343 /* Fixed value: */ 344 345 /* HOOK BEFORE REG INIT----------- */ 346 ODM_CMNINFO_PLATFORM = 0, 347 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 348 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 349 ODM_CMNINFO_MP_TEST_CHIP, 350 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 351 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 352 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 353 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 354 ODM_CMNINFO_RFE_TYPE, 355 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 356 ODM_CMNINFO_PACKAGE_TYPE, 357 ODM_CMNINFO_EXT_LNA, /* true */ 358 ODM_CMNINFO_5G_EXT_LNA, 359 ODM_CMNINFO_EXT_PA, 360 ODM_CMNINFO_5G_EXT_PA, 361 ODM_CMNINFO_GPA, 362 ODM_CMNINFO_APA, 363 ODM_CMNINFO_GLNA, 364 ODM_CMNINFO_ALNA, 365 ODM_CMNINFO_EXT_TRSW, 366 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 367 ODM_CMNINFO_BINHCT_TEST, 368 ODM_CMNINFO_BWIFI_TEST, 369 ODM_CMNINFO_SMART_CONCURRENT, 370 /* HOOK BEFORE REG INIT----------- */ 371 372 373 /* Dynamic value: */ 374 /* POINTER REFERENCE----------- */ 375 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 376 ODM_CMNINFO_TX_UNI, 377 ODM_CMNINFO_RX_UNI, 378 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 379 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 380 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 381 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 382 ODM_CMNINFO_BW, /* ODM_BW_E */ 383 ODM_CMNINFO_CHNL, 384 ODM_CMNINFO_FORCED_RATE, 385 386 ODM_CMNINFO_DMSP_GET_VALUE, 387 ODM_CMNINFO_BUDDY_ADAPTOR, 388 ODM_CMNINFO_DMSP_IS_MASTER, 389 ODM_CMNINFO_SCAN, 390 ODM_CMNINFO_POWER_SAVING, 391 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 392 ODM_CMNINFO_DRV_STOP, 393 ODM_CMNINFO_PNP_IN, 394 ODM_CMNINFO_INIT_ON, 395 ODM_CMNINFO_ANT_TEST, 396 ODM_CMNINFO_NET_CLOSED, 397 ODM_CMNINFO_MP_MODE, 398 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 399 ODM_CMNINFO_FORCED_IGI_LB, 400 ODM_CMNINFO_IS1ANTENNA, 401 ODM_CMNINFO_RFDEFAULTPATH, 402 /* POINTER REFERENCE----------- */ 403 404 /* CALL BY VALUE------------- */ 405 ODM_CMNINFO_WIFI_DIRECT, 406 ODM_CMNINFO_WIFI_DISPLAY, 407 ODM_CMNINFO_LINK_IN_PROGRESS, 408 ODM_CMNINFO_LINK, 409 ODM_CMNINFO_STATION_STATE, 410 ODM_CMNINFO_RSSI_MIN, 411 ODM_CMNINFO_DBG_COMP, /* u64 */ 412 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 413 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 414 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 415 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 416 ODM_CMNINFO_BT_ENABLED, 417 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 418 ODM_CMNINFO_BT_HS_RSSI, 419 ODM_CMNINFO_BT_OPERATION, 420 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 421 ODM_CMNINFO_BT_DISABLE_EDCA, 422 /* CALL BY VALUE------------- */ 423 424 /* Dynamic ptr array hook itms. */ 425 ODM_CMNINFO_STA_STATUS, 426 ODM_CMNINFO_PHY_STATUS, 427 ODM_CMNINFO_MAC_STATUS, 428 429 ODM_CMNINFO_MAX, 430 431 432 } ODM_CMNINFO_E; 433 434 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 435 typedef enum _ODM_Support_Ability_Definition { 436 /* */ 437 /* BB ODM section BIT 0-15 */ 438 /* */ 439 ODM_BB_DIG = BIT0, 440 ODM_BB_RA_MASK = BIT1, 441 ODM_BB_DYNAMIC_TXPWR = BIT2, 442 ODM_BB_FA_CNT = BIT3, 443 ODM_BB_RSSI_MONITOR = BIT4, 444 ODM_BB_CCK_PD = BIT5, 445 ODM_BB_ANT_DIV = BIT6, 446 ODM_BB_PWR_SAVE = BIT7, 447 ODM_BB_PWR_TRAIN = BIT8, 448 ODM_BB_RATE_ADAPTIVE = BIT9, 449 ODM_BB_PATH_DIV = BIT10, 450 ODM_BB_PSD = BIT11, 451 ODM_BB_RXHP = BIT12, 452 ODM_BB_ADAPTIVITY = BIT13, 453 ODM_BB_CFO_TRACKING = BIT14, 454 455 /* MAC DM section BIT 16-23 */ 456 ODM_MAC_EDCA_TURBO = BIT16, 457 ODM_MAC_EARLY_MODE = BIT17, 458 459 /* RF ODM section BIT 24-31 */ 460 ODM_RF_TX_PWR_TRACK = BIT24, 461 ODM_RF_RX_GAIN_TRACK = BIT25, 462 ODM_RF_CALIBRATION = BIT26, 463 } ODM_ABILITY_E; 464 465 /* ODM_CMNINFO_INTERFACE */ 466 typedef enum tag_ODM_Support_Interface_Definition { 467 ODM_ITRF_SDIO = 0x4, 468 ODM_ITRF_ALL = 0x7, 469 } ODM_INTERFACE_E; 470 471 /* ODM_CMNINFO_IC_TYPE */ 472 typedef enum tag_ODM_Support_IC_Type_Definition { 473 ODM_RTL8723B = BIT8, 474 } ODM_IC_TYPE_E; 475 476 /* ODM_CMNINFO_CUT_VER */ 477 typedef enum tag_ODM_Cut_Version_Definition { 478 ODM_CUT_A = 0, 479 ODM_CUT_B = 1, 480 ODM_CUT_C = 2, 481 ODM_CUT_D = 3, 482 ODM_CUT_E = 4, 483 ODM_CUT_F = 5, 484 485 ODM_CUT_I = 8, 486 ODM_CUT_J = 9, 487 ODM_CUT_K = 10, 488 ODM_CUT_TEST = 15, 489 } ODM_CUT_VERSION_E; 490 491 /* ODM_CMNINFO_FAB_VER */ 492 typedef enum tag_ODM_Fab_Version_Definition { 493 ODM_TSMC = 0, 494 ODM_UMC = 1, 495 } ODM_FAB_E; 496 497 /* ODM_CMNINFO_RF_TYPE */ 498 /* */ 499 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 500 /* */ 501 typedef enum tag_ODM_RF_Path_Bit_Definition { 502 ODM_RF_TX_A = BIT0, 503 ODM_RF_TX_B = BIT1, 504 ODM_RF_TX_C = BIT2, 505 ODM_RF_TX_D = BIT3, 506 ODM_RF_RX_A = BIT4, 507 ODM_RF_RX_B = BIT5, 508 ODM_RF_RX_C = BIT6, 509 ODM_RF_RX_D = BIT7, 510 } ODM_RF_PATH_E; 511 512 513 typedef enum tag_ODM_RF_Type_Definition { 514 ODM_1T1R = 0, 515 ODM_1T2R = 1, 516 ODM_2T2R = 2, 517 ODM_2T3R = 3, 518 ODM_2T4R = 4, 519 ODM_3T3R = 5, 520 ODM_3T4R = 6, 521 ODM_4T4R = 7, 522 } ODM_RF_TYPE_E; 523 524 525 /* */ 526 /* ODM Dynamic common info value definition */ 527 /* */ 528 529 /* typedef enum _MACPHY_MODE_8192D{ */ 530 /* SINGLEMAC_SINGLEPHY, */ 531 /* DUALMAC_DUALPHY, */ 532 /* DUALMAC_SINGLEPHY, */ 533 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */ 534 /* Above is the original define in MP driver. Please use the same define. THX. */ 535 typedef enum tag_ODM_MAC_PHY_Mode_Definition { 536 ODM_SMSP = 0, 537 ODM_DMSP = 1, 538 ODM_DMDP = 2, 539 } ODM_MAC_PHY_MODE_E; 540 541 542 typedef enum tag_BT_Coexist_Definition { 543 ODM_BT_BUSY = 1, 544 ODM_BT_ON = 2, 545 ODM_BT_OFF = 3, 546 ODM_BT_NONE = 4, 547 } ODM_BT_COEXIST_E; 548 549 /* ODM_CMNINFO_OP_MODE */ 550 typedef enum tag_Operation_Mode_Definition { 551 ODM_NO_LINK = BIT0, 552 ODM_LINK = BIT1, 553 ODM_SCAN = BIT2, 554 ODM_POWERSAVE = BIT3, 555 ODM_AP_MODE = BIT4, 556 ODM_CLIENT_MODE = BIT5, 557 ODM_AD_HOC = BIT6, 558 ODM_WIFI_DIRECT = BIT7, 559 ODM_WIFI_DISPLAY = BIT8, 560 } ODM_OPERATION_MODE_E; 561 562 /* ODM_CMNINFO_WM_MODE */ 563 typedef enum tag_Wireless_Mode_Definition { 564 ODM_WM_UNKNOW = 0x0, 565 ODM_WM_B = BIT0, 566 ODM_WM_G = BIT1, 567 ODM_WM_A = BIT2, 568 ODM_WM_N24G = BIT3, 569 ODM_WM_N5G = BIT4, 570 ODM_WM_AUTO = BIT5, 571 ODM_WM_AC = BIT6, 572 } ODM_WIRELESS_MODE_E; 573 574 /* ODM_CMNINFO_BAND */ 575 typedef enum tag_Band_Type_Definition { 576 ODM_BAND_2_4G = 0, 577 ODM_BAND_5G, 578 ODM_BAND_ON_BOTH, 579 ODM_BANDMAX 580 } ODM_BAND_TYPE_E; 581 582 /* ODM_CMNINFO_SEC_CHNL_OFFSET */ 583 typedef enum tag_Secondary_Channel_Offset_Definition { 584 ODM_DONT_CARE = 0, 585 ODM_BELOW = 1, 586 ODM_ABOVE = 2 587 } ODM_SEC_CHNL_OFFSET_E; 588 589 /* ODM_CMNINFO_SEC_MODE */ 590 typedef enum tag_Security_Definition { 591 ODM_SEC_OPEN = 0, 592 ODM_SEC_WEP40 = 1, 593 ODM_SEC_TKIP = 2, 594 ODM_SEC_RESERVE = 3, 595 ODM_SEC_AESCCMP = 4, 596 ODM_SEC_WEP104 = 5, 597 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */ 598 ODM_SEC_SMS4 = 7, 599 } ODM_SECURITY_E; 600 601 /* ODM_CMNINFO_BW */ 602 typedef enum tag_Bandwidth_Definition { 603 ODM_BW20M = 0, 604 ODM_BW40M = 1, 605 ODM_BW80M = 2, 606 ODM_BW160M = 3, 607 ODM_BW10M = 4, 608 } ODM_BW_E; 609 610 611 /* ODM_CMNINFO_BOARD_TYPE */ 612 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 613 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 614 typedef enum tag_Board_Definition { 615 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */ 616 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */ 617 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */ 618 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */ 619 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */ 620 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */ 621 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */ 622 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */ 623 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */ 624 } ODM_BOARD_TYPE_E; 625 626 typedef enum tag_ODM_Package_Definition { 627 ODM_PACKAGE_DEFAULT = 0, 628 ODM_PACKAGE_QFN68 = BIT(0), 629 ODM_PACKAGE_TFBGA90 = BIT(1), 630 ODM_PACKAGE_TFBGA79 = BIT(2), 631 } ODM_Package_TYPE_E; 632 633 typedef enum tag_ODM_TYPE_GPA_Definition { 634 TYPE_GPA0 = 0, 635 TYPE_GPA1 = BIT(1)|BIT(0) 636 } ODM_TYPE_GPA_E; 637 638 typedef enum tag_ODM_TYPE_APA_Definition { 639 TYPE_APA0 = 0, 640 TYPE_APA1 = BIT(1)|BIT(0) 641 } ODM_TYPE_APA_E; 642 643 typedef enum tag_ODM_TYPE_GLNA_Definition { 644 TYPE_GLNA0 = 0, 645 TYPE_GLNA1 = BIT(2)|BIT(0), 646 TYPE_GLNA2 = BIT(3)|BIT(1), 647 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 648 } ODM_TYPE_GLNA_E; 649 650 typedef enum tag_ODM_TYPE_ALNA_Definition { 651 TYPE_ALNA0 = 0, 652 TYPE_ALNA1 = BIT(2)|BIT(0), 653 TYPE_ALNA2 = BIT(3)|BIT(1), 654 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 655 } ODM_TYPE_ALNA_E; 656 657 /* ODM_CMNINFO_ONE_PATH_CCA */ 658 typedef enum tag_CCA_Path { 659 ODM_CCA_2R = 0, 660 ODM_CCA_1R_A = 1, 661 ODM_CCA_1R_B = 2, 662 } ODM_CCA_PATH_E; 663 664 665 typedef struct _ODM_RA_Info_ { 666 u8 RateID; 667 u32 RateMask; 668 u32 RAUseRate; 669 u8 RateSGI; 670 u8 RssiStaRA; 671 u8 PreRssiStaRA; 672 u8 SGIEnable; 673 u8 DecisionRate; 674 u8 PreRate; 675 u8 HighestRate; 676 u8 LowestRate; 677 u32 NscUp; 678 u32 NscDown; 679 u16 RTY[5]; 680 u32 TOTAL; 681 u16 DROP; 682 u8 Active; 683 u16 RptTime; 684 u8 RAWaitingCounter; 685 u8 RAPendingCounter; 686 u8 PTActive; /* on or off */ 687 u8 PTTryState; /* 0 trying state, 1 for decision state */ 688 u8 PTStage; /* 0~6 */ 689 u8 PTStopCount; /* Stop PT counter */ 690 u8 PTPreRate; /* if rate change do PT */ 691 u8 PTPreRssi; /* if RSSI change 5% do PT */ 692 u8 PTModeSS; /* decide whitch rate should do PT */ 693 u8 RAstage; /* StageRA, decide how many times RA will be done between PT */ 694 u8 PTSmoothFactor; 695 } ODM_RA_INFO_T, *PODM_RA_INFO_T; 696 697 typedef struct _IQK_MATRIX_REGS_SETTING { 698 bool bIQKDone; 699 s32 Value[3][IQK_Matrix_REG_NUM]; 700 bool bBWIqkResultSaved[3]; 701 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING; 702 703 704 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 705 706 typedef struct ODM_RF_Calibration_Structure { 707 /* for tx power tracking */ 708 709 u32 RegA24; /* for TempCCK */ 710 s32 RegE94; 711 s32 RegE9C; 712 s32 RegEB4; 713 s32 RegEBC; 714 715 u8 TXPowercount; 716 bool bTXPowerTrackingInit; 717 bool bTXPowerTracking; 718 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 719 u8 TM_Trigger; 720 u8 InternalPA5G[2]; /* pathA / pathB */ 721 722 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 723 u8 ThermalValue; 724 u8 ThermalValue_LCK; 725 u8 ThermalValue_IQK; 726 u8 ThermalValue_DPK; 727 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 728 u8 ThermalValue_AVG_index; 729 u8 ThermalValue_RxGain; 730 u8 ThermalValue_Crystal; 731 u8 ThermalValue_DPKstore; 732 u8 ThermalValue_DPKtrack; 733 bool TxPowerTrackingInProgress; 734 735 bool bReloadtxpowerindex; 736 u8 bRfPiEnable; 737 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 738 739 740 /* Tx power Tracking ------------------------- */ 741 u8 bCCKinCH14; 742 u8 CCK_index; 743 u8 OFDM_index[MAX_RF_PATH]; 744 s8 PowerIndexOffset[MAX_RF_PATH]; 745 s8 DeltaPowerIndex[MAX_RF_PATH]; 746 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 747 bool bTxPowerChanged; 748 749 u8 ThermalValue_HP[HP_THERMAL_NUM]; 750 u8 ThermalValue_HP_index; 751 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 752 bool bNeedIQK; 753 bool bIQKInProgress; 754 u8 Delta_IQK; 755 u8 Delta_LCK; 756 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 757 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 758 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 759 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 760 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 761 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 762 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 763 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 764 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 765 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 766 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 767 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 768 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 769 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 770 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 771 772 /* */ 773 774 /* for IQK */ 775 u32 RegC04; 776 u32 Reg874; 777 u32 RegC08; 778 u32 RegB68; 779 u32 RegB6C; 780 u32 Reg870; 781 u32 Reg860; 782 u32 Reg864; 783 784 bool bIQKInitialized; 785 bool bLCKInProgress; 786 bool bAntennaDetected; 787 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 788 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 789 u32 IQK_BB_backup_recover[9]; 790 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 791 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 792 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 793 794 795 /* for APK */ 796 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 797 u8 bAPKdone; 798 u8 bAPKThermalMeterIgnore; 799 800 /* DPK */ 801 bool bDPKFail; 802 u8 bDPdone; 803 u8 bDPPathAOK; 804 u8 bDPPathBOK; 805 806 u32 TxLOK[2]; 807 808 } ODM_RF_CAL_T, *PODM_RF_CAL_T; 809 /* */ 810 /* ODM Dynamic common info value definition */ 811 /* */ 812 813 typedef struct _FAST_ANTENNA_TRAINNING_ { 814 u8 Bssid[6]; 815 u8 antsel_rx_keep_0; 816 u8 antsel_rx_keep_1; 817 u8 antsel_rx_keep_2; 818 u8 antsel_rx_keep_3; 819 u32 antSumRSSI[7]; 820 u32 antRSSIcnt[7]; 821 u32 antAveRSSI[7]; 822 u8 FAT_State; 823 u32 TrainIdx; 824 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 825 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 826 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 827 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 828 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 829 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 830 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 831 u8 RxIdleAnt; 832 bool bBecomeLinked; 833 u32 MinMaxRSSI; 834 u8 idx_AntDiv_counter_2G; 835 u8 idx_AntDiv_counter_5G; 836 u32 AntDiv_2G_5G; 837 u32 CCK_counter_main; 838 u32 CCK_counter_aux; 839 u32 OFDM_counter_main; 840 u32 OFDM_counter_aux; 841 842 843 u32 CCK_CtrlFrame_Cnt_main; 844 u32 CCK_CtrlFrame_Cnt_aux; 845 u32 OFDM_CtrlFrame_Cnt_main; 846 u32 OFDM_CtrlFrame_Cnt_aux; 847 u32 MainAnt_CtrlFrame_Sum; 848 u32 AuxAnt_CtrlFrame_Sum; 849 u32 MainAnt_CtrlFrame_Cnt; 850 u32 AuxAnt_CtrlFrame_Cnt; 851 852 } FAT_T, *pFAT_T; 853 854 typedef enum _FAT_STATE { 855 FAT_NORMAL_STATE = 0, 856 FAT_TRAINING_STATE = 1, 857 } FAT_STATE_E, *PFAT_STATE_E; 858 859 typedef enum _ANT_DIV_TYPE { 860 NO_ANTDIV = 0xFF, 861 CG_TRX_HW_ANTDIV = 0x01, 862 CGCS_RX_HW_ANTDIV = 0x02, 863 FIXED_HW_ANTDIV = 0x03, 864 CG_TRX_SMART_ANTDIV = 0x04, 865 CGCS_RX_SW_ANTDIV = 0x05, 866 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 867 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E; 868 869 typedef struct _ODM_PATH_DIVERSITY_ { 870 u8 RespTxPath; 871 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 872 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 873 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 874 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 875 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 876 } PATHDIV_T, *pPATHDIV_T; 877 878 879 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{ 880 PHY_REG_PG_RELATIVE_VALUE = 0, 881 PHY_REG_PG_EXACT_VALUE = 1 882 } PHY_REG_PG_TYPE; 883 884 885 /* */ 886 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 887 /* */ 888 typedef struct _ANT_DETECTED_INFO { 889 bool bAntDetected; 890 u32 dBForAntA; 891 u32 dBForAntB; 892 u32 dBForAntO; 893 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO; 894 895 /* */ 896 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 897 /* */ 898 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure { 899 /* RT_TIMER FastAntTrainingTimer; */ 900 /* */ 901 /* Add for different team use temporarily */ 902 /* */ 903 struct adapter *Adapter; /* For CE/NIC team */ 904 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 905 bool odm_ready; 906 907 PHY_REG_PG_TYPE PhyRegPgValueType; 908 u8 PhyRegPgVersion; 909 910 u64 DebugComponents; 911 u32 DebugLevel; 912 913 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 914 u32 LastNumQryPhyStatusAll; 915 u32 RxPWDBAve; 916 bool MPDIG_2G; /* off MPDIG */ 917 u8 Times_2G; 918 919 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 920 bool bCckHighPower; 921 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 922 u8 ControlChannel; 923 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 924 925 /* REMOVED COMMON INFO---------- */ 926 /* u8 PseudoMacPhyMode; */ 927 /* bool *BTCoexist; */ 928 /* bool PseudoBtCoexist; */ 929 /* u8 OPMode; */ 930 /* bool bAPMode; */ 931 /* bool bClientMode; */ 932 /* bool bAdHocMode; */ 933 /* bool bSlaveOfDMSP; */ 934 /* REMOVED COMMON INFO---------- */ 935 936 937 /* 1 COMMON INFORMATION */ 938 939 /* */ 940 /* Init Value */ 941 /* */ 942 /* HOOK BEFORE REG INIT----------- */ 943 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 944 u8 SupportPlatform; 945 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ?K?K = 1/2/3/?K */ 946 u32 SupportAbility; 947 /* ODM PCIE/USB/SDIO = 1/2/3 */ 948 u8 SupportInterface; 949 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 950 u32 SupportICType; 951 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 952 u8 CutVersion; 953 /* Fab Version TSMC/UMC = 0/1 */ 954 u8 FabVersion; 955 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 956 u8 RFType; 957 u8 RFEType; 958 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 959 u8 BoardType; 960 u8 PackageType; 961 u8 TypeGLNA; 962 u8 TypeGPA; 963 u8 TypeALNA; 964 u8 TypeAPA; 965 /* with external LNA NO/Yes = 0/1 */ 966 u8 ExtLNA; 967 u8 ExtLNA5G; 968 /* with external PA NO/Yes = 0/1 */ 969 u8 ExtPA; 970 u8 ExtPA5G; 971 /* with external TRSW NO/Yes = 0/1 */ 972 u8 ExtTRSW; 973 u8 PatchID; /* Customer ID */ 974 bool bInHctTest; 975 bool bWIFITest; 976 977 bool bDualMacSmartConcurrent; 978 u32 BK_SupportAbility; 979 u8 AntDivType; 980 /* HOOK BEFORE REG INIT----------- */ 981 982 /* */ 983 /* Dynamic Value */ 984 /* */ 985 /* POINTER REFERENCE----------- */ 986 987 u8 u8_temp; 988 bool bool_temp; 989 struct adapter *adapter_temp; 990 991 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 992 u8 *pMacPhyMode; 993 /* TX Unicast byte count */ 994 u64 *pNumTxBytesUnicast; 995 /* RX Unicast byte count */ 996 u64 *pNumRxBytesUnicast; 997 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 998 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 999 /* Frequence band 2.4G/5G = 0/1 */ 1000 u8 *pBandType; 1001 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 1002 u8 *pSecChOffset; 1003 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 1004 u8 *pSecurity; 1005 /* BW info 20M/40M/80M = 0/1/2 */ 1006 u8 *pBandWidth; 1007 /* Central channel location Ch1/Ch2/.... */ 1008 u8 *pChannel; /* central channel number */ 1009 bool DPK_Done; 1010 /* Common info for 92D DMSP */ 1011 1012 bool *pbGetValueFromOtherMac; 1013 struct adapter **pBuddyAdapter; 1014 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 1015 /* Common info for Status */ 1016 bool *pbScanInProcess; 1017 bool *pbPowerSaving; 1018 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 1019 u8 *pOnePathCCA; 1020 /* pMgntInfo->AntennaTest */ 1021 u8 *pAntennaTest; 1022 bool *pbNet_closed; 1023 u8 *mp_mode; 1024 /* u8 *pAidMap; */ 1025 u8 *pu1ForcedIgiLb; 1026 /* For 8723B IQK----------- */ 1027 bool *pIs1Antenna; 1028 u8 *pRFDefaultPath; 1029 /* 0:S1, 1:S0 */ 1030 1031 /* POINTER REFERENCE----------- */ 1032 u16 *pForcedDataRate; 1033 /* CALL BY VALUE------------- */ 1034 bool bLinkInProcess; 1035 bool bWIFI_Direct; 1036 bool bWIFI_Display; 1037 bool bLinked; 1038 1039 bool bsta_state; 1040 u8 RSSI_Min; 1041 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 1042 bool bIsMPChip; 1043 bool bOneEntryOnly; 1044 /* Common info for BTDM */ 1045 bool bBtEnabled; /* BT is disabled */ 1046 bool bBtConnectProcess; /* BT HS is under connection progress. */ 1047 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 1048 bool bBtHsOperation; /* BT HS mode is under progress */ 1049 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 1050 bool bBtLimitedDig; /* BT is busy. */ 1051 /* CALL BY VALUE------------- */ 1052 u8 RSSI_A; 1053 u8 RSSI_B; 1054 u64 RSSI_TRSW; 1055 u64 RSSI_TRSW_H; 1056 u64 RSSI_TRSW_L; 1057 u64 RSSI_TRSW_iso; 1058 1059 u8 RxRate; 1060 bool bNoisyState; 1061 u8 TxRate; 1062 u8 LinkedInterval; 1063 u8 preChannel; 1064 u32 TxagcOffsetValueA; 1065 bool IsTxagcOffsetPositiveA; 1066 u32 TxagcOffsetValueB; 1067 bool IsTxagcOffsetPositiveB; 1068 u64 lastTxOkCnt; 1069 u64 lastRxOkCnt; 1070 u32 BbSwingOffsetA; 1071 bool IsBbSwingOffsetPositiveA; 1072 u32 BbSwingOffsetB; 1073 bool IsBbSwingOffsetPositiveB; 1074 s8 TH_L2H_ini; 1075 s8 TH_EDCCA_HL_diff; 1076 s8 IGI_Base; 1077 u8 IGI_target; 1078 bool ForceEDCCA; 1079 u8 AdapEn_RSSI; 1080 s8 Force_TH_H; 1081 s8 Force_TH_L; 1082 u8 IGI_LowerBound; 1083 u8 antdiv_rssi; 1084 u8 AntType; 1085 u8 pre_AntType; 1086 u8 antdiv_period; 1087 u8 antdiv_select; 1088 u8 NdpaPeriod; 1089 bool H2C_RARpt_connect; 1090 1091 /* add by Yu Cehn for adaptivtiy */ 1092 bool adaptivity_flag; 1093 bool NHM_disable; 1094 bool TxHangFlg; 1095 bool Carrier_Sense_enable; 1096 u8 tolerance_cnt; 1097 u64 NHMCurTxOkcnt; 1098 u64 NHMCurRxOkcnt; 1099 u64 NHMLastTxOkcnt; 1100 u64 NHMLastRxOkcnt; 1101 u8 txEdcca1; 1102 u8 txEdcca0; 1103 s8 H2L_lb; 1104 s8 L2H_lb; 1105 u8 Adaptivity_IGI_upper; 1106 u8 NHM_cnt_0; 1107 1108 1109 ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 1110 /* */ 1111 /* 2 Define STA info. */ 1112 /* _ODM_STA_INFO */ 1113 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 1114 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 1115 1116 /* */ 1117 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 1118 /* We need to colelct all support abilit to a proper area. */ 1119 /* */ 1120 bool RaSupport88E; 1121 1122 /* Define ........... */ 1123 1124 /* Latest packet phy info (ODM write) */ 1125 ODM_PHY_DBG_INFO_T PhyDbgInfo; 1126 /* PHY_INFO_88E PhyInfo; */ 1127 1128 /* Latest packet phy info (ODM write) */ 1129 ODM_MAC_INFO *pMacInfo; 1130 /* MAC_INFO_88E MacInfo; */ 1131 1132 /* Different Team independt structure?? */ 1133 1134 /* */ 1135 /* TX_RTP_CMN TX_retrpo; */ 1136 /* TX_RTP_88E TX_retrpo; */ 1137 /* TX_RTP_8195 TX_retrpo; */ 1138 1139 /* */ 1140 /* ODM Structure */ 1141 /* */ 1142 FAT_T DM_FatTable; 1143 DIG_T DM_DigTable; 1144 PS_T DM_PSTable; 1145 Pri_CCA_T DM_PriCCA; 1146 RXHP_T DM_RXHP_Table; 1147 RA_T DM_RA_Table; 1148 false_ALARM_STATISTICS FalseAlmCnt; 1149 false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 1150 SWAT_T DM_SWAT_Table; 1151 bool RSSI_test; 1152 CFO_TRACKING DM_CfoTrack; 1153 1154 EDCA_T DM_EDCA_Table; 1155 u32 WMMEDCA_BE; 1156 PATHDIV_T DM_PathDiv; 1157 /* Copy from SD4 structure */ 1158 /* */ 1159 /* ================================================== */ 1160 /* */ 1161 1162 /* common */ 1163 /* u8 DM_Type; */ 1164 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 1165 /* u8 PSD_func_flag; Add By Gary */ 1166 /* for DIG */ 1167 /* u8 bDMInitialGainEnable; */ 1168 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 1169 /* for Antenna diversity */ 1170 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 1171 /* PSTA_INFO_T RSSI_target; */ 1172 1173 bool *pbDriverStopped; 1174 bool *pbDriverIsGoingToPnpSetPowerSleep; 1175 bool *pinit_adpt_in_progress; 1176 1177 /* PSD */ 1178 bool bUserAssignLevel; 1179 RT_TIMER PSDTimer; 1180 u8 RSSI_BT; /* come from BT */ 1181 bool bPSDinProcess; 1182 bool bPSDactive; 1183 bool bDMInitialGainEnable; 1184 1185 /* MPT DIG */ 1186 RT_TIMER MPT_DIGTimer; 1187 1188 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 1189 u8 bUseRAMask; 1190 1191 ODM_RATE_ADAPTIVE RateAdaptive; 1192 1193 ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool */ 1194 1195 ODM_RF_CAL_T RFCalibrateInfo; 1196 1197 /* */ 1198 /* TX power tracking */ 1199 /* */ 1200 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 1201 u8 BbSwingIdxOfdmCurrent; 1202 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 1203 bool BbSwingFlagOfdm; 1204 u8 BbSwingIdxCck; 1205 u8 BbSwingIdxCckCurrent; 1206 u8 BbSwingIdxCckBase; 1207 u8 DefaultOfdmIndex; 1208 u8 DefaultCckIndex; 1209 bool BbSwingFlagCck; 1210 1211 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 1212 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 1213 s8 Remnant_CCKSwingIdx; 1214 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 1215 bool Modify_TxAGC_Flag_PathA; 1216 bool Modify_TxAGC_Flag_PathB; 1217 bool Modify_TxAGC_Flag_PathC; 1218 bool Modify_TxAGC_Flag_PathD; 1219 bool Modify_TxAGC_Flag_PathA_CCK; 1220 1221 s8 KfreeOffset[MAX_RF_PATH]; 1222 /* */ 1223 /* ODM system resource. */ 1224 /* */ 1225 1226 /* ODM relative time. */ 1227 RT_TIMER PathDivSwitchTimer; 1228 /* 2011.09.27 add for Path Diversity */ 1229 RT_TIMER CCKPathDiversityTimer; 1230 RT_TIMER FastAntTrainingTimer; 1231 1232 /* ODM relative workitem. */ 1233 1234 #if (BEAMFORMING_SUPPORT == 1) 1235 RT_BEAMFORMING_INFO BeamformingInfo; 1236 #endif 1237 } DM_ODM_T, *PDM_ODM_T; /* DM_Dynamic_Mechanism_Structure */ 1238 1239 #define ODM_RF_PATH_MAX 2 1240 1241 typedef enum _ODM_RF_RADIO_PATH { 1242 ODM_RF_PATH_A = 0, /* Radio Path A */ 1243 ODM_RF_PATH_B = 1, /* Radio Path B */ 1244 ODM_RF_PATH_C = 2, /* Radio Path C */ 1245 ODM_RF_PATH_D = 3, /* Radio Path D */ 1246 ODM_RF_PATH_AB, 1247 ODM_RF_PATH_AC, 1248 ODM_RF_PATH_AD, 1249 ODM_RF_PATH_BC, 1250 ODM_RF_PATH_BD, 1251 ODM_RF_PATH_CD, 1252 ODM_RF_PATH_ABC, 1253 ODM_RF_PATH_ACD, 1254 ODM_RF_PATH_BCD, 1255 ODM_RF_PATH_ABCD, 1256 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1257 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E; 1258 1259 typedef enum _ODM_RF_CONTENT { 1260 odm_radioa_txt = 0x1000, 1261 odm_radiob_txt = 0x1001, 1262 odm_radioc_txt = 0x1002, 1263 odm_radiod_txt = 0x1003 1264 } ODM_RF_CONTENT; 1265 1266 typedef enum _ODM_BB_Config_Type { 1267 CONFIG_BB_PHY_REG, 1268 CONFIG_BB_AGC_TAB, 1269 CONFIG_BB_AGC_TAB_2G, 1270 CONFIG_BB_AGC_TAB_5G, 1271 CONFIG_BB_PHY_REG_PG, 1272 CONFIG_BB_PHY_REG_MP, 1273 CONFIG_BB_AGC_TAB_DIFF, 1274 } ODM_BB_Config_Type, *PODM_BB_Config_Type; 1275 1276 typedef enum _ODM_RF_Config_Type { 1277 CONFIG_RF_RADIO, 1278 CONFIG_RF_TXPWR_LMT, 1279 } ODM_RF_Config_Type, *PODM_RF_Config_Type; 1280 1281 typedef enum _ODM_FW_Config_Type { 1282 CONFIG_FW_NIC, 1283 CONFIG_FW_NIC_2, 1284 CONFIG_FW_AP, 1285 CONFIG_FW_WoWLAN, 1286 CONFIG_FW_WoWLAN_2, 1287 CONFIG_FW_AP_WoWLAN, 1288 CONFIG_FW_BT, 1289 } ODM_FW_Config_Type; 1290 1291 /* Status code */ 1292 typedef enum _RT_STATUS { 1293 RT_STATUS_SUCCESS, 1294 RT_STATUS_FAILURE, 1295 RT_STATUS_PENDING, 1296 RT_STATUS_RESOURCE, 1297 RT_STATUS_INVALID_CONTEXT, 1298 RT_STATUS_INVALID_PARAMETER, 1299 RT_STATUS_NOT_SUPPORT, 1300 RT_STATUS_OS_API_FAILED, 1301 } RT_STATUS, *PRT_STATUS; 1302 1303 #ifdef REMOVE_PACK 1304 #pragma pack() 1305 #endif 1306 1307 /* include "odm_function.h" */ 1308 1309 /* 3 =========================================================== */ 1310 /* 3 DIG */ 1311 /* 3 =========================================================== */ 1312 1313 /* Remove DIG by Yuchen */ 1314 1315 /* 3 =========================================================== */ 1316 /* 3 AGC RX High Power Mode */ 1317 /* 3 =========================================================== */ 1318 #define LNA_Low_Gain_1 0x64 1319 #define LNA_Low_Gain_2 0x5A 1320 #define LNA_Low_Gain_3 0x58 1321 1322 #define FA_RXHP_TH1 5000 1323 #define FA_RXHP_TH2 1500 1324 #define FA_RXHP_TH3 800 1325 #define FA_RXHP_TH4 600 1326 #define FA_RXHP_TH5 500 1327 1328 /* 3 =========================================================== */ 1329 /* 3 EDCA */ 1330 /* 3 =========================================================== */ 1331 1332 /* 3 =========================================================== */ 1333 /* 3 Dynamic Tx Power */ 1334 /* 3 =========================================================== */ 1335 /* Dynamic Tx Power Control Threshold */ 1336 1337 /* 3 =========================================================== */ 1338 /* 3 Rate Adaptive */ 1339 /* 3 =========================================================== */ 1340 #define DM_RATR_STA_INIT 0 1341 #define DM_RATR_STA_HIGH 1 1342 #define DM_RATR_STA_MIDDLE 2 1343 #define DM_RATR_STA_LOW 3 1344 1345 /* 3 =========================================================== */ 1346 /* 3 BB Power Save */ 1347 /* 3 =========================================================== */ 1348 1349 typedef enum tag_1R_CCA_Type_Definition { 1350 CCA_1R = 0, 1351 CCA_2R = 1, 1352 CCA_MAX = 2, 1353 } DM_1R_CCA_E; 1354 1355 typedef enum tag_RF_Type_Definition { 1356 RF_Save = 0, 1357 RF_Normal = 1, 1358 RF_MAX = 2, 1359 } DM_RF_E; 1360 1361 /* 3 =========================================================== */ 1362 /* 3 Antenna Diversity */ 1363 /* 3 =========================================================== */ 1364 typedef enum tag_SW_Antenna_Switch_Definition { 1365 Antenna_A = 1, 1366 Antenna_B = 2, 1367 Antenna_MAX = 3, 1368 } DM_SWAS_E; 1369 1370 1371 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1372 #define MAX_ANTENNA_DETECTION_CNT 10 1373 1374 /* */ 1375 /* Extern Global Variables. */ 1376 /* */ 1377 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1378 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1379 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1380 1381 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1382 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1383 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1384 1385 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1386 1387 /* */ 1388 /* check Sta pointer valid or not */ 1389 /* */ 1390 #define IS_STA_VALID(pSta) (pSta) 1391 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1392 /* This indicates two different the steps. */ 1393 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1394 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1395 /* with original RSSI to determine if it is necessary to switch antenna. */ 1396 #define SWAW_STEP_PEAK 0 1397 #define SWAW_STEP_DETERMINE 1 1398 1399 /* Remove DIG by yuchen */ 1400 1401 void ODM_SetAntenna(PDM_ODM_T pDM_Odm, u8 Antenna); 1402 1403 1404 /* Remove BB power saving by Yuchen */ 1405 1406 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1407 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm); 1408 1409 bool ODM_RAStateCheck( 1410 PDM_ODM_T pDM_Odm, 1411 s32 RSSI, 1412 bool bForceUpdate, 1413 u8 *pRATRState 1414 ); 1415 1416 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1417 void ODM_SwAntDivChkPerPktRssi( 1418 PDM_ODM_T pDM_Odm, 1419 u8 StationID, 1420 PODM_PHY_INFO_T pPhyInfo 1421 ); 1422 1423 u32 ODM_Get_Rate_Bitmap( 1424 PDM_ODM_T pDM_Odm, 1425 u32 macid, 1426 u32 ra_mask, 1427 u8 rssi_level 1428 ); 1429 1430 #if (BEAMFORMING_SUPPORT == 1) 1431 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1432 #endif 1433 1434 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm); 1435 1436 void ODM_DMInit(PDM_ODM_T pDM_Odm); 1437 1438 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /* For common use in the future */ 1439 1440 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value); 1441 1442 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue); 1443 1444 void ODM_CmnInfoPtrArrayHook( 1445 PDM_ODM_T pDM_Odm, 1446 ODM_CMNINFO_E CmnInfo, 1447 u16 Index, 1448 void *pValue 1449 ); 1450 1451 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value); 1452 1453 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm); 1454 1455 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm); 1456 1457 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm); 1458 1459 void ODM_AntselStatistics_88C( 1460 PDM_ODM_T pDM_Odm, 1461 u8 MacId, 1462 u32 PWDBAll, 1463 bool isCCKrate 1464 ); 1465 1466 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State); 1467 1468 #endif 1469