1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_DynamicBBPowerSaving.h" 15 #include "odm_DynamicTxPower.h" 16 #include "odm_CfoTracking.h" 17 #include "odm_NoiseMonitor.h" 18 19 #define TP_MODE 0 20 #define RSSI_MODE 1 21 #define TRAFFIC_LOW 0 22 #define TRAFFIC_HIGH 1 23 #define NONE 0 24 25 /* 3 Tx Power Tracking */ 26 /* 3 ============================================================ */ 27 #define DPK_DELTA_MAPPING_NUM 13 28 #define index_mapping_HP_NUM 15 29 #define OFDM_TABLE_SIZE 43 30 #define CCK_TABLE_SIZE 33 31 #define TXSCALE_TABLE_SIZE 37 32 #define TXPWR_TRACK_TABLE_SIZE 30 33 #define DELTA_SWINGIDX_SIZE 30 34 #define BAND_NUM 4 35 36 /* 3 PSD Handler */ 37 /* 3 ============================================================ */ 38 39 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 40 #define MODE_40M 0 /* 0:20M, 1:40M */ 41 #define PSD_TH2 3 42 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 43 #define SIR_STEP_SIZE 3 44 #define Smooth_Size_1 5 45 #define Smooth_TH_1 3 46 #define Smooth_Size_2 10 47 #define Smooth_TH_2 4 48 #define Smooth_Size_3 20 49 #define Smooth_TH_3 4 50 #define Smooth_Step_Size 5 51 #define Adaptive_SIR 1 52 #define PSD_RESCAN 4 53 #define PSD_SCAN_INTERVAL 700 /* ms */ 54 55 /* 8723A High Power IGI Setting */ 56 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 57 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 58 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 59 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 60 61 /* ANT Test */ 62 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 63 #define ANTTESTA 0x01 /* Ant A will be Testing */ 64 #define ANTTESTB 0x02 /* Ant B will be testing */ 65 66 #define PS_MODE_ACTIVE 0x01 67 68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 69 #define MAIN_ANT 1 /* Ant A or Ant Main */ 70 #define AUX_ANT 2 /* AntB or Ant Aux */ 71 #define MAX_ANT 3 /* 3 for AP using */ 72 73 /* Antenna Diversity Type */ 74 #define SW_ANTDIV 0 75 #define HW_ANTDIV 1 76 /* structure and define */ 77 78 /* Remove DIG by Yuchen */ 79 80 /* Remoce BB power saving by Yuchn */ 81 82 /* Remove DIG by yuchen */ 83 84 struct dynamic_primary_CCA { 85 u8 PriCCA_flag; 86 u8 intf_flag; 87 u8 intf_type; 88 u8 DupRTS_flag; 89 u8 Monitor_flag; 90 u8 CH_offset; 91 u8 MF_state; 92 }; 93 94 struct ra_t { 95 u8 firstconnect; 96 }; 97 98 struct rxhp_t { 99 u8 RXHP_flag; 100 u8 PSD_func_trigger; 101 u8 PSD_bitmap_RXHP[80]; 102 u8 Pre_IGI; 103 u8 Cur_IGI; 104 u8 Pre_pw_th; 105 u8 Cur_pw_th; 106 bool First_time_enter; 107 bool RXHP_enable; 108 u8 TP_Mode; 109 struct timer_list PSDTimer; 110 }; 111 112 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 113 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 114 115 /* This indicates two different the steps. */ 116 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 117 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 118 /* with original RSSI to determine if it is necessary to switch antenna. */ 119 #define SWAW_STEP_PEAK 0 120 #define SWAW_STEP_DETERMINE 1 121 122 #define TP_MODE 0 123 #define RSSI_MODE 1 124 #define TRAFFIC_LOW 0 125 #define TRAFFIC_HIGH 1 126 #define TRAFFIC_UltraLOW 2 127 128 struct swat_t { /* _SW_Antenna_Switch_ */ 129 u8 Double_chk_flag; 130 u8 try_flag; 131 s32 PreRSSI; 132 u8 CurAntenna; 133 u8 PreAntenna; 134 u8 RSSI_Trying; 135 u8 TestMode; 136 u8 bTriggerAntennaSwitch; 137 u8 SelectAntennaMap; 138 u8 RSSI_target; 139 u8 reset_idx; 140 u16 Single_Ant_Counter; 141 u16 Dual_Ant_Counter; 142 u16 Aux_FailDetec_Counter; 143 u16 Retry_Counter; 144 145 /* Before link Antenna Switch check */ 146 u8 SWAS_NoLink_State; 147 u32 SWAS_NoLink_BK_Reg860; 148 u32 SWAS_NoLink_BK_Reg92c; 149 u32 SWAS_NoLink_BK_Reg948; 150 bool ANTA_ON; /* To indicate Ant A is or not */ 151 bool ANTB_ON; /* To indicate Ant B is on or not */ 152 bool Pre_Aux_FailDetec; 153 bool RSSI_AntDect_bResult; 154 u8 Ant2G; 155 156 s32 RSSI_sum_A; 157 s32 RSSI_sum_B; 158 s32 RSSI_cnt_A; 159 s32 RSSI_cnt_B; 160 161 u64 lastTxOkCnt; 162 u64 lastRxOkCnt; 163 u64 TXByteCnt_A; 164 u64 TXByteCnt_B; 165 u64 RXByteCnt_A; 166 u64 RXByteCnt_B; 167 u8 TrafficLoad; 168 u8 Train_time; 169 u8 Train_time_flag; 170 struct timer_list SwAntennaSwitchTimer; 171 struct timer_list SwAntennaSwitchTimer_8723B; 172 u32 PktCnt_SWAntDivByCtrlFrame; 173 bool bSWAntDivByCtrlFrame; 174 }; 175 176 /* Remove Edca by YuChen */ 177 178 179 struct odm_rate_adaptive { 180 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 181 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 182 bool bUseLdpc; 183 bool bLowerRtsRate; 184 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 185 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 186 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 187 188 }; 189 190 #define IQK_MAC_REG_NUM 4 191 #define IQK_ADDA_REG_NUM 16 192 #define IQK_BB_REG_NUM_MAX 10 193 #define IQK_BB_REG_NUM 9 194 #define HP_THERMAL_NUM 8 195 196 #define AVG_THERMAL_NUM 8 197 #define IQK_Matrix_REG_NUM 8 198 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */ 199 200 #define DM_Type_ByFW 0 201 #define DM_Type_ByDriver 1 202 203 /* */ 204 /* Declare for common info */ 205 /* */ 206 #define MAX_PATH_NUM_92CS 2 207 #define MAX_PATH_NUM_8188E 1 208 #define MAX_PATH_NUM_8192E 2 209 #define MAX_PATH_NUM_8723B 1 210 #define MAX_PATH_NUM_8812A 2 211 #define MAX_PATH_NUM_8821A 1 212 #define MAX_PATH_NUM_8814A 4 213 #define MAX_PATH_NUM_8822B 2 214 215 #define IQK_THRESHOLD 8 216 #define DPK_THRESHOLD 4 217 218 struct odm_phy_info { 219 /* 220 * Be care, if you want to add any element, please insert it between 221 * rx_pwd_ball and signal_strength. 222 */ 223 u8 rx_pwd_ba11; 224 225 u8 signal_quality; /* in 0-100 index. */ 226 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 227 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 228 229 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 230 231 u16 cfo_short[4]; /* per-path's Cfo_short */ 232 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 233 234 s8 rx_power; /* in dBm Translate from PWdB */ 235 236 /* 237 * Real power in dBm for this packet, no beautification and 238 * aggregation. Keep this raw info to be used for the other procedures. 239 */ 240 s8 recv_signal_power; 241 u8 bt_rx_rssi_percentage; 242 u8 signal_strength; /* in 0-100 index. */ 243 244 s8 rx_pwr[4]; /* per-path's pwdb */ 245 246 u8 rx_snr[4]; /* per-path's SNR */ 247 u8 band_width; 248 u8 bt_coex_pwr_adjust; 249 }; 250 251 struct odm_packet_info { 252 u8 data_rate; 253 u8 station_id; 254 bool bssid_match; 255 bool to_self; 256 bool is_beacon; 257 }; 258 259 struct odm_phy_dbg_info { 260 /* ODM Write, debug info */ 261 s8 RxSNRdB[4]; 262 u32 NumQryPhyStatus; 263 u32 NumQryPhyStatusCCK; 264 u32 NumQryPhyStatusOFDM; 265 u8 NumQryBeaconPkt; 266 /* Others */ 267 s32 RxEVM[4]; 268 269 }; 270 271 struct odm_mac_status_info { 272 u8 test; 273 }; 274 275 /* */ 276 /* 2011/10/20 MH Define Common info enum for all team. */ 277 /* */ 278 enum odm_cmninfo_e { 279 /* Fixed value: */ 280 281 /* HOOK BEFORE REG INIT----------- */ 282 ODM_CMNINFO_PLATFORM = 0, 283 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 284 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 285 ODM_CMNINFO_MP_TEST_CHIP, 286 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 287 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 288 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 289 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 290 ODM_CMNINFO_RFE_TYPE, 291 ODM_CMNINFO_PACKAGE_TYPE, 292 ODM_CMNINFO_EXT_LNA, /* true */ 293 ODM_CMNINFO_EXT_PA, 294 ODM_CMNINFO_GPA, 295 ODM_CMNINFO_APA, 296 ODM_CMNINFO_GLNA, 297 ODM_CMNINFO_ALNA, 298 ODM_CMNINFO_EXT_TRSW, 299 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 300 ODM_CMNINFO_BINHCT_TEST, 301 ODM_CMNINFO_BWIFI_TEST, 302 ODM_CMNINFO_SMART_CONCURRENT, 303 /* HOOK BEFORE REG INIT----------- */ 304 305 /* Dynamic value: */ 306 /* POINTER REFERENCE----------- */ 307 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 308 ODM_CMNINFO_TX_UNI, 309 ODM_CMNINFO_RX_UNI, 310 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 311 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 312 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 313 ODM_CMNINFO_BW, /* ODM_BW_E */ 314 ODM_CMNINFO_CHNL, 315 ODM_CMNINFO_FORCED_RATE, 316 317 ODM_CMNINFO_DMSP_GET_VALUE, 318 ODM_CMNINFO_BUDDY_ADAPTOR, 319 ODM_CMNINFO_DMSP_IS_MASTER, 320 ODM_CMNINFO_SCAN, 321 ODM_CMNINFO_POWER_SAVING, 322 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 323 ODM_CMNINFO_DRV_STOP, 324 ODM_CMNINFO_PNP_IN, 325 ODM_CMNINFO_INIT_ON, 326 ODM_CMNINFO_ANT_TEST, 327 ODM_CMNINFO_NET_CLOSED, 328 ODM_CMNINFO_MP_MODE, 329 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 330 ODM_CMNINFO_FORCED_IGI_LB, 331 ODM_CMNINFO_IS1ANTENNA, 332 ODM_CMNINFO_RFDEFAULTPATH, 333 /* POINTER REFERENCE----------- */ 334 335 /* CALL BY VALUE------------- */ 336 ODM_CMNINFO_WIFI_DIRECT, 337 ODM_CMNINFO_WIFI_DISPLAY, 338 ODM_CMNINFO_LINK_IN_PROGRESS, 339 ODM_CMNINFO_LINK, 340 ODM_CMNINFO_STATION_STATE, 341 ODM_CMNINFO_RSSI_MIN, 342 ODM_CMNINFO_DBG_COMP, /* u64 */ 343 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 344 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 345 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 346 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 347 ODM_CMNINFO_BT_ENABLED, 348 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 349 ODM_CMNINFO_BT_HS_RSSI, 350 ODM_CMNINFO_BT_OPERATION, 351 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 352 ODM_CMNINFO_BT_DISABLE_EDCA, 353 /* CALL BY VALUE------------- */ 354 355 /* Dynamic ptr array hook itms. */ 356 ODM_CMNINFO_STA_STATUS, 357 ODM_CMNINFO_PHY_STATUS, 358 ODM_CMNINFO_MAC_STATUS, 359 360 ODM_CMNINFO_MAX, 361 }; 362 363 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 364 enum { /* _ODM_Support_Ability_Definition */ 365 /* */ 366 /* BB ODM section BIT 0-15 */ 367 /* */ 368 ODM_BB_DIG = BIT0, 369 ODM_BB_RA_MASK = BIT1, 370 ODM_BB_DYNAMIC_TXPWR = BIT2, 371 ODM_BB_FA_CNT = BIT3, 372 ODM_BB_RSSI_MONITOR = BIT4, 373 ODM_BB_CCK_PD = BIT5, 374 ODM_BB_ANT_DIV = BIT6, 375 ODM_BB_PWR_SAVE = BIT7, 376 ODM_BB_PWR_TRAIN = BIT8, 377 ODM_BB_RATE_ADAPTIVE = BIT9, 378 ODM_BB_PATH_DIV = BIT10, 379 ODM_BB_PSD = BIT11, 380 ODM_BB_RXHP = BIT12, 381 ODM_BB_ADAPTIVITY = BIT13, 382 ODM_BB_CFO_TRACKING = BIT14, 383 384 /* MAC DM section BIT 16-23 */ 385 ODM_MAC_EDCA_TURBO = BIT16, 386 ODM_MAC_EARLY_MODE = BIT17, 387 388 /* RF ODM section BIT 24-31 */ 389 ODM_RF_TX_PWR_TRACK = BIT24, 390 ODM_RF_RX_GAIN_TRACK = BIT25, 391 ODM_RF_CALIBRATION = BIT26, 392 }; 393 394 /* ODM_CMNINFO_INTERFACE */ 395 enum { /* tag_ODM_Support_Interface_Definition */ 396 ODM_ITRF_SDIO = 0x4, 397 ODM_ITRF_ALL = 0x7, 398 }; 399 400 /* ODM_CMNINFO_IC_TYPE */ 401 enum { /* tag_ODM_Support_IC_Type_Definition */ 402 ODM_RTL8723B = BIT8, 403 }; 404 405 /* ODM_CMNINFO_CUT_VER */ 406 enum { /* tag_ODM_Cut_Version_Definition */ 407 ODM_CUT_A = 0, 408 ODM_CUT_B = 1, 409 ODM_CUT_C = 2, 410 ODM_CUT_D = 3, 411 ODM_CUT_E = 4, 412 ODM_CUT_F = 5, 413 414 ODM_CUT_I = 8, 415 ODM_CUT_J = 9, 416 ODM_CUT_K = 10, 417 ODM_CUT_TEST = 15, 418 }; 419 420 /* ODM_CMNINFO_FAB_VER */ 421 enum { /* tag_ODM_Fab_Version_Definition */ 422 ODM_TSMC = 0, 423 ODM_UMC = 1, 424 }; 425 426 /* ODM_CMNINFO_RF_TYPE */ 427 /* */ 428 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 429 /* */ 430 enum { /* tag_ODM_RF_Type_Definition */ 431 ODM_1T1R = 0, 432 ODM_1T2R = 1, 433 ODM_2T2R = 2, 434 ODM_2T3R = 3, 435 ODM_2T4R = 4, 436 ODM_3T3R = 5, 437 ODM_3T4R = 6, 438 ODM_4T4R = 7, 439 }; 440 441 /* */ 442 /* ODM Dynamic common info value definition */ 443 /* */ 444 445 /* ODM_CMNINFO_WM_MODE */ 446 enum { /* tag_Wireless_Mode_Definition */ 447 ODM_WM_UNKNOWN = 0x0, 448 ODM_WM_B = BIT0, 449 ODM_WM_G = BIT1, 450 ODM_WM_N24G = BIT3, 451 ODM_WM_AUTO = BIT5, 452 }; 453 454 /* ODM_CMNINFO_BW */ 455 enum { /* tag_Bandwidth_Definition */ 456 ODM_BW20M = 0, 457 ODM_BW40M = 1, 458 }; 459 460 /* For AC-series IC, external PA & LNA can be individually added on 2.4G */ 461 462 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 463 TYPE_GPA0 = 0, 464 TYPE_GPA1 = BIT(1)|BIT(0) 465 }; 466 467 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 468 TYPE_APA0 = 0, 469 TYPE_APA1 = BIT(1)|BIT(0) 470 }; 471 472 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 473 TYPE_GLNA0 = 0, 474 TYPE_GLNA1 = BIT(2)|BIT(0), 475 TYPE_GLNA2 = BIT(3)|BIT(1), 476 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 477 }; 478 479 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 480 TYPE_ALNA0 = 0, 481 TYPE_ALNA1 = BIT(2)|BIT(0), 482 TYPE_ALNA2 = BIT(3)|BIT(1), 483 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 484 }; 485 486 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 487 bool bIQKDone; 488 s32 Value[3][IQK_Matrix_REG_NUM]; 489 bool bBWIqkResultSaved[3]; 490 }; 491 492 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 493 494 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 495 /* for tx power tracking */ 496 497 u32 RegA24; /* for TempCCK */ 498 s32 RegE94; 499 s32 RegE9C; 500 s32 RegEB4; 501 s32 RegEBC; 502 503 u8 TXPowercount; 504 bool bTXPowerTrackingInit; 505 bool bTXPowerTracking; 506 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 507 u8 TM_Trigger; 508 509 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 510 u8 ThermalValue; 511 u8 ThermalValue_LCK; 512 u8 ThermalValue_IQK; 513 u8 ThermalValue_DPK; 514 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 515 u8 ThermalValue_AVG_index; 516 u8 ThermalValue_RxGain; 517 u8 ThermalValue_Crystal; 518 u8 ThermalValue_DPKstore; 519 u8 ThermalValue_DPKtrack; 520 bool TxPowerTrackingInProgress; 521 522 bool bReloadtxpowerindex; 523 u8 bRfPiEnable; 524 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 525 526 /* Tx power Tracking ------------------------- */ 527 u8 bCCKinCH14; 528 u8 CCK_index; 529 u8 OFDM_index[MAX_RF_PATH]; 530 s8 PowerIndexOffset[MAX_RF_PATH]; 531 s8 DeltaPowerIndex[MAX_RF_PATH]; 532 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 533 bool bTxPowerChanged; 534 535 u8 ThermalValue_HP[HP_THERMAL_NUM]; 536 u8 ThermalValue_HP_index; 537 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 538 bool bNeedIQK; 539 bool bIQKInProgress; 540 u8 Delta_IQK; 541 u8 Delta_LCK; 542 s8 BBSwingDiff2G; /* Unit: dB */ 543 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 544 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 545 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 546 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 547 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 548 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 549 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 550 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 551 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 552 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 553 554 /* */ 555 556 /* for IQK */ 557 u32 RegC04; 558 u32 Reg874; 559 u32 RegC08; 560 u32 RegB68; 561 u32 RegB6C; 562 u32 Reg870; 563 u32 Reg860; 564 u32 Reg864; 565 566 bool bIQKInitialized; 567 bool bLCKInProgress; 568 bool bAntennaDetected; 569 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 570 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 571 u32 IQK_BB_backup_recover[9]; 572 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 573 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 574 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 575 576 /* for APK */ 577 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 578 u8 bAPKdone; 579 u8 bAPKThermalMeterIgnore; 580 581 /* DPK */ 582 bool bDPKFail; 583 u8 bDPdone; 584 u8 bDPPathAOK; 585 u8 bDPPathBOK; 586 587 u32 TxLOK[2]; 588 589 }; 590 /* */ 591 /* ODM Dynamic common info value definition */ 592 /* */ 593 594 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 595 u8 Bssid[6]; 596 u8 antsel_rx_keep_0; 597 u8 antsel_rx_keep_1; 598 u8 antsel_rx_keep_2; 599 u8 antsel_rx_keep_3; 600 u32 antSumRSSI[7]; 601 u32 antRSSIcnt[7]; 602 u32 antAveRSSI[7]; 603 u8 FAT_State; 604 u32 TrainIdx; 605 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 606 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 607 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 608 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 609 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 610 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 611 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 612 u8 RxIdleAnt; 613 bool bBecomeLinked; 614 u32 MinMaxRSSI; 615 u8 idx_AntDiv_counter_2G; 616 u32 CCK_counter_main; 617 u32 CCK_counter_aux; 618 u32 OFDM_counter_main; 619 u32 OFDM_counter_aux; 620 621 u32 CCK_CtrlFrame_Cnt_main; 622 u32 CCK_CtrlFrame_Cnt_aux; 623 u32 OFDM_CtrlFrame_Cnt_main; 624 u32 OFDM_CtrlFrame_Cnt_aux; 625 u32 MainAnt_CtrlFrame_Sum; 626 u32 AuxAnt_CtrlFrame_Sum; 627 u32 MainAnt_CtrlFrame_Cnt; 628 u32 AuxAnt_CtrlFrame_Cnt; 629 630 }; 631 632 enum { 633 NO_ANTDIV = 0xFF, 634 CG_TRX_HW_ANTDIV = 0x01, 635 CGCS_RX_HW_ANTDIV = 0x02, 636 FIXED_HW_ANTDIV = 0x03, 637 CG_TRX_SMART_ANTDIV = 0x04, 638 CGCS_RX_SW_ANTDIV = 0x05, 639 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 640 }; 641 642 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 643 u8 RespTxPath; 644 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 645 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 646 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 647 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 648 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 649 }; 650 651 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 652 PHY_REG_PG_RELATIVE_VALUE = 0, 653 PHY_REG_PG_EXACT_VALUE = 1 654 }; 655 656 /* */ 657 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 658 /* */ 659 struct ant_detected_info { 660 bool bAntDetected; 661 u32 dBForAntA; 662 u32 dBForAntB; 663 u32 dBForAntO; 664 }; 665 666 /* */ 667 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 668 /* */ 669 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 670 /* struct timer_list FastAntTrainingTimer; */ 671 /* */ 672 /* Add for different team use temporarily */ 673 /* */ 674 struct adapter *Adapter; /* For CE/NIC team */ 675 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 676 bool odm_ready; 677 678 enum phy_reg_pg_type PhyRegPgValueType; 679 u8 PhyRegPgVersion; 680 681 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 682 u32 LastNumQryPhyStatusAll; 683 u32 RxPWDBAve; 684 bool MPDIG_2G; /* off MPDIG */ 685 u8 Times_2G; 686 687 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 688 bool bCckHighPower; 689 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 690 u8 ControlChannel; 691 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 692 693 /* REMOVED COMMON INFO---------- */ 694 /* u8 PseudoMacPhyMode; */ 695 /* bool *BTCoexist; */ 696 /* bool PseudoBtCoexist; */ 697 /* u8 OPMode; */ 698 /* bool bAPMode; */ 699 /* bool bClientMode; */ 700 /* bool bAdHocMode; */ 701 /* bool bSlaveOfDMSP; */ 702 /* REMOVED COMMON INFO---------- */ 703 704 /* 1 COMMON INFORMATION */ 705 706 /* */ 707 /* Init Value */ 708 /* */ 709 /* HOOK BEFORE REG INIT----------- */ 710 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 711 u8 SupportPlatform; 712 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 713 u32 SupportAbility; 714 /* ODM PCIE/USB/SDIO = 1/2/3 */ 715 u8 SupportInterface; 716 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 717 u32 SupportICType; 718 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 719 u8 CutVersion; 720 /* Fab Version TSMC/UMC = 0/1 */ 721 u8 FabVersion; 722 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 723 u8 RFType; 724 u8 RFEType; 725 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 726 u8 BoardType; 727 u8 PackageType; 728 u8 TypeGLNA; 729 u8 TypeGPA; 730 u8 TypeALNA; 731 u8 TypeAPA; 732 /* with external LNA NO/Yes = 0/1 */ 733 u8 ExtLNA; 734 /* with external PA NO/Yes = 0/1 */ 735 u8 ExtPA; 736 /* with external TRSW NO/Yes = 0/1 */ 737 u8 ExtTRSW; 738 u8 PatchID; /* Customer ID */ 739 bool bInHctTest; 740 bool bWIFITest; 741 742 bool bDualMacSmartConcurrent; 743 u32 BK_SupportAbility; 744 u8 AntDivType; 745 /* HOOK BEFORE REG INIT----------- */ 746 747 /* */ 748 /* Dynamic Value */ 749 /* */ 750 /* POINTER REFERENCE----------- */ 751 752 u8 u8_temp; 753 bool bool_temp; 754 struct adapter *adapter_temp; 755 756 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 757 u8 *pMacPhyMode; 758 /* TX Unicast byte count */ 759 u64 *pNumTxBytesUnicast; 760 /* RX Unicast byte count */ 761 u64 *pNumRxBytesUnicast; 762 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 763 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 764 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 765 u8 *pSecChOffset; 766 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 767 u8 *pSecurity; 768 /* BW info 20M/40M/80M = 0/1/2 */ 769 u8 *pBandWidth; 770 /* Central channel location Ch1/Ch2/.... */ 771 u8 *pChannel; /* central channel number */ 772 bool DPK_Done; 773 /* Common info for 92D DMSP */ 774 775 bool *pbGetValueFromOtherMac; 776 struct adapter **pBuddyAdapter; 777 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 778 /* Common info for Status */ 779 bool *pbScanInProcess; 780 bool *pbPowerSaving; 781 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 782 u8 *pOnePathCCA; 783 /* pMgntInfo->AntennaTest */ 784 u8 *pAntennaTest; 785 bool *pbNet_closed; 786 u8 *mp_mode; 787 /* u8 *pAidMap; */ 788 u8 *pu1ForcedIgiLb; 789 /* For 8723B IQK----------- */ 790 bool *pIs1Antenna; 791 u8 *pRFDefaultPath; 792 /* 0:S1, 1:S0 */ 793 794 /* POINTER REFERENCE----------- */ 795 u16 *pForcedDataRate; 796 /* CALL BY VALUE------------- */ 797 bool bLinkInProcess; 798 bool bWIFI_Direct; 799 bool bWIFI_Display; 800 bool bLinked; 801 802 bool bsta_state; 803 u8 RSSI_Min; 804 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 805 bool bIsMPChip; 806 bool bOneEntryOnly; 807 /* Common info for BTDM */ 808 bool bBtEnabled; /* BT is disabled */ 809 bool bBtConnectProcess; /* BT HS is under connection progress. */ 810 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 811 bool bBtHsOperation; /* BT HS mode is under progress */ 812 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 813 bool bBtLimitedDig; /* BT is busy. */ 814 /* CALL BY VALUE------------- */ 815 u8 RSSI_A; 816 u8 RSSI_B; 817 u64 RSSI_TRSW; 818 u64 RSSI_TRSW_H; 819 u64 RSSI_TRSW_L; 820 u64 RSSI_TRSW_iso; 821 822 u8 RxRate; 823 bool bNoisyState; 824 u8 TxRate; 825 u8 LinkedInterval; 826 u8 preChannel; 827 u32 TxagcOffsetValueA; 828 bool IsTxagcOffsetPositiveA; 829 u32 TxagcOffsetValueB; 830 bool IsTxagcOffsetPositiveB; 831 u64 lastTxOkCnt; 832 u64 lastRxOkCnt; 833 u32 BbSwingOffsetA; 834 bool IsBbSwingOffsetPositiveA; 835 u32 BbSwingOffsetB; 836 bool IsBbSwingOffsetPositiveB; 837 s8 TH_L2H_ini; 838 s8 TH_EDCCA_HL_diff; 839 s8 IGI_Base; 840 u8 IGI_target; 841 bool ForceEDCCA; 842 u8 AdapEn_RSSI; 843 s8 Force_TH_H; 844 s8 Force_TH_L; 845 u8 IGI_LowerBound; 846 u8 antdiv_rssi; 847 u8 AntType; 848 u8 pre_AntType; 849 u8 antdiv_period; 850 u8 antdiv_select; 851 u8 NdpaPeriod; 852 bool H2C_RARpt_connect; 853 854 /* add by Yu Cehn for adaptivtiy */ 855 bool adaptivity_flag; 856 bool NHM_disable; 857 bool TxHangFlg; 858 bool Carrier_Sense_enable; 859 u8 tolerance_cnt; 860 u64 NHMCurTxOkcnt; 861 u64 NHMCurRxOkcnt; 862 u64 NHMLastTxOkcnt; 863 u64 NHMLastRxOkcnt; 864 u8 txEdcca1; 865 u8 txEdcca0; 866 s8 H2L_lb; 867 s8 L2H_lb; 868 u8 Adaptivity_IGI_upper; 869 u8 NHM_cnt_0; 870 871 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 872 /* */ 873 /* 2 Define STA info. */ 874 /* _ODM_STA_INFO */ 875 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 876 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 877 878 /* */ 879 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 880 /* We need to colelct all support abilit to a proper area. */ 881 /* */ 882 bool RaSupport88E; 883 884 /* Define ........... */ 885 886 /* Latest packet phy info (ODM write) */ 887 struct odm_phy_dbg_info PhyDbgInfo; 888 /* PHY_INFO_88E PhyInfo; */ 889 890 /* Latest packet phy info (ODM write) */ 891 struct odm_mac_status_info *pMacInfo; 892 /* MAC_INFO_88E MacInfo; */ 893 894 /* Different Team independt structure?? */ 895 896 /* */ 897 /* TX_RTP_CMN TX_retrpo; */ 898 /* TX_RTP_88E TX_retrpo; */ 899 /* TX_RTP_8195 TX_retrpo; */ 900 901 /* */ 902 /* ODM Structure */ 903 /* */ 904 struct fat_t DM_FatTable; 905 struct dig_t DM_DigTable; 906 struct ps_t DM_PSTable; 907 struct dynamic_primary_CCA DM_PriCCA; 908 struct rxhp_t dM_RXHP_Table; 909 struct ra_t DM_RA_Table; 910 struct false_ALARM_STATISTICS FalseAlmCnt; 911 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 912 struct swat_t DM_SWAT_Table; 913 bool RSSI_test; 914 struct cfo_tracking DM_CfoTrack; 915 916 struct edca_t DM_EDCA_Table; 917 u32 WMMEDCA_BE; 918 struct pathdiv_t DM_PathDiv; 919 /* Copy from SD4 structure */ 920 /* */ 921 /* ================================================== */ 922 /* */ 923 924 /* common */ 925 /* u8 DM_Type; */ 926 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 927 /* u8 PSD_func_flag; Add By Gary */ 928 /* for DIG */ 929 /* u8 bDMInitialGainEnable; */ 930 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 931 /* for Antenna diversity */ 932 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 933 /* PSTA_INFO_T RSSI_target; */ 934 935 bool *pbDriverStopped; 936 bool *pbDriverIsGoingToPnpSetPowerSleep; 937 bool *pinit_adpt_in_progress; 938 939 /* PSD */ 940 bool bUserAssignLevel; 941 struct timer_list PSDTimer; 942 u8 RSSI_BT; /* come from BT */ 943 bool bPSDinProcess; 944 bool bPSDactive; 945 bool bDMInitialGainEnable; 946 947 /* MPT DIG */ 948 struct timer_list MPT_DIGTimer; 949 950 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 951 u8 bUseRAMask; 952 953 struct odm_rate_adaptive RateAdaptive; 954 955 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 956 957 struct odm_rf_cal_t RFCalibrateInfo; 958 959 /* */ 960 /* TX power tracking */ 961 /* */ 962 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 963 u8 BbSwingIdxOfdmCurrent; 964 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 965 bool BbSwingFlagOfdm; 966 u8 BbSwingIdxCck; 967 u8 BbSwingIdxCckCurrent; 968 u8 BbSwingIdxCckBase; 969 u8 DefaultOfdmIndex; 970 u8 DefaultCckIndex; 971 bool BbSwingFlagCck; 972 973 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 974 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 975 s8 Remnant_CCKSwingIdx; 976 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 977 bool Modify_TxAGC_Flag_PathA; 978 bool Modify_TxAGC_Flag_PathB; 979 bool Modify_TxAGC_Flag_PathC; 980 bool Modify_TxAGC_Flag_PathD; 981 bool Modify_TxAGC_Flag_PathA_CCK; 982 983 s8 KfreeOffset[MAX_RF_PATH]; 984 /* */ 985 /* ODM system resource. */ 986 /* */ 987 988 /* ODM relative time. */ 989 struct timer_list PathDivSwitchTimer; 990 /* 2011.09.27 add for Path Diversity */ 991 struct timer_list CCKPathDiversityTimer; 992 struct timer_list FastAntTrainingTimer; 993 994 /* ODM relative workitem. */ 995 996 #if (BEAMFORMING_SUPPORT == 1) 997 RT_BEAMFORMING_INFO BeamformingInfo; 998 #endif 999 }; 1000 1001 #define ODM_RF_PATH_MAX 2 1002 1003 enum odm_rf_radio_path_e { 1004 ODM_RF_PATH_A = 0, /* Radio Path A */ 1005 ODM_RF_PATH_B = 1, /* Radio Path B */ 1006 ODM_RF_PATH_C = 2, /* Radio Path C */ 1007 ODM_RF_PATH_D = 3, /* Radio Path D */ 1008 ODM_RF_PATH_AB, 1009 ODM_RF_PATH_AC, 1010 ODM_RF_PATH_AD, 1011 ODM_RF_PATH_BC, 1012 ODM_RF_PATH_BD, 1013 ODM_RF_PATH_CD, 1014 ODM_RF_PATH_ABC, 1015 ODM_RF_PATH_ACD, 1016 ODM_RF_PATH_BCD, 1017 ODM_RF_PATH_ABCD, 1018 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1019 }; 1020 1021 enum odm_rf_content { 1022 odm_radioa_txt = 0x1000, 1023 odm_radiob_txt = 0x1001, 1024 odm_radioc_txt = 0x1002, 1025 odm_radiod_txt = 0x1003 1026 }; 1027 1028 enum ODM_BB_Config_Type { 1029 CONFIG_BB_PHY_REG, 1030 CONFIG_BB_AGC_TAB, 1031 CONFIG_BB_AGC_TAB_2G, 1032 CONFIG_BB_PHY_REG_PG, 1033 CONFIG_BB_PHY_REG_MP, 1034 CONFIG_BB_AGC_TAB_DIFF, 1035 }; 1036 1037 enum ODM_RF_Config_Type { 1038 CONFIG_RF_RADIO, 1039 CONFIG_RF_TXPWR_LMT, 1040 }; 1041 1042 enum ODM_FW_Config_Type { 1043 CONFIG_FW_NIC, 1044 CONFIG_FW_NIC_2, 1045 CONFIG_FW_AP, 1046 CONFIG_FW_WoWLAN, 1047 CONFIG_FW_WoWLAN_2, 1048 CONFIG_FW_AP_WoWLAN, 1049 CONFIG_FW_BT, 1050 }; 1051 1052 #ifdef REMOVE_PACK 1053 #pragma pack() 1054 #endif 1055 1056 /* include "odm_function.h" */ 1057 1058 /* 3 =========================================================== */ 1059 /* 3 DIG */ 1060 /* 3 =========================================================== */ 1061 1062 /* Remove DIG by Yuchen */ 1063 1064 /* 3 =========================================================== */ 1065 /* 3 AGC RX High Power Mode */ 1066 /* 3 =========================================================== */ 1067 #define LNA_Low_Gain_1 0x64 1068 #define LNA_Low_Gain_2 0x5A 1069 #define LNA_Low_Gain_3 0x58 1070 1071 #define FA_RXHP_TH1 5000 1072 #define FA_RXHP_TH2 1500 1073 #define FA_RXHP_TH3 800 1074 #define FA_RXHP_TH4 600 1075 #define FA_RXHP_TH5 500 1076 1077 /* 3 =========================================================== */ 1078 /* 3 EDCA */ 1079 /* 3 =========================================================== */ 1080 1081 /* 3 =========================================================== */ 1082 /* 3 Dynamic Tx Power */ 1083 /* 3 =========================================================== */ 1084 /* Dynamic Tx Power Control Threshold */ 1085 1086 /* 3 =========================================================== */ 1087 /* 3 Rate Adaptive */ 1088 /* 3 =========================================================== */ 1089 #define DM_RATR_STA_INIT 0 1090 #define DM_RATR_STA_HIGH 1 1091 #define DM_RATR_STA_MIDDLE 2 1092 #define DM_RATR_STA_LOW 3 1093 1094 /* 3 =========================================================== */ 1095 /* 3 BB Power Save */ 1096 /* 3 =========================================================== */ 1097 1098 enum { /* tag_1R_CCA_Type_Definition */ 1099 CCA_1R = 0, 1100 CCA_2R = 1, 1101 CCA_MAX = 2, 1102 }; 1103 1104 enum { /* tag_RF_Type_Definition */ 1105 RF_Save = 0, 1106 RF_Normal = 1, 1107 RF_MAX = 2, 1108 }; 1109 1110 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1111 #define MAX_ANTENNA_DETECTION_CNT 10 1112 1113 /* */ 1114 /* Extern Global Variables. */ 1115 /* */ 1116 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1117 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1118 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1119 1120 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1121 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1122 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1123 1124 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1125 1126 /* */ 1127 /* check Sta pointer valid or not */ 1128 /* */ 1129 #define IS_STA_VALID(pSta) (pSta) 1130 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1131 /* This indicates two different the steps. */ 1132 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1133 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1134 /* with original RSSI to determine if it is necessary to switch antenna. */ 1135 #define SWAW_STEP_PEAK 0 1136 #define SWAW_STEP_DETERMINE 1 1137 1138 /* Remove BB power saving by Yuchen */ 1139 1140 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1141 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1142 1143 bool ODM_RAStateCheck( 1144 struct dm_odm_t *pDM_Odm, 1145 s32 RSSI, 1146 bool bForceUpdate, 1147 u8 *pRATRState 1148 ); 1149 1150 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1151 void ODM_SwAntDivChkPerPktRssi( 1152 struct dm_odm_t *pDM_Odm, 1153 u8 StationID, 1154 struct odm_phy_info *pPhyInfo 1155 ); 1156 1157 u32 ODM_Get_Rate_Bitmap( 1158 struct dm_odm_t *pDM_Odm, 1159 u32 macid, 1160 u32 ra_mask, 1161 u8 rssi_level 1162 ); 1163 1164 #if (BEAMFORMING_SUPPORT == 1) 1165 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1166 #endif 1167 1168 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1169 1170 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1171 1172 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1173 1174 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1175 1176 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1177 1178 void ODM_CmnInfoPtrArrayHook( 1179 struct dm_odm_t *pDM_Odm, 1180 enum odm_cmninfo_e CmnInfo, 1181 u16 Index, 1182 void *pValue 1183 ); 1184 1185 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1186 1187 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1188 1189 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1190 1191 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1192 1193 void ODM_AntselStatistics_88C( 1194 struct dm_odm_t *pDM_Odm, 1195 u8 MacId, 1196 u32 PWDBAll, 1197 bool isCCKrate 1198 ); 1199 1200 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1201 1202 #endif 1203