1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_DynamicBBPowerSaving.h" 15 #include "odm_DynamicTxPower.h" 16 #include "odm_CfoTracking.h" 17 #include "odm_NoiseMonitor.h" 18 19 #define TP_MODE 0 20 #define RSSI_MODE 1 21 #define TRAFFIC_LOW 0 22 #define TRAFFIC_HIGH 1 23 #define NONE 0 24 25 /* 3 Tx Power Tracking */ 26 /* 3 ============================================================ */ 27 #define DPK_DELTA_MAPPING_NUM 13 28 #define index_mapping_HP_NUM 15 29 #define OFDM_TABLE_SIZE 43 30 #define CCK_TABLE_SIZE 33 31 #define TXSCALE_TABLE_SIZE 37 32 #define TXPWR_TRACK_TABLE_SIZE 30 33 #define DELTA_SWINGIDX_SIZE 30 34 #define BAND_NUM 4 35 36 /* 3 PSD Handler */ 37 /* 3 ============================================================ */ 38 39 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 40 #define MODE_40M 0 /* 0:20M, 1:40M */ 41 #define PSD_TH2 3 42 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 43 #define SIR_STEP_SIZE 3 44 #define Smooth_Size_1 5 45 #define Smooth_TH_1 3 46 #define Smooth_Size_2 10 47 #define Smooth_TH_2 4 48 #define Smooth_Size_3 20 49 #define Smooth_TH_3 4 50 #define Smooth_Step_Size 5 51 #define Adaptive_SIR 1 52 #define PSD_RESCAN 4 53 #define PSD_SCAN_INTERVAL 700 /* ms */ 54 55 /* 8723A High Power IGI Setting */ 56 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 57 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 58 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 59 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 60 61 /* ANT Test */ 62 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 63 #define ANTTESTA 0x01 /* Ant A will be Testing */ 64 #define ANTTESTB 0x02 /* Ant B will be testing */ 65 66 #define PS_MODE_ACTIVE 0x01 67 68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 69 #define MAIN_ANT 1 /* Ant A or Ant Main */ 70 #define AUX_ANT 2 /* AntB or Ant Aux */ 71 #define MAX_ANT 3 /* 3 for AP using */ 72 73 /* Antenna Diversity Type */ 74 #define SW_ANTDIV 0 75 #define HW_ANTDIV 1 76 /* structure and define */ 77 78 /* Remove DIG by Yuchen */ 79 80 /* Remoce BB power saving by Yuchn */ 81 82 /* Remove DIG by yuchen */ 83 84 struct dynamic_primary_CCA { 85 u8 PriCCA_flag; 86 u8 intf_flag; 87 u8 intf_type; 88 u8 DupRTS_flag; 89 u8 Monitor_flag; 90 u8 CH_offset; 91 u8 MF_state; 92 }; 93 94 struct ra_t { 95 u8 firstconnect; 96 }; 97 98 struct rxhp_t { 99 u8 RXHP_flag; 100 u8 PSD_func_trigger; 101 u8 PSD_bitmap_RXHP[80]; 102 u8 Pre_IGI; 103 u8 Cur_IGI; 104 u8 Pre_pw_th; 105 u8 Cur_pw_th; 106 bool First_time_enter; 107 bool RXHP_enable; 108 u8 TP_Mode; 109 struct timer_list PSDTimer; 110 }; 111 112 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 113 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 114 115 /* This indicates two different the steps. */ 116 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 117 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 118 /* with original RSSI to determine if it is necessary to switch antenna. */ 119 #define SWAW_STEP_PEAK 0 120 #define SWAW_STEP_DETERMINE 1 121 122 #define TP_MODE 0 123 #define RSSI_MODE 1 124 #define TRAFFIC_LOW 0 125 #define TRAFFIC_HIGH 1 126 #define TRAFFIC_UltraLOW 2 127 128 struct swat_t { /* _SW_Antenna_Switch_ */ 129 u8 Double_chk_flag; 130 u8 try_flag; 131 s32 PreRSSI; 132 u8 CurAntenna; 133 u8 PreAntenna; 134 u8 RSSI_Trying; 135 u8 TestMode; 136 u8 bTriggerAntennaSwitch; 137 u8 SelectAntennaMap; 138 u8 RSSI_target; 139 u8 reset_idx; 140 u16 Single_Ant_Counter; 141 u16 Dual_Ant_Counter; 142 u16 Aux_FailDetec_Counter; 143 u16 Retry_Counter; 144 145 /* Before link Antenna Switch check */ 146 u8 SWAS_NoLink_State; 147 u32 SWAS_NoLink_BK_Reg860; 148 u32 SWAS_NoLink_BK_Reg92c; 149 u32 SWAS_NoLink_BK_Reg948; 150 bool ANTA_ON; /* To indicate Ant A is or not */ 151 bool ANTB_ON; /* To indicate Ant B is on or not */ 152 bool Pre_Aux_FailDetec; 153 bool RSSI_AntDect_bResult; 154 u8 Ant2G; 155 156 s32 RSSI_sum_A; 157 s32 RSSI_sum_B; 158 s32 RSSI_cnt_A; 159 s32 RSSI_cnt_B; 160 161 u64 lastTxOkCnt; 162 u64 lastRxOkCnt; 163 u64 TXByteCnt_A; 164 u64 TXByteCnt_B; 165 u64 RXByteCnt_A; 166 u64 RXByteCnt_B; 167 u8 TrafficLoad; 168 u8 Train_time; 169 u8 Train_time_flag; 170 struct timer_list SwAntennaSwitchTimer; 171 struct timer_list SwAntennaSwitchTimer_8723B; 172 u32 PktCnt_SWAntDivByCtrlFrame; 173 bool bSWAntDivByCtrlFrame; 174 }; 175 176 /* Remove Edca by YuChen */ 177 178 179 struct odm_rate_adaptive { 180 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 181 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 182 bool bUseLdpc; 183 bool bLowerRtsRate; 184 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 185 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 186 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 187 188 }; 189 190 #define IQK_MAC_REG_NUM 4 191 #define IQK_ADDA_REG_NUM 16 192 #define IQK_BB_REG_NUM_MAX 10 193 #define IQK_BB_REG_NUM 9 194 #define HP_THERMAL_NUM 8 195 196 #define AVG_THERMAL_NUM 8 197 #define IQK_Matrix_REG_NUM 8 198 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 199 * + Channels_5G_20M_NUM 200 * + Channels_5G 201 */ 202 203 #define DM_Type_ByFW 0 204 #define DM_Type_ByDriver 1 205 206 /* */ 207 /* Declare for common info */ 208 /* */ 209 #define MAX_PATH_NUM_92CS 2 210 #define MAX_PATH_NUM_8188E 1 211 #define MAX_PATH_NUM_8192E 2 212 #define MAX_PATH_NUM_8723B 1 213 #define MAX_PATH_NUM_8812A 2 214 #define MAX_PATH_NUM_8821A 1 215 #define MAX_PATH_NUM_8814A 4 216 #define MAX_PATH_NUM_8822B 2 217 218 #define IQK_THRESHOLD 8 219 #define DPK_THRESHOLD 4 220 221 struct odm_phy_info { 222 /* 223 * Be care, if you want to add any element, please insert it between 224 * rx_pwd_ball and signal_strength. 225 */ 226 u8 rx_pwd_ba11; 227 228 u8 signal_quality; /* in 0-100 index. */ 229 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 230 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 231 232 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 233 234 u16 cfo_short[4]; /* per-path's Cfo_short */ 235 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 236 237 s8 rx_power; /* in dBm Translate from PWdB */ 238 239 /* 240 * Real power in dBm for this packet, no beautification and 241 * aggregation. Keep this raw info to be used for the other procedures. 242 */ 243 s8 recv_signal_power; 244 u8 bt_rx_rssi_percentage; 245 u8 signal_strength; /* in 0-100 index. */ 246 247 s8 rx_pwr[4]; /* per-path's pwdb */ 248 249 u8 rx_snr[4]; /* per-path's SNR */ 250 u8 band_width; 251 u8 bt_coex_pwr_adjust; 252 }; 253 254 struct odm_packet_info { 255 u8 data_rate; 256 u8 station_id; 257 bool bssid_match; 258 bool to_self; 259 bool is_beacon; 260 }; 261 262 struct odm_phy_dbg_info { 263 /* ODM Write, debug info */ 264 s8 RxSNRdB[4]; 265 u32 NumQryPhyStatus; 266 u32 NumQryPhyStatusCCK; 267 u32 NumQryPhyStatusOFDM; 268 u8 NumQryBeaconPkt; 269 /* Others */ 270 s32 RxEVM[4]; 271 272 }; 273 274 struct odm_mac_status_info { 275 u8 test; 276 }; 277 278 /* */ 279 /* 2011/10/20 MH Define Common info enum for all team. */ 280 /* */ 281 enum odm_cmninfo_e { 282 /* Fixed value: */ 283 284 /* HOOK BEFORE REG INIT----------- */ 285 ODM_CMNINFO_PLATFORM = 0, 286 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 287 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 288 ODM_CMNINFO_MP_TEST_CHIP, 289 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 290 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 291 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 292 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 293 ODM_CMNINFO_RFE_TYPE, 294 ODM_CMNINFO_PACKAGE_TYPE, 295 ODM_CMNINFO_EXT_LNA, /* true */ 296 ODM_CMNINFO_EXT_PA, 297 ODM_CMNINFO_GPA, 298 ODM_CMNINFO_APA, 299 ODM_CMNINFO_GLNA, 300 ODM_CMNINFO_ALNA, 301 ODM_CMNINFO_EXT_TRSW, 302 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 303 ODM_CMNINFO_BINHCT_TEST, 304 ODM_CMNINFO_BWIFI_TEST, 305 ODM_CMNINFO_SMART_CONCURRENT, 306 /* HOOK BEFORE REG INIT----------- */ 307 308 /* Dynamic value: */ 309 /* POINTER REFERENCE----------- */ 310 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 311 ODM_CMNINFO_TX_UNI, 312 ODM_CMNINFO_RX_UNI, 313 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 314 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 315 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 316 ODM_CMNINFO_BW, /* ODM_BW_E */ 317 ODM_CMNINFO_CHNL, 318 ODM_CMNINFO_FORCED_RATE, 319 320 ODM_CMNINFO_DMSP_GET_VALUE, 321 ODM_CMNINFO_BUDDY_ADAPTOR, 322 ODM_CMNINFO_DMSP_IS_MASTER, 323 ODM_CMNINFO_SCAN, 324 ODM_CMNINFO_POWER_SAVING, 325 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 326 ODM_CMNINFO_DRV_STOP, 327 ODM_CMNINFO_PNP_IN, 328 ODM_CMNINFO_INIT_ON, 329 ODM_CMNINFO_ANT_TEST, 330 ODM_CMNINFO_NET_CLOSED, 331 ODM_CMNINFO_MP_MODE, 332 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 333 ODM_CMNINFO_FORCED_IGI_LB, 334 ODM_CMNINFO_IS1ANTENNA, 335 ODM_CMNINFO_RFDEFAULTPATH, 336 /* POINTER REFERENCE----------- */ 337 338 /* CALL BY VALUE------------- */ 339 ODM_CMNINFO_WIFI_DIRECT, 340 ODM_CMNINFO_WIFI_DISPLAY, 341 ODM_CMNINFO_LINK_IN_PROGRESS, 342 ODM_CMNINFO_LINK, 343 ODM_CMNINFO_STATION_STATE, 344 ODM_CMNINFO_RSSI_MIN, 345 ODM_CMNINFO_DBG_COMP, /* u64 */ 346 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 347 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 348 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 349 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 350 ODM_CMNINFO_BT_ENABLED, 351 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 352 ODM_CMNINFO_BT_HS_RSSI, 353 ODM_CMNINFO_BT_OPERATION, 354 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 355 ODM_CMNINFO_BT_DISABLE_EDCA, 356 /* CALL BY VALUE------------- */ 357 358 /* Dynamic ptr array hook itms. */ 359 ODM_CMNINFO_STA_STATUS, 360 ODM_CMNINFO_PHY_STATUS, 361 ODM_CMNINFO_MAC_STATUS, 362 363 ODM_CMNINFO_MAX, 364 }; 365 366 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 367 enum { /* _ODM_Support_Ability_Definition */ 368 /* */ 369 /* BB ODM section BIT 0-15 */ 370 /* */ 371 ODM_BB_DIG = BIT0, 372 ODM_BB_RA_MASK = BIT1, 373 ODM_BB_DYNAMIC_TXPWR = BIT2, 374 ODM_BB_FA_CNT = BIT3, 375 ODM_BB_RSSI_MONITOR = BIT4, 376 ODM_BB_CCK_PD = BIT5, 377 ODM_BB_ANT_DIV = BIT6, 378 ODM_BB_PWR_SAVE = BIT7, 379 ODM_BB_PWR_TRAIN = BIT8, 380 ODM_BB_RATE_ADAPTIVE = BIT9, 381 ODM_BB_PATH_DIV = BIT10, 382 ODM_BB_PSD = BIT11, 383 ODM_BB_RXHP = BIT12, 384 ODM_BB_ADAPTIVITY = BIT13, 385 ODM_BB_CFO_TRACKING = BIT14, 386 387 /* MAC DM section BIT 16-23 */ 388 ODM_MAC_EDCA_TURBO = BIT16, 389 ODM_MAC_EARLY_MODE = BIT17, 390 391 /* RF ODM section BIT 24-31 */ 392 ODM_RF_TX_PWR_TRACK = BIT24, 393 ODM_RF_RX_GAIN_TRACK = BIT25, 394 ODM_RF_CALIBRATION = BIT26, 395 }; 396 397 /* ODM_CMNINFO_INTERFACE */ 398 enum { /* tag_ODM_Support_Interface_Definition */ 399 ODM_ITRF_SDIO = 0x4, 400 ODM_ITRF_ALL = 0x7, 401 }; 402 403 /* ODM_CMNINFO_IC_TYPE */ 404 enum { /* tag_ODM_Support_IC_Type_Definition */ 405 ODM_RTL8723B = BIT8, 406 }; 407 408 /* ODM_CMNINFO_CUT_VER */ 409 enum { /* tag_ODM_Cut_Version_Definition */ 410 ODM_CUT_A = 0, 411 ODM_CUT_B = 1, 412 ODM_CUT_C = 2, 413 ODM_CUT_D = 3, 414 ODM_CUT_E = 4, 415 ODM_CUT_F = 5, 416 417 ODM_CUT_I = 8, 418 ODM_CUT_J = 9, 419 ODM_CUT_K = 10, 420 ODM_CUT_TEST = 15, 421 }; 422 423 /* ODM_CMNINFO_FAB_VER */ 424 enum { /* tag_ODM_Fab_Version_Definition */ 425 ODM_TSMC = 0, 426 ODM_UMC = 1, 427 }; 428 429 /* ODM_CMNINFO_RF_TYPE */ 430 /* */ 431 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 432 /* */ 433 enum { /* tag_ODM_RF_Type_Definition */ 434 ODM_1T1R = 0, 435 ODM_1T2R = 1, 436 ODM_2T2R = 2, 437 ODM_2T3R = 3, 438 ODM_2T4R = 4, 439 ODM_3T3R = 5, 440 ODM_3T4R = 6, 441 ODM_4T4R = 7, 442 }; 443 444 /* */ 445 /* ODM Dynamic common info value definition */ 446 /* */ 447 448 /* ODM_CMNINFO_WM_MODE */ 449 enum { /* tag_Wireless_Mode_Definition */ 450 ODM_WM_UNKNOWN = 0x0, 451 ODM_WM_B = BIT0, 452 ODM_WM_G = BIT1, 453 ODM_WM_N24G = BIT3, 454 ODM_WM_AUTO = BIT5, 455 }; 456 457 /* ODM_CMNINFO_BW */ 458 enum { /* tag_Bandwidth_Definition */ 459 ODM_BW20M = 0, 460 ODM_BW40M = 1, 461 }; 462 463 /* For AC-series IC, external PA & LNA can be individually added on 2.4G */ 464 465 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 466 TYPE_GPA0 = 0, 467 TYPE_GPA1 = BIT(1)|BIT(0) 468 }; 469 470 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 471 TYPE_APA0 = 0, 472 TYPE_APA1 = BIT(1)|BIT(0) 473 }; 474 475 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 476 TYPE_GLNA0 = 0, 477 TYPE_GLNA1 = BIT(2)|BIT(0), 478 TYPE_GLNA2 = BIT(3)|BIT(1), 479 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 480 }; 481 482 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 483 TYPE_ALNA0 = 0, 484 TYPE_ALNA1 = BIT(2)|BIT(0), 485 TYPE_ALNA2 = BIT(3)|BIT(1), 486 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 487 }; 488 489 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 490 bool bIQKDone; 491 s32 Value[3][IQK_Matrix_REG_NUM]; 492 bool bBWIqkResultSaved[3]; 493 }; 494 495 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 496 497 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 498 /* for tx power tracking */ 499 500 u32 RegA24; /* for TempCCK */ 501 s32 RegE94; 502 s32 RegE9C; 503 s32 RegEB4; 504 s32 RegEBC; 505 506 u8 TXPowercount; 507 bool bTXPowerTrackingInit; 508 bool bTXPowerTracking; 509 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 510 u8 TM_Trigger; 511 512 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 513 u8 ThermalValue; 514 u8 ThermalValue_LCK; 515 u8 ThermalValue_IQK; 516 u8 ThermalValue_DPK; 517 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 518 u8 ThermalValue_AVG_index; 519 u8 ThermalValue_RxGain; 520 u8 ThermalValue_Crystal; 521 u8 ThermalValue_DPKstore; 522 u8 ThermalValue_DPKtrack; 523 bool TxPowerTrackingInProgress; 524 525 bool bReloadtxpowerindex; 526 u8 bRfPiEnable; 527 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 528 529 /* Tx power Tracking ------------------------- */ 530 u8 bCCKinCH14; 531 u8 CCK_index; 532 u8 OFDM_index[MAX_RF_PATH]; 533 s8 PowerIndexOffset[MAX_RF_PATH]; 534 s8 DeltaPowerIndex[MAX_RF_PATH]; 535 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 536 bool bTxPowerChanged; 537 538 u8 ThermalValue_HP[HP_THERMAL_NUM]; 539 u8 ThermalValue_HP_index; 540 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 541 bool bNeedIQK; 542 bool bIQKInProgress; 543 u8 Delta_IQK; 544 u8 Delta_LCK; 545 s8 BBSwingDiff2G; /* Unit: dB */ 546 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 547 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 548 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 549 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 550 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 551 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 552 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 553 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 554 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 555 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 556 557 /* */ 558 559 /* for IQK */ 560 u32 RegC04; 561 u32 Reg874; 562 u32 RegC08; 563 u32 RegB68; 564 u32 RegB6C; 565 u32 Reg870; 566 u32 Reg860; 567 u32 Reg864; 568 569 bool bIQKInitialized; 570 bool bLCKInProgress; 571 bool bAntennaDetected; 572 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 573 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 574 u32 IQK_BB_backup_recover[9]; 575 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 576 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 577 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 578 579 /* for APK */ 580 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 581 u8 bAPKdone; 582 u8 bAPKThermalMeterIgnore; 583 584 /* DPK */ 585 bool bDPKFail; 586 u8 bDPdone; 587 u8 bDPPathAOK; 588 u8 bDPPathBOK; 589 590 u32 TxLOK[2]; 591 592 }; 593 /* */ 594 /* ODM Dynamic common info value definition */ 595 /* */ 596 597 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 598 u8 Bssid[6]; 599 u8 antsel_rx_keep_0; 600 u8 antsel_rx_keep_1; 601 u8 antsel_rx_keep_2; 602 u8 antsel_rx_keep_3; 603 u32 antSumRSSI[7]; 604 u32 antRSSIcnt[7]; 605 u32 antAveRSSI[7]; 606 u8 FAT_State; 607 u32 TrainIdx; 608 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 609 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 610 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 611 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 612 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 613 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 614 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 615 u8 RxIdleAnt; 616 bool bBecomeLinked; 617 u32 MinMaxRSSI; 618 u8 idx_AntDiv_counter_2G; 619 u32 CCK_counter_main; 620 u32 CCK_counter_aux; 621 u32 OFDM_counter_main; 622 u32 OFDM_counter_aux; 623 624 u32 CCK_CtrlFrame_Cnt_main; 625 u32 CCK_CtrlFrame_Cnt_aux; 626 u32 OFDM_CtrlFrame_Cnt_main; 627 u32 OFDM_CtrlFrame_Cnt_aux; 628 u32 MainAnt_CtrlFrame_Sum; 629 u32 AuxAnt_CtrlFrame_Sum; 630 u32 MainAnt_CtrlFrame_Cnt; 631 u32 AuxAnt_CtrlFrame_Cnt; 632 633 }; 634 635 enum { 636 NO_ANTDIV = 0xFF, 637 CG_TRX_HW_ANTDIV = 0x01, 638 CGCS_RX_HW_ANTDIV = 0x02, 639 FIXED_HW_ANTDIV = 0x03, 640 CG_TRX_SMART_ANTDIV = 0x04, 641 CGCS_RX_SW_ANTDIV = 0x05, 642 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 643 }; 644 645 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 646 u8 RespTxPath; 647 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 648 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 649 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 650 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 651 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 652 }; 653 654 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 655 PHY_REG_PG_RELATIVE_VALUE = 0, 656 PHY_REG_PG_EXACT_VALUE = 1 657 }; 658 659 /* */ 660 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 661 /* */ 662 struct ant_detected_info { 663 bool bAntDetected; 664 u32 dBForAntA; 665 u32 dBForAntB; 666 u32 dBForAntO; 667 }; 668 669 /* */ 670 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 671 /* */ 672 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 673 /* struct timer_list FastAntTrainingTimer; */ 674 /* */ 675 /* Add for different team use temporarily */ 676 /* */ 677 struct adapter *Adapter; /* For CE/NIC team */ 678 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 679 bool odm_ready; 680 681 enum phy_reg_pg_type PhyRegPgValueType; 682 u8 PhyRegPgVersion; 683 684 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 685 u32 LastNumQryPhyStatusAll; 686 u32 RxPWDBAve; 687 bool MPDIG_2G; /* off MPDIG */ 688 u8 Times_2G; 689 690 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 691 bool bCckHighPower; 692 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 693 u8 ControlChannel; 694 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 695 696 /* REMOVED COMMON INFO---------- */ 697 /* u8 PseudoMacPhyMode; */ 698 /* bool *BTCoexist; */ 699 /* bool PseudoBtCoexist; */ 700 /* u8 OPMode; */ 701 /* bool bAPMode; */ 702 /* bool bClientMode; */ 703 /* bool bAdHocMode; */ 704 /* bool bSlaveOfDMSP; */ 705 /* REMOVED COMMON INFO---------- */ 706 707 /* 1 COMMON INFORMATION */ 708 709 /* */ 710 /* Init Value */ 711 /* */ 712 /* HOOK BEFORE REG INIT----------- */ 713 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 714 u8 SupportPlatform; 715 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 716 u32 SupportAbility; 717 /* ODM PCIE/USB/SDIO = 1/2/3 */ 718 u8 SupportInterface; 719 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 720 u32 SupportICType; 721 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 722 u8 CutVersion; 723 /* Fab Version TSMC/UMC = 0/1 */ 724 u8 FabVersion; 725 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 726 u8 RFType; 727 u8 RFEType; 728 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 729 u8 BoardType; 730 u8 PackageType; 731 u8 TypeGLNA; 732 u8 TypeGPA; 733 u8 TypeALNA; 734 u8 TypeAPA; 735 /* with external LNA NO/Yes = 0/1 */ 736 u8 ExtLNA; 737 /* with external PA NO/Yes = 0/1 */ 738 u8 ExtPA; 739 /* with external TRSW NO/Yes = 0/1 */ 740 u8 ExtTRSW; 741 u8 PatchID; /* Customer ID */ 742 bool bInHctTest; 743 bool bWIFITest; 744 745 bool bDualMacSmartConcurrent; 746 u32 BK_SupportAbility; 747 u8 AntDivType; 748 /* HOOK BEFORE REG INIT----------- */ 749 750 /* */ 751 /* Dynamic Value */ 752 /* */ 753 /* POINTER REFERENCE----------- */ 754 755 u8 u8_temp; 756 bool bool_temp; 757 struct adapter *adapter_temp; 758 759 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 760 u8 *pMacPhyMode; 761 /* TX Unicast byte count */ 762 u64 *pNumTxBytesUnicast; 763 /* RX Unicast byte count */ 764 u64 *pNumRxBytesUnicast; 765 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 766 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 767 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 768 u8 *pSecChOffset; 769 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 770 u8 *pSecurity; 771 /* BW info 20M/40M/80M = 0/1/2 */ 772 u8 *pBandWidth; 773 /* Central channel location Ch1/Ch2/.... */ 774 u8 *pChannel; /* central channel number */ 775 bool DPK_Done; 776 /* Common info for 92D DMSP */ 777 778 bool *pbGetValueFromOtherMac; 779 struct adapter **pBuddyAdapter; 780 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 781 /* Common info for Status */ 782 bool *pbScanInProcess; 783 bool *pbPowerSaving; 784 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 785 u8 *pOnePathCCA; 786 /* pMgntInfo->AntennaTest */ 787 u8 *pAntennaTest; 788 bool *pbNet_closed; 789 u8 *mp_mode; 790 /* u8 *pAidMap; */ 791 u8 *pu1ForcedIgiLb; 792 /* For 8723B IQK----------- */ 793 bool *pIs1Antenna; 794 u8 *pRFDefaultPath; 795 /* 0:S1, 1:S0 */ 796 797 /* POINTER REFERENCE----------- */ 798 u16 *pForcedDataRate; 799 /* CALL BY VALUE------------- */ 800 bool bLinkInProcess; 801 bool bWIFI_Direct; 802 bool bWIFI_Display; 803 bool bLinked; 804 805 bool bsta_state; 806 u8 RSSI_Min; 807 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 808 bool bIsMPChip; 809 bool bOneEntryOnly; 810 /* Common info for BTDM */ 811 bool bBtEnabled; /* BT is disabled */ 812 bool bBtConnectProcess; /* BT HS is under connection progress. */ 813 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 814 bool bBtHsOperation; /* BT HS mode is under progress */ 815 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 816 bool bBtLimitedDig; /* BT is busy. */ 817 /* CALL BY VALUE------------- */ 818 u8 RSSI_A; 819 u8 RSSI_B; 820 u64 RSSI_TRSW; 821 u64 RSSI_TRSW_H; 822 u64 RSSI_TRSW_L; 823 u64 RSSI_TRSW_iso; 824 825 u8 RxRate; 826 bool bNoisyState; 827 u8 TxRate; 828 u8 LinkedInterval; 829 u8 preChannel; 830 u32 TxagcOffsetValueA; 831 bool IsTxagcOffsetPositiveA; 832 u32 TxagcOffsetValueB; 833 bool IsTxagcOffsetPositiveB; 834 u64 lastTxOkCnt; 835 u64 lastRxOkCnt; 836 u32 BbSwingOffsetA; 837 bool IsBbSwingOffsetPositiveA; 838 u32 BbSwingOffsetB; 839 bool IsBbSwingOffsetPositiveB; 840 s8 TH_L2H_ini; 841 s8 TH_EDCCA_HL_diff; 842 s8 IGI_Base; 843 u8 IGI_target; 844 bool ForceEDCCA; 845 u8 AdapEn_RSSI; 846 s8 Force_TH_H; 847 s8 Force_TH_L; 848 u8 IGI_LowerBound; 849 u8 antdiv_rssi; 850 u8 AntType; 851 u8 pre_AntType; 852 u8 antdiv_period; 853 u8 antdiv_select; 854 u8 NdpaPeriod; 855 bool H2C_RARpt_connect; 856 857 /* add by Yu Cehn for adaptivtiy */ 858 bool adaptivity_flag; 859 bool NHM_disable; 860 bool TxHangFlg; 861 bool Carrier_Sense_enable; 862 u8 tolerance_cnt; 863 u64 NHMCurTxOkcnt; 864 u64 NHMCurRxOkcnt; 865 u64 NHMLastTxOkcnt; 866 u64 NHMLastRxOkcnt; 867 u8 txEdcca1; 868 u8 txEdcca0; 869 s8 H2L_lb; 870 s8 L2H_lb; 871 u8 Adaptivity_IGI_upper; 872 u8 NHM_cnt_0; 873 874 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 875 /* */ 876 /* 2 Define STA info. */ 877 /* _ODM_STA_INFO */ 878 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 879 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 880 881 /* */ 882 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 883 /* We need to colelct all support abilit to a proper area. */ 884 /* */ 885 bool RaSupport88E; 886 887 /* Define ........... */ 888 889 /* Latest packet phy info (ODM write) */ 890 struct odm_phy_dbg_info PhyDbgInfo; 891 /* PHY_INFO_88E PhyInfo; */ 892 893 /* Latest packet phy info (ODM write) */ 894 struct odm_mac_status_info *pMacInfo; 895 /* MAC_INFO_88E MacInfo; */ 896 897 /* Different Team independt structure?? */ 898 899 /* */ 900 /* TX_RTP_CMN TX_retrpo; */ 901 /* TX_RTP_88E TX_retrpo; */ 902 /* TX_RTP_8195 TX_retrpo; */ 903 904 /* */ 905 /* ODM Structure */ 906 /* */ 907 struct fat_t DM_FatTable; 908 struct dig_t DM_DigTable; 909 struct ps_t DM_PSTable; 910 struct dynamic_primary_CCA DM_PriCCA; 911 struct rxhp_t dM_RXHP_Table; 912 struct ra_t DM_RA_Table; 913 struct false_ALARM_STATISTICS FalseAlmCnt; 914 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 915 struct swat_t DM_SWAT_Table; 916 bool RSSI_test; 917 struct cfo_tracking DM_CfoTrack; 918 919 struct edca_t DM_EDCA_Table; 920 u32 WMMEDCA_BE; 921 struct pathdiv_t DM_PathDiv; 922 /* Copy from SD4 structure */ 923 /* */ 924 /* ================================================== */ 925 /* */ 926 927 /* common */ 928 /* u8 DM_Type; */ 929 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 930 /* u8 PSD_func_flag; Add By Gary */ 931 /* for DIG */ 932 /* u8 bDMInitialGainEnable; */ 933 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 934 /* for Antenna diversity */ 935 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 936 /* PSTA_INFO_T RSSI_target; */ 937 938 bool *pbDriverStopped; 939 bool *pbDriverIsGoingToPnpSetPowerSleep; 940 bool *pinit_adpt_in_progress; 941 942 /* PSD */ 943 bool bUserAssignLevel; 944 struct timer_list PSDTimer; 945 u8 RSSI_BT; /* come from BT */ 946 bool bPSDinProcess; 947 bool bPSDactive; 948 bool bDMInitialGainEnable; 949 950 /* MPT DIG */ 951 struct timer_list MPT_DIGTimer; 952 953 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 954 u8 bUseRAMask; 955 956 struct odm_rate_adaptive RateAdaptive; 957 958 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 959 960 struct odm_rf_cal_t RFCalibrateInfo; 961 962 /* */ 963 /* TX power tracking */ 964 /* */ 965 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 966 u8 BbSwingIdxOfdmCurrent; 967 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 968 bool BbSwingFlagOfdm; 969 u8 BbSwingIdxCck; 970 u8 BbSwingIdxCckCurrent; 971 u8 BbSwingIdxCckBase; 972 u8 DefaultOfdmIndex; 973 u8 DefaultCckIndex; 974 bool BbSwingFlagCck; 975 976 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 977 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 978 s8 Remnant_CCKSwingIdx; 979 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 980 bool Modify_TxAGC_Flag_PathA; 981 bool Modify_TxAGC_Flag_PathB; 982 bool Modify_TxAGC_Flag_PathC; 983 bool Modify_TxAGC_Flag_PathD; 984 bool Modify_TxAGC_Flag_PathA_CCK; 985 986 s8 KfreeOffset[MAX_RF_PATH]; 987 /* */ 988 /* ODM system resource. */ 989 /* */ 990 991 /* ODM relative time. */ 992 struct timer_list PathDivSwitchTimer; 993 /* 2011.09.27 add for Path Diversity */ 994 struct timer_list CCKPathDiversityTimer; 995 struct timer_list FastAntTrainingTimer; 996 997 /* ODM relative workitem. */ 998 999 #if (BEAMFORMING_SUPPORT == 1) 1000 RT_BEAMFORMING_INFO BeamformingInfo; 1001 #endif 1002 }; 1003 1004 #define ODM_RF_PATH_MAX 2 1005 1006 enum odm_rf_radio_path_e { 1007 ODM_RF_PATH_A = 0, /* Radio Path A */ 1008 ODM_RF_PATH_B = 1, /* Radio Path B */ 1009 ODM_RF_PATH_C = 2, /* Radio Path C */ 1010 ODM_RF_PATH_D = 3, /* Radio Path D */ 1011 ODM_RF_PATH_AB, 1012 ODM_RF_PATH_AC, 1013 ODM_RF_PATH_AD, 1014 ODM_RF_PATH_BC, 1015 ODM_RF_PATH_BD, 1016 ODM_RF_PATH_CD, 1017 ODM_RF_PATH_ABC, 1018 ODM_RF_PATH_ACD, 1019 ODM_RF_PATH_BCD, 1020 ODM_RF_PATH_ABCD, 1021 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1022 }; 1023 1024 enum odm_rf_content { 1025 odm_radioa_txt = 0x1000, 1026 odm_radiob_txt = 0x1001, 1027 odm_radioc_txt = 0x1002, 1028 odm_radiod_txt = 0x1003 1029 }; 1030 1031 enum ODM_BB_Config_Type { 1032 CONFIG_BB_PHY_REG, 1033 CONFIG_BB_AGC_TAB, 1034 CONFIG_BB_AGC_TAB_2G, 1035 CONFIG_BB_PHY_REG_PG, 1036 CONFIG_BB_PHY_REG_MP, 1037 CONFIG_BB_AGC_TAB_DIFF, 1038 }; 1039 1040 enum ODM_RF_Config_Type { 1041 CONFIG_RF_RADIO, 1042 CONFIG_RF_TXPWR_LMT, 1043 }; 1044 1045 enum ODM_FW_Config_Type { 1046 CONFIG_FW_NIC, 1047 CONFIG_FW_NIC_2, 1048 CONFIG_FW_AP, 1049 CONFIG_FW_WoWLAN, 1050 CONFIG_FW_WoWLAN_2, 1051 CONFIG_FW_AP_WoWLAN, 1052 CONFIG_FW_BT, 1053 }; 1054 1055 #ifdef REMOVE_PACK 1056 #pragma pack() 1057 #endif 1058 1059 /* include "odm_function.h" */ 1060 1061 /* 3 =========================================================== */ 1062 /* 3 DIG */ 1063 /* 3 =========================================================== */ 1064 1065 /* Remove DIG by Yuchen */ 1066 1067 /* 3 =========================================================== */ 1068 /* 3 AGC RX High Power Mode */ 1069 /* 3 =========================================================== */ 1070 #define LNA_Low_Gain_1 0x64 1071 #define LNA_Low_Gain_2 0x5A 1072 #define LNA_Low_Gain_3 0x58 1073 1074 #define FA_RXHP_TH1 5000 1075 #define FA_RXHP_TH2 1500 1076 #define FA_RXHP_TH3 800 1077 #define FA_RXHP_TH4 600 1078 #define FA_RXHP_TH5 500 1079 1080 /* 3 =========================================================== */ 1081 /* 3 EDCA */ 1082 /* 3 =========================================================== */ 1083 1084 /* 3 =========================================================== */ 1085 /* 3 Dynamic Tx Power */ 1086 /* 3 =========================================================== */ 1087 /* Dynamic Tx Power Control Threshold */ 1088 1089 /* 3 =========================================================== */ 1090 /* 3 Rate Adaptive */ 1091 /* 3 =========================================================== */ 1092 #define DM_RATR_STA_INIT 0 1093 #define DM_RATR_STA_HIGH 1 1094 #define DM_RATR_STA_MIDDLE 2 1095 #define DM_RATR_STA_LOW 3 1096 1097 /* 3 =========================================================== */ 1098 /* 3 BB Power Save */ 1099 /* 3 =========================================================== */ 1100 1101 enum { /* tag_1R_CCA_Type_Definition */ 1102 CCA_1R = 0, 1103 CCA_2R = 1, 1104 CCA_MAX = 2, 1105 }; 1106 1107 enum { /* tag_RF_Type_Definition */ 1108 RF_Save = 0, 1109 RF_Normal = 1, 1110 RF_MAX = 2, 1111 }; 1112 1113 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1114 #define MAX_ANTENNA_DETECTION_CNT 10 1115 1116 /* */ 1117 /* Extern Global Variables. */ 1118 /* */ 1119 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1120 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1121 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1122 1123 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1124 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1125 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1126 1127 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1128 1129 /* */ 1130 /* check Sta pointer valid or not */ 1131 /* */ 1132 #define IS_STA_VALID(pSta) (pSta) 1133 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1134 /* This indicates two different the steps. */ 1135 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1136 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1137 /* with original RSSI to determine if it is necessary to switch antenna. */ 1138 #define SWAW_STEP_PEAK 0 1139 #define SWAW_STEP_DETERMINE 1 1140 1141 /* Remove BB power saving by Yuchen */ 1142 1143 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1144 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1145 1146 bool ODM_RAStateCheck( 1147 struct dm_odm_t *pDM_Odm, 1148 s32 RSSI, 1149 bool bForceUpdate, 1150 u8 *pRATRState 1151 ); 1152 1153 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1154 void ODM_SwAntDivChkPerPktRssi( 1155 struct dm_odm_t *pDM_Odm, 1156 u8 StationID, 1157 struct odm_phy_info *pPhyInfo 1158 ); 1159 1160 u32 ODM_Get_Rate_Bitmap( 1161 struct dm_odm_t *pDM_Odm, 1162 u32 macid, 1163 u32 ra_mask, 1164 u8 rssi_level 1165 ); 1166 1167 #if (BEAMFORMING_SUPPORT == 1) 1168 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1169 #endif 1170 1171 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1172 1173 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1174 1175 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1176 1177 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1178 1179 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1180 1181 void ODM_CmnInfoPtrArrayHook( 1182 struct dm_odm_t *pDM_Odm, 1183 enum odm_cmninfo_e CmnInfo, 1184 u16 Index, 1185 void *pValue 1186 ); 1187 1188 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1189 1190 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1191 1192 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1193 1194 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1195 1196 void ODM_AntselStatistics_88C( 1197 struct dm_odm_t *pDM_Odm, 1198 u8 MacId, 1199 u32 PWDBAll, 1200 bool isCCKrate 1201 ); 1202 1203 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1204 1205 #endif 1206