1 /******************************************************************************
2  *
3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12  * more details.
13  *
14  ******************************************************************************/
15 
16 
17 #ifndef	__HALDMOUTSRC_H__
18 #define __HALDMOUTSRC_H__
19 
20 
21 #include "odm_EdcaTurboCheck.h"
22 #include "odm_DIG.h"
23 #include "odm_PathDiv.h"
24 #include "odm_DynamicBBPowerSaving.h"
25 #include "odm_DynamicTxPower.h"
26 #include "odm_CfoTracking.h"
27 #include "odm_NoiseMonitor.h"
28 
29 #define	TP_MODE		0
30 #define	RSSI_MODE		1
31 #define	TRAFFIC_LOW	0
32 #define	TRAFFIC_HIGH	1
33 #define	NONE			0
34 
35 
36 /* 3 Tx Power Tracking */
37 /* 3 ============================================================ */
38 #define		DPK_DELTA_MAPPING_NUM	13
39 #define		index_mapping_HP_NUM	15
40 #define	OFDM_TABLE_SIZE		43
41 #define	CCK_TABLE_SIZE			33
42 #define TXSCALE_TABLE_SIZE		37
43 #define TXPWR_TRACK_TABLE_SIZE	30
44 #define DELTA_SWINGIDX_SIZE     30
45 #define BAND_NUM				4
46 
47 /* 3 PSD Handler */
48 /* 3 ============================================================ */
49 
50 #define	AFH_PSD		1	/* 0:normal PSD scan, 1: only do 20 pts PSD */
51 #define	MODE_40M		0	/* 0:20M, 1:40M */
52 #define	PSD_TH2		3
53 #define	PSD_CHMIN		20   /*  Minimum channel number for BT AFH */
54 #define	SIR_STEP_SIZE	3
55 #define   Smooth_Size_1		5
56 #define	Smooth_TH_1	3
57 #define   Smooth_Size_2		10
58 #define	Smooth_TH_2	4
59 #define   Smooth_Size_3		20
60 #define	Smooth_TH_3	4
61 #define   Smooth_Step_Size 5
62 #define	Adaptive_SIR	1
63 #define	PSD_RESCAN		4
64 #define	PSD_SCAN_INTERVAL	700 /* ms */
65 
66 /* 8723A High Power IGI Setting */
67 #define		DM_DIG_HIGH_PWR_IGI_LOWER_BOUND	0x22
68 #define			DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
69 #define		DM_DIG_HIGH_PWR_THRESHOLD	0x3a
70 #define		DM_DIG_LOW_PWR_THRESHOLD	0x14
71 
72 /* ANT Test */
73 #define			ANTTESTALL		0x00		/* Ant A or B will be Testing */
74 #define		ANTTESTA		0x01		/* Ant A will be Testing */
75 #define		ANTTESTB		0x02		/* Ant B will be testing */
76 
77 #define	PS_MODE_ACTIVE 0x01
78 
79 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
80 #define		MAIN_ANT		1		/* Ant A or Ant Main */
81 #define		AUX_ANT		2		/* AntB or Ant Aux */
82 #define		MAX_ANT		3		/*  3 for AP using */
83 
84 
85 /* Antenna Diversity Type */
86 #define	SW_ANTDIV	0
87 #define	HW_ANTDIV	1
88 /*  structure and define */
89 
90 /* Remove DIG by Yuchen */
91 
92 /* Remoce BB power saving by Yuchn */
93 
94 /* Remove DIG by yuchen */
95 
96 typedef struct _Dynamic_Primary_CCA {
97 	u8 PriCCA_flag;
98 	u8 intf_flag;
99 	u8 intf_type;
100 	u8 DupRTS_flag;
101 	u8 Monitor_flag;
102 	u8 CH_offset;
103 	u8 	MF_state;
104 } Pri_CCA_T, *pPri_CCA_T;
105 
106 typedef struct _Rate_Adaptive_Table_ {
107 	u8 firstconnect;
108 } RA_T, *pRA_T;
109 
110 typedef struct _RX_High_Power_ {
111 	u8 RXHP_flag;
112 	u8 PSD_func_trigger;
113 	u8 PSD_bitmap_RXHP[80];
114 	u8 Pre_IGI;
115 	u8 Cur_IGI;
116 	u8 Pre_pw_th;
117 	u8 Cur_pw_th;
118 	bool First_time_enter;
119 	bool RXHP_enable;
120 	u8 TP_Mode;
121 	RT_TIMER PSDTimer;
122 } RXHP_T, *pRXHP_T;
123 
124 #define ASSOCIATE_ENTRY_NUM					32 /*  Max size of AsocEntry[]. */
125 #define	ODM_ASSOCIATE_ENTRY_NUM				ASSOCIATE_ENTRY_NUM
126 
127 /*  This indicates two different the steps. */
128 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
129 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
130 /*  with original RSSI to determine if it is necessary to switch antenna. */
131 #define SWAW_STEP_PEAK		0
132 #define SWAW_STEP_DETERMINE	1
133 
134 #define	TP_MODE		0
135 #define	RSSI_MODE		1
136 #define	TRAFFIC_LOW	0
137 #define	TRAFFIC_HIGH	1
138 #define	TRAFFIC_UltraLOW	2
139 
140 typedef struct _SW_Antenna_Switch_ {
141 	u8 Double_chk_flag;
142 	u8 try_flag;
143 	s32 PreRSSI;
144 	u8 CurAntenna;
145 	u8 PreAntenna;
146 	u8 RSSI_Trying;
147 	u8 TestMode;
148 	u8 bTriggerAntennaSwitch;
149 	u8 SelectAntennaMap;
150 	u8 RSSI_target;
151 	u8 reset_idx;
152 	u16 Single_Ant_Counter;
153 	u16 Dual_Ant_Counter;
154 	u16 Aux_FailDetec_Counter;
155 	u16 Retry_Counter;
156 
157 	/*  Before link Antenna Switch check */
158 	u8 SWAS_NoLink_State;
159 	u32 SWAS_NoLink_BK_Reg860;
160 	u32 SWAS_NoLink_BK_Reg92c;
161 	u32 SWAS_NoLink_BK_Reg948;
162 	bool ANTA_ON;	/* To indicate Ant A is or not */
163 	bool ANTB_ON;	/* To indicate Ant B is on or not */
164 	bool Pre_Aux_FailDetec;
165 	bool RSSI_AntDect_bResult;
166 	u8 Ant5G;
167 	u8 Ant2G;
168 
169 	s32 RSSI_sum_A;
170 	s32 RSSI_sum_B;
171 	s32 RSSI_cnt_A;
172 	s32 RSSI_cnt_B;
173 
174 	u64 lastTxOkCnt;
175 	u64 lastRxOkCnt;
176 	u64 TXByteCnt_A;
177 	u64 TXByteCnt_B;
178 	u64 RXByteCnt_A;
179 	u64 RXByteCnt_B;
180 	u8 TrafficLoad;
181 	u8 Train_time;
182 	u8 Train_time_flag;
183 	RT_TIMER SwAntennaSwitchTimer;
184 	RT_TIMER SwAntennaSwitchTimer_8723B;
185 	u32 PktCnt_SWAntDivByCtrlFrame;
186 	bool bSWAntDivByCtrlFrame;
187 } SWAT_T, *pSWAT_T;
188 
189 /* Remove Edca by YuChen */
190 
191 
192 typedef struct _ODM_RATE_ADAPTIVE {
193 	u8 Type;				/*  DM_Type_ByFW/DM_Type_ByDriver */
194 	u8 LdpcThres;			/*  if RSSI > LdpcThres => switch from LPDC to BCC */
195 	bool bUseLdpc;
196 	bool bLowerRtsRate;
197 	u8 HighRSSIThresh;		/*  if RSSI > HighRSSIThresh	=> RATRState is DM_RATR_STA_HIGH */
198 	u8 LowRSSIThresh;		/*  if RSSI <= LowRSSIThresh	=> RATRState is DM_RATR_STA_LOW */
199 	u8 RATRState;			/*  Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
200 
201 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
202 
203 
204 #define IQK_MAC_REG_NUM		4
205 #define IQK_ADDA_REG_NUM		16
206 #define IQK_BB_REG_NUM_MAX	10
207 #define IQK_BB_REG_NUM		9
208 #define HP_THERMAL_NUM		8
209 
210 #define AVG_THERMAL_NUM		8
211 #define IQK_Matrix_REG_NUM	8
212 #define IQK_Matrix_Settings_NUM	(14 + 24 + 21) /*   Channels_2_4G_NUM
213 						* + Channels_5G_20M_NUM
214 						* + Channels_5G
215 						*/
216 
217 #define		DM_Type_ByFW			0
218 #define		DM_Type_ByDriver		1
219 
220 /*  */
221 /*  Declare for common info */
222 /*  */
223 #define MAX_PATH_NUM_92CS		2
224 #define MAX_PATH_NUM_8188E		1
225 #define MAX_PATH_NUM_8192E		2
226 #define MAX_PATH_NUM_8723B		1
227 #define MAX_PATH_NUM_8812A		2
228 #define MAX_PATH_NUM_8821A		1
229 #define MAX_PATH_NUM_8814A		4
230 #define MAX_PATH_NUM_8822B		2
231 
232 
233 #define IQK_THRESHOLD			8
234 #define DPK_THRESHOLD			4
235 
236 typedef struct _ODM_Phy_Status_Info_ {
237 	/*  */
238 	/*  Be care, if you want to add any element please insert between */
239 	/*  RxPWDBAll & SignalStrength. */
240 	/*  */
241 	u8 RxPWDBAll;
242 
243 	u8 SignalQuality;			/*  in 0-100 index. */
244 	s8 RxMIMOSignalQuality[4];	/* per-path's EVM */
245 	u8 RxMIMOEVMdbm[4];		/* per-path's EVM dbm */
246 
247 	u8 RxMIMOSignalStrength[4];/*  in 0~100 index */
248 
249 	u16 Cfo_short[4];			/*  per-path's Cfo_short */
250 	u16 Cfo_tail[4];			/*  per-path's Cfo_tail */
251 
252 	s8 RxPower;				/*  in dBm Translate from PWdB */
253 	s8 RecvSignalPower;		/*  Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
254 	u8 BTRxRSSIPercentage;
255 	u8 SignalStrength;			/*  in 0-100 index. */
256 
257 	s8 RxPwr[4];				/* per-path's pwdb */
258 
259 	u8 RxSNR[4];				/* per-path's SNR */
260 	u8 BandWidth;
261 	u8 btCoexPwrAdjust;
262 } ODM_PHY_INFO_T, *PODM_PHY_INFO_T;
263 
264 
265 struct odm_packet_info {
266 	u8 data_rate;
267 	u8 station_id;
268 	bool bssid_match;
269 	bool to_self;
270 	bool is_beacon;
271 };
272 
273 
274 typedef struct _ODM_Phy_Dbg_Info_ {
275 	/* ODM Write, debug info */
276 	s8 RxSNRdB[4];
277 	u32 NumQryPhyStatus;
278 	u32 NumQryPhyStatusCCK;
279 	u32 NumQryPhyStatusOFDM;
280 	u8 NumQryBeaconPkt;
281 	/* Others */
282 	s32 RxEVM[4];
283 
284 } ODM_PHY_DBG_INFO_T;
285 
286 
287 typedef struct _ODM_Mac_Status_Info_ {
288 	u8 test;
289 } ODM_MAC_INFO;
290 
291 
292 typedef enum tag_Dynamic_ODM_Support_Ability_Type {
293 	/*  BB Team */
294 	ODM_DIG				= 0x00000001,
295 	ODM_HIGH_POWER		= 0x00000002,
296 	ODM_CCK_CCA_TH		= 0x00000004,
297 	ODM_FA_STATISTICS	= 0x00000008,
298 	ODM_RAMASK			= 0x00000010,
299 	ODM_RSSI_MONITOR	= 0x00000020,
300 	ODM_SW_ANTDIV		= 0x00000040,
301 	ODM_HW_ANTDIV		= 0x00000080,
302 	ODM_BB_PWRSV		= 0x00000100,
303 	ODM_2TPATHDIV		= 0x00000200,
304 	ODM_1TPATHDIV		= 0x00000400,
305 	ODM_PSD2AFH			= 0x00000800
306 } ODM_Ability_E;
307 
308 /*  */
309 /*  2011/20/20 MH For MP driver RT_WLAN_STA =  STA_INFO_T */
310 /*  Please declare below ODM relative info in your STA info structure. */
311 /*  */
312 typedef struct _ODM_STA_INFO {
313 	/*  Driver Write */
314 	bool bUsed;				/*  record the sta status link or not? */
315 	/* u8 WirelessMode;		 */
316 	u8 IOTPeer;			/*  Enum value.	HT_IOT_PEER_E */
317 
318 	/*  ODM Write */
319 	/* 1 PHY_STATUS_INFO */
320 	u8 RSSI_Path[4];		/*  */
321 	u8 RSSI_Ave;
322 	u8 RXEVM[4];
323 	u8 RXSNR[4];
324 
325 	/*  ODM Write */
326 	/* 1 TX_INFO (may changed by IC) */
327 	/* TX_INFO_T		pTxInfo;		Define in IC folder. Move lower layer. */
328 
329 	/*  */
330 	/* 	Please use compile flag to disabe the strcutrue for other IC except 88E. */
331 	/* 	Move To lower layer. */
332 	/*  */
333 	/*  ODM Write Wilson will handle this part(said by Luke.Lee) */
334 	/* TX_RPT_T		pTxRpt;			Define in IC folder. Move lower layer. */
335 } ODM_STA_INFO_T, *PODM_STA_INFO_T;
336 
337 /*  */
338 /*  2011/10/20 MH Define Common info enum for all team. */
339 /*  */
340 typedef enum _ODM_Common_Info_Definition {
341 	/*  Fixed value: */
342 
343 	/* HOOK BEFORE REG INIT----------- */
344 	ODM_CMNINFO_PLATFORM = 0,
345 	ODM_CMNINFO_ABILITY,					/*  ODM_ABILITY_E */
346 	ODM_CMNINFO_INTERFACE,				/*  ODM_INTERFACE_E */
347 	ODM_CMNINFO_MP_TEST_CHIP,
348 	ODM_CMNINFO_IC_TYPE,					/*  ODM_IC_TYPE_E */
349 	ODM_CMNINFO_CUT_VER,					/*  ODM_CUT_VERSION_E */
350 	ODM_CMNINFO_FAB_VER,					/*  ODM_FAB_E */
351 	ODM_CMNINFO_RF_TYPE,					/*  ODM_RF_PATH_E or ODM_RF_TYPE_E? */
352 	ODM_CMNINFO_RFE_TYPE,
353 	ODM_CMNINFO_BOARD_TYPE,				/*  ODM_BOARD_TYPE_E */
354 	ODM_CMNINFO_PACKAGE_TYPE,
355 	ODM_CMNINFO_EXT_LNA,					/*  true */
356 	ODM_CMNINFO_5G_EXT_LNA,
357 	ODM_CMNINFO_EXT_PA,
358 	ODM_CMNINFO_5G_EXT_PA,
359 	ODM_CMNINFO_GPA,
360 	ODM_CMNINFO_APA,
361 	ODM_CMNINFO_GLNA,
362 	ODM_CMNINFO_ALNA,
363 	ODM_CMNINFO_EXT_TRSW,
364 	ODM_CMNINFO_PATCH_ID,				/* CUSTOMER ID */
365 	ODM_CMNINFO_BINHCT_TEST,
366 	ODM_CMNINFO_BWIFI_TEST,
367 	ODM_CMNINFO_SMART_CONCURRENT,
368 	/* HOOK BEFORE REG INIT----------- */
369 
370 
371 	/*  Dynamic value: */
372 /*  POINTER REFERENCE----------- */
373 	ODM_CMNINFO_MAC_PHY_MODE,	/*  ODM_MAC_PHY_MODE_E */
374 	ODM_CMNINFO_TX_UNI,
375 	ODM_CMNINFO_RX_UNI,
376 	ODM_CMNINFO_WM_MODE,		/*  ODM_WIRELESS_MODE_E */
377 	ODM_CMNINFO_BAND,		/*  ODM_BAND_TYPE_E */
378 	ODM_CMNINFO_SEC_CHNL_OFFSET,	/*  ODM_SEC_CHNL_OFFSET_E */
379 	ODM_CMNINFO_SEC_MODE,		/*  ODM_SECURITY_E */
380 	ODM_CMNINFO_BW,			/*  ODM_BW_E */
381 	ODM_CMNINFO_CHNL,
382 	ODM_CMNINFO_FORCED_RATE,
383 
384 	ODM_CMNINFO_DMSP_GET_VALUE,
385 	ODM_CMNINFO_BUDDY_ADAPTOR,
386 	ODM_CMNINFO_DMSP_IS_MASTER,
387 	ODM_CMNINFO_SCAN,
388 	ODM_CMNINFO_POWER_SAVING,
389 	ODM_CMNINFO_ONE_PATH_CCA,	/*  ODM_CCA_PATH_E */
390 	ODM_CMNINFO_DRV_STOP,
391 	ODM_CMNINFO_PNP_IN,
392 	ODM_CMNINFO_INIT_ON,
393 	ODM_CMNINFO_ANT_TEST,
394 	ODM_CMNINFO_NET_CLOSED,
395 	ODM_CMNINFO_MP_MODE,
396 	/* ODM_CMNINFO_RTSTA_AID,	 For win driver only? */
397 	ODM_CMNINFO_FORCED_IGI_LB,
398 	ODM_CMNINFO_IS1ANTENNA,
399 	ODM_CMNINFO_RFDEFAULTPATH,
400 /*  POINTER REFERENCE----------- */
401 
402 /* CALL BY VALUE------------- */
403 	ODM_CMNINFO_WIFI_DIRECT,
404 	ODM_CMNINFO_WIFI_DISPLAY,
405 	ODM_CMNINFO_LINK_IN_PROGRESS,
406 	ODM_CMNINFO_LINK,
407 	ODM_CMNINFO_STATION_STATE,
408 	ODM_CMNINFO_RSSI_MIN,
409 	ODM_CMNINFO_DBG_COMP,			/*  u64 */
410 	ODM_CMNINFO_DBG_LEVEL,			/*  u32 */
411 	ODM_CMNINFO_RA_THRESHOLD_HIGH,		/*  u8 */
412 	ODM_CMNINFO_RA_THRESHOLD_LOW,		/*  u8 */
413 	ODM_CMNINFO_RF_ANTENNA_TYPE,		/*  u8 */
414 	ODM_CMNINFO_BT_ENABLED,
415 	ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
416 	ODM_CMNINFO_BT_HS_RSSI,
417 	ODM_CMNINFO_BT_OPERATION,
418 	ODM_CMNINFO_BT_LIMITED_DIG,		/* Need to Limited Dig or not */
419 	ODM_CMNINFO_BT_DISABLE_EDCA,
420 /* CALL BY VALUE------------- */
421 
422 	/*  Dynamic ptr array hook itms. */
423 	ODM_CMNINFO_STA_STATUS,
424 	ODM_CMNINFO_PHY_STATUS,
425 	ODM_CMNINFO_MAC_STATUS,
426 
427 	ODM_CMNINFO_MAX,
428 
429 
430 } ODM_CMNINFO_E;
431 
432 /*  2011/10/20 MH Define ODM support ability.  ODM_CMNINFO_ABILITY */
433 typedef enum _ODM_Support_Ability_Definition {
434 	/*  */
435 	/*  BB ODM section BIT 0-15 */
436 	/*  */
437 	ODM_BB_DIG			= BIT0,
438 	ODM_BB_RA_MASK			= BIT1,
439 	ODM_BB_DYNAMIC_TXPWR		= BIT2,
440 	ODM_BB_FA_CNT			= BIT3,
441 	ODM_BB_RSSI_MONITOR		= BIT4,
442 	ODM_BB_CCK_PD			= BIT5,
443 	ODM_BB_ANT_DIV			= BIT6,
444 	ODM_BB_PWR_SAVE			= BIT7,
445 	ODM_BB_PWR_TRAIN		= BIT8,
446 	ODM_BB_RATE_ADAPTIVE		= BIT9,
447 	ODM_BB_PATH_DIV			= BIT10,
448 	ODM_BB_PSD			= BIT11,
449 	ODM_BB_RXHP			= BIT12,
450 	ODM_BB_ADAPTIVITY		= BIT13,
451 	ODM_BB_CFO_TRACKING		= BIT14,
452 
453 	/*  MAC DM section BIT 16-23 */
454 	ODM_MAC_EDCA_TURBO		= BIT16,
455 	ODM_MAC_EARLY_MODE		= BIT17,
456 
457 	/*  RF ODM section BIT 24-31 */
458 	ODM_RF_TX_PWR_TRACK		= BIT24,
459 	ODM_RF_RX_GAIN_TRACK	= BIT25,
460 	ODM_RF_CALIBRATION		= BIT26,
461 } ODM_ABILITY_E;
462 
463 /* 	ODM_CMNINFO_INTERFACE */
464 typedef enum tag_ODM_Support_Interface_Definition {
465 	ODM_ITRF_SDIO	=	0x4,
466 	ODM_ITRF_ALL	=	0x7,
467 } ODM_INTERFACE_E;
468 
469 /*  ODM_CMNINFO_IC_TYPE */
470 typedef enum tag_ODM_Support_IC_Type_Definition {
471 	ODM_RTL8723B	=	BIT8,
472 } ODM_IC_TYPE_E;
473 
474 /* ODM_CMNINFO_CUT_VER */
475 typedef enum tag_ODM_Cut_Version_Definition {
476 	ODM_CUT_A		=	0,
477 	ODM_CUT_B		=	1,
478 	ODM_CUT_C		=	2,
479 	ODM_CUT_D		=	3,
480 	ODM_CUT_E		=	4,
481 	ODM_CUT_F		=	5,
482 
483 	ODM_CUT_I		=	8,
484 	ODM_CUT_J		=	9,
485 	ODM_CUT_K		=	10,
486 	ODM_CUT_TEST	=	15,
487 } ODM_CUT_VERSION_E;
488 
489 /*  ODM_CMNINFO_FAB_VER */
490 typedef enum tag_ODM_Fab_Version_Definition {
491 	ODM_TSMC	=	0,
492 	ODM_UMC		=	1,
493 } ODM_FAB_E;
494 
495 /*  ODM_CMNINFO_RF_TYPE */
496 /*  */
497 /*  For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
498 /*  */
499 typedef enum tag_ODM_RF_Path_Bit_Definition {
500 	ODM_RF_TX_A	=	BIT0,
501 	ODM_RF_TX_B	=	BIT1,
502 	ODM_RF_TX_C	=	BIT2,
503 	ODM_RF_TX_D	=	BIT3,
504 	ODM_RF_RX_A	=	BIT4,
505 	ODM_RF_RX_B	=	BIT5,
506 	ODM_RF_RX_C	=	BIT6,
507 	ODM_RF_RX_D	=	BIT7,
508 } ODM_RF_PATH_E;
509 
510 
511 typedef enum tag_ODM_RF_Type_Definition {
512 	ODM_1T1R	=	0,
513 	ODM_1T2R	=	1,
514 	ODM_2T2R	=	2,
515 	ODM_2T3R	=	3,
516 	ODM_2T4R	=	4,
517 	ODM_3T3R	=	5,
518 	ODM_3T4R	=	6,
519 	ODM_4T4R	=	7,
520 } ODM_RF_TYPE_E;
521 
522 
523 /*  */
524 /*  ODM Dynamic common info value definition */
525 /*  */
526 
527 /* typedef enum _MACPHY_MODE_8192D{ */
528 /* 	SINGLEMAC_SINGLEPHY, */
529 /* 	DUALMAC_DUALPHY, */
530 /* 	DUALMAC_SINGLEPHY, */
531 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */
532 /*  Above is the original define in MP driver. Please use the same define. THX. */
533 typedef enum tag_ODM_MAC_PHY_Mode_Definition {
534 	ODM_SMSP	= 0,
535 	ODM_DMSP	= 1,
536 	ODM_DMDP	= 2,
537 } ODM_MAC_PHY_MODE_E;
538 
539 
540 typedef enum tag_BT_Coexist_Definition {
541 	ODM_BT_BUSY		= 1,
542 	ODM_BT_ON		= 2,
543 	ODM_BT_OFF		= 3,
544 	ODM_BT_NONE		= 4,
545 } ODM_BT_COEXIST_E;
546 
547 /*  ODM_CMNINFO_OP_MODE */
548 typedef enum tag_Operation_Mode_Definition {
549 	ODM_NO_LINK      = BIT0,
550 	ODM_LINK         = BIT1,
551 	ODM_SCAN         = BIT2,
552 	ODM_POWERSAVE    = BIT3,
553 	ODM_AP_MODE      = BIT4,
554 	ODM_CLIENT_MODE  = BIT5,
555 	ODM_AD_HOC       = BIT6,
556 	ODM_WIFI_DIRECT  = BIT7,
557 	ODM_WIFI_DISPLAY = BIT8,
558 } ODM_OPERATION_MODE_E;
559 
560 /*  ODM_CMNINFO_WM_MODE */
561 typedef enum tag_Wireless_Mode_Definition {
562 	ODM_WM_UNKNOW     = 0x0,
563 	ODM_WM_B          = BIT0,
564 	ODM_WM_G          = BIT1,
565 	ODM_WM_A          = BIT2,
566 	ODM_WM_N24G       = BIT3,
567 	ODM_WM_N5G        = BIT4,
568 	ODM_WM_AUTO       = BIT5,
569 	ODM_WM_AC         = BIT6,
570 } ODM_WIRELESS_MODE_E;
571 
572 /*  ODM_CMNINFO_BAND */
573 typedef enum tag_Band_Type_Definition {
574 	ODM_BAND_2_4G = 0,
575 	ODM_BAND_5G,
576 	ODM_BAND_ON_BOTH,
577 	ODM_BANDMAX
578 } ODM_BAND_TYPE_E;
579 
580 /*  ODM_CMNINFO_SEC_CHNL_OFFSET */
581 typedef enum tag_Secondary_Channel_Offset_Definition {
582 	ODM_DONT_CARE	= 0,
583 	ODM_BELOW		= 1,
584 	ODM_ABOVE		= 2
585 } ODM_SEC_CHNL_OFFSET_E;
586 
587 /*  ODM_CMNINFO_SEC_MODE */
588 typedef enum tag_Security_Definition {
589 	ODM_SEC_OPEN		= 0,
590 	ODM_SEC_WEP40		= 1,
591 	ODM_SEC_TKIP		= 2,
592 	ODM_SEC_RESERVE		= 3,
593 	ODM_SEC_AESCCMP		= 4,
594 	ODM_SEC_WEP104		= 5,
595 	ODM_WEP_WPA_MIXED	= 6, /*  WEP + WPA */
596 	ODM_SEC_SMS4		= 7,
597 } ODM_SECURITY_E;
598 
599 /*  ODM_CMNINFO_BW */
600 typedef enum tag_Bandwidth_Definition {
601 	ODM_BW20M		= 0,
602 	ODM_BW40M		= 1,
603 	ODM_BW80M		= 2,
604 	ODM_BW160M		= 3,
605 	ODM_BW10M		= 4,
606 } ODM_BW_E;
607 
608 
609 /*  ODM_CMNINFO_BOARD_TYPE */
610 /*  For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */
611 /*  For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */
612 typedef enum tag_Board_Definition {
613 	ODM_BOARD_DEFAULT    = 0,      /*  The DEFAULT case. */
614 	ODM_BOARD_MINICARD   = BIT(0), /*  0 = non-mini card, 1 = mini card. */
615 	ODM_BOARD_SLIM       = BIT(1), /*  0 = non-slim card, 1 = slim card */
616 	ODM_BOARD_BT         = BIT(2), /*  0 = without BT card, 1 = with BT */
617 	ODM_BOARD_EXT_PA     = BIT(3), /*  0 = no 2G ext-PA, 1 = existing 2G ext-PA */
618 	ODM_BOARD_EXT_LNA    = BIT(4), /*  0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
619 	ODM_BOARD_EXT_TRSW   = BIT(5), /*  0 = no ext-TRSW, 1 = existing ext-TRSW */
620 	ODM_BOARD_EXT_PA_5G  = BIT(6), /*  0 = no 5G ext-PA, 1 = existing 5G ext-PA */
621 	ODM_BOARD_EXT_LNA_5G = BIT(7), /*  0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
622 } ODM_BOARD_TYPE_E;
623 
624 typedef enum tag_ODM_Package_Definition {
625 	ODM_PACKAGE_DEFAULT      = 0,
626 	ODM_PACKAGE_QFN68        = BIT(0),
627 	ODM_PACKAGE_TFBGA90      = BIT(1),
628 	ODM_PACKAGE_TFBGA79      = BIT(2),
629 } ODM_Package_TYPE_E;
630 
631 typedef enum tag_ODM_TYPE_GPA_Definition {
632 	TYPE_GPA0 = 0,
633 	TYPE_GPA1 = BIT(1)|BIT(0)
634 } ODM_TYPE_GPA_E;
635 
636 typedef enum tag_ODM_TYPE_APA_Definition {
637 	TYPE_APA0 = 0,
638 	TYPE_APA1 = BIT(1)|BIT(0)
639 } ODM_TYPE_APA_E;
640 
641 typedef enum tag_ODM_TYPE_GLNA_Definition {
642 	TYPE_GLNA0 = 0,
643 	TYPE_GLNA1 = BIT(2)|BIT(0),
644 	TYPE_GLNA2 = BIT(3)|BIT(1),
645 	TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
646 } ODM_TYPE_GLNA_E;
647 
648 typedef enum tag_ODM_TYPE_ALNA_Definition {
649 	TYPE_ALNA0 = 0,
650 	TYPE_ALNA1 = BIT(2)|BIT(0),
651 	TYPE_ALNA2 = BIT(3)|BIT(1),
652 	TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
653 } ODM_TYPE_ALNA_E;
654 
655 /*  ODM_CMNINFO_ONE_PATH_CCA */
656 typedef enum tag_CCA_Path {
657 	ODM_CCA_2R			= 0,
658 	ODM_CCA_1R_A		= 1,
659 	ODM_CCA_1R_B		= 2,
660 } ODM_CCA_PATH_E;
661 
662 
663 typedef struct _ODM_RA_Info_ {
664 	u8 RateID;
665 	u32 RateMask;
666 	u32 RAUseRate;
667 	u8 RateSGI;
668 	u8 RssiStaRA;
669 	u8 PreRssiStaRA;
670 	u8 SGIEnable;
671 	u8 DecisionRate;
672 	u8 PreRate;
673 	u8 HighestRate;
674 	u8 LowestRate;
675 	u32 NscUp;
676 	u32 NscDown;
677 	u16 RTY[5];
678 	u32 TOTAL;
679 	u16 DROP;
680 	u8 Active;
681 	u16 RptTime;
682 	u8 RAWaitingCounter;
683 	u8 RAPendingCounter;
684 	u8 PTActive;  /*  on or off */
685 	u8 PTTryState;  /*  0 trying state, 1 for decision state */
686 	u8 PTStage;  /*  0~6 */
687 	u8 PTStopCount; /* Stop PT counter */
688 	u8 PTPreRate;  /*  if rate change do PT */
689 	u8 PTPreRssi; /*  if RSSI change 5% do PT */
690 	u8 PTModeSS;  /*  decide whitch rate should do PT */
691 	u8 RAstage;  /*  StageRA, decide how many times RA will be done between PT */
692 	u8 PTSmoothFactor;
693 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
694 
695 typedef struct _IQK_MATRIX_REGS_SETTING {
696 	bool bIQKDone;
697 	s32 Value[3][IQK_Matrix_REG_NUM];
698 	bool bBWIqkResultSaved[3];
699 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING;
700 
701 
702 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
703 
704 typedef struct ODM_RF_Calibration_Structure {
705 	/* for tx power tracking */
706 
707 	u32 RegA24; /*  for TempCCK */
708 	s32 RegE94;
709 	s32 RegE9C;
710 	s32 RegEB4;
711 	s32 RegEBC;
712 
713 	u8 TXPowercount;
714 	bool bTXPowerTrackingInit;
715 	bool bTXPowerTracking;
716 	u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
717 	u8 TM_Trigger;
718 	u8 InternalPA5G[2];	/* pathA / pathB */
719 
720 	u8 ThermalMeter[2];    /*  ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
721 	u8 ThermalValue;
722 	u8 ThermalValue_LCK;
723 	u8 ThermalValue_IQK;
724 	u8 ThermalValue_DPK;
725 	u8 ThermalValue_AVG[AVG_THERMAL_NUM];
726 	u8 ThermalValue_AVG_index;
727 	u8 ThermalValue_RxGain;
728 	u8 ThermalValue_Crystal;
729 	u8 ThermalValue_DPKstore;
730 	u8 ThermalValue_DPKtrack;
731 	bool TxPowerTrackingInProgress;
732 
733 	bool bReloadtxpowerindex;
734 	u8 bRfPiEnable;
735 	u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
736 
737 
738 	/*  Tx power Tracking ------------------------- */
739 	u8 bCCKinCH14;
740 	u8 CCK_index;
741 	u8 OFDM_index[MAX_RF_PATH];
742 	s8 PowerIndexOffset[MAX_RF_PATH];
743 	s8 DeltaPowerIndex[MAX_RF_PATH];
744 	s8 DeltaPowerIndexLast[MAX_RF_PATH];
745 	bool bTxPowerChanged;
746 
747 	u8 ThermalValue_HP[HP_THERMAL_NUM];
748 	u8 ThermalValue_HP_index;
749 	IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
750 	bool bNeedIQK;
751 	bool bIQKInProgress;
752 	u8 Delta_IQK;
753 	u8 Delta_LCK;
754 	s8 BBSwingDiff2G, BBSwingDiff5G; /*  Unit: dB */
755 	u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
756 	u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
757 	u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
758 	u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
759 	u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
760 	u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
761 	u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
762 	u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
763 	u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
764 	u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
765 	u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
766 	u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
767 	u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
768 	u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
769 
770 	/*  */
771 
772 	/* for IQK */
773 	u32 RegC04;
774 	u32 Reg874;
775 	u32 RegC08;
776 	u32 RegB68;
777 	u32 RegB6C;
778 	u32 Reg870;
779 	u32 Reg860;
780 	u32 Reg864;
781 
782 	bool bIQKInitialized;
783 	bool bLCKInProgress;
784 	bool bAntennaDetected;
785 	u32 ADDA_backup[IQK_ADDA_REG_NUM];
786 	u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
787 	u32 IQK_BB_backup_recover[9];
788 	u32 IQK_BB_backup[IQK_BB_REG_NUM];
789 	u32 TxIQC_8723B[2][3][2]; /*  { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
790 	u32 RxIQC_8723B[2][2][2]; /*  { {S1: 0xc14, 0xca0} ,           {S0: 0xc14, 0xca0}} */
791 
792 
793 	/* for APK */
794 	u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
795 	u8 bAPKdone;
796 	u8 bAPKThermalMeterIgnore;
797 
798 	/*  DPK */
799 	bool bDPKFail;
800 	u8 bDPdone;
801 	u8 bDPPathAOK;
802 	u8 bDPPathBOK;
803 
804 	u32 TxLOK[2];
805 
806 } ODM_RF_CAL_T, *PODM_RF_CAL_T;
807 /*  */
808 /*  ODM Dynamic common info value definition */
809 /*  */
810 
811 typedef struct _FAST_ANTENNA_TRAINNING_ {
812 	u8 Bssid[6];
813 	u8 antsel_rx_keep_0;
814 	u8 antsel_rx_keep_1;
815 	u8 antsel_rx_keep_2;
816 	u8 antsel_rx_keep_3;
817 	u32 antSumRSSI[7];
818 	u32 antRSSIcnt[7];
819 	u32 antAveRSSI[7];
820 	u8 FAT_State;
821 	u32 TrainIdx;
822 	u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
823 	u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
824 	u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
825 	u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
826 	u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
827 	u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
828 	u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
829 	u8 RxIdleAnt;
830 	bool	bBecomeLinked;
831 	u32 MinMaxRSSI;
832 	u8 idx_AntDiv_counter_2G;
833 	u8 idx_AntDiv_counter_5G;
834 	u32 AntDiv_2G_5G;
835 	u32 CCK_counter_main;
836 	u32 CCK_counter_aux;
837 	u32 OFDM_counter_main;
838 	u32 OFDM_counter_aux;
839 
840 
841 	u32 CCK_CtrlFrame_Cnt_main;
842 	u32 CCK_CtrlFrame_Cnt_aux;
843 	u32 OFDM_CtrlFrame_Cnt_main;
844 	u32 OFDM_CtrlFrame_Cnt_aux;
845 	u32 MainAnt_CtrlFrame_Sum;
846 	u32 AuxAnt_CtrlFrame_Sum;
847 	u32 MainAnt_CtrlFrame_Cnt;
848 	u32 AuxAnt_CtrlFrame_Cnt;
849 
850 } FAT_T, *pFAT_T;
851 
852 typedef enum _FAT_STATE {
853 	FAT_NORMAL_STATE			= 0,
854 	FAT_TRAINING_STATE		= 1,
855 } FAT_STATE_E, *PFAT_STATE_E;
856 
857 typedef enum _ANT_DIV_TYPE {
858 	NO_ANTDIV			= 0xFF,
859 	CG_TRX_HW_ANTDIV		= 0x01,
860 	CGCS_RX_HW_ANTDIV	= 0x02,
861 	FIXED_HW_ANTDIV		= 0x03,
862 	CG_TRX_SMART_ANTDIV	= 0x04,
863 	CGCS_RX_SW_ANTDIV	= 0x05,
864 	S0S1_SW_ANTDIV          = 0x06 /* 8723B intrnal switch S0 S1 */
865 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
866 
867 typedef struct _ODM_PATH_DIVERSITY_ {
868 	u8 RespTxPath;
869 	u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
870 	u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
871 	u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
872 	u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
873 	u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
874 } PATHDIV_T, *pPATHDIV_T;
875 
876 
877 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
878 	PHY_REG_PG_RELATIVE_VALUE = 0,
879 	PHY_REG_PG_EXACT_VALUE = 1
880 } PHY_REG_PG_TYPE;
881 
882 
883 /*  */
884 /*  Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
885 /*  */
886 typedef struct _ANT_DETECTED_INFO {
887 	bool bAntDetected;
888 	u32 dBForAntA;
889 	u32 dBForAntB;
890 	u32 dBForAntO;
891 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
892 
893 /*  */
894 /*  2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
895 /*  */
896 typedef  struct DM_Out_Source_Dynamic_Mechanism_Structure {
897 	/* RT_TIMER	FastAntTrainingTimer; */
898 	/*  */
899 	/* 	Add for different team use temporarily */
900 	/*  */
901 	struct adapter *Adapter;		/*  For CE/NIC team */
902 	/*  WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
903 	bool odm_ready;
904 
905 	PHY_REG_PG_TYPE PhyRegPgValueType;
906 	u8 PhyRegPgVersion;
907 
908 	u64	DebugComponents;
909 	u32 DebugLevel;
910 
911 	u32 NumQryPhyStatusAll;	/* CCK + OFDM */
912 	u32 LastNumQryPhyStatusAll;
913 	u32 RxPWDBAve;
914 	bool MPDIG_2G;		/* off MPDIG */
915 	u8 Times_2G;
916 
917 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
918 	bool bCckHighPower;
919 	u8 RFPathRxEnable;		/*  ODM_CMNINFO_RFPATH_ENABLE */
920 	u8 ControlChannel;
921 /*  ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
922 
923 /* REMOVED COMMON INFO---------- */
924 	/* u8 		PseudoMacPhyMode; */
925 	/* bool			*BTCoexist; */
926 	/* bool			PseudoBtCoexist; */
927 	/* u8 		OPMode; */
928 	/* bool			bAPMode; */
929 	/* bool			bClientMode; */
930 	/* bool			bAdHocMode; */
931 	/* bool			bSlaveOfDMSP; */
932 /* REMOVED COMMON INFO---------- */
933 
934 
935 /* 1  COMMON INFORMATION */
936 
937 	/*  */
938 	/*  Init Value */
939 	/*  */
940 /* HOOK BEFORE REG INIT----------- */
941 	/*  ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
942 	u8 SupportPlatform;
943 	/*  ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ?K?K = 1/2/3/?K */
944 	u32 SupportAbility;
945 	/*  ODM PCIE/USB/SDIO = 1/2/3 */
946 	u8 SupportInterface;
947 	/*  ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
948 	u32 SupportICType;
949 	/*  Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
950 	u8 CutVersion;
951 	/*  Fab Version TSMC/UMC = 0/1 */
952 	u8 FabVersion;
953 	/*  RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
954 	u8 RFType;
955 	u8 RFEType;
956 	/*  Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
957 	u8 BoardType;
958 	u8 PackageType;
959 	u8 TypeGLNA;
960 	u8 TypeGPA;
961 	u8 TypeALNA;
962 	u8 TypeAPA;
963 	/*  with external LNA  NO/Yes = 0/1 */
964 	u8 ExtLNA;
965 	u8 ExtLNA5G;
966 	/*  with external PA  NO/Yes = 0/1 */
967 	u8 ExtPA;
968 	u8 ExtPA5G;
969 	/*  with external TRSW  NO/Yes = 0/1 */
970 	u8 ExtTRSW;
971 	u8 PatchID; /* Customer ID */
972 	bool bInHctTest;
973 	bool bWIFITest;
974 
975 	bool bDualMacSmartConcurrent;
976 	u32 BK_SupportAbility;
977 	u8 AntDivType;
978 /* HOOK BEFORE REG INIT----------- */
979 
980 	/*  */
981 	/*  Dynamic Value */
982 	/*  */
983 /*  POINTER REFERENCE----------- */
984 
985 	u8 u8_temp;
986 	bool bool_temp;
987 	struct adapter *adapter_temp;
988 
989 	/*  MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
990 	u8 *pMacPhyMode;
991 	/* TX Unicast byte count */
992 	u64 *pNumTxBytesUnicast;
993 	/* RX Unicast byte count */
994 	u64 *pNumRxBytesUnicast;
995 	/*  Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
996 	u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
997 	/*  Frequence band 2.4G/5G = 0/1 */
998 	u8 *pBandType;
999 	/*  Secondary channel offset don't_care/below/above = 0/1/2 */
1000 	u8 *pSecChOffset;
1001 	/*  Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
1002 	u8 *pSecurity;
1003 	/*  BW info 20M/40M/80M = 0/1/2 */
1004 	u8 *pBandWidth;
1005 	/*  Central channel location Ch1/Ch2/.... */
1006 	u8 *pChannel; /* central channel number */
1007 	bool DPK_Done;
1008 	/*  Common info for 92D DMSP */
1009 
1010 	bool *pbGetValueFromOtherMac;
1011 	struct adapter **pBuddyAdapter;
1012 	bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
1013 	/*  Common info for Status */
1014 	bool *pbScanInProcess;
1015 	bool *pbPowerSaving;
1016 	/*  CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
1017 	u8 *pOnePathCCA;
1018 	/* pMgntInfo->AntennaTest */
1019 	u8 *pAntennaTest;
1020 	bool *pbNet_closed;
1021 	u8 *mp_mode;
1022 	/* u8 	*pAidMap; */
1023 	u8 *pu1ForcedIgiLb;
1024 /*  For 8723B IQK----------- */
1025 	bool *pIs1Antenna;
1026 	u8 *pRFDefaultPath;
1027 	/*  0:S1, 1:S0 */
1028 
1029 /*  POINTER REFERENCE----------- */
1030 	u16 *pForcedDataRate;
1031 /* CALL BY VALUE------------- */
1032 	bool bLinkInProcess;
1033 	bool bWIFI_Direct;
1034 	bool bWIFI_Display;
1035 	bool bLinked;
1036 
1037 	bool bsta_state;
1038 	u8 RSSI_Min;
1039 	u8 InterfaceIndex; /*  Add for 92D  dual MAC: 0--Mac0 1--Mac1 */
1040 	bool bIsMPChip;
1041 	bool bOneEntryOnly;
1042 	/*  Common info for BTDM */
1043 	bool bBtEnabled;			/*  BT is disabled */
1044 	bool bBtConnectProcess;	/*  BT HS is under connection progress. */
1045 	u8 btHsRssi;				/*  BT HS mode wifi rssi value. */
1046 	bool bBtHsOperation;		/*  BT HS mode is under progress */
1047 	bool bBtDisableEdcaTurbo;	/*  Under some condition, don't enable the EDCA Turbo */
1048 	bool bBtLimitedDig;			/*  BT is busy. */
1049 /* CALL BY VALUE------------- */
1050 	u8 RSSI_A;
1051 	u8 RSSI_B;
1052 	u64 RSSI_TRSW;
1053 	u64 RSSI_TRSW_H;
1054 	u64 RSSI_TRSW_L;
1055 	u64 RSSI_TRSW_iso;
1056 
1057 	u8 RxRate;
1058 	bool bNoisyState;
1059 	u8 TxRate;
1060 	u8 LinkedInterval;
1061 	u8 preChannel;
1062 	u32 TxagcOffsetValueA;
1063 	bool IsTxagcOffsetPositiveA;
1064 	u32 TxagcOffsetValueB;
1065 	bool IsTxagcOffsetPositiveB;
1066 	u64	lastTxOkCnt;
1067 	u64	lastRxOkCnt;
1068 	u32 BbSwingOffsetA;
1069 	bool IsBbSwingOffsetPositiveA;
1070 	u32 BbSwingOffsetB;
1071 	bool IsBbSwingOffsetPositiveB;
1072 	s8 TH_L2H_ini;
1073 	s8 TH_EDCCA_HL_diff;
1074 	s8 IGI_Base;
1075 	u8 IGI_target;
1076 	bool ForceEDCCA;
1077 	u8 AdapEn_RSSI;
1078 	s8 Force_TH_H;
1079 	s8 Force_TH_L;
1080 	u8 IGI_LowerBound;
1081 	u8 antdiv_rssi;
1082 	u8 AntType;
1083 	u8 pre_AntType;
1084 	u8 antdiv_period;
1085 	u8 antdiv_select;
1086 	u8 NdpaPeriod;
1087 	bool H2C_RARpt_connect;
1088 
1089 	/*  add by Yu Cehn for adaptivtiy */
1090 	bool adaptivity_flag;
1091 	bool NHM_disable;
1092 	bool TxHangFlg;
1093 	bool Carrier_Sense_enable;
1094 	u8 tolerance_cnt;
1095 	u64 NHMCurTxOkcnt;
1096 	u64 NHMCurRxOkcnt;
1097 	u64 NHMLastTxOkcnt;
1098 	u64 NHMLastRxOkcnt;
1099 	u8 txEdcca1;
1100 	u8 txEdcca0;
1101 	s8 H2L_lb;
1102 	s8 L2H_lb;
1103 	u8 Adaptivity_IGI_upper;
1104 	u8 NHM_cnt_0;
1105 
1106 
1107 	ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */
1108 	/*  */
1109 	/* 2 Define STA info. */
1110 	/*  _ODM_STA_INFO */
1111 	/*  2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
1112 	PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
1113 
1114 	/*  */
1115 	/*  2012/02/14 MH Add to share 88E ra with other SW team. */
1116 	/*  We need to colelct all support abilit to a proper area. */
1117 	/*  */
1118 	bool RaSupport88E;
1119 
1120 	/*  Define ........... */
1121 
1122 	/*  Latest packet phy info (ODM write) */
1123 	ODM_PHY_DBG_INFO_T PhyDbgInfo;
1124 	/* PHY_INFO_88E		PhyInfo; */
1125 
1126 	/*  Latest packet phy info (ODM write) */
1127 	ODM_MAC_INFO *pMacInfo;
1128 	/* MAC_INFO_88E		MacInfo; */
1129 
1130 	/*  Different Team independt structure?? */
1131 
1132 	/*  */
1133 	/* TX_RTP_CMN		TX_retrpo; */
1134 	/* TX_RTP_88E		TX_retrpo; */
1135 	/* TX_RTP_8195		TX_retrpo; */
1136 
1137 	/*  */
1138 	/* ODM Structure */
1139 	/*  */
1140 	FAT_T DM_FatTable;
1141 	DIG_T DM_DigTable;
1142 	PS_T DM_PSTable;
1143 	Pri_CCA_T DM_PriCCA;
1144 	RXHP_T DM_RXHP_Table;
1145 	RA_T DM_RA_Table;
1146 	false_ALARM_STATISTICS FalseAlmCnt;
1147 	false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
1148 	SWAT_T DM_SWAT_Table;
1149 	bool RSSI_test;
1150 	CFO_TRACKING DM_CfoTrack;
1151 
1152 	EDCA_T DM_EDCA_Table;
1153 	u32 WMMEDCA_BE;
1154 	PATHDIV_T DM_PathDiv;
1155 	/*  Copy from SD4 structure */
1156 	/*  */
1157 	/*  ================================================== */
1158 	/*  */
1159 
1160 	/* common */
1161 	/* u8 DM_Type; */
1162 	/* u8    PSD_Report_RXHP[80];    Add By Gary */
1163 	/* u8    PSD_func_flag;                Add By Gary */
1164 	/* for DIG */
1165 	/* u8 bDMInitialGainEnable; */
1166 	/* u8 binitialized;  for dm_initial_gain_Multi_STA use. */
1167 	/* for Antenna diversity */
1168 	/* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
1169 	/* PSTA_INFO_T RSSI_target; */
1170 
1171 	bool *pbDriverStopped;
1172 	bool *pbDriverIsGoingToPnpSetPowerSleep;
1173 	bool *pinit_adpt_in_progress;
1174 
1175 	/* PSD */
1176 	bool bUserAssignLevel;
1177 	RT_TIMER PSDTimer;
1178 	u8 RSSI_BT;			/* come from BT */
1179 	bool bPSDinProcess;
1180 	bool bPSDactive;
1181 	bool bDMInitialGainEnable;
1182 
1183 	/* MPT DIG */
1184 	RT_TIMER MPT_DIGTimer;
1185 
1186 	/* for rate adaptive, in fact,  88c/92c fw will handle this */
1187 	u8 bUseRAMask;
1188 
1189 	ODM_RATE_ADAPTIVE RateAdaptive;
1190 
1191 	ANT_DETECTED_INFO AntDetectedInfo; /*  Antenna detected information for RSSI tool */
1192 
1193 	ODM_RF_CAL_T RFCalibrateInfo;
1194 
1195 	/*  */
1196 	/*  TX power tracking */
1197 	/*  */
1198 	u8 BbSwingIdxOfdm[MAX_RF_PATH];
1199 	u8 BbSwingIdxOfdmCurrent;
1200 	u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
1201 	bool BbSwingFlagOfdm;
1202 	u8 BbSwingIdxCck;
1203 	u8 BbSwingIdxCckCurrent;
1204 	u8 BbSwingIdxCckBase;
1205 	u8 DefaultOfdmIndex;
1206 	u8 DefaultCckIndex;
1207 	bool BbSwingFlagCck;
1208 
1209 	s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
1210 	s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
1211 	s8 Remnant_CCKSwingIdx;
1212 	s8 Modify_TxAGC_Value;       /* Remnat compensate value at TxAGC */
1213 	bool Modify_TxAGC_Flag_PathA;
1214 	bool Modify_TxAGC_Flag_PathB;
1215 	bool Modify_TxAGC_Flag_PathC;
1216 	bool Modify_TxAGC_Flag_PathD;
1217 	bool Modify_TxAGC_Flag_PathA_CCK;
1218 
1219 	s8 KfreeOffset[MAX_RF_PATH];
1220 	/*  */
1221 	/*  ODM system resource. */
1222 	/*  */
1223 
1224 	/*  ODM relative time. */
1225 	RT_TIMER PathDivSwitchTimer;
1226 	/* 2011.09.27 add for Path Diversity */
1227 	RT_TIMER CCKPathDiversityTimer;
1228 	RT_TIMER FastAntTrainingTimer;
1229 
1230 	/*  ODM relative workitem. */
1231 
1232 	#if (BEAMFORMING_SUPPORT == 1)
1233 	RT_BEAMFORMING_INFO BeamformingInfo;
1234 	#endif
1235 } DM_ODM_T, *PDM_ODM_T; /*  DM_Dynamic_Mechanism_Structure */
1236 
1237 #define ODM_RF_PATH_MAX 2
1238 
1239 typedef enum _ODM_RF_RADIO_PATH {
1240 	ODM_RF_PATH_A = 0,   /* Radio Path A */
1241 	ODM_RF_PATH_B = 1,   /* Radio Path B */
1242 	ODM_RF_PATH_C = 2,   /* Radio Path C */
1243 	ODM_RF_PATH_D = 3,   /* Radio Path D */
1244 	ODM_RF_PATH_AB,
1245 	ODM_RF_PATH_AC,
1246 	ODM_RF_PATH_AD,
1247 	ODM_RF_PATH_BC,
1248 	ODM_RF_PATH_BD,
1249 	ODM_RF_PATH_CD,
1250 	ODM_RF_PATH_ABC,
1251 	ODM_RF_PATH_ACD,
1252 	ODM_RF_PATH_BCD,
1253 	ODM_RF_PATH_ABCD,
1254 	/*   ODM_RF_PATH_MAX,    Max RF number 90 support */
1255 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
1256 
1257  typedef enum _ODM_RF_CONTENT {
1258 	odm_radioa_txt = 0x1000,
1259 	odm_radiob_txt = 0x1001,
1260 	odm_radioc_txt = 0x1002,
1261 	odm_radiod_txt = 0x1003
1262 } ODM_RF_CONTENT;
1263 
1264 typedef enum _ODM_BB_Config_Type {
1265 	CONFIG_BB_PHY_REG,
1266 	CONFIG_BB_AGC_TAB,
1267 	CONFIG_BB_AGC_TAB_2G,
1268 	CONFIG_BB_AGC_TAB_5G,
1269 	CONFIG_BB_PHY_REG_PG,
1270 	CONFIG_BB_PHY_REG_MP,
1271 	CONFIG_BB_AGC_TAB_DIFF,
1272 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
1273 
1274 typedef enum _ODM_RF_Config_Type {
1275 	CONFIG_RF_RADIO,
1276 	CONFIG_RF_TXPWR_LMT,
1277 } ODM_RF_Config_Type, *PODM_RF_Config_Type;
1278 
1279 typedef enum _ODM_FW_Config_Type {
1280 	CONFIG_FW_NIC,
1281 	CONFIG_FW_NIC_2,
1282 	CONFIG_FW_AP,
1283 	CONFIG_FW_WoWLAN,
1284 	CONFIG_FW_WoWLAN_2,
1285 	CONFIG_FW_AP_WoWLAN,
1286 	CONFIG_FW_BT,
1287 } ODM_FW_Config_Type;
1288 
1289 /*  Status code */
1290 typedef enum _RT_STATUS {
1291 	RT_STATUS_SUCCESS,
1292 	RT_STATUS_FAILURE,
1293 	RT_STATUS_PENDING,
1294 	RT_STATUS_RESOURCE,
1295 	RT_STATUS_INVALID_CONTEXT,
1296 	RT_STATUS_INVALID_PARAMETER,
1297 	RT_STATUS_NOT_SUPPORT,
1298 	RT_STATUS_OS_API_FAILED,
1299 } RT_STATUS, *PRT_STATUS;
1300 
1301 #ifdef REMOVE_PACK
1302 #pragma pack()
1303 #endif
1304 
1305 /* include "odm_function.h" */
1306 
1307 /* 3 =========================================================== */
1308 /* 3 DIG */
1309 /* 3 =========================================================== */
1310 
1311 /* Remove DIG by Yuchen */
1312 
1313 /* 3 =========================================================== */
1314 /* 3 AGC RX High Power Mode */
1315 /* 3 =========================================================== */
1316 #define          LNA_Low_Gain_1                      0x64
1317 #define          LNA_Low_Gain_2                      0x5A
1318 #define          LNA_Low_Gain_3                      0x58
1319 
1320 #define          FA_RXHP_TH1                           5000
1321 #define          FA_RXHP_TH2                           1500
1322 #define          FA_RXHP_TH3                             800
1323 #define          FA_RXHP_TH4                             600
1324 #define          FA_RXHP_TH5                             500
1325 
1326 /* 3 =========================================================== */
1327 /* 3 EDCA */
1328 /* 3 =========================================================== */
1329 
1330 /* 3 =========================================================== */
1331 /* 3 Dynamic Tx Power */
1332 /* 3 =========================================================== */
1333 /* Dynamic Tx Power Control Threshold */
1334 
1335 /* 3 =========================================================== */
1336 /* 3 Rate Adaptive */
1337 /* 3 =========================================================== */
1338 #define		DM_RATR_STA_INIT			0
1339 #define		DM_RATR_STA_HIGH			1
1340 #define		DM_RATR_STA_MIDDLE			2
1341 #define		DM_RATR_STA_LOW				3
1342 
1343 /* 3 =========================================================== */
1344 /* 3 BB Power Save */
1345 /* 3 =========================================================== */
1346 
1347 typedef enum tag_1R_CCA_Type_Definition {
1348 	CCA_1R = 0,
1349 	CCA_2R = 1,
1350 	CCA_MAX = 2,
1351 } DM_1R_CCA_E;
1352 
1353 typedef enum tag_RF_Type_Definition {
1354 	RF_Save = 0,
1355 	RF_Normal = 1,
1356 	RF_MAX = 2,
1357 } DM_RF_E;
1358 
1359 /* 3 =========================================================== */
1360 /* 3 Antenna Diversity */
1361 /* 3 =========================================================== */
1362 typedef enum tag_SW_Antenna_Switch_Definition {
1363 	Antenna_A = 1,
1364 	Antenna_B = 2,
1365 	Antenna_MAX = 3,
1366 } DM_SWAS_E;
1367 
1368 
1369 /*  Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1370 #define	MAX_ANTENNA_DETECTION_CNT	10
1371 
1372 /*  */
1373 /*  Extern Global Variables. */
1374 /*  */
1375 extern	u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1376 extern	u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1377 extern	u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1378 
1379 extern	u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1380 extern	u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1381 extern	u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1382 
1383 extern  u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1384 
1385 /*  */
1386 /*  check Sta pointer valid or not */
1387 /*  */
1388 #define IS_STA_VALID(pSta)		(pSta)
1389 /*  20100514 Joseph: Add definition for antenna switching test after link. */
1390 /*  This indicates two different the steps. */
1391 /*  In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1392 /*  In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1393 /*  with original RSSI to determine if it is necessary to switch antenna. */
1394 #define SWAW_STEP_PEAK		0
1395 #define SWAW_STEP_DETERMINE	1
1396 
1397 /* Remove DIG by yuchen */
1398 
1399 void ODM_SetAntenna(PDM_ODM_T pDM_Odm, u8 Antenna);
1400 
1401 
1402 /* Remove BB power saving by Yuchen */
1403 
1404 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1405 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm);
1406 
1407 bool ODM_RAStateCheck(
1408 	PDM_ODM_T pDM_Odm,
1409 	s32	RSSI,
1410 	bool bForceUpdate,
1411 	u8 *pRATRState
1412 );
1413 
1414 #define dm_SWAW_RSSI_Check	ODM_SwAntDivChkPerPktRssi
1415 void ODM_SwAntDivChkPerPktRssi(
1416 	PDM_ODM_T pDM_Odm,
1417 	u8 StationID,
1418 	PODM_PHY_INFO_T pPhyInfo
1419 );
1420 
1421 u32 ODM_Get_Rate_Bitmap(
1422 	PDM_ODM_T pDM_Odm,
1423 	u32 macid,
1424 	u32 ra_mask,
1425 	u8 rssi_level
1426 );
1427 
1428 #if (BEAMFORMING_SUPPORT == 1)
1429 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1430 #endif
1431 
1432 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm);
1433 
1434 void ODM_DMInit(PDM_ODM_T pDM_Odm);
1435 
1436 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /*  For common use in the future */
1437 
1438 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value);
1439 
1440 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue);
1441 
1442 void ODM_CmnInfoPtrArrayHook(
1443 	PDM_ODM_T pDM_Odm,
1444 	ODM_CMNINFO_E CmnInfo,
1445 	u16 Index,
1446 	void *pValue
1447 );
1448 
1449 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value);
1450 
1451 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm);
1452 
1453 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm);
1454 
1455 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm);
1456 
1457 void ODM_AntselStatistics_88C(
1458 	PDM_ODM_T pDM_Odm,
1459 	u8 MacId,
1460 	u32 PWDBAll,
1461 	bool isCCKrate
1462 );
1463 
1464 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State);
1465 
1466 #endif
1467