1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 9 #ifndef __HALDMOUTSRC_H__ 10 #define __HALDMOUTSRC_H__ 11 12 #include "odm_EdcaTurboCheck.h" 13 #include "odm_DIG.h" 14 #include "odm_DynamicBBPowerSaving.h" 15 #include "odm_DynamicTxPower.h" 16 #include "odm_CfoTracking.h" 17 #include "odm_NoiseMonitor.h" 18 19 #define TP_MODE 0 20 #define RSSI_MODE 1 21 #define TRAFFIC_LOW 0 22 #define TRAFFIC_HIGH 1 23 #define NONE 0 24 25 /* 3 Tx Power Tracking */ 26 /* 3 ============================================================ */ 27 #define DPK_DELTA_MAPPING_NUM 13 28 #define index_mapping_HP_NUM 15 29 #define OFDM_TABLE_SIZE 43 30 #define CCK_TABLE_SIZE 33 31 #define TXSCALE_TABLE_SIZE 37 32 #define TXPWR_TRACK_TABLE_SIZE 30 33 #define DELTA_SWINGIDX_SIZE 30 34 #define BAND_NUM 4 35 36 /* 3 PSD Handler */ 37 /* 3 ============================================================ */ 38 39 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */ 40 #define MODE_40M 0 /* 0:20M, 1:40M */ 41 #define PSD_TH2 3 42 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */ 43 #define SIR_STEP_SIZE 3 44 #define Smooth_Size_1 5 45 #define Smooth_TH_1 3 46 #define Smooth_Size_2 10 47 #define Smooth_TH_2 4 48 #define Smooth_Size_3 20 49 #define Smooth_TH_3 4 50 #define Smooth_Step_Size 5 51 #define Adaptive_SIR 1 52 #define PSD_RESCAN 4 53 #define PSD_SCAN_INTERVAL 700 /* ms */ 54 55 /* 8723A High Power IGI Setting */ 56 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22 57 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28 58 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a 59 #define DM_DIG_LOW_PWR_THRESHOLD 0x14 60 61 /* ANT Test */ 62 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */ 63 #define ANTTESTA 0x01 /* Ant A will be Testing */ 64 #define ANTTESTB 0x02 /* Ant B will be testing */ 65 66 #define PS_MODE_ACTIVE 0x01 67 68 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */ 69 #define MAIN_ANT 1 /* Ant A or Ant Main */ 70 #define AUX_ANT 2 /* AntB or Ant Aux */ 71 #define MAX_ANT 3 /* 3 for AP using */ 72 73 /* Antenna Diversity Type */ 74 #define SW_ANTDIV 0 75 #define HW_ANTDIV 1 76 /* structure and define */ 77 78 /* Remove DIG by Yuchen */ 79 80 /* Remoce BB power saving by Yuchn */ 81 82 /* Remove DIG by yuchen */ 83 84 struct dynamic_primary_CCA { 85 u8 PriCCA_flag; 86 u8 intf_flag; 87 u8 intf_type; 88 u8 DupRTS_flag; 89 u8 Monitor_flag; 90 u8 CH_offset; 91 u8 MF_state; 92 }; 93 94 struct ra_t { 95 u8 firstconnect; 96 }; 97 98 struct rxhp_t { 99 u8 RXHP_flag; 100 u8 PSD_func_trigger; 101 u8 PSD_bitmap_RXHP[80]; 102 u8 Pre_IGI; 103 u8 Cur_IGI; 104 u8 Pre_pw_th; 105 u8 Cur_pw_th; 106 bool First_time_enter; 107 bool RXHP_enable; 108 u8 TP_Mode; 109 struct timer_list PSDTimer; 110 }; 111 112 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */ 113 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM 114 115 /* This indicates two different the steps. */ 116 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 117 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 118 /* with original RSSI to determine if it is necessary to switch antenna. */ 119 #define SWAW_STEP_PEAK 0 120 #define SWAW_STEP_DETERMINE 1 121 122 #define TP_MODE 0 123 #define RSSI_MODE 1 124 #define TRAFFIC_LOW 0 125 #define TRAFFIC_HIGH 1 126 #define TRAFFIC_UltraLOW 2 127 128 struct swat_t { /* _SW_Antenna_Switch_ */ 129 u8 Double_chk_flag; 130 u8 try_flag; 131 s32 PreRSSI; 132 u8 CurAntenna; 133 u8 PreAntenna; 134 u8 RSSI_Trying; 135 u8 TestMode; 136 u8 bTriggerAntennaSwitch; 137 u8 SelectAntennaMap; 138 u8 RSSI_target; 139 u8 reset_idx; 140 u16 Single_Ant_Counter; 141 u16 Dual_Ant_Counter; 142 u16 Aux_FailDetec_Counter; 143 u16 Retry_Counter; 144 145 /* Before link Antenna Switch check */ 146 u8 SWAS_NoLink_State; 147 u32 SWAS_NoLink_BK_Reg860; 148 u32 SWAS_NoLink_BK_Reg92c; 149 u32 SWAS_NoLink_BK_Reg948; 150 bool ANTA_ON; /* To indicate Ant A is or not */ 151 bool ANTB_ON; /* To indicate Ant B is on or not */ 152 bool Pre_Aux_FailDetec; 153 bool RSSI_AntDect_bResult; 154 u8 Ant5G; 155 u8 Ant2G; 156 157 s32 RSSI_sum_A; 158 s32 RSSI_sum_B; 159 s32 RSSI_cnt_A; 160 s32 RSSI_cnt_B; 161 162 u64 lastTxOkCnt; 163 u64 lastRxOkCnt; 164 u64 TXByteCnt_A; 165 u64 TXByteCnt_B; 166 u64 RXByteCnt_A; 167 u64 RXByteCnt_B; 168 u8 TrafficLoad; 169 u8 Train_time; 170 u8 Train_time_flag; 171 struct timer_list SwAntennaSwitchTimer; 172 struct timer_list SwAntennaSwitchTimer_8723B; 173 u32 PktCnt_SWAntDivByCtrlFrame; 174 bool bSWAntDivByCtrlFrame; 175 }; 176 177 /* Remove Edca by YuChen */ 178 179 180 struct odm_rate_adaptive { 181 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */ 182 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */ 183 bool bUseLdpc; 184 bool bLowerRtsRate; 185 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */ 186 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */ 187 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */ 188 189 }; 190 191 #define IQK_MAC_REG_NUM 4 192 #define IQK_ADDA_REG_NUM 16 193 #define IQK_BB_REG_NUM_MAX 10 194 #define IQK_BB_REG_NUM 9 195 #define HP_THERMAL_NUM 8 196 197 #define AVG_THERMAL_NUM 8 198 #define IQK_Matrix_REG_NUM 8 199 #define IQK_Matrix_Settings_NUM (14 + 24 + 21) /* Channels_2_4G_NUM 200 * + Channels_5G_20M_NUM 201 * + Channels_5G 202 */ 203 204 #define DM_Type_ByFW 0 205 #define DM_Type_ByDriver 1 206 207 /* */ 208 /* Declare for common info */ 209 /* */ 210 #define MAX_PATH_NUM_92CS 2 211 #define MAX_PATH_NUM_8188E 1 212 #define MAX_PATH_NUM_8192E 2 213 #define MAX_PATH_NUM_8723B 1 214 #define MAX_PATH_NUM_8812A 2 215 #define MAX_PATH_NUM_8821A 1 216 #define MAX_PATH_NUM_8814A 4 217 #define MAX_PATH_NUM_8822B 2 218 219 #define IQK_THRESHOLD 8 220 #define DPK_THRESHOLD 4 221 222 struct odm_phy_info { 223 /* 224 * Be care, if you want to add any element, please insert it between 225 * rx_pwd_ball and signal_strength. 226 */ 227 u8 rx_pwd_ba11; 228 229 u8 signal_quality; /* in 0-100 index. */ 230 s8 rx_mimo_signal_quality[4]; /* per-path's EVM */ 231 u8 rx_mimo_evm_dbm[4]; /* per-path's EVM dbm */ 232 233 u8 rx_mimo_signal_strength[4]; /* in 0~100 index */ 234 235 u16 cfo_short[4]; /* per-path's Cfo_short */ 236 u16 cfo_tail[4]; /* per-path's Cfo_tail */ 237 238 s8 rx_power; /* in dBm Translate from PWdB */ 239 240 /* 241 * Real power in dBm for this packet, no beautification and 242 * aggregation. Keep this raw info to be used for the other procedures. 243 */ 244 s8 recv_signal_power; 245 u8 bt_rx_rssi_percentage; 246 u8 signal_strength; /* in 0-100 index. */ 247 248 s8 rx_pwr[4]; /* per-path's pwdb */ 249 250 u8 rx_snr[4]; /* per-path's SNR */ 251 u8 band_width; 252 u8 bt_coex_pwr_adjust; 253 }; 254 255 struct odm_packet_info { 256 u8 data_rate; 257 u8 station_id; 258 bool bssid_match; 259 bool to_self; 260 bool is_beacon; 261 }; 262 263 struct odm_phy_dbg_info { 264 /* ODM Write, debug info */ 265 s8 RxSNRdB[4]; 266 u32 NumQryPhyStatus; 267 u32 NumQryPhyStatusCCK; 268 u32 NumQryPhyStatusOFDM; 269 u8 NumQryBeaconPkt; 270 /* Others */ 271 s32 RxEVM[4]; 272 273 }; 274 275 struct odm_mac_status_info { 276 u8 test; 277 }; 278 279 /* */ 280 /* 2011/10/20 MH Define Common info enum for all team. */ 281 /* */ 282 enum odm_cmninfo_e { 283 /* Fixed value: */ 284 285 /* HOOK BEFORE REG INIT----------- */ 286 ODM_CMNINFO_PLATFORM = 0, 287 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */ 288 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */ 289 ODM_CMNINFO_MP_TEST_CHIP, 290 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */ 291 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */ 292 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */ 293 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */ 294 ODM_CMNINFO_RFE_TYPE, 295 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */ 296 ODM_CMNINFO_PACKAGE_TYPE, 297 ODM_CMNINFO_EXT_LNA, /* true */ 298 ODM_CMNINFO_5G_EXT_LNA, 299 ODM_CMNINFO_EXT_PA, 300 ODM_CMNINFO_5G_EXT_PA, 301 ODM_CMNINFO_GPA, 302 ODM_CMNINFO_APA, 303 ODM_CMNINFO_GLNA, 304 ODM_CMNINFO_ALNA, 305 ODM_CMNINFO_EXT_TRSW, 306 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */ 307 ODM_CMNINFO_BINHCT_TEST, 308 ODM_CMNINFO_BWIFI_TEST, 309 ODM_CMNINFO_SMART_CONCURRENT, 310 /* HOOK BEFORE REG INIT----------- */ 311 312 /* Dynamic value: */ 313 /* POINTER REFERENCE----------- */ 314 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */ 315 ODM_CMNINFO_TX_UNI, 316 ODM_CMNINFO_RX_UNI, 317 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */ 318 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */ 319 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */ 320 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */ 321 ODM_CMNINFO_BW, /* ODM_BW_E */ 322 ODM_CMNINFO_CHNL, 323 ODM_CMNINFO_FORCED_RATE, 324 325 ODM_CMNINFO_DMSP_GET_VALUE, 326 ODM_CMNINFO_BUDDY_ADAPTOR, 327 ODM_CMNINFO_DMSP_IS_MASTER, 328 ODM_CMNINFO_SCAN, 329 ODM_CMNINFO_POWER_SAVING, 330 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */ 331 ODM_CMNINFO_DRV_STOP, 332 ODM_CMNINFO_PNP_IN, 333 ODM_CMNINFO_INIT_ON, 334 ODM_CMNINFO_ANT_TEST, 335 ODM_CMNINFO_NET_CLOSED, 336 ODM_CMNINFO_MP_MODE, 337 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */ 338 ODM_CMNINFO_FORCED_IGI_LB, 339 ODM_CMNINFO_IS1ANTENNA, 340 ODM_CMNINFO_RFDEFAULTPATH, 341 /* POINTER REFERENCE----------- */ 342 343 /* CALL BY VALUE------------- */ 344 ODM_CMNINFO_WIFI_DIRECT, 345 ODM_CMNINFO_WIFI_DISPLAY, 346 ODM_CMNINFO_LINK_IN_PROGRESS, 347 ODM_CMNINFO_LINK, 348 ODM_CMNINFO_STATION_STATE, 349 ODM_CMNINFO_RSSI_MIN, 350 ODM_CMNINFO_DBG_COMP, /* u64 */ 351 ODM_CMNINFO_DBG_LEVEL, /* u32 */ 352 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */ 353 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */ 354 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */ 355 ODM_CMNINFO_BT_ENABLED, 356 ODM_CMNINFO_BT_HS_CONNECT_PROCESS, 357 ODM_CMNINFO_BT_HS_RSSI, 358 ODM_CMNINFO_BT_OPERATION, 359 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */ 360 ODM_CMNINFO_BT_DISABLE_EDCA, 361 /* CALL BY VALUE------------- */ 362 363 /* Dynamic ptr array hook itms. */ 364 ODM_CMNINFO_STA_STATUS, 365 ODM_CMNINFO_PHY_STATUS, 366 ODM_CMNINFO_MAC_STATUS, 367 368 ODM_CMNINFO_MAX, 369 }; 370 371 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */ 372 enum { /* _ODM_Support_Ability_Definition */ 373 /* */ 374 /* BB ODM section BIT 0-15 */ 375 /* */ 376 ODM_BB_DIG = BIT0, 377 ODM_BB_RA_MASK = BIT1, 378 ODM_BB_DYNAMIC_TXPWR = BIT2, 379 ODM_BB_FA_CNT = BIT3, 380 ODM_BB_RSSI_MONITOR = BIT4, 381 ODM_BB_CCK_PD = BIT5, 382 ODM_BB_ANT_DIV = BIT6, 383 ODM_BB_PWR_SAVE = BIT7, 384 ODM_BB_PWR_TRAIN = BIT8, 385 ODM_BB_RATE_ADAPTIVE = BIT9, 386 ODM_BB_PATH_DIV = BIT10, 387 ODM_BB_PSD = BIT11, 388 ODM_BB_RXHP = BIT12, 389 ODM_BB_ADAPTIVITY = BIT13, 390 ODM_BB_CFO_TRACKING = BIT14, 391 392 /* MAC DM section BIT 16-23 */ 393 ODM_MAC_EDCA_TURBO = BIT16, 394 ODM_MAC_EARLY_MODE = BIT17, 395 396 /* RF ODM section BIT 24-31 */ 397 ODM_RF_TX_PWR_TRACK = BIT24, 398 ODM_RF_RX_GAIN_TRACK = BIT25, 399 ODM_RF_CALIBRATION = BIT26, 400 }; 401 402 /* ODM_CMNINFO_INTERFACE */ 403 enum { /* tag_ODM_Support_Interface_Definition */ 404 ODM_ITRF_SDIO = 0x4, 405 ODM_ITRF_ALL = 0x7, 406 }; 407 408 /* ODM_CMNINFO_IC_TYPE */ 409 enum { /* tag_ODM_Support_IC_Type_Definition */ 410 ODM_RTL8723B = BIT8, 411 }; 412 413 /* ODM_CMNINFO_CUT_VER */ 414 enum { /* tag_ODM_Cut_Version_Definition */ 415 ODM_CUT_A = 0, 416 ODM_CUT_B = 1, 417 ODM_CUT_C = 2, 418 ODM_CUT_D = 3, 419 ODM_CUT_E = 4, 420 ODM_CUT_F = 5, 421 422 ODM_CUT_I = 8, 423 ODM_CUT_J = 9, 424 ODM_CUT_K = 10, 425 ODM_CUT_TEST = 15, 426 }; 427 428 /* ODM_CMNINFO_FAB_VER */ 429 enum { /* tag_ODM_Fab_Version_Definition */ 430 ODM_TSMC = 0, 431 ODM_UMC = 1, 432 }; 433 434 /* ODM_CMNINFO_RF_TYPE */ 435 /* */ 436 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */ 437 /* */ 438 enum { /* tag_ODM_RF_Type_Definition */ 439 ODM_1T1R = 0, 440 ODM_1T2R = 1, 441 ODM_2T2R = 2, 442 ODM_2T3R = 3, 443 ODM_2T4R = 4, 444 ODM_3T3R = 5, 445 ODM_3T4R = 6, 446 ODM_4T4R = 7, 447 }; 448 449 /* */ 450 /* ODM Dynamic common info value definition */ 451 /* */ 452 453 /* ODM_CMNINFO_WM_MODE */ 454 enum { /* tag_Wireless_Mode_Definition */ 455 ODM_WM_UNKNOWN = 0x0, 456 ODM_WM_B = BIT0, 457 ODM_WM_G = BIT1, 458 ODM_WM_A = BIT2, 459 ODM_WM_N24G = BIT3, 460 ODM_WM_N5G = BIT4, 461 ODM_WM_AUTO = BIT5, 462 ODM_WM_AC = BIT6, 463 }; 464 465 /* ODM_CMNINFO_BAND */ 466 enum { /* tag_Band_Type_Definition */ 467 ODM_BAND_2_4G = 0, 468 ODM_BAND_5G, 469 ODM_BAND_ON_BOTH, 470 ODM_BANDMAX 471 }; 472 473 /* ODM_CMNINFO_BW */ 474 enum { /* tag_Bandwidth_Definition */ 475 ODM_BW20M = 0, 476 ODM_BW40M = 1, 477 ODM_BW80M = 2, 478 ODM_BW160M = 3, 479 ODM_BW10M = 4, 480 }; 481 482 /* ODM_CMNINFO_BOARD_TYPE */ 483 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */ 484 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */ 485 486 enum odm_type_gpa_e { /* tag_ODM_TYPE_GPA_Definition */ 487 TYPE_GPA0 = 0, 488 TYPE_GPA1 = BIT(1)|BIT(0) 489 }; 490 491 enum odm_type_apa_e { /* tag_ODM_TYPE_APA_Definition */ 492 TYPE_APA0 = 0, 493 TYPE_APA1 = BIT(1)|BIT(0) 494 }; 495 496 enum odm_type_glna_e { /* tag_ODM_TYPE_GLNA_Definition */ 497 TYPE_GLNA0 = 0, 498 TYPE_GLNA1 = BIT(2)|BIT(0), 499 TYPE_GLNA2 = BIT(3)|BIT(1), 500 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 501 }; 502 503 enum odm_type_alna_e { /* tag_ODM_TYPE_ALNA_Definition */ 504 TYPE_ALNA0 = 0, 505 TYPE_ALNA1 = BIT(2)|BIT(0), 506 TYPE_ALNA2 = BIT(3)|BIT(1), 507 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0) 508 }; 509 510 struct iqk_matrix_regs_setting { /* _IQK_MATRIX_REGS_SETTING */ 511 bool bIQKDone; 512 s32 Value[3][IQK_Matrix_REG_NUM]; 513 bool bBWIqkResultSaved[3]; 514 }; 515 516 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */ 517 518 struct odm_rf_cal_t { /* ODM_RF_Calibration_Structure */ 519 /* for tx power tracking */ 520 521 u32 RegA24; /* for TempCCK */ 522 s32 RegE94; 523 s32 RegE9C; 524 s32 RegEB4; 525 s32 RegEBC; 526 527 u8 TXPowercount; 528 bool bTXPowerTrackingInit; 529 bool bTXPowerTracking; 530 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */ 531 u8 TM_Trigger; 532 u8 InternalPA5G[2]; /* pathA / pathB */ 533 534 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */ 535 u8 ThermalValue; 536 u8 ThermalValue_LCK; 537 u8 ThermalValue_IQK; 538 u8 ThermalValue_DPK; 539 u8 ThermalValue_AVG[AVG_THERMAL_NUM]; 540 u8 ThermalValue_AVG_index; 541 u8 ThermalValue_RxGain; 542 u8 ThermalValue_Crystal; 543 u8 ThermalValue_DPKstore; 544 u8 ThermalValue_DPKtrack; 545 bool TxPowerTrackingInProgress; 546 547 bool bReloadtxpowerindex; 548 u8 bRfPiEnable; 549 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */ 550 551 /* Tx power Tracking ------------------------- */ 552 u8 bCCKinCH14; 553 u8 CCK_index; 554 u8 OFDM_index[MAX_RF_PATH]; 555 s8 PowerIndexOffset[MAX_RF_PATH]; 556 s8 DeltaPowerIndex[MAX_RF_PATH]; 557 s8 DeltaPowerIndexLast[MAX_RF_PATH]; 558 bool bTxPowerChanged; 559 560 u8 ThermalValue_HP[HP_THERMAL_NUM]; 561 u8 ThermalValue_HP_index; 562 struct iqk_matrix_regs_setting IQKMatrixRegSetting[IQK_Matrix_Settings_NUM]; 563 bool bNeedIQK; 564 bool bIQKInProgress; 565 u8 Delta_IQK; 566 u8 Delta_LCK; 567 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */ 568 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE]; 569 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE]; 570 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE]; 571 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE]; 572 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE]; 573 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE]; 574 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE]; 575 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE]; 576 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 577 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 578 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE]; 579 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE]; 580 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE]; 581 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE]; 582 583 /* */ 584 585 /* for IQK */ 586 u32 RegC04; 587 u32 Reg874; 588 u32 RegC08; 589 u32 RegB68; 590 u32 RegB6C; 591 u32 Reg870; 592 u32 Reg860; 593 u32 Reg864; 594 595 bool bIQKInitialized; 596 bool bLCKInProgress; 597 bool bAntennaDetected; 598 u32 ADDA_backup[IQK_ADDA_REG_NUM]; 599 u32 IQK_MAC_backup[IQK_MAC_REG_NUM]; 600 u32 IQK_BB_backup_recover[9]; 601 u32 IQK_BB_backup[IQK_BB_REG_NUM]; 602 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */ 603 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */ 604 605 /* for APK */ 606 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */ 607 u8 bAPKdone; 608 u8 bAPKThermalMeterIgnore; 609 610 /* DPK */ 611 bool bDPKFail; 612 u8 bDPdone; 613 u8 bDPPathAOK; 614 u8 bDPPathBOK; 615 616 u32 TxLOK[2]; 617 618 }; 619 /* */ 620 /* ODM Dynamic common info value definition */ 621 /* */ 622 623 struct fat_t { /* _FAST_ANTENNA_TRAINNING_ */ 624 u8 Bssid[6]; 625 u8 antsel_rx_keep_0; 626 u8 antsel_rx_keep_1; 627 u8 antsel_rx_keep_2; 628 u8 antsel_rx_keep_3; 629 u32 antSumRSSI[7]; 630 u32 antRSSIcnt[7]; 631 u32 antAveRSSI[7]; 632 u8 FAT_State; 633 u32 TrainIdx; 634 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM]; 635 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM]; 636 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM]; 637 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 638 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 639 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 640 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 641 u8 RxIdleAnt; 642 bool bBecomeLinked; 643 u32 MinMaxRSSI; 644 u8 idx_AntDiv_counter_2G; 645 u8 idx_AntDiv_counter_5G; 646 u32 AntDiv_2G_5G; 647 u32 CCK_counter_main; 648 u32 CCK_counter_aux; 649 u32 OFDM_counter_main; 650 u32 OFDM_counter_aux; 651 652 u32 CCK_CtrlFrame_Cnt_main; 653 u32 CCK_CtrlFrame_Cnt_aux; 654 u32 OFDM_CtrlFrame_Cnt_main; 655 u32 OFDM_CtrlFrame_Cnt_aux; 656 u32 MainAnt_CtrlFrame_Sum; 657 u32 AuxAnt_CtrlFrame_Sum; 658 u32 MainAnt_CtrlFrame_Cnt; 659 u32 AuxAnt_CtrlFrame_Cnt; 660 661 }; 662 663 enum { 664 NO_ANTDIV = 0xFF, 665 CG_TRX_HW_ANTDIV = 0x01, 666 CGCS_RX_HW_ANTDIV = 0x02, 667 FIXED_HW_ANTDIV = 0x03, 668 CG_TRX_SMART_ANTDIV = 0x04, 669 CGCS_RX_SW_ANTDIV = 0x05, 670 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */ 671 }; 672 673 struct pathdiv_t { /* _ODM_PATH_DIVERSITY_ */ 674 u8 RespTxPath; 675 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM]; 676 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 677 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM]; 678 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 679 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM]; 680 }; 681 682 enum phy_reg_pg_type { /* _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE */ 683 PHY_REG_PG_RELATIVE_VALUE = 0, 684 PHY_REG_PG_EXACT_VALUE = 1 685 }; 686 687 /* */ 688 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */ 689 /* */ 690 struct ant_detected_info { 691 bool bAntDetected; 692 u32 dBForAntA; 693 u32 dBForAntB; 694 u32 dBForAntO; 695 }; 696 697 /* */ 698 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */ 699 /* */ 700 struct dm_odm_t { /* DM_Out_Source_Dynamic_Mechanism_Structure */ 701 /* struct timer_list FastAntTrainingTimer; */ 702 /* */ 703 /* Add for different team use temporarily */ 704 /* */ 705 struct adapter *Adapter; /* For CE/NIC team */ 706 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */ 707 bool odm_ready; 708 709 enum phy_reg_pg_type PhyRegPgValueType; 710 u8 PhyRegPgVersion; 711 712 u32 NumQryPhyStatusAll; /* CCK + OFDM */ 713 u32 LastNumQryPhyStatusAll; 714 u32 RxPWDBAve; 715 bool MPDIG_2G; /* off MPDIG */ 716 u8 Times_2G; 717 718 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 719 bool bCckHighPower; 720 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */ 721 u8 ControlChannel; 722 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */ 723 724 /* REMOVED COMMON INFO---------- */ 725 /* u8 PseudoMacPhyMode; */ 726 /* bool *BTCoexist; */ 727 /* bool PseudoBtCoexist; */ 728 /* u8 OPMode; */ 729 /* bool bAPMode; */ 730 /* bool bClientMode; */ 731 /* bool bAdHocMode; */ 732 /* bool bSlaveOfDMSP; */ 733 /* REMOVED COMMON INFO---------- */ 734 735 /* 1 COMMON INFORMATION */ 736 737 /* */ 738 /* Init Value */ 739 /* */ 740 /* HOOK BEFORE REG INIT----------- */ 741 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */ 742 u8 SupportPlatform; 743 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/... = 1/2/3/... */ 744 u32 SupportAbility; 745 /* ODM PCIE/USB/SDIO = 1/2/3 */ 746 u8 SupportInterface; 747 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */ 748 u32 SupportICType; 749 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */ 750 u8 CutVersion; 751 /* Fab Version TSMC/UMC = 0/1 */ 752 u8 FabVersion; 753 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */ 754 u8 RFType; 755 u8 RFEType; 756 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */ 757 u8 BoardType; 758 u8 PackageType; 759 u8 TypeGLNA; 760 u8 TypeGPA; 761 u8 TypeALNA; 762 u8 TypeAPA; 763 /* with external LNA NO/Yes = 0/1 */ 764 u8 ExtLNA; 765 u8 ExtLNA5G; 766 /* with external PA NO/Yes = 0/1 */ 767 u8 ExtPA; 768 u8 ExtPA5G; 769 /* with external TRSW NO/Yes = 0/1 */ 770 u8 ExtTRSW; 771 u8 PatchID; /* Customer ID */ 772 bool bInHctTest; 773 bool bWIFITest; 774 775 bool bDualMacSmartConcurrent; 776 u32 BK_SupportAbility; 777 u8 AntDivType; 778 /* HOOK BEFORE REG INIT----------- */ 779 780 /* */ 781 /* Dynamic Value */ 782 /* */ 783 /* POINTER REFERENCE----------- */ 784 785 u8 u8_temp; 786 bool bool_temp; 787 struct adapter *adapter_temp; 788 789 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */ 790 u8 *pMacPhyMode; 791 /* TX Unicast byte count */ 792 u64 *pNumTxBytesUnicast; 793 /* RX Unicast byte count */ 794 u64 *pNumRxBytesUnicast; 795 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */ 796 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */ 797 /* Frequence band 2.4G/5G = 0/1 */ 798 u8 *pBandType; 799 /* Secondary channel offset don't_care/below/above = 0/1/2 */ 800 u8 *pSecChOffset; 801 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */ 802 u8 *pSecurity; 803 /* BW info 20M/40M/80M = 0/1/2 */ 804 u8 *pBandWidth; 805 /* Central channel location Ch1/Ch2/.... */ 806 u8 *pChannel; /* central channel number */ 807 bool DPK_Done; 808 /* Common info for 92D DMSP */ 809 810 bool *pbGetValueFromOtherMac; 811 struct adapter **pBuddyAdapter; 812 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */ 813 /* Common info for Status */ 814 bool *pbScanInProcess; 815 bool *pbPowerSaving; 816 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */ 817 u8 *pOnePathCCA; 818 /* pMgntInfo->AntennaTest */ 819 u8 *pAntennaTest; 820 bool *pbNet_closed; 821 u8 *mp_mode; 822 /* u8 *pAidMap; */ 823 u8 *pu1ForcedIgiLb; 824 /* For 8723B IQK----------- */ 825 bool *pIs1Antenna; 826 u8 *pRFDefaultPath; 827 /* 0:S1, 1:S0 */ 828 829 /* POINTER REFERENCE----------- */ 830 u16 *pForcedDataRate; 831 /* CALL BY VALUE------------- */ 832 bool bLinkInProcess; 833 bool bWIFI_Direct; 834 bool bWIFI_Display; 835 bool bLinked; 836 837 bool bsta_state; 838 u8 RSSI_Min; 839 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */ 840 bool bIsMPChip; 841 bool bOneEntryOnly; 842 /* Common info for BTDM */ 843 bool bBtEnabled; /* BT is disabled */ 844 bool bBtConnectProcess; /* BT HS is under connection progress. */ 845 u8 btHsRssi; /* BT HS mode wifi rssi value. */ 846 bool bBtHsOperation; /* BT HS mode is under progress */ 847 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */ 848 bool bBtLimitedDig; /* BT is busy. */ 849 /* CALL BY VALUE------------- */ 850 u8 RSSI_A; 851 u8 RSSI_B; 852 u64 RSSI_TRSW; 853 u64 RSSI_TRSW_H; 854 u64 RSSI_TRSW_L; 855 u64 RSSI_TRSW_iso; 856 857 u8 RxRate; 858 bool bNoisyState; 859 u8 TxRate; 860 u8 LinkedInterval; 861 u8 preChannel; 862 u32 TxagcOffsetValueA; 863 bool IsTxagcOffsetPositiveA; 864 u32 TxagcOffsetValueB; 865 bool IsTxagcOffsetPositiveB; 866 u64 lastTxOkCnt; 867 u64 lastRxOkCnt; 868 u32 BbSwingOffsetA; 869 bool IsBbSwingOffsetPositiveA; 870 u32 BbSwingOffsetB; 871 bool IsBbSwingOffsetPositiveB; 872 s8 TH_L2H_ini; 873 s8 TH_EDCCA_HL_diff; 874 s8 IGI_Base; 875 u8 IGI_target; 876 bool ForceEDCCA; 877 u8 AdapEn_RSSI; 878 s8 Force_TH_H; 879 s8 Force_TH_L; 880 u8 IGI_LowerBound; 881 u8 antdiv_rssi; 882 u8 AntType; 883 u8 pre_AntType; 884 u8 antdiv_period; 885 u8 antdiv_select; 886 u8 NdpaPeriod; 887 bool H2C_RARpt_connect; 888 889 /* add by Yu Cehn for adaptivtiy */ 890 bool adaptivity_flag; 891 bool NHM_disable; 892 bool TxHangFlg; 893 bool Carrier_Sense_enable; 894 u8 tolerance_cnt; 895 u64 NHMCurTxOkcnt; 896 u64 NHMCurRxOkcnt; 897 u64 NHMLastTxOkcnt; 898 u64 NHMLastRxOkcnt; 899 u8 txEdcca1; 900 u8 txEdcca0; 901 s8 H2L_lb; 902 s8 L2H_lb; 903 u8 Adaptivity_IGI_upper; 904 u8 NHM_cnt_0; 905 906 struct odm_noise_monitor noise_level;/* ODM_MAX_CHANNEL_NUM]; */ 907 /* */ 908 /* 2 Define STA info. */ 909 /* _ODM_STA_INFO */ 910 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */ 911 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM]; 912 913 /* */ 914 /* 2012/02/14 MH Add to share 88E ra with other SW team. */ 915 /* We need to colelct all support abilit to a proper area. */ 916 /* */ 917 bool RaSupport88E; 918 919 /* Define ........... */ 920 921 /* Latest packet phy info (ODM write) */ 922 struct odm_phy_dbg_info PhyDbgInfo; 923 /* PHY_INFO_88E PhyInfo; */ 924 925 /* Latest packet phy info (ODM write) */ 926 struct odm_mac_status_info *pMacInfo; 927 /* MAC_INFO_88E MacInfo; */ 928 929 /* Different Team independt structure?? */ 930 931 /* */ 932 /* TX_RTP_CMN TX_retrpo; */ 933 /* TX_RTP_88E TX_retrpo; */ 934 /* TX_RTP_8195 TX_retrpo; */ 935 936 /* */ 937 /* ODM Structure */ 938 /* */ 939 struct fat_t DM_FatTable; 940 struct dig_t DM_DigTable; 941 struct ps_t DM_PSTable; 942 struct dynamic_primary_CCA DM_PriCCA; 943 struct rxhp_t dM_RXHP_Table; 944 struct ra_t DM_RA_Table; 945 struct false_ALARM_STATISTICS FalseAlmCnt; 946 struct false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter; 947 struct swat_t DM_SWAT_Table; 948 bool RSSI_test; 949 struct cfo_tracking DM_CfoTrack; 950 951 struct edca_t DM_EDCA_Table; 952 u32 WMMEDCA_BE; 953 struct pathdiv_t DM_PathDiv; 954 /* Copy from SD4 structure */ 955 /* */ 956 /* ================================================== */ 957 /* */ 958 959 /* common */ 960 /* u8 DM_Type; */ 961 /* u8 PSD_Report_RXHP[80]; Add By Gary */ 962 /* u8 PSD_func_flag; Add By Gary */ 963 /* for DIG */ 964 /* u8 bDMInitialGainEnable; */ 965 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */ 966 /* for Antenna diversity */ 967 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */ 968 /* PSTA_INFO_T RSSI_target; */ 969 970 bool *pbDriverStopped; 971 bool *pbDriverIsGoingToPnpSetPowerSleep; 972 bool *pinit_adpt_in_progress; 973 974 /* PSD */ 975 bool bUserAssignLevel; 976 struct timer_list PSDTimer; 977 u8 RSSI_BT; /* come from BT */ 978 bool bPSDinProcess; 979 bool bPSDactive; 980 bool bDMInitialGainEnable; 981 982 /* MPT DIG */ 983 struct timer_list MPT_DIGTimer; 984 985 /* for rate adaptive, in fact, 88c/92c fw will handle this */ 986 u8 bUseRAMask; 987 988 struct odm_rate_adaptive RateAdaptive; 989 990 struct ant_detected_info AntDetectedInfo; /* Antenna detected information for RSSI tool */ 991 992 struct odm_rf_cal_t RFCalibrateInfo; 993 994 /* */ 995 /* TX power tracking */ 996 /* */ 997 u8 BbSwingIdxOfdm[MAX_RF_PATH]; 998 u8 BbSwingIdxOfdmCurrent; 999 u8 BbSwingIdxOfdmBase[MAX_RF_PATH]; 1000 bool BbSwingFlagOfdm; 1001 u8 BbSwingIdxCck; 1002 u8 BbSwingIdxCckCurrent; 1003 u8 BbSwingIdxCckBase; 1004 u8 DefaultOfdmIndex; 1005 u8 DefaultCckIndex; 1006 bool BbSwingFlagCck; 1007 1008 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH]; 1009 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH]; 1010 s8 Remnant_CCKSwingIdx; 1011 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */ 1012 bool Modify_TxAGC_Flag_PathA; 1013 bool Modify_TxAGC_Flag_PathB; 1014 bool Modify_TxAGC_Flag_PathC; 1015 bool Modify_TxAGC_Flag_PathD; 1016 bool Modify_TxAGC_Flag_PathA_CCK; 1017 1018 s8 KfreeOffset[MAX_RF_PATH]; 1019 /* */ 1020 /* ODM system resource. */ 1021 /* */ 1022 1023 /* ODM relative time. */ 1024 struct timer_list PathDivSwitchTimer; 1025 /* 2011.09.27 add for Path Diversity */ 1026 struct timer_list CCKPathDiversityTimer; 1027 struct timer_list FastAntTrainingTimer; 1028 1029 /* ODM relative workitem. */ 1030 1031 #if (BEAMFORMING_SUPPORT == 1) 1032 RT_BEAMFORMING_INFO BeamformingInfo; 1033 #endif 1034 }; 1035 1036 #define ODM_RF_PATH_MAX 2 1037 1038 enum odm_rf_radio_path_e { 1039 ODM_RF_PATH_A = 0, /* Radio Path A */ 1040 ODM_RF_PATH_B = 1, /* Radio Path B */ 1041 ODM_RF_PATH_C = 2, /* Radio Path C */ 1042 ODM_RF_PATH_D = 3, /* Radio Path D */ 1043 ODM_RF_PATH_AB, 1044 ODM_RF_PATH_AC, 1045 ODM_RF_PATH_AD, 1046 ODM_RF_PATH_BC, 1047 ODM_RF_PATH_BD, 1048 ODM_RF_PATH_CD, 1049 ODM_RF_PATH_ABC, 1050 ODM_RF_PATH_ACD, 1051 ODM_RF_PATH_BCD, 1052 ODM_RF_PATH_ABCD, 1053 /* ODM_RF_PATH_MAX, Max RF number 90 support */ 1054 }; 1055 1056 enum odm_rf_content { 1057 odm_radioa_txt = 0x1000, 1058 odm_radiob_txt = 0x1001, 1059 odm_radioc_txt = 0x1002, 1060 odm_radiod_txt = 0x1003 1061 }; 1062 1063 enum ODM_BB_Config_Type { 1064 CONFIG_BB_PHY_REG, 1065 CONFIG_BB_AGC_TAB, 1066 CONFIG_BB_AGC_TAB_2G, 1067 CONFIG_BB_AGC_TAB_5G, 1068 CONFIG_BB_PHY_REG_PG, 1069 CONFIG_BB_PHY_REG_MP, 1070 CONFIG_BB_AGC_TAB_DIFF, 1071 }; 1072 1073 enum ODM_RF_Config_Type { 1074 CONFIG_RF_RADIO, 1075 CONFIG_RF_TXPWR_LMT, 1076 }; 1077 1078 enum ODM_FW_Config_Type { 1079 CONFIG_FW_NIC, 1080 CONFIG_FW_NIC_2, 1081 CONFIG_FW_AP, 1082 CONFIG_FW_WoWLAN, 1083 CONFIG_FW_WoWLAN_2, 1084 CONFIG_FW_AP_WoWLAN, 1085 CONFIG_FW_BT, 1086 }; 1087 1088 #ifdef REMOVE_PACK 1089 #pragma pack() 1090 #endif 1091 1092 /* include "odm_function.h" */ 1093 1094 /* 3 =========================================================== */ 1095 /* 3 DIG */ 1096 /* 3 =========================================================== */ 1097 1098 /* Remove DIG by Yuchen */ 1099 1100 /* 3 =========================================================== */ 1101 /* 3 AGC RX High Power Mode */ 1102 /* 3 =========================================================== */ 1103 #define LNA_Low_Gain_1 0x64 1104 #define LNA_Low_Gain_2 0x5A 1105 #define LNA_Low_Gain_3 0x58 1106 1107 #define FA_RXHP_TH1 5000 1108 #define FA_RXHP_TH2 1500 1109 #define FA_RXHP_TH3 800 1110 #define FA_RXHP_TH4 600 1111 #define FA_RXHP_TH5 500 1112 1113 /* 3 =========================================================== */ 1114 /* 3 EDCA */ 1115 /* 3 =========================================================== */ 1116 1117 /* 3 =========================================================== */ 1118 /* 3 Dynamic Tx Power */ 1119 /* 3 =========================================================== */ 1120 /* Dynamic Tx Power Control Threshold */ 1121 1122 /* 3 =========================================================== */ 1123 /* 3 Rate Adaptive */ 1124 /* 3 =========================================================== */ 1125 #define DM_RATR_STA_INIT 0 1126 #define DM_RATR_STA_HIGH 1 1127 #define DM_RATR_STA_MIDDLE 2 1128 #define DM_RATR_STA_LOW 3 1129 1130 /* 3 =========================================================== */ 1131 /* 3 BB Power Save */ 1132 /* 3 =========================================================== */ 1133 1134 enum { /* tag_1R_CCA_Type_Definition */ 1135 CCA_1R = 0, 1136 CCA_2R = 1, 1137 CCA_MAX = 2, 1138 }; 1139 1140 enum { /* tag_RF_Type_Definition */ 1141 RF_Save = 0, 1142 RF_Normal = 1, 1143 RF_MAX = 2, 1144 }; 1145 1146 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */ 1147 #define MAX_ANTENNA_DETECTION_CNT 10 1148 1149 /* */ 1150 /* Extern Global Variables. */ 1151 /* */ 1152 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE]; 1153 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8]; 1154 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8]; 1155 1156 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE]; 1157 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8]; 1158 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]; 1159 1160 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE]; 1161 1162 /* */ 1163 /* check Sta pointer valid or not */ 1164 /* */ 1165 #define IS_STA_VALID(pSta) (pSta) 1166 /* 20100514 Joseph: Add definition for antenna switching test after link. */ 1167 /* This indicates two different the steps. */ 1168 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */ 1169 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */ 1170 /* with original RSSI to determine if it is necessary to switch antenna. */ 1171 #define SWAW_STEP_PEAK 0 1172 #define SWAW_STEP_DETERMINE 1 1173 1174 /* Remove BB power saving by Yuchen */ 1175 1176 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck 1177 void ODM_TXPowerTrackingCheck(struct dm_odm_t *pDM_Odm); 1178 1179 bool ODM_RAStateCheck( 1180 struct dm_odm_t *pDM_Odm, 1181 s32 RSSI, 1182 bool bForceUpdate, 1183 u8 *pRATRState 1184 ); 1185 1186 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi 1187 void ODM_SwAntDivChkPerPktRssi( 1188 struct dm_odm_t *pDM_Odm, 1189 u8 StationID, 1190 struct odm_phy_info *pPhyInfo 1191 ); 1192 1193 u32 ODM_Get_Rate_Bitmap( 1194 struct dm_odm_t *pDM_Odm, 1195 u32 macid, 1196 u32 ra_mask, 1197 u8 rssi_level 1198 ); 1199 1200 #if (BEAMFORMING_SUPPORT == 1) 1201 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId); 1202 #endif 1203 1204 void odm_TXPowerTrackingInit(struct dm_odm_t *pDM_Odm); 1205 1206 void ODM_DMInit(struct dm_odm_t *pDM_Odm); 1207 1208 void ODM_DMWatchdog(struct dm_odm_t *pDM_Odm); /* For common use in the future */ 1209 1210 void ODM_CmnInfoInit(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, u32 Value); 1211 1212 void ODM_CmnInfoHook(struct dm_odm_t *pDM_Odm, enum odm_cmninfo_e CmnInfo, void *pValue); 1213 1214 void ODM_CmnInfoPtrArrayHook( 1215 struct dm_odm_t *pDM_Odm, 1216 enum odm_cmninfo_e CmnInfo, 1217 u16 Index, 1218 void *pValue 1219 ); 1220 1221 void ODM_CmnInfoUpdate(struct dm_odm_t *pDM_Odm, u32 CmnInfo, u64 Value); 1222 1223 void ODM_InitAllTimers(struct dm_odm_t *pDM_Odm); 1224 1225 void ODM_CancelAllTimers(struct dm_odm_t *pDM_Odm); 1226 1227 void ODM_ReleaseAllTimers(struct dm_odm_t *pDM_Odm); 1228 1229 void ODM_AntselStatistics_88C( 1230 struct dm_odm_t *pDM_Odm, 1231 u8 MacId, 1232 u32 PWDBAll, 1233 bool isCCKrate 1234 ); 1235 1236 void ODM_DynamicARFBSelect(struct dm_odm_t *pDM_Odm, u8 rate, bool Collision_State); 1237 1238 #endif 1239