1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 #define _HAL_COM_PHYCFG_C_ 8 9 #include <drv_types.h> 10 #include <rtw_debug.h> 11 #include <hal_data.h> 12 #include <linux/kernel.h> 13 14 u8 PHY_GetTxPowerByRateBase(struct adapter *Adapter, u8 RfPath, 15 u8 TxNum, enum rate_section RateSection) 16 { 17 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 18 u8 value = 0; 19 20 if (RfPath > ODM_RF_PATH_D) 21 return 0; 22 23 switch (RateSection) { 24 case CCK: 25 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0]; 26 break; 27 case OFDM: 28 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1]; 29 break; 30 case HT_MCS0_MCS7: 31 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2]; 32 break; 33 case HT_MCS8_MCS15: 34 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][3]; 35 break; 36 case HT_MCS16_MCS23: 37 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][4]; 38 break; 39 case HT_MCS24_MCS31: 40 value = pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][5]; 41 break; 42 default: 43 break; 44 } 45 46 return value; 47 } 48 49 static void 50 phy_SetTxPowerByRateBase( 51 struct adapter *Adapter, 52 u8 RfPath, 53 enum rate_section RateSection, 54 u8 TxNum, 55 u8 Value 56 ) 57 { 58 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 59 60 if (RfPath > ODM_RF_PATH_D) 61 return; 62 63 switch (RateSection) { 64 case CCK: 65 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][0] = Value; 66 break; 67 case OFDM: 68 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][1] = Value; 69 break; 70 case HT_MCS0_MCS7: 71 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][2] = Value; 72 break; 73 case HT_MCS8_MCS15: 74 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][3] = Value; 75 break; 76 case HT_MCS16_MCS23: 77 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][4] = Value; 78 break; 79 case HT_MCS24_MCS31: 80 pHalData->TxPwrByRateBase2_4G[RfPath][TxNum][5] = Value; 81 break; 82 default: 83 break; 84 } 85 } 86 87 static void 88 phy_StoreTxPowerByRateBase( 89 struct adapter *padapter 90 ) 91 { 92 u8 path, base; 93 94 for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_B; ++path) { 95 base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_11M); 96 phy_SetTxPowerByRateBase(padapter, path, CCK, RF_1TX, base); 97 98 base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_54M); 99 phy_SetTxPowerByRateBase(padapter, path, OFDM, RF_1TX, base); 100 101 base = PHY_GetTxPowerByRate(padapter, path, RF_1TX, MGN_MCS7); 102 phy_SetTxPowerByRateBase(padapter, path, HT_MCS0_MCS7, RF_1TX, base); 103 104 base = PHY_GetTxPowerByRate(padapter, path, RF_2TX, MGN_MCS15); 105 phy_SetTxPowerByRateBase(padapter, path, HT_MCS8_MCS15, RF_2TX, base); 106 107 base = PHY_GetTxPowerByRate(padapter, path, RF_3TX, MGN_MCS23); 108 phy_SetTxPowerByRateBase(padapter, path, HT_MCS16_MCS23, RF_3TX, base); 109 110 } 111 } 112 113 u8 PHY_GetRateSectionIndexOfTxPowerByRate( 114 struct adapter *padapter, u32 RegAddr, u32 BitMask 115 ) 116 { 117 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 118 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 119 u8 index = 0; 120 121 if (pDM_Odm->PhyRegPgVersion == 0) { 122 switch (RegAddr) { 123 case rTxAGC_A_Rate18_06: 124 index = 0; 125 break; 126 case rTxAGC_A_Rate54_24: 127 index = 1; 128 break; 129 case rTxAGC_A_CCK1_Mcs32: 130 index = 6; 131 break; 132 case rTxAGC_B_CCK11_A_CCK2_11: 133 if (BitMask == bMaskH3Bytes) 134 index = 7; 135 else if (BitMask == 0x000000ff) 136 index = 15; 137 break; 138 139 case rTxAGC_A_Mcs03_Mcs00: 140 index = 2; 141 break; 142 case rTxAGC_A_Mcs07_Mcs04: 143 index = 3; 144 break; 145 case rTxAGC_A_Mcs11_Mcs08: 146 index = 4; 147 break; 148 case rTxAGC_A_Mcs15_Mcs12: 149 index = 5; 150 break; 151 case rTxAGC_B_Rate18_06: 152 index = 8; 153 break; 154 case rTxAGC_B_Rate54_24: 155 index = 9; 156 break; 157 case rTxAGC_B_CCK1_55_Mcs32: 158 index = 14; 159 break; 160 case rTxAGC_B_Mcs03_Mcs00: 161 index = 10; 162 break; 163 case rTxAGC_B_Mcs07_Mcs04: 164 index = 11; 165 break; 166 case rTxAGC_B_Mcs11_Mcs08: 167 index = 12; 168 break; 169 case rTxAGC_B_Mcs15_Mcs12: 170 index = 13; 171 break; 172 default: 173 break; 174 } 175 } 176 177 return index; 178 } 179 180 void 181 PHY_GetRateValuesOfTxPowerByRate( 182 struct adapter *padapter, 183 u32 RegAddr, 184 u32 BitMask, 185 u32 Value, 186 u8 *RateIndex, 187 s8 *PwrByRateVal, 188 u8 *RateNum 189 ) 190 { 191 u8 i = 0; 192 193 switch (RegAddr) { 194 case rTxAGC_A_Rate18_06: 195 case rTxAGC_B_Rate18_06: 196 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M); 197 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M); 198 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M); 199 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M); 200 for (i = 0; i < 4; ++i) { 201 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 202 ((Value >> (i * 8)) & 0xF)); 203 } 204 *RateNum = 4; 205 break; 206 207 case rTxAGC_A_Rate54_24: 208 case rTxAGC_B_Rate54_24: 209 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M); 210 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M); 211 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M); 212 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M); 213 for (i = 0; i < 4; ++i) { 214 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 215 ((Value >> (i * 8)) & 0xF)); 216 } 217 *RateNum = 4; 218 break; 219 220 case rTxAGC_A_CCK1_Mcs32: 221 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M); 222 PwrByRateVal[0] = (s8) ((((Value >> (8 + 4)) & 0xF)) * 10 + 223 ((Value >> 8) & 0xF)); 224 *RateNum = 1; 225 break; 226 227 case rTxAGC_B_CCK11_A_CCK2_11: 228 if (BitMask == 0xffffff00) { 229 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M); 230 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M); 231 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M); 232 for (i = 1; i < 4; ++i) { 233 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 234 ((Value >> (i * 8)) & 0xF)); 235 } 236 *RateNum = 3; 237 } else if (BitMask == 0x000000ff) { 238 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M); 239 PwrByRateVal[0] = (s8) ((((Value >> 4) & 0xF)) * 10 + (Value & 0xF)); 240 *RateNum = 1; 241 } 242 break; 243 244 case rTxAGC_A_Mcs03_Mcs00: 245 case rTxAGC_B_Mcs03_Mcs00: 246 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0); 247 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1); 248 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2); 249 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3); 250 for (i = 0; i < 4; ++i) { 251 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 252 ((Value >> (i * 8)) & 0xF)); 253 } 254 *RateNum = 4; 255 break; 256 257 case rTxAGC_A_Mcs07_Mcs04: 258 case rTxAGC_B_Mcs07_Mcs04: 259 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4); 260 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5); 261 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6); 262 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7); 263 for (i = 0; i < 4; ++i) { 264 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 265 ((Value >> (i * 8)) & 0xF)); 266 } 267 *RateNum = 4; 268 break; 269 270 case rTxAGC_A_Mcs11_Mcs08: 271 case rTxAGC_B_Mcs11_Mcs08: 272 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS8); 273 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS9); 274 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS10); 275 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS11); 276 for (i = 0; i < 4; ++i) { 277 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 278 ((Value >> (i * 8)) & 0xF)); 279 } 280 *RateNum = 4; 281 break; 282 283 case rTxAGC_A_Mcs15_Mcs12: 284 case rTxAGC_B_Mcs15_Mcs12: 285 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS12); 286 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS13); 287 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS14); 288 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS15); 289 for (i = 0; i < 4; ++i) { 290 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 291 ((Value >> (i * 8)) & 0xF)); 292 } 293 *RateNum = 4; 294 295 break; 296 297 case rTxAGC_B_CCK1_55_Mcs32: 298 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M); 299 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M); 300 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M); 301 for (i = 1; i < 4; ++i) { 302 PwrByRateVal[i - 1] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 303 ((Value >> (i * 8)) & 0xF)); 304 } 305 *RateNum = 3; 306 break; 307 308 case 0xC20: 309 case 0xE20: 310 case 0x1820: 311 case 0x1a20: 312 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_1M); 313 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_2M); 314 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_5_5M); 315 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_11M); 316 for (i = 0; i < 4; ++i) { 317 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 318 ((Value >> (i * 8)) & 0xF)); 319 } 320 *RateNum = 4; 321 break; 322 323 case 0xC24: 324 case 0xE24: 325 case 0x1824: 326 case 0x1a24: 327 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_6M); 328 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_9M); 329 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_12M); 330 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_18M); 331 for (i = 0; i < 4; ++i) { 332 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 333 ((Value >> (i * 8)) & 0xF)); 334 } 335 *RateNum = 4; 336 break; 337 338 case 0xC28: 339 case 0xE28: 340 case 0x1828: 341 case 0x1a28: 342 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_24M); 343 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_36M); 344 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_48M); 345 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_54M); 346 for (i = 0; i < 4; ++i) { 347 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 348 ((Value >> (i * 8)) & 0xF)); 349 } 350 *RateNum = 4; 351 break; 352 353 case 0xC2C: 354 case 0xE2C: 355 case 0x182C: 356 case 0x1a2C: 357 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS0); 358 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS1); 359 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS2); 360 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS3); 361 for (i = 0; i < 4; ++i) { 362 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 363 ((Value >> (i * 8)) & 0xF)); 364 } 365 *RateNum = 4; 366 break; 367 368 case 0xC30: 369 case 0xE30: 370 case 0x1830: 371 case 0x1a30: 372 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS4); 373 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS5); 374 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS6); 375 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS7); 376 for (i = 0; i < 4; ++i) { 377 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 378 ((Value >> (i * 8)) & 0xF)); 379 } 380 *RateNum = 4; 381 break; 382 383 case 0xC34: 384 case 0xE34: 385 case 0x1834: 386 case 0x1a34: 387 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS8); 388 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS9); 389 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS10); 390 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS11); 391 for (i = 0; i < 4; ++i) { 392 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 393 ((Value >> (i * 8)) & 0xF)); 394 } 395 *RateNum = 4; 396 break; 397 398 case 0xC38: 399 case 0xE38: 400 case 0x1838: 401 case 0x1a38: 402 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS12); 403 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS13); 404 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS14); 405 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS15); 406 for (i = 0; i < 4; ++i) { 407 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 408 ((Value >> (i * 8)) & 0xF)); 409 } 410 *RateNum = 4; 411 break; 412 413 case 0xCD8: 414 case 0xED8: 415 case 0x18D8: 416 case 0x1aD8: 417 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS16); 418 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS17); 419 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS18); 420 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS19); 421 for (i = 0; i < 4; ++i) { 422 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 423 ((Value >> (i * 8)) & 0xF)); 424 } 425 *RateNum = 4; 426 break; 427 428 case 0xCDC: 429 case 0xEDC: 430 case 0x18DC: 431 case 0x1aDC: 432 RateIndex[0] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS20); 433 RateIndex[1] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS21); 434 RateIndex[2] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS22); 435 RateIndex[3] = PHY_GetRateIndexOfTxPowerByRate(MGN_MCS23); 436 for (i = 0; i < 4; ++i) { 437 PwrByRateVal[i] = (s8) ((((Value >> (i * 8 + 4)) & 0xF)) * 10 + 438 ((Value >> (i * 8)) & 0xF)); 439 } 440 *RateNum = 4; 441 break; 442 443 default: 444 break; 445 } 446 } 447 448 static void PHY_StoreTxPowerByRateNew( 449 struct adapter *padapter, 450 u32 RfPath, 451 u32 TxNum, 452 u32 RegAddr, 453 u32 BitMask, 454 u32 Data 455 ) 456 { 457 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 458 u8 i = 0, rateIndex[4] = {0}, rateNum = 0; 459 s8 PwrByRateVal[4] = {0}; 460 461 PHY_GetRateValuesOfTxPowerByRate(padapter, RegAddr, BitMask, Data, rateIndex, PwrByRateVal, &rateNum); 462 463 if (RfPath > ODM_RF_PATH_D) 464 return; 465 466 if (TxNum > ODM_RF_PATH_D) 467 return; 468 469 for (i = 0; i < rateNum; ++i) { 470 pHalData->TxPwrByRateOffset[RfPath][TxNum][rateIndex[i]] = PwrByRateVal[i]; 471 } 472 } 473 474 static void PHY_StoreTxPowerByRateOld( 475 struct adapter *padapter, u32 RegAddr, u32 BitMask, u32 Data 476 ) 477 { 478 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 479 u8 index = PHY_GetRateSectionIndexOfTxPowerByRate(padapter, RegAddr, BitMask); 480 481 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][index] = Data; 482 } 483 484 void PHY_InitTxPowerByRate(struct adapter *padapter) 485 { 486 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 487 u8 rfPath, TxNum, rate; 488 489 for (rfPath = 0; rfPath < TX_PWR_BY_RATE_NUM_RF; ++rfPath) 490 for (TxNum = 0; TxNum < TX_PWR_BY_RATE_NUM_RF; ++TxNum) 491 for (rate = 0; rate < TX_PWR_BY_RATE_NUM_RATE; ++rate) 492 pHalData->TxPwrByRateOffset[rfPath][TxNum][rate] = 0; 493 } 494 495 void PHY_StoreTxPowerByRate( 496 struct adapter *padapter, 497 u32 RfPath, 498 u32 TxNum, 499 u32 RegAddr, 500 u32 BitMask, 501 u32 Data 502 ) 503 { 504 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 505 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 506 507 if (pDM_Odm->PhyRegPgVersion > 0) 508 PHY_StoreTxPowerByRateNew(padapter, RfPath, TxNum, RegAddr, BitMask, Data); 509 else if (pDM_Odm->PhyRegPgVersion == 0) { 510 PHY_StoreTxPowerByRateOld(padapter, RegAddr, BitMask, Data); 511 512 if (RegAddr == rTxAGC_A_Mcs15_Mcs12 && pHalData->rf_type == RF_1T1R) 513 pHalData->pwrGroupCnt++; 514 else if (RegAddr == rTxAGC_B_Mcs15_Mcs12 && pHalData->rf_type != RF_1T1R) 515 pHalData->pwrGroupCnt++; 516 } 517 } 518 519 static void 520 phy_ConvertTxPowerByRateInDbmToRelativeValues( 521 struct adapter *padapter 522 ) 523 { 524 u8 base = 0, i = 0, value = 0, path = 0, txNum = 0; 525 u8 cckRates[4] = { 526 MGN_1M, MGN_2M, MGN_5_5M, MGN_11M 527 }; 528 u8 ofdmRates[8] = { 529 MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M 530 }; 531 u8 mcs0_7Rates[8] = { 532 MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7 533 }; 534 u8 mcs8_15Rates[8] = { 535 MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15 536 }; 537 u8 mcs16_23Rates[8] = { 538 MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23 539 }; 540 541 for (path = ODM_RF_PATH_A; path <= ODM_RF_PATH_D; ++path) { 542 for (txNum = RF_1TX; txNum < RF_MAX_TX_NUM; ++txNum) { 543 /* CCK */ 544 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_11M); 545 for (i = 0; i < ARRAY_SIZE(cckRates); ++i) { 546 value = PHY_GetTxPowerByRate(padapter, path, txNum, cckRates[i]); 547 PHY_SetTxPowerByRate(padapter, path, txNum, cckRates[i], value - base); 548 } 549 550 /* OFDM */ 551 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_54M); 552 for (i = 0; i < sizeof(ofdmRates); ++i) { 553 value = PHY_GetTxPowerByRate(padapter, path, txNum, ofdmRates[i]); 554 PHY_SetTxPowerByRate(padapter, path, txNum, ofdmRates[i], value - base); 555 } 556 557 /* HT MCS0~7 */ 558 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_MCS7); 559 for (i = 0; i < sizeof(mcs0_7Rates); ++i) { 560 value = PHY_GetTxPowerByRate(padapter, path, txNum, mcs0_7Rates[i]); 561 PHY_SetTxPowerByRate(padapter, path, txNum, mcs0_7Rates[i], value - base); 562 } 563 564 /* HT MCS8~15 */ 565 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_MCS15); 566 for (i = 0; i < sizeof(mcs8_15Rates); ++i) { 567 value = PHY_GetTxPowerByRate(padapter, path, txNum, mcs8_15Rates[i]); 568 PHY_SetTxPowerByRate(padapter, path, txNum, mcs8_15Rates[i], value - base); 569 } 570 571 /* HT MCS16~23 */ 572 base = PHY_GetTxPowerByRate(padapter, path, txNum, MGN_MCS23); 573 for (i = 0; i < sizeof(mcs16_23Rates); ++i) { 574 value = PHY_GetTxPowerByRate(padapter, path, txNum, mcs16_23Rates[i]); 575 PHY_SetTxPowerByRate(padapter, path, txNum, mcs16_23Rates[i], value - base); 576 } 577 } 578 } 579 } 580 581 /* 582 * This function must be called if the value in the PHY_REG_PG.txt(or header) 583 * is exact dBm values 584 */ 585 void PHY_TxPowerByRateConfiguration(struct adapter *padapter) 586 { 587 phy_StoreTxPowerByRateBase(padapter); 588 phy_ConvertTxPowerByRateInDbmToRelativeValues(padapter); 589 } 590 591 void PHY_SetTxPowerIndexByRateSection( 592 struct adapter *padapter, u8 RFPath, u8 Channel, u8 RateSection 593 ) 594 { 595 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 596 597 if (RateSection == CCK) { 598 u8 cckRates[] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M}; 599 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 600 pHalData->CurrentChannelBW, 601 Channel, cckRates, 602 ARRAY_SIZE(cckRates)); 603 604 } else if (RateSection == OFDM) { 605 u8 ofdmRates[] = {MGN_6M, MGN_9M, MGN_12M, MGN_18M, MGN_24M, MGN_36M, MGN_48M, MGN_54M}; 606 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 607 pHalData->CurrentChannelBW, 608 Channel, ofdmRates, 609 ARRAY_SIZE(ofdmRates)); 610 611 } else if (RateSection == HT_MCS0_MCS7) { 612 u8 htRates1T[] = {MGN_MCS0, MGN_MCS1, MGN_MCS2, MGN_MCS3, MGN_MCS4, MGN_MCS5, MGN_MCS6, MGN_MCS7}; 613 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 614 pHalData->CurrentChannelBW, 615 Channel, htRates1T, 616 ARRAY_SIZE(htRates1T)); 617 618 } else if (RateSection == HT_MCS8_MCS15) { 619 u8 htRates2T[] = {MGN_MCS8, MGN_MCS9, MGN_MCS10, MGN_MCS11, MGN_MCS12, MGN_MCS13, MGN_MCS14, MGN_MCS15}; 620 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 621 pHalData->CurrentChannelBW, 622 Channel, htRates2T, 623 ARRAY_SIZE(htRates2T)); 624 625 } else if (RateSection == HT_MCS16_MCS23) { 626 u8 htRates3T[] = {MGN_MCS16, MGN_MCS17, MGN_MCS18, MGN_MCS19, MGN_MCS20, MGN_MCS21, MGN_MCS22, MGN_MCS23}; 627 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 628 pHalData->CurrentChannelBW, 629 Channel, htRates3T, 630 ARRAY_SIZE(htRates3T)); 631 632 } else if (RateSection == HT_MCS24_MCS31) { 633 u8 htRates4T[] = {MGN_MCS24, MGN_MCS25, MGN_MCS26, MGN_MCS27, MGN_MCS28, MGN_MCS29, MGN_MCS30, MGN_MCS31}; 634 PHY_SetTxPowerIndexByRateArray(padapter, RFPath, 635 pHalData->CurrentChannelBW, 636 Channel, htRates4T, 637 ARRAY_SIZE(htRates4T)); 638 639 } 640 } 641 642 u8 PHY_GetTxPowerIndexBase( 643 struct adapter *padapter, 644 u8 RFPath, 645 u8 Rate, 646 enum channel_width BandWidth, 647 u8 Channel 648 ) 649 { 650 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 651 u8 txPower = 0; 652 u8 chnlIdx = (Channel-1); 653 654 if (HAL_IsLegalChannel(padapter, Channel) == false) 655 chnlIdx = 0; 656 657 if (IS_CCK_RATE(Rate)) 658 txPower = pHalData->Index24G_CCK_Base[RFPath][chnlIdx]; 659 else if (MGN_6M <= Rate) 660 txPower = pHalData->Index24G_BW40_Base[RFPath][chnlIdx]; 661 662 /* OFDM-1T */ 663 if ((MGN_6M <= Rate && Rate <= MGN_54M) && !IS_CCK_RATE(Rate)) 664 txPower += pHalData->OFDM_24G_Diff[RFPath][TX_1S]; 665 666 if (BandWidth == CHANNEL_WIDTH_20) { /* BW20-1S, BW20-2S */ 667 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) 668 txPower += pHalData->BW20_24G_Diff[RFPath][TX_1S]; 669 if (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) 670 txPower += pHalData->BW20_24G_Diff[RFPath][TX_2S]; 671 if (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) 672 txPower += pHalData->BW20_24G_Diff[RFPath][TX_3S]; 673 if (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) 674 txPower += pHalData->BW20_24G_Diff[RFPath][TX_4S]; 675 676 } else if (BandWidth == CHANNEL_WIDTH_40) { /* BW40-1S, BW40-2S */ 677 if (MGN_MCS0 <= Rate && Rate <= MGN_MCS31) 678 txPower += pHalData->BW40_24G_Diff[RFPath][TX_1S]; 679 if (MGN_MCS8 <= Rate && Rate <= MGN_MCS31) 680 txPower += pHalData->BW40_24G_Diff[RFPath][TX_2S]; 681 if (MGN_MCS16 <= Rate && Rate <= MGN_MCS31) 682 txPower += pHalData->BW40_24G_Diff[RFPath][TX_3S]; 683 if (MGN_MCS24 <= Rate && Rate <= MGN_MCS31) 684 txPower += pHalData->BW40_24G_Diff[RFPath][TX_4S]; 685 686 } 687 688 return txPower; 689 } 690 691 s8 PHY_GetTxPowerTrackingOffset(struct adapter *padapter, u8 RFPath, u8 Rate) 692 { 693 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 694 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 695 s8 offset = 0; 696 697 if (pDM_Odm->RFCalibrateInfo.TxPowerTrackControl == false) 698 return offset; 699 700 if ((Rate == MGN_1M) || (Rate == MGN_2M) || (Rate == MGN_5_5M) || (Rate == MGN_11M)) 701 offset = pDM_Odm->Remnant_CCKSwingIdx; 702 else 703 offset = pDM_Odm->Remnant_OFDMSwingIdx[RFPath]; 704 705 return offset; 706 } 707 708 u8 PHY_GetRateIndexOfTxPowerByRate(u8 Rate) 709 { 710 u8 index = 0; 711 switch (Rate) { 712 case MGN_1M: 713 index = 0; 714 break; 715 case MGN_2M: 716 index = 1; 717 break; 718 case MGN_5_5M: 719 index = 2; 720 break; 721 case MGN_11M: 722 index = 3; 723 break; 724 case MGN_6M: 725 index = 4; 726 break; 727 case MGN_9M: 728 index = 5; 729 break; 730 case MGN_12M: 731 index = 6; 732 break; 733 case MGN_18M: 734 index = 7; 735 break; 736 case MGN_24M: 737 index = 8; 738 break; 739 case MGN_36M: 740 index = 9; 741 break; 742 case MGN_48M: 743 index = 10; 744 break; 745 case MGN_54M: 746 index = 11; 747 break; 748 case MGN_MCS0: 749 index = 12; 750 break; 751 case MGN_MCS1: 752 index = 13; 753 break; 754 case MGN_MCS2: 755 index = 14; 756 break; 757 case MGN_MCS3: 758 index = 15; 759 break; 760 case MGN_MCS4: 761 index = 16; 762 break; 763 case MGN_MCS5: 764 index = 17; 765 break; 766 case MGN_MCS6: 767 index = 18; 768 break; 769 case MGN_MCS7: 770 index = 19; 771 break; 772 case MGN_MCS8: 773 index = 20; 774 break; 775 case MGN_MCS9: 776 index = 21; 777 break; 778 case MGN_MCS10: 779 index = 22; 780 break; 781 case MGN_MCS11: 782 index = 23; 783 break; 784 case MGN_MCS12: 785 index = 24; 786 break; 787 case MGN_MCS13: 788 index = 25; 789 break; 790 case MGN_MCS14: 791 index = 26; 792 break; 793 case MGN_MCS15: 794 index = 27; 795 break; 796 case MGN_MCS16: 797 index = 28; 798 break; 799 case MGN_MCS17: 800 index = 29; 801 break; 802 case MGN_MCS18: 803 index = 30; 804 break; 805 case MGN_MCS19: 806 index = 31; 807 break; 808 case MGN_MCS20: 809 index = 32; 810 break; 811 case MGN_MCS21: 812 index = 33; 813 break; 814 case MGN_MCS22: 815 index = 34; 816 break; 817 case MGN_MCS23: 818 index = 35; 819 break; 820 case MGN_MCS24: 821 index = 36; 822 break; 823 case MGN_MCS25: 824 index = 37; 825 break; 826 case MGN_MCS26: 827 index = 38; 828 break; 829 case MGN_MCS27: 830 index = 39; 831 break; 832 case MGN_MCS28: 833 index = 40; 834 break; 835 case MGN_MCS29: 836 index = 41; 837 break; 838 case MGN_MCS30: 839 index = 42; 840 break; 841 case MGN_MCS31: 842 index = 43; 843 break; 844 default: 845 break; 846 } 847 return index; 848 } 849 850 s8 PHY_GetTxPowerByRate( 851 struct adapter *padapter, u8 RFPath, u8 TxNum, u8 Rate 852 ) 853 { 854 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 855 s8 value = 0; 856 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); 857 858 if ((padapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory == 2) || 859 padapter->registrypriv.RegEnableTxPowerByRate == 0) 860 return 0; 861 862 if (RFPath > ODM_RF_PATH_D) 863 return value; 864 865 if (TxNum >= RF_MAX_TX_NUM) 866 return value; 867 868 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) 869 return value; 870 871 return pHalData->TxPwrByRateOffset[RFPath][TxNum][rateIndex]; 872 873 } 874 875 void PHY_SetTxPowerByRate( 876 struct adapter *padapter, 877 u8 RFPath, 878 u8 TxNum, 879 u8 Rate, 880 s8 Value 881 ) 882 { 883 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 884 u8 rateIndex = PHY_GetRateIndexOfTxPowerByRate(Rate); 885 886 if (RFPath > ODM_RF_PATH_D) 887 return; 888 889 if (TxNum >= RF_MAX_TX_NUM) 890 return; 891 892 if (rateIndex >= TX_PWR_BY_RATE_NUM_RATE) 893 return; 894 895 pHalData->TxPwrByRateOffset[RFPath][TxNum][rateIndex] = Value; 896 } 897 898 void PHY_SetTxPowerLevelByPath(struct adapter *Adapter, u8 channel, u8 path) 899 { 900 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 901 902 /* if (pMgntInfo->RegNByteAccess == 0) */ 903 { 904 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, CCK); 905 906 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, OFDM); 907 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS0_MCS7); 908 909 if (pHalData->NumTotalRFPath >= 2) 910 PHY_SetTxPowerIndexByRateSection(Adapter, path, channel, HT_MCS8_MCS15); 911 912 } 913 } 914 915 void PHY_SetTxPowerIndexByRateArray( 916 struct adapter *padapter, 917 u8 RFPath, 918 enum channel_width BandWidth, 919 u8 Channel, 920 u8 *Rates, 921 u8 RateArraySize 922 ) 923 { 924 u32 powerIndex = 0; 925 int i = 0; 926 927 for (i = 0; i < RateArraySize; ++i) { 928 powerIndex = PHY_GetTxPowerIndex(padapter, RFPath, Rates[i], BandWidth, Channel); 929 PHY_SetTxPowerIndex(padapter, powerIndex, RFPath, Rates[i]); 930 } 931 } 932 933 static s8 phy_GetWorldWideLimit(s8 *LimitTable) 934 { 935 s8 min = LimitTable[0]; 936 u8 i = 0; 937 938 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 939 if (LimitTable[i] < min) 940 min = LimitTable[i]; 941 } 942 943 return min; 944 } 945 946 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Channel) 947 { 948 return Channel - 1; 949 } 950 951 static s16 get_bandwidth_idx(const enum channel_width bandwidth) 952 { 953 switch (bandwidth) { 954 case CHANNEL_WIDTH_20: 955 return 0; 956 case CHANNEL_WIDTH_40: 957 return 1; 958 default: 959 return -1; 960 } 961 } 962 963 static s16 get_rate_sctn_idx(const u8 rate) 964 { 965 switch (rate) { 966 case MGN_1M: case MGN_2M: case MGN_5_5M: case MGN_11M: 967 return 0; 968 case MGN_6M: case MGN_9M: case MGN_12M: case MGN_18M: 969 case MGN_24M: case MGN_36M: case MGN_48M: case MGN_54M: 970 return 1; 971 case MGN_MCS0: case MGN_MCS1: case MGN_MCS2: case MGN_MCS3: 972 case MGN_MCS4: case MGN_MCS5: case MGN_MCS6: case MGN_MCS7: 973 return 2; 974 case MGN_MCS8: case MGN_MCS9: case MGN_MCS10: case MGN_MCS11: 975 case MGN_MCS12: case MGN_MCS13: case MGN_MCS14: case MGN_MCS15: 976 return 3; 977 case MGN_MCS16: case MGN_MCS17: case MGN_MCS18: case MGN_MCS19: 978 case MGN_MCS20: case MGN_MCS21: case MGN_MCS22: case MGN_MCS23: 979 return 4; 980 case MGN_MCS24: case MGN_MCS25: case MGN_MCS26: case MGN_MCS27: 981 case MGN_MCS28: case MGN_MCS29: case MGN_MCS30: case MGN_MCS31: 982 return 5; 983 default: 984 return -1; 985 } 986 } 987 988 s8 phy_get_tx_pwr_lmt(struct adapter *adapter, u32 reg_pwr_tbl_sel, 989 enum channel_width bandwidth, 990 u8 rf_path, u8 data_rate, u8 channel) 991 { 992 s16 idx_regulation = -1; 993 s16 idx_bandwidth = -1; 994 s16 idx_rate_sctn = -1; 995 s16 idx_channel = -1; 996 s8 pwr_lmt = MAX_POWER_INDEX; 997 struct hal_com_data *hal_data = GET_HAL_DATA(adapter); 998 s8 limits[10] = {0}; u8 i = 0; 999 1000 if (((adapter->registrypriv.RegEnableTxPowerLimit == 2) && 1001 (hal_data->EEPROMRegulatory != 1)) || 1002 (adapter->registrypriv.RegEnableTxPowerLimit == 0)) 1003 return MAX_POWER_INDEX; 1004 1005 switch (adapter->registrypriv.RegPwrTblSel) { 1006 case 1: 1007 idx_regulation = TXPWR_LMT_ETSI; 1008 break; 1009 case 2: 1010 idx_regulation = TXPWR_LMT_MKK; 1011 break; 1012 case 3: 1013 idx_regulation = TXPWR_LMT_FCC; 1014 break; 1015 case 4: 1016 idx_regulation = TXPWR_LMT_WW; 1017 break; 1018 default: 1019 idx_regulation = hal_data->Regulation2_4G; 1020 break; 1021 } 1022 1023 idx_bandwidth = get_bandwidth_idx(bandwidth); 1024 idx_rate_sctn = get_rate_sctn_idx(data_rate); 1025 1026 /* workaround for wrong index combination to obtain tx power limit, */ 1027 /* OFDM only exists in BW 20M */ 1028 /* CCK table will only be given in BW 20M */ 1029 /* HT on 80M will reference to HT on 40M */ 1030 if (idx_rate_sctn == 0 || idx_rate_sctn == 1) 1031 idx_bandwidth = 0; 1032 1033 channel = phy_GetChannelIndexOfTxPowerLimit(channel); 1034 1035 if (idx_regulation == -1 || idx_bandwidth == -1 || 1036 idx_rate_sctn == -1 || idx_channel == -1) 1037 return MAX_POWER_INDEX; 1038 1039 1040 for (i = 0; i < MAX_REGULATION_NUM; i++) 1041 limits[i] = hal_data->TxPwrLimit_2_4G[i] 1042 [idx_bandwidth] 1043 [idx_rate_sctn] 1044 [idx_channel] 1045 [rf_path]; 1046 1047 pwr_lmt = (idx_regulation == TXPWR_LMT_WW) ? 1048 phy_GetWorldWideLimit(limits) : 1049 hal_data->TxPwrLimit_2_4G[idx_regulation] 1050 [idx_bandwidth] 1051 [idx_rate_sctn] 1052 [idx_channel] 1053 [rf_path]; 1054 1055 return pwr_lmt; 1056 } 1057 1058 void PHY_ConvertTxPowerLimitToPowerIndex(struct adapter *Adapter) 1059 { 1060 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1061 u8 BW40PwrBasedBm2_4G = 0x2E; 1062 u8 regulation, bw, channel, rateSection; 1063 s8 tempValue = 0, tempPwrLmt = 0; 1064 u8 rfPath = 0; 1065 1066 for (regulation = 0; regulation < MAX_REGULATION_NUM; ++regulation) { 1067 for (bw = 0; bw < MAX_2_4G_BANDWIDTH_NUM; ++bw) { 1068 for (channel = 0; channel < CHANNEL_MAX_NUMBER_2G; ++channel) { 1069 for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) { 1070 tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A]; 1071 1072 for (rfPath = ODM_RF_PATH_A; rfPath < MAX_RF_PATH_NUM; ++rfPath) { 1073 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE) { 1074 if (rateSection == 5) /* HT 4T */ 1075 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_4TX, HT_MCS24_MCS31); 1076 else if (rateSection == 4) /* HT 3T */ 1077 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_3TX, HT_MCS16_MCS23); 1078 else if (rateSection == 3) /* HT 2T */ 1079 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_2TX, HT_MCS8_MCS15); 1080 else if (rateSection == 2) /* HT 1T */ 1081 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, HT_MCS0_MCS7); 1082 else if (rateSection == 1) /* OFDM */ 1083 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, OFDM); 1084 else if (rateSection == 0) /* CCK */ 1085 BW40PwrBasedBm2_4G = PHY_GetTxPowerByRateBase(Adapter, rfPath, RF_1TX, CCK); 1086 } else 1087 BW40PwrBasedBm2_4G = Adapter->registrypriv.RegPowerBase * 2; 1088 1089 if (tempPwrLmt != MAX_POWER_INDEX) { 1090 tempValue = tempPwrLmt - BW40PwrBasedBm2_4G; 1091 pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue; 1092 } 1093 } 1094 } 1095 } 1096 } 1097 } 1098 } 1099 1100 void PHY_InitTxPowerLimit(struct adapter *Adapter) 1101 { 1102 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1103 u8 i, j, k, l, m; 1104 1105 for (i = 0; i < MAX_REGULATION_NUM; ++i) { 1106 for (j = 0; j < MAX_2_4G_BANDWIDTH_NUM; ++j) 1107 for (k = 0; k < MAX_RATE_SECTION_NUM; ++k) 1108 for (m = 0; m < CHANNEL_MAX_NUMBER_2G; ++m) 1109 for (l = 0; l < MAX_RF_PATH_NUM; ++l) 1110 pHalData->TxPwrLimit_2_4G[i][j][k][m][l] = MAX_POWER_INDEX; 1111 } 1112 } 1113 1114 void PHY_SetTxPowerLimit( 1115 struct adapter *Adapter, 1116 u8 *Regulation, 1117 u8 *Bandwidth, 1118 u8 *RateSection, 1119 u8 *RfPath, 1120 u8 *Channel, 1121 u8 *PowerLimit 1122 ) 1123 { 1124 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1125 u8 regulation = 0, bandwidth = 0, rateSection = 0, channel; 1126 s8 powerLimit = 0, prevPowerLimit, channelIndex; 1127 1128 GetU1ByteIntegerFromStringInDecimal((s8 *)Channel, &channel); 1129 GetU1ByteIntegerFromStringInDecimal((s8 *)PowerLimit, &powerLimit); 1130 1131 powerLimit = powerLimit > MAX_POWER_INDEX ? MAX_POWER_INDEX : powerLimit; 1132 1133 if (eqNByte(Regulation, (u8 *)("FCC"), 3)) 1134 regulation = 0; 1135 else if (eqNByte(Regulation, (u8 *)("MKK"), 3)) 1136 regulation = 1; 1137 else if (eqNByte(Regulation, (u8 *)("ETSI"), 4)) 1138 regulation = 2; 1139 else if (eqNByte(Regulation, (u8 *)("WW13"), 4)) 1140 regulation = 3; 1141 1142 if (eqNByte(RateSection, (u8 *)("CCK"), 3) && eqNByte(RfPath, (u8 *)("1T"), 2)) 1143 rateSection = 0; 1144 else if (eqNByte(RateSection, (u8 *)("OFDM"), 4) && eqNByte(RfPath, (u8 *)("1T"), 2)) 1145 rateSection = 1; 1146 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("1T"), 2)) 1147 rateSection = 2; 1148 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("2T"), 2)) 1149 rateSection = 3; 1150 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("3T"), 2)) 1151 rateSection = 4; 1152 else if (eqNByte(RateSection, (u8 *)("HT"), 2) && eqNByte(RfPath, (u8 *)("4T"), 2)) 1153 rateSection = 5; 1154 else 1155 return; 1156 1157 if (eqNByte(Bandwidth, (u8 *)("20M"), 3)) 1158 bandwidth = 0; 1159 else if (eqNByte(Bandwidth, (u8 *)("40M"), 3)) 1160 bandwidth = 1; 1161 else if (eqNByte(Bandwidth, (u8 *)("80M"), 3)) 1162 bandwidth = 2; 1163 else if (eqNByte(Bandwidth, (u8 *)("160M"), 4)) 1164 bandwidth = 3; 1165 1166 channelIndex = phy_GetChannelIndexOfTxPowerLimit(channel); 1167 1168 if (channelIndex == -1) 1169 return; 1170 1171 prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A]; 1172 1173 if (powerLimit < prevPowerLimit) 1174 pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit; 1175 } 1176 1177 void Hal_ChannelPlanToRegulation(struct adapter *Adapter, u16 ChannelPlan) 1178 { 1179 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 1180 pHalData->Regulation2_4G = TXPWR_LMT_WW; 1181 1182 switch (ChannelPlan) { 1183 case RT_CHANNEL_DOMAIN_WORLD_NULL: 1184 pHalData->Regulation2_4G = TXPWR_LMT_WW; 1185 break; 1186 case RT_CHANNEL_DOMAIN_ETSI1_NULL: 1187 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1188 break; 1189 case RT_CHANNEL_DOMAIN_FCC1_NULL: 1190 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1191 break; 1192 case RT_CHANNEL_DOMAIN_MKK1_NULL: 1193 pHalData->Regulation2_4G = TXPWR_LMT_MKK; 1194 break; 1195 case RT_CHANNEL_DOMAIN_ETSI2_NULL: 1196 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1197 break; 1198 case RT_CHANNEL_DOMAIN_FCC1_FCC1: 1199 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1200 break; 1201 case RT_CHANNEL_DOMAIN_WORLD_ETSI1: 1202 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1203 break; 1204 case RT_CHANNEL_DOMAIN_MKK1_MKK1: 1205 pHalData->Regulation2_4G = TXPWR_LMT_MKK; 1206 break; 1207 case RT_CHANNEL_DOMAIN_WORLD_KCC1: 1208 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1209 break; 1210 case RT_CHANNEL_DOMAIN_WORLD_FCC2: 1211 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1212 break; 1213 case RT_CHANNEL_DOMAIN_WORLD_FCC3: 1214 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1215 break; 1216 case RT_CHANNEL_DOMAIN_WORLD_FCC4: 1217 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1218 break; 1219 case RT_CHANNEL_DOMAIN_WORLD_FCC5: 1220 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1221 break; 1222 case RT_CHANNEL_DOMAIN_WORLD_FCC6: 1223 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1224 break; 1225 case RT_CHANNEL_DOMAIN_FCC1_FCC7: 1226 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1227 break; 1228 case RT_CHANNEL_DOMAIN_WORLD_ETSI2: 1229 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1230 break; 1231 case RT_CHANNEL_DOMAIN_WORLD_ETSI3: 1232 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1233 break; 1234 case RT_CHANNEL_DOMAIN_MKK1_MKK2: 1235 pHalData->Regulation2_4G = TXPWR_LMT_MKK; 1236 break; 1237 case RT_CHANNEL_DOMAIN_MKK1_MKK3: 1238 pHalData->Regulation2_4G = TXPWR_LMT_MKK; 1239 break; 1240 case RT_CHANNEL_DOMAIN_FCC1_NCC1: 1241 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1242 break; 1243 case RT_CHANNEL_DOMAIN_FCC1_NCC2: 1244 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1245 break; 1246 case RT_CHANNEL_DOMAIN_GLOBAL_NULL: 1247 pHalData->Regulation2_4G = TXPWR_LMT_WW; 1248 break; 1249 case RT_CHANNEL_DOMAIN_ETSI1_ETSI4: 1250 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1251 break; 1252 case RT_CHANNEL_DOMAIN_FCC1_FCC2: 1253 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1254 break; 1255 case RT_CHANNEL_DOMAIN_FCC1_NCC3: 1256 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1257 break; 1258 case RT_CHANNEL_DOMAIN_WORLD_ETSI5: 1259 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1260 break; 1261 case RT_CHANNEL_DOMAIN_FCC1_FCC8: 1262 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1263 break; 1264 case RT_CHANNEL_DOMAIN_WORLD_ETSI6: 1265 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1266 break; 1267 case RT_CHANNEL_DOMAIN_WORLD_ETSI7: 1268 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1269 break; 1270 case RT_CHANNEL_DOMAIN_WORLD_ETSI8: 1271 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1272 break; 1273 case RT_CHANNEL_DOMAIN_WORLD_ETSI9: 1274 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1275 break; 1276 case RT_CHANNEL_DOMAIN_WORLD_ETSI10: 1277 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1278 break; 1279 case RT_CHANNEL_DOMAIN_WORLD_ETSI11: 1280 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1281 break; 1282 case RT_CHANNEL_DOMAIN_FCC1_NCC4: 1283 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1284 break; 1285 case RT_CHANNEL_DOMAIN_WORLD_ETSI12: 1286 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1287 break; 1288 case RT_CHANNEL_DOMAIN_FCC1_FCC9: 1289 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1290 break; 1291 case RT_CHANNEL_DOMAIN_WORLD_ETSI13: 1292 pHalData->Regulation2_4G = TXPWR_LMT_ETSI; 1293 break; 1294 case RT_CHANNEL_DOMAIN_FCC1_FCC10: 1295 pHalData->Regulation2_4G = TXPWR_LMT_FCC; 1296 break; 1297 case RT_CHANNEL_DOMAIN_REALTEK_DEFINE: /* Realtek Reserve */ 1298 pHalData->Regulation2_4G = TXPWR_LMT_WW; 1299 break; 1300 default: 1301 break; 1302 } 1303 } 1304