1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 #include <drv_types.h> 9 #include <rtw_debug.h> 10 #include "odm_precomp.h" 11 12 13 14 /*---------------------------Define Local Constant---------------------------*/ 15 /* 2010/04/25 MH Define the max tx power tracking tx agc power. */ 16 #define ODM_TXPWRTRACK_MAX_IDX8723B 6 17 18 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */ 19 #define PATH_S0 1 /* RF_PATH_B */ 20 #define IDX_0xC94 0 21 #define IDX_0xC80 1 22 #define IDX_0xC4C 2 23 #define IDX_0xC14 0 24 #define IDX_0xCA0 1 25 #define KEY 0 26 #define VAL 1 27 28 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */ 29 #define PATH_S1 0 /* RF_PATH_A */ 30 #define IDX_0xC9C 0 31 #define IDX_0xC88 1 32 #define IDX_0xC4C 2 33 #define IDX_0xC1C 0 34 #define IDX_0xC78 1 35 36 37 /*---------------------------Define Local Constant---------------------------*/ 38 39 /* In the case that we fail to read TxPowerTrack.txt, we use the table for 40 * 88E as the default table. 41 */ 42 static u8 DeltaSwingTableIdx_2GA_N_8188E[] = { 43 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 44 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 45 }; 46 static u8 DeltaSwingTableIdx_2GA_P_8188E[] = { 47 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 48 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9 49 }; 50 51 /* 3 ============================================================ */ 52 /* 3 Tx Power Tracking */ 53 /* 3 ============================================================ */ 54 55 56 static void setIqkMatrix_8723B( 57 PDM_ODM_T pDM_Odm, 58 u8 OFDM_index, 59 u8 RFPath, 60 s32 IqkResult_X, 61 s32 IqkResult_Y 62 ) 63 { 64 s32 ele_A = 0, ele_D, ele_C = 0, value32; 65 66 if (OFDM_index >= OFDM_TABLE_SIZE) 67 OFDM_index = OFDM_TABLE_SIZE-1; 68 69 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; 70 71 /* new element A = element D x X */ 72 if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { 73 if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ 74 IqkResult_X = IqkResult_X | 0xFFFFFC00; 75 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; 76 77 /* new element C = element D x Y */ 78 if ((IqkResult_Y & 0x00000200) != 0) 79 IqkResult_Y = IqkResult_Y | 0xFFFFFC00; 80 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; 81 82 /* if (RFPath == ODM_RF_PATH_A) */ 83 switch (RFPath) { 84 case ODM_RF_PATH_A: 85 /* wirte new elements A, C, D to regC80 and regC94, element B is always 0 */ 86 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; 87 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32); 88 89 value32 = (ele_C&0x000003C0)>>6; 90 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); 91 92 value32 = ((IqkResult_X * ele_D)>>7)&0x01; 93 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); 94 break; 95 case ODM_RF_PATH_B: 96 /* wirte new elements A, C, D to regC88 and regC9C, element B is always 0 */ 97 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; 98 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); 99 100 value32 = (ele_C&0x000003C0)>>6; 101 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); 102 103 value32 = ((IqkResult_X * ele_D)>>7)&0x01; 104 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); 105 106 break; 107 default: 108 break; 109 } 110 } else { 111 switch (RFPath) { 112 case ODM_RF_PATH_A: 113 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 114 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); 115 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); 116 break; 117 118 case ODM_RF_PATH_B: 119 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 120 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); 121 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); 122 break; 123 124 default: 125 break; 126 } 127 } 128 129 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", 130 (u32)IqkResult_X, (u32)IqkResult_Y, (u32)ele_A, (u32)ele_C, (u32)ele_D, (u32)IqkResult_X, (u32)IqkResult_Y)); 131 } 132 133 134 static void setCCKFilterCoefficient(PDM_ODM_T pDM_Odm, u8 CCKSwingIndex) 135 { 136 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { 137 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); 138 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); 139 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); 140 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); 141 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); 142 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); 143 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); 144 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); 145 } else { 146 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); 147 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); 148 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); 149 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); 150 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); 151 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); 152 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); 153 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); 154 } 155 } 156 157 void DoIQK_8723B( 158 PDM_ODM_T pDM_Odm, 159 u8 DeltaThermalIndex, 160 u8 ThermalValue, 161 u8 Threshold 162 ) 163 { 164 } 165 166 /*----------------------------------------------------------------------------- 167 * Function: odm_TxPwrTrackSetPwr88E() 168 * 169 * Overview: 88E change all channel tx power accordign to flag. 170 * OFDM & CCK are all different. 171 * 172 * Input: NONE 173 * 174 * Output: NONE 175 * 176 * Return: NONE 177 * 178 * Revised History: 179 *When Who Remark 180 *04/23/2012 MHC Create Version 0. 181 * 182 *---------------------------------------------------------------------------*/ 183 void ODM_TxPwrTrackSetPwr_8723B( 184 PDM_ODM_T pDM_Odm, 185 PWRTRACK_METHOD Method, 186 u8 RFPath, 187 u8 ChannelMappedIndex 188 ) 189 { 190 struct adapter *Adapter = pDM_Odm->Adapter; 191 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 192 u8 PwrTrackingLimit_OFDM = 34; /* 0dB */ 193 u8 PwrTrackingLimit_CCK = 28; /* 2dB */ 194 u8 TxRate = 0xFF; 195 u8 Final_OFDM_Swing_Index = 0; 196 u8 Final_CCK_Swing_Index = 0; 197 198 { 199 u16 rate = *(pDM_Odm->pForcedDataRate); 200 201 if (!rate) { /* auto rate */ 202 if (pDM_Odm->TxRate != 0xFF) 203 TxRate = HwRateToMRate(pDM_Odm->TxRate); 204 } else /* force rate */ 205 TxRate = (u8)rate; 206 207 } 208 209 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("===>ODM_TxPwrTrackSetPwr8723B\n")); 210 211 if (TxRate != 0xFF) { 212 /* 2 CCK */ 213 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M)) 214 PwrTrackingLimit_CCK = 28; /* 2dB */ 215 /* 2 OFDM */ 216 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) 217 PwrTrackingLimit_OFDM = 36; /* 3dB */ 218 else if (TxRate == MGN_54M) 219 PwrTrackingLimit_OFDM = 34; /* 2dB */ 220 221 /* 2 HT */ 222 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */ 223 PwrTrackingLimit_OFDM = 38; /* 4dB */ 224 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */ 225 PwrTrackingLimit_OFDM = 36; /* 3dB */ 226 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */ 227 PwrTrackingLimit_OFDM = 34; /* 2dB */ 228 229 else 230 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; /* Default OFDM index = 30 */ 231 } 232 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxRate = 0x%x, PwrTrackingLimit =%d\n", TxRate, PwrTrackingLimit_OFDM)); 233 234 if (Method == TXAGC) { 235 struct adapter *Adapter = pDM_Odm->Adapter; 236 237 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr8723B CH =%d\n", *(pDM_Odm->pChannel))); 238 239 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 240 241 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 242 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 243 244 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 245 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 246 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 247 } else if (Method == BBSWING) { 248 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 249 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 250 251 /* Adjust BB swing by OFDM IQ matrix */ 252 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) 253 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; 254 else if (Final_OFDM_Swing_Index <= 0) 255 Final_OFDM_Swing_Index = 0; 256 257 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) 258 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; 259 else if (pDM_Odm->BbSwingIdxCck <= 0) 260 Final_CCK_Swing_Index = 0; 261 262 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, 263 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 264 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 265 266 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); 267 268 } else if (Method == MIX_MODE) { 269 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 270 ("pDM_Odm->DefaultOfdmIndex =%d, pDM_Odm->DefaultCCKIndex =%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n", 271 pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath], RFPath)); 272 273 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 274 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 275 276 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */ 277 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; 278 279 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, 280 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 281 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 282 283 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 284 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 285 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 286 287 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 288 ("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d\n", 289 PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath])); 290 } else if (Final_OFDM_Swing_Index <= 0) { 291 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; 292 293 setIqkMatrix_8723B(pDM_Odm, 0, RFPath, 294 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 295 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 296 297 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 298 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 299 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 300 301 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 302 ("******Path_A Lower then BBSwing lower bound 0 , Remnant TxAGC Value = %d\n", 303 pDM_Odm->Remnant_OFDMSwingIdx[RFPath])); 304 } else { 305 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, 306 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 307 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 308 309 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 310 ("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d\n", Final_OFDM_Swing_Index)); 311 312 if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */ 313 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0; 314 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 315 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 316 pDM_Odm->Modify_TxAGC_Flag_PathA = false; 317 318 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 319 ("******Path_A pDM_Odm->Modify_TxAGC_Flag = false\n")); 320 } 321 } 322 323 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { 324 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; 325 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); 326 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 327 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 328 329 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 330 ("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx)); 331 } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */ 332 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; 333 setCCKFilterCoefficient(pDM_Odm, 0); 334 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 335 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 336 337 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 338 ("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx = %d\n", 0, pDM_Odm->Remnant_CCKSwingIdx)); 339 } else { 340 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); 341 342 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 343 ("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d\n", Final_CCK_Swing_Index)); 344 345 if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */ 346 pDM_Odm->Remnant_CCKSwingIdx = 0; 347 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 348 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false; 349 350 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, 351 ("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = false\n")); 352 } 353 } 354 } else 355 return; /* This method is not supported. */ 356 } 357 358 static void GetDeltaSwingTable_8723B( 359 PDM_ODM_T pDM_Odm, 360 u8 **TemperatureUP_A, 361 u8 **TemperatureDOWN_A, 362 u8 **TemperatureUP_B, 363 u8 **TemperatureDOWN_B 364 ) 365 { 366 struct adapter *Adapter = pDM_Odm->Adapter; 367 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); 368 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 369 u16 rate = *(pDM_Odm->pForcedDataRate); 370 u8 channel = pHalData->CurrentChannel; 371 372 if (1 <= channel && channel <= 14) { 373 if (IS_CCK_RATE(rate)) { 374 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; 375 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; 376 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; 377 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; 378 } else { 379 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; 380 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; 381 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; 382 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; 383 } 384 } /*else if (36 <= channel && channel <= 64) { 385 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; 386 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; 387 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; 388 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; 389 } else if (100 <= channel && channel <= 140) { 390 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; 391 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; 392 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; 393 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; 394 } else if (149 <= channel && channel <= 173) { 395 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; 396 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; 397 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; 398 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; 399 }*/else { 400 *TemperatureUP_A = (u8 *)DeltaSwingTableIdx_2GA_P_8188E; 401 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E; 402 *TemperatureUP_B = (u8 *)DeltaSwingTableIdx_2GA_P_8188E; 403 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E; 404 } 405 406 return; 407 } 408 409 410 void ConfigureTxpowerTrack_8723B(PTXPWRTRACK_CFG pConfig) 411 { 412 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; 413 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; 414 pConfig->Threshold_IQK = IQK_THRESHOLD; 415 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; 416 pConfig->RfPathCount = MAX_PATH_NUM_8723B; 417 pConfig->ThermalRegAddr = RF_T_METER_8723B; 418 419 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; 420 pConfig->DoIQK = DoIQK_8723B; 421 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; 422 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; 423 } 424 425 /* 1 7. IQK */ 426 #define MAX_TOLERANCE 5 427 #define IQK_DELAY_TIME 1 /* ms */ 428 429 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 430 static u8 phy_PathA_IQK_8723B( 431 struct adapter *padapter, bool configPathB, u8 RF_Path 432 ) 433 { 434 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; 435 u8 result = 0x00; 436 437 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 438 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 439 440 /* Save RF Path */ 441 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 442 443 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n")); 444 445 /* leave IQK mode */ 446 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 447 448 /* enable path A PA in TXIQK mode */ 449 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 450 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 451 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); 452 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); 453 /* disable path B PA in TXIQK mode */ 454 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */ 455 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */ 456 457 /* 1 Tx IQK */ 458 /* IQK setting */ 459 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 460 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 461 /* path-A IQK setting */ 462 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); */ 463 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 464 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 465 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 466 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 467 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */ 468 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); 469 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 470 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 471 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 472 473 /* LO calibration setting */ 474 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 475 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); 476 477 /* enter IQK mode */ 478 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 479 480 /* Ant switch */ 481 if (configPathB || (RF_Path == 0)) 482 /* wifi switch to S1 */ 483 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 484 else 485 /* wifi switch to S0 */ 486 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 487 488 /* GNT_BT = 0 */ 489 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 490 491 /* One shot, path A LOK & IQK */ 492 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 493 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 494 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 495 496 /* delay x ms */ 497 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */ 498 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 499 mdelay(IQK_DELAY_TIME_8723B); 500 501 /* restore Ant Path */ 502 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 503 /* GNT_BT = 1 */ 504 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 505 506 /* leave IQK mode */ 507 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 508 509 510 /* Check failed */ 511 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 512 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 513 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 514 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 515 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); 516 /* monitor image power before & after IQK */ 517 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n", 518 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord))); 519 520 521 /* Allen 20131125 */ 522 tmp = (regE9C & 0x03FF0000)>>16; 523 if ((tmp & 0x200) > 0) 524 tmp = 0x400 - tmp; 525 526 if ( 527 !(regEAC & BIT28) && 528 (((regE94 & 0x03FF0000)>>16) != 0x142) && 529 (((regE9C & 0x03FF0000)>>16) != 0x42) && 530 (((regE94 & 0x03FF0000)>>16) < 0x110) && 531 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 532 (tmp < 0xf) 533 ) 534 result |= 0x01; 535 else /* if Tx not OK, ignore Rx */ 536 return result; 537 538 return result; 539 } 540 541 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 542 static u8 phy_PathA_RxIQK8723B( 543 struct adapter *padapter, bool configPathB, u8 RF_Path 544 ) 545 { 546 u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; 547 u8 result = 0x00; 548 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 549 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 550 551 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); */ 552 553 /* Save RF Path */ 554 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 555 556 /* leave IQK mode */ 557 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 558 559 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK:Get TXIMR setting\n")); 560 /* 1 Get TXIMR setting */ 561 /* modify RXIQK mode table */ 562 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */ 563 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 564 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 565 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 566 /* LNA2 off, PA on for Dcut */ 567 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 568 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 569 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 570 571 /* IQK setting */ 572 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 573 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 574 575 /* path-A IQK setting */ 576 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 577 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 578 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 579 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 580 581 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ 582 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); 583 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 584 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 585 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 586 587 /* LO calibration setting */ 588 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 589 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); 590 591 /* enter IQK mode */ 592 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 593 594 /* Ant switch */ 595 if (configPathB || (RF_Path == 0)) 596 /* wifi switch to S1 */ 597 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 598 else 599 /* wifi switch to S0 */ 600 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 601 602 /* GNT_BT = 0 */ 603 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 604 605 /* One shot, path A LOK & IQK */ 606 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 607 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 608 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 609 610 /* delay x ms */ 611 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */ 612 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 613 mdelay(IQK_DELAY_TIME_8723B); 614 615 /* restore Ant Path */ 616 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 617 /* GNT_BT = 1 */ 618 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 619 620 /* leave IQK mode */ 621 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 622 623 /* Check failed */ 624 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 625 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 626 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 627 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 628 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); 629 /* monitor image power before & after IQK */ 630 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n", 631 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord))); 632 633 /* Allen 20131125 */ 634 tmp = (regE9C & 0x03FF0000)>>16; 635 if ((tmp & 0x200) > 0) 636 tmp = 0x400 - tmp; 637 638 if ( 639 !(regEAC & BIT28) && 640 (((regE94 & 0x03FF0000)>>16) != 0x142) && 641 (((regE9C & 0x03FF0000)>>16) != 0x42) && 642 (((regE94 & 0x03FF0000)>>16) < 0x110) && 643 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 644 (tmp < 0xf) 645 ) 646 result |= 0x01; 647 else /* if Tx not OK, ignore Rx */ 648 return result; 649 650 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); 651 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); 652 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp)); 653 654 655 /* 1 RX IQK */ 656 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A RX IQK\n")); 657 658 /* modify RXIQK mode table */ 659 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); */ 660 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 661 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 662 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 663 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 664 /* LAN2 on, PA off for Dcut */ 665 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 666 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 667 668 /* PA, PAD setting */ 669 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); 670 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); 671 672 673 /* IQK setting */ 674 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 675 676 /* path-A IQK setting */ 677 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 678 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 679 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 680 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 681 682 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); 683 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ 684 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); 685 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 686 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 687 688 /* LO calibration setting */ 689 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 690 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); 691 692 /* enter IQK mode */ 693 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 694 695 /* Ant switch */ 696 if (configPathB || (RF_Path == 0)) 697 /* wifi switch to S1 */ 698 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 699 else 700 /* wifi switch to S0 */ 701 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 702 703 /* GNT_BT = 0 */ 704 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 705 706 /* One shot, path A LOK & IQK */ 707 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 708 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 709 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 710 711 /* delay x ms */ 712 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 713 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 714 mdelay(IQK_DELAY_TIME_8723B); 715 716 /* restore Ant Path */ 717 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 718 /* GNT_BT = 1 */ 719 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 720 721 /* leave IQK mode */ 722 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 723 724 /* Check failed */ 725 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 726 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord); 727 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 728 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); 729 /* monitor image power before & after IQK */ 730 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n", 731 PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord))); 732 733 /* PA/PAD controlled by 0x0 */ 734 /* leave IQK mode */ 735 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 736 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); 737 738 /* Allen 20131125 */ 739 tmp = (regEAC & 0x03FF0000)>>16; 740 if ((tmp & 0x200) > 0) 741 tmp = 0x400 - tmp; 742 743 if ( 744 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ 745 (((regEA4 & 0x03FF0000)>>16) != 0x132) && 746 (((regEAC & 0x03FF0000)>>16) != 0x36) && 747 (((regEA4 & 0x03FF0000)>>16) < 0x110) && 748 (((regEA4 & 0x03FF0000)>>16) > 0xf0) && 749 (tmp < 0xf) 750 ) 751 result |= 0x02; 752 else /* if Tx not OK, ignore Rx */ 753 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK fail!!\n")); 754 return result; 755 } 756 757 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 758 static u8 phy_PathB_IQK_8723B(struct adapter *padapter) 759 { 760 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; 761 u8 result = 0x00; 762 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 763 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 764 765 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK!\n")); 766 767 /* Save RF Path */ 768 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 769 770 /* leave IQK mode */ 771 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 772 773 /* in TXIQK mode */ 774 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ 775 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */ 776 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */ 777 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */ 778 /* enable path B PA in TXIQK mode */ 779 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 780 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1); 781 782 783 784 /* 1 Tx IQK */ 785 /* IQK setting */ 786 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 787 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 788 /* path-A IQK setting */ 789 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); */ 790 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 791 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 792 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 793 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 794 795 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */ 796 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); 797 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 798 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 799 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 800 801 /* LO calibration setting */ 802 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 803 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); 804 805 /* enter IQK mode */ 806 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 807 808 /* switch to path B */ 809 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 810 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 811 812 /* GNT_BT = 0 */ 813 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 814 815 /* One shot, path B LOK & IQK */ 816 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 817 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 818 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 819 820 /* delay x ms */ 821 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 822 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 823 mdelay(IQK_DELAY_TIME_8723B); 824 825 /* restore Ant Path */ 826 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 827 /* GNT_BT = 1 */ 828 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 829 830 /* leave IQK mode */ 831 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 832 833 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord))); */ 834 835 836 /* Check failed */ 837 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 838 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 839 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 840 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 841 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); 842 /* monitor image power before & after IQK */ 843 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n", 844 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord))); 845 846 /* Allen 20131125 */ 847 tmp = (regE9C & 0x03FF0000)>>16; 848 if ((tmp & 0x200) > 0) 849 tmp = 0x400 - tmp; 850 851 if ( 852 !(regEAC & BIT28) && 853 (((regE94 & 0x03FF0000)>>16) != 0x142) && 854 (((regE9C & 0x03FF0000)>>16) != 0x42) && 855 (((regE94 & 0x03FF0000)>>16) < 0x110) && 856 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 857 (tmp < 0xf) 858 ) 859 result |= 0x01; 860 861 return result; 862 } 863 864 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 865 static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB) 866 { 867 u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; 868 u8 result = 0x00; 869 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 870 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 871 872 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); */ 873 874 /* Save RF Path */ 875 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 876 /* leave IQK mode */ 877 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 878 879 /* switch to path B */ 880 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 881 882 /* 1 Get TXIMR setting */ 883 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK:Get TXIMR setting!\n")); 884 /* modify RXIQK mode table */ 885 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */ 886 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 887 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 888 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 889 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 890 /* open PA S1 & SMIXER */ 891 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 892 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd); 893 894 895 /* IQK setting */ 896 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 897 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 898 899 900 /* path-B IQK setting */ 901 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 902 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 903 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 904 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 905 906 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ 907 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); 908 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 909 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 910 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 911 912 /* LO calibration setting */ 913 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 914 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); 915 916 /* enter IQK mode */ 917 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 918 919 /* switch to path B */ 920 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 921 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 922 923 /* GNT_BT = 0 */ 924 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 925 926 /* One shot, path B TXIQK @ RXIQK */ 927 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 928 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 929 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 930 931 932 /* delay x ms */ 933 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 934 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 935 mdelay(IQK_DELAY_TIME_8723B); 936 937 /* restore Ant Path */ 938 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 939 /* GNT_BT = 1 */ 940 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 941 942 /* leave IQK mode */ 943 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 944 945 /* Check failed */ 946 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 947 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 948 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 949 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 950 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x, 0xe9c = 0x%x\n", regE94, regE9C)); 951 /* monitor image power before & after IQK */ 952 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe90(before IQK) = 0x%x, 0xe98(afer IQK) = 0x%x\n", 953 PHY_QueryBBReg(pDM_Odm->Adapter, 0xe90, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xe98, bMaskDWord))); 954 955 /* Allen 20131125 */ 956 tmp = (regE9C & 0x03FF0000)>>16; 957 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp1 = 0x%x\n", tmp)); */ 958 if ((tmp & 0x200) > 0) 959 tmp = 0x400 - tmp; 960 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp2 = 0x%x\n", tmp)); */ 961 962 if ( 963 !(regEAC & BIT28) && 964 (((regE94 & 0x03FF0000)>>16) != 0x142) && 965 (((regE9C & 0x03FF0000)>>16) != 0x42) && 966 (((regE94 & 0x03FF0000)>>16) < 0x110) && 967 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 968 (tmp < 0xf) 969 ) 970 result |= 0x01; 971 else /* if Tx not OK, ignore Rx */ 972 return result; 973 974 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); 975 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); 976 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord), u4tmp)); 977 978 /* 1 RX IQK */ 979 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B RX IQK\n")); 980 981 /* modify RXIQK mode table */ 982 /* 20121009, Kordan> RF Mode = 3 */ 983 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 984 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 985 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 986 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 987 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 988 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 989 990 /* open PA S1 & close SMIXER */ 991 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 992 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd); 993 994 /* PA, PAD setting */ 995 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */ 996 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ 997 998 /* IQK setting */ 999 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 1000 1001 /* path-B IQK setting */ 1002 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 1003 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 1004 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 1005 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 1006 1007 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); 1008 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ 1009 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); 1010 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 1011 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 1012 1013 /* LO calibration setting */ 1014 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 1015 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); 1016 1017 /* enter IQK mode */ 1018 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 1019 1020 /* switch to path B */ 1021 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 1022 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 1023 1024 /* GNT_BT = 0 */ 1025 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 1026 1027 /* One shot, path B LOK & IQK */ 1028 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 1029 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 1030 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 1031 1032 /* delay x ms */ 1033 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 1034 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 1035 mdelay(IQK_DELAY_TIME_8723B); 1036 1037 /* restore Ant Path */ 1038 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 1039 /* GNT_BT = 1 */ 1040 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 1041 1042 /* leave IQK mode */ 1043 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1044 1045 /* Check failed */ 1046 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 1047 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord); 1048 1049 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC)); 1050 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x, 0xeac = 0x%x\n", regEA4, regEAC)); 1051 /* monitor image power before & after IQK */ 1052 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea0(before IQK) = 0x%x, 0xea8(afer IQK) = 0x%x\n", 1053 PHY_QueryBBReg(pDM_Odm->Adapter, 0xea0, bMaskDWord), PHY_QueryBBReg(pDM_Odm->Adapter, 0xea8, bMaskDWord))); 1054 1055 /* PA/PAD controlled by 0x0 */ 1056 /* leave IQK mode */ 1057 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */ 1058 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */ 1059 1060 1061 1062 /* Allen 20131125 */ 1063 tmp = (regEAC & 0x03FF0000)>>16; 1064 if ((tmp & 0x200) > 0) 1065 tmp = 0x400 - tmp; 1066 1067 if ( 1068 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ 1069 (((regEA4 & 0x03FF0000)>>16) != 0x132) && 1070 (((regEAC & 0x03FF0000)>>16) != 0x36) && 1071 (((regEA4 & 0x03FF0000)>>16) < 0x110) && 1072 (((regEA4 & 0x03FF0000)>>16) > 0xf0) && 1073 (tmp < 0xf) 1074 ) 1075 result |= 0x02; 1076 else 1077 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK fail!!\n")); 1078 1079 return result; 1080 } 1081 1082 static void _PHY_PathAFillIQKMatrix8723B( 1083 struct adapter *padapter, 1084 bool bIQKOK, 1085 s32 result[][8], 1086 u8 final_candidate, 1087 bool bTxOnly 1088 ) 1089 { 1090 u32 Oldval_0, X, TX0_A, reg; 1091 s32 Y, TX0_C; 1092 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1093 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1094 1095 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); 1096 1097 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); 1098 1099 if (final_candidate == 0xFF) 1100 return; 1101 1102 else if (bIQKOK) { 1103 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; 1104 1105 X = result[final_candidate][0]; 1106 if ((X & 0x00000200) != 0) 1107 X = X | 0xFFFFFC00; 1108 TX0_A = (X * Oldval_0) >> 8; 1109 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0)); 1110 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); 1111 1112 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1)); 1113 1114 Y = result[final_candidate][1]; 1115 if ((Y & 0x00000200) != 0) 1116 Y = Y | 0xFFFFFC00; 1117 1118 /* 2 Tx IQC */ 1119 TX0_C = (Y * Oldval_0) >> 8; 1120 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C)); 1121 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); 1122 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; 1123 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord); 1124 1125 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); 1126 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; 1127 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord); 1128 1129 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1)); 1130 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; 1131 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); 1132 1133 if (bTxOnly) { 1134 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathAFillIQKMatrix8723B only Tx OK\n")); 1135 1136 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */ 1137 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1138 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1139 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1140 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ 1141 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; 1142 return; 1143 } 1144 1145 reg = result[final_candidate][2]; 1146 1147 /* 2 Rx IQC */ 1148 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); 1149 reg = result[final_candidate][3] & 0x3F; 1150 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); 1151 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1152 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); 1153 1154 reg = (result[final_candidate][3] >> 6) & 0xF; 1155 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); 1156 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1157 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1158 1159 } 1160 } 1161 1162 static void _PHY_PathBFillIQKMatrix8723B( 1163 struct adapter *padapter, 1164 bool bIQKOK, 1165 s32 result[][8], 1166 u8 final_candidate, 1167 bool bTxOnly /* do Tx only */ 1168 ) 1169 { 1170 u32 Oldval_1, X, TX1_A, reg; 1171 s32 Y, TX1_C; 1172 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1173 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1174 1175 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); 1176 1177 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n", (bIQKOK)?"Success":"Failed")); 1178 1179 if (final_candidate == 0xFF) 1180 return; 1181 1182 else if (bIQKOK) { 1183 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; 1184 1185 X = result[final_candidate][4]; 1186 if ((X & 0x00000200) != 0) 1187 X = X | 0xFFFFFC00; 1188 TX1_A = (X * Oldval_1) >> 8; 1189 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A)); 1190 1191 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); 1192 1193 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1)); 1194 1195 Y = result[final_candidate][5]; 1196 if ((Y & 0x00000200) != 0) 1197 Y = Y | 0xFFFFFC00; 1198 1199 TX1_C = (Y * Oldval_1) >> 8; 1200 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C)); 1201 1202 /* 2 Tx IQC */ 1203 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); 1204 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */ 1205 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */ 1206 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; 1207 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); 1208 1209 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); 1210 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; 1211 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord); 1212 1213 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1)); 1214 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; 1215 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); 1216 1217 if (bTxOnly) { 1218 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("_PHY_PathBFillIQKMatrix8723B only Tx OK\n")); 1219 1220 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1221 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ 1222 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; 1223 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1224 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1225 return; 1226 } 1227 1228 /* 2 Rx IQC */ 1229 reg = result[final_candidate][6]; 1230 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); 1231 reg = result[final_candidate][7] & 0x3F; 1232 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); 1233 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1234 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord); 1235 1236 reg = (result[final_candidate][7] >> 6) & 0xF; 1237 /* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */ 1238 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1239 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff); 1240 } 1241 } 1242 1243 /* */ 1244 /* 2011/07/26 MH Add an API for testing IQK fail case. */ 1245 /* */ 1246 /* MP Already declare in odm.c */ 1247 1248 void ODM_SetIQCbyRFpath(PDM_ODM_T pDM_Odm, u32 RFpath) 1249 { 1250 1251 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); 1252 1253 if ( 1254 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && 1255 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && 1256 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && 1257 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0) 1258 ) { 1259 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */ 1260 /* S0 TX IQC */ 1261 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); 1262 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); 1263 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); 1264 /* S0 RX IQC */ 1265 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); 1266 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); 1267 } else { 1268 /* S1 TX IQC */ 1269 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); 1270 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); 1271 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); 1272 /* S1 RX IQC */ 1273 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); 1274 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); 1275 } 1276 } 1277 } 1278 1279 static bool ODM_CheckPowerStatus(struct adapter *Adapter) 1280 { 1281 return true; 1282 } 1283 1284 static void _PHY_SaveADDARegisters8723B( 1285 struct adapter *padapter, 1286 u32 *ADDAReg, 1287 u32 *ADDABackup, 1288 u32 RegisterNum 1289 ) 1290 { 1291 u32 i; 1292 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1293 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1294 1295 if (ODM_CheckPowerStatus(padapter) == false) 1296 return; 1297 1298 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n")); 1299 for (i = 0 ; i < RegisterNum ; i++) { 1300 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord); 1301 } 1302 } 1303 1304 1305 static void _PHY_SaveMACRegisters8723B( 1306 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1307 ) 1308 { 1309 u32 i; 1310 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1311 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1312 1313 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n")); 1314 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1315 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]); 1316 } 1317 MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]); 1318 1319 } 1320 1321 1322 static void _PHY_ReloadADDARegisters8723B( 1323 struct adapter *padapter, 1324 u32 *ADDAReg, 1325 u32 *ADDABackup, 1326 u32 RegiesterNum 1327 ) 1328 { 1329 u32 i; 1330 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1331 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1332 1333 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n")); 1334 for (i = 0 ; i < RegiesterNum; i++) { 1335 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]); 1336 } 1337 } 1338 1339 static void _PHY_ReloadMACRegisters8723B( 1340 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1341 ) 1342 { 1343 u32 i; 1344 1345 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1346 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]); 1347 } 1348 rtw_write32(padapter, MACReg[i], MACBackup[i]); 1349 } 1350 1351 1352 static void _PHY_PathADDAOn8723B( 1353 struct adapter *padapter, 1354 u32 *ADDAReg, 1355 bool isPathAOn, 1356 bool is2T 1357 ) 1358 { 1359 u32 pathOn; 1360 u32 i; 1361 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1362 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1363 1364 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n")); 1365 1366 pathOn = isPathAOn ? 0x01c00014 : 0x01c00014; 1367 if (false == is2T) { 1368 pathOn = 0x01c00014; 1369 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014); 1370 } else { 1371 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn); 1372 } 1373 1374 for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) { 1375 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn); 1376 } 1377 1378 } 1379 1380 static void _PHY_MACSettingCalibration8723B( 1381 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1382 ) 1383 { 1384 u32 i = 0; 1385 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1386 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1387 1388 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n")); 1389 1390 rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F); 1391 1392 for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1393 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); 1394 } 1395 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); 1396 1397 } 1398 1399 static bool phy_SimularityCompare_8723B( 1400 struct adapter *padapter, 1401 s32 result[][8], 1402 u8 c1, 1403 u8 c2 1404 ) 1405 { 1406 u32 i, j, diff, SimularityBitMap, bound = 0; 1407 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 1408 bool bResult = true; 1409 bool is2T = true; 1410 s32 tmp1 = 0, tmp2 = 0; 1411 1412 if (is2T) 1413 bound = 8; 1414 else 1415 bound = 4; 1416 1417 SimularityBitMap = 0; 1418 1419 for (i = 0; i < bound; i++) { 1420 1421 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { 1422 if ((result[c1][i] & 0x00000200) != 0) 1423 tmp1 = result[c1][i] | 0xFFFFFC00; 1424 else 1425 tmp1 = result[c1][i]; 1426 1427 if ((result[c2][i] & 0x00000200) != 0) 1428 tmp2 = result[c2][i] | 0xFFFFFC00; 1429 else 1430 tmp2 = result[c2][i]; 1431 } else { 1432 tmp1 = result[c1][i]; 1433 tmp2 = result[c2][i]; 1434 } 1435 1436 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 1437 1438 if (diff > MAX_TOLERANCE) { 1439 if ((i == 2 || i == 6) && !SimularityBitMap) { 1440 if (result[c1][i]+result[c1][i+1] == 0) 1441 final_candidate[(i/4)] = c2; 1442 else if (result[c2][i]+result[c2][i+1] == 0) 1443 final_candidate[(i/4)] = c1; 1444 else 1445 SimularityBitMap = SimularityBitMap|(1<<i); 1446 } else 1447 SimularityBitMap = SimularityBitMap|(1<<i); 1448 } 1449 } 1450 1451 if (SimularityBitMap == 0) { 1452 for (i = 0; i < (bound/4); i++) { 1453 if (final_candidate[i] != 0xFF) { 1454 for (j = i*4; j < (i+1)*4-2; j++) 1455 result[3][j] = result[final_candidate[i]][j]; 1456 bResult = false; 1457 } 1458 } 1459 return bResult; 1460 } else { 1461 1462 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */ 1463 for (i = 0; i < 2; i++) 1464 result[3][i] = result[c1][i]; 1465 } 1466 1467 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */ 1468 for (i = 2; i < 4; i++) 1469 result[3][i] = result[c1][i]; 1470 } 1471 1472 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */ 1473 for (i = 4; i < 6; i++) 1474 result[3][i] = result[c1][i]; 1475 } 1476 1477 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */ 1478 for (i = 6; i < 8; i++) 1479 result[3][i] = result[c1][i]; 1480 } 1481 return false; 1482 } 1483 } 1484 1485 1486 1487 static void phy_IQCalibrate_8723B( 1488 struct adapter *padapter, 1489 s32 result[][8], 1490 u8 t, 1491 bool is2T, 1492 u8 RF_Path 1493 ) 1494 { 1495 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1496 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1497 1498 u32 i; 1499 u8 PathAOK, PathBOK; 1500 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0); 1501 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0); 1502 u32 ADDA_REG[IQK_ADDA_REG_NUM] = { 1503 rFPGA0_XCD_SwitchControl, 1504 rBlue_Tooth, 1505 rRx_Wait_CCA, 1506 rTx_CCK_RFON, 1507 rTx_CCK_BBON, 1508 rTx_OFDM_RFON, 1509 rTx_OFDM_BBON, 1510 rTx_To_Rx, 1511 rTx_To_Tx, 1512 rRx_CCK, 1513 rRx_OFDM, 1514 rRx_Wait_RIFS, 1515 rRx_TO_Rx, 1516 rStandby, 1517 rSleep, 1518 rPMPD_ANAEN 1519 }; 1520 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = { 1521 REG_TXPAUSE, 1522 REG_BCN_CTRL, 1523 REG_BCN_CTRL_1, 1524 REG_GPIO_MUXCFG 1525 }; 1526 1527 /* since 92C & 92D have the different define in IQK_BB_REG */ 1528 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { 1529 rOFDM0_TRxPathEnable, 1530 rOFDM0_TRMuxPar, 1531 rFPGA0_XCD_RFInterfaceSW, 1532 rConfig_AntA, 1533 rConfig_AntB, 1534 rFPGA0_XAB_RFInterfaceSW, 1535 rFPGA0_XA_RFInterfaceOE, 1536 rFPGA0_XB_RFInterfaceOE, 1537 rCCK0_AFESetting 1538 }; 1539 const u32 retryCount = 2; 1540 1541 /* Note: IQ calibration must be performed after loading */ 1542 /* PHY_REG.txt , and radio_a, radio_b.txt */ 1543 1544 /* u32 bbvalue; */ 1545 1546 if (t == 0) { 1547 /* bbvalue = PHY_QueryBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, bMaskDWord); */ 1548 /* RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E() ==>0x%08x\n", bbvalue)); */ 1549 1550 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); 1551 1552 /* Save ADDA parameters, turn Path A ADDA on */ 1553 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); 1554 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1555 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); 1556 } 1557 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t)); 1558 1559 _PHY_PathADDAOn8723B(padapter, ADDA_REG, true, is2T); 1560 1561 /* no serial mode */ 1562 1563 /* save RF path for 8723B */ 1564 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1565 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1566 1567 /* MAC settings */ 1568 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1569 1570 /* BB setting */ 1571 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */ 1572 PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf); 1573 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); 1574 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); 1575 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); 1576 1577 1578 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */ 1579 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */ 1580 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */ 1581 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */ 1582 1583 1584 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */ 1585 1586 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1587 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1588 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); 1589 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1590 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 1591 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 1592 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); 1593 1594 /* path A TX IQK */ 1595 for (i = 0 ; i < retryCount ; i++) { 1596 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path); 1597 /* if (PathAOK == 0x03) { */ 1598 if (PathAOK == 0x01) { 1599 /* Path A Tx IQK Success */ 1600 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1601 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); 1602 1603 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n")); 1604 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1605 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1606 break; 1607 } 1608 } 1609 1610 /* path A RXIQK */ 1611 for (i = 0 ; i < retryCount ; i++) { 1612 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path); 1613 if (PathAOK == 0x03) { 1614 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Success!!\n")); 1615 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1616 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1617 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1618 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1619 break; 1620 } else { 1621 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n")); 1622 } 1623 } 1624 1625 if (0x00 == PathAOK) { 1626 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n")); 1627 } 1628 1629 /* path B IQK */ 1630 if (is2T) { 1631 1632 /* path B TX IQK */ 1633 for (i = 0 ; i < retryCount ; i++) { 1634 PathBOK = phy_PathB_IQK_8723B(padapter); 1635 if (PathBOK == 0x01) { 1636 /* Path B Tx IQK Success */ 1637 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1638 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); 1639 1640 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Tx IQK Success!!\n")); 1641 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1642 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1643 break; 1644 } 1645 } 1646 1647 /* path B RX IQK */ 1648 for (i = 0 ; i < retryCount ; i++) { 1649 PathBOK = phy_PathB_RxIQK8723B(padapter, is2T); 1650 if (PathBOK == 0x03) { 1651 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Success!!\n")); 1652 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1653 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1654 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1655 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1656 break; 1657 } else { 1658 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK Fail!!\n")); 1659 } 1660 } 1661 1662 /* Allen end */ 1663 if (0x00 == PathBOK) { 1664 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n")); 1665 } 1666 } 1667 1668 /* Back to BB mode, load original value */ 1669 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n")); 1670 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0); 1671 1672 if (t != 0) { 1673 /* Reload ADDA power saving parameters */ 1674 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); 1675 1676 /* Reload MAC parameters */ 1677 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1678 1679 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); 1680 1681 /* Reload RF path */ 1682 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 1683 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1684 1685 /* Allen initial gain 0xc50 */ 1686 /* Restore RX initial gain */ 1687 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50); 1688 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50); 1689 if (is2T) { 1690 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50); 1691 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58); 1692 } 1693 1694 /* load 0xe30 IQC default value */ 1695 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); 1696 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); 1697 1698 } 1699 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8723B() <==\n")); 1700 1701 } 1702 1703 1704 static void phy_LCCalibrate_8723B(PDM_ODM_T pDM_Odm, bool is2T) 1705 { 1706 u8 tmpReg; 1707 u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal; 1708 struct adapter *padapter = pDM_Odm->Adapter; 1709 1710 /* Check continuous TX and Packet TX */ 1711 tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03); 1712 1713 if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */ 1714 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */ 1715 else /* Deal with Packet TX case */ 1716 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */ 1717 1718 if ((tmpReg&0x70) != 0) { 1719 /* 1. Read original RF mode */ 1720 /* Path-A */ 1721 RF_Amode = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); 1722 1723 /* Path-B */ 1724 if (is2T) 1725 RF_Bmode = PHY_QueryRFReg(padapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); 1726 1727 /* 2. Set RF mode = standby mode */ 1728 /* Path-A */ 1729 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); 1730 1731 /* Path-B */ 1732 if (is2T) 1733 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); 1734 } 1735 1736 /* 3. Read RF reg18 */ 1737 LC_Cal = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); 1738 1739 /* 4. Set LC calibration begin bit15 */ 1740 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */ 1741 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); 1742 1743 mdelay(100); 1744 1745 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */ 1746 1747 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ 1748 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) { 1749 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); 1750 } 1751 1752 /* Restore original situation */ 1753 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */ 1754 /* Path-A */ 1755 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg); 1756 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); 1757 1758 /* Path-B */ 1759 if (is2T) 1760 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); 1761 } else /* Deal with Packet TX case */ 1762 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00); 1763 } 1764 1765 /* Analog Pre-distortion calibration */ 1766 #define APK_BB_REG_NUM 8 1767 #define APK_CURVE_REG_NUM 4 1768 #define PATH_NUM 2 1769 1770 #define DP_BB_REG_NUM 7 1771 #define DP_RF_REG_NUM 1 1772 #define DP_RETRY_LIMIT 10 1773 #define DP_PATH_NUM 2 1774 #define DP_DPK_NUM 3 1775 #define DP_DPK_VALUE_NUM 2 1776 1777 1778 1779 /* IQK version:V2.5 20140123 */ 1780 /* IQK is controlled by Is2ant, RF path */ 1781 void PHY_IQCalibrate_8723B( 1782 struct adapter *padapter, 1783 bool bReCovery, 1784 bool bRestore, 1785 bool Is2ant, /* false:1ant, true:2-ant */ 1786 u8 RF_Path /* 0:S1, 1:S0 */ 1787 ) 1788 { 1789 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1790 1791 PDM_ODM_T pDM_Odm = &pHalData->odmpriv; 1792 1793 s32 result[4][8]; /* last is final result */ 1794 u8 i, final_candidate, Indexforchannel; 1795 bool bPathAOK, bPathBOK; 1796 s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; 1797 bool is12simular, is13simular, is23simular; 1798 bool bSingleTone = false, bCarrierSuppression = false; 1799 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { 1800 rOFDM0_XARxIQImbalance, 1801 rOFDM0_XBRxIQImbalance, 1802 rOFDM0_ECCAThreshold, 1803 rOFDM0_AGCRSSITable, 1804 rOFDM0_XATxIQImbalance, 1805 rOFDM0_XBTxIQImbalance, 1806 rOFDM0_XCTxAFE, 1807 rOFDM0_XDTxAFE, 1808 rOFDM0_RxIQExtAnta 1809 }; 1810 /* u32 Path_SEL_BB = 0; */ 1811 u32 GNT_BT_default; 1812 u32 StartTime; 1813 s32 ProgressingTime; 1814 1815 if (ODM_CheckPowerStatus(padapter) == false) 1816 return; 1817 1818 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) 1819 return; 1820 1821 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ 1822 if (bSingleTone || bCarrierSuppression) 1823 return; 1824 1825 #if DISABLE_BB_RF 1826 return; 1827 #endif 1828 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) 1829 return; 1830 1831 1832 pDM_Odm->RFCalibrateInfo.bIQKInProgress = true; 1833 1834 if (bRestore) { 1835 u32 offset, data; 1836 u8 path, bResult = SUCCESS; 1837 PODM_RF_CAL_T pRFCalibrateInfo = &(pDM_Odm->RFCalibrateInfo); 1838 1839 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B; 1840 1841 /* Restore TX IQK */ 1842 for (i = 0; i < 3; ++i) { 1843 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; 1844 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; 1845 if ((offset == 0) || (data == 0)) { 1846 DBG_871X( 1847 "%s =>path:%s Restore TX IQK result failed\n", 1848 __func__, 1849 (path == ODM_RF_PATH_A)?"A":"B" 1850 ); 1851 bResult = FAIL; 1852 break; 1853 } 1854 /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 TxIQC(offset, data) = (0x%X, 0x%X)\n", offset, data)); */ 1855 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); 1856 } 1857 1858 /* Restore RX IQK */ 1859 for (i = 0; i < 2; ++i) { 1860 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; 1861 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; 1862 if ((offset == 0) || (data == 0)) { 1863 DBG_871X( 1864 "%s =>path:%s Restore RX IQK result failed\n", 1865 __func__, 1866 (path == ODM_RF_PATH_A)?"A":"B" 1867 ); 1868 bResult = FAIL; 1869 break; 1870 } 1871 /* RT_TRACE(_module_mp_, _drv_notice_, ("Switch to S1 RxIQC (offset, data) = (0x%X, 0x%X)\n", offset, data)); */ 1872 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); 1873 } 1874 1875 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { 1876 DBG_871X("%s => Restore Path-A TxLOK result failed\n", __func__); 1877 bResult = FAIL; 1878 } else { 1879 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); 1880 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); 1881 } 1882 1883 if (bResult == SUCCESS) 1884 return; 1885 } 1886 1887 if (bReCovery) { 1888 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8723B: Return due to bReCovery!\n")); 1889 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); 1890 return; 1891 } 1892 StartTime = jiffies; 1893 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Start!!!\n")); 1894 1895 /* save default GNT_BT */ 1896 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord); 1897 /* Save RF Path */ 1898 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1899 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1900 1901 /* set GNT_BT = 0, pause BT traffic */ 1902 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ 1903 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */ 1904 1905 1906 for (i = 0; i < 8; i++) { 1907 result[0][i] = 0; 1908 result[1][i] = 0; 1909 result[2][i] = 0; 1910 result[3][i] = 0; 1911 } 1912 1913 final_candidate = 0xff; 1914 bPathAOK = false; 1915 bPathBOK = false; 1916 is12simular = false; 1917 is23simular = false; 1918 is13simular = false; 1919 1920 1921 for (i = 0; i < 3; i++) { 1922 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path); 1923 1924 if (i == 1) { 1925 is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1); 1926 if (is12simular) { 1927 final_candidate = 0; 1928 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n", final_candidate)); 1929 break; 1930 } 1931 } 1932 1933 if (i == 2) { 1934 is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2); 1935 if (is13simular) { 1936 final_candidate = 0; 1937 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n", final_candidate)); 1938 1939 break; 1940 } 1941 1942 is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2); 1943 if (is23simular) { 1944 final_candidate = 1; 1945 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n", final_candidate)); 1946 } else { 1947 for (i = 0; i < 8; i++) 1948 RegTmp += result[3][i]; 1949 1950 if (RegTmp != 0) 1951 final_candidate = 3; 1952 else 1953 final_candidate = 0xFF; 1954 } 1955 } 1956 } 1957 /* RT_TRACE(COMP_INIT, DBG_LOUD, ("Release Mutex in IQCalibrate\n")); */ 1958 1959 for (i = 0; i < 4; i++) { 1960 RegE94 = result[i][0]; 1961 RegE9C = result[i][1]; 1962 RegEA4 = result[i][2]; 1963 RegEAC = result[i][3]; 1964 RegEB4 = result[i][4]; 1965 RegEBC = result[i][5]; 1966 RegEC4 = result[i][6]; 1967 RegECC = result[i][7]; 1968 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); 1969 } 1970 1971 if (final_candidate != 0xff) { 1972 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; 1973 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; 1974 RegEA4 = result[final_candidate][2]; 1975 RegEAC = result[final_candidate][3]; 1976 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; 1977 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; 1978 RegEC4 = result[final_candidate][6]; 1979 RegECC = result[final_candidate][7]; 1980 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: final_candidate is %x\n", final_candidate)); 1981 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94 =%x RegE9C =%x RegEA4 =%x RegEAC =%x RegEB4 =%x RegEBC =%x RegEC4 =%x RegECC =%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC)); 1982 bPathAOK = bPathBOK = true; 1983 } else { 1984 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: FAIL use default value\n")); 1985 1986 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */ 1987 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */ 1988 } 1989 1990 { 1991 if (RegE94 != 0) 1992 _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); 1993 } 1994 { 1995 if (RegEB4 != 0) 1996 _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); 1997 } 1998 1999 Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel); 2000 2001 /* To Fix BSOD when final_candidate is 0xff */ 2002 /* by sherry 20120321 */ 2003 if (final_candidate < 4) { 2004 for (i = 0; i < IQK_Matrix_REG_NUM; i++) 2005 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i]; 2006 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = true; 2007 } 2008 /* RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); */ 2009 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel)); 2010 2011 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); 2012 2013 /* restore GNT_BT */ 2014 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default); 2015 /* Restore RF Path */ 2016 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 2017 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 2018 2019 /* Resotr RX mode table parameter */ 2020 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 2021 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 2022 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 2023 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); 2024 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 2025 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); 2026 2027 /* set GNT_BT = HW control */ 2028 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ 2029 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */ 2030 2031 if (Is2ant) { 2032 if (RF_Path == 0x0) /* S1 */ 2033 ODM_SetIQCbyRFpath(pDM_Odm, 0); 2034 else /* S0 */ 2035 ODM_SetIQCbyRFpath(pDM_Odm, 1); 2036 } 2037 2038 pDM_Odm->RFCalibrateInfo.bIQKInProgress = false; 2039 2040 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK finished\n")); 2041 ProgressingTime = jiffies_to_msecs(jiffies - StartTime); 2042 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK ProgressingTime = %d\n", ProgressingTime)); 2043 2044 2045 } 2046 2047 2048 void PHY_LCCalibrate_8723B(PDM_ODM_T pDM_Odm) 2049 { 2050 bool bSingleTone = false, bCarrierSuppression = false; 2051 u32 timeout = 2000, timecount = 0; 2052 u32 StartTime; 2053 s32 ProgressingTime; 2054 2055 #if DISABLE_BB_RF 2056 return; 2057 #endif 2058 2059 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) 2060 return; 2061 2062 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ 2063 if (bSingleTone || bCarrierSuppression) 2064 return; 2065 2066 StartTime = jiffies; 2067 while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { 2068 mdelay(50); 2069 timecount += 50; 2070 } 2071 2072 pDM_Odm->RFCalibrateInfo.bLCKInProgress = true; 2073 2074 2075 phy_LCCalibrate_8723B(pDM_Odm, false); 2076 2077 2078 pDM_Odm->RFCalibrateInfo.bLCKInProgress = false; 2079 2080 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex)); 2081 ProgressingTime = jiffies_to_msecs(jiffies - StartTime); 2082 ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK ProgressingTime = %d\n", ProgressingTime)); 2083 } 2084