1 // SPDX-License-Identifier: GPL-2.0 2 /***************************************************************************** 3 * 4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 #include <drv_types.h> 9 #include <rtw_debug.h> 10 #include "odm_precomp.h" 11 12 13 14 /*---------------------------Define Local Constant---------------------------*/ 15 /* 2010/04/25 MH Define the max tx power tracking tx agc power. */ 16 #define ODM_TXPWRTRACK_MAX_IDX8723B 6 17 18 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[0] */ 19 #define PATH_S0 1 /* RF_PATH_B */ 20 #define IDX_0xC94 0 21 #define IDX_0xC80 1 22 #define IDX_0xC4C 2 23 #define IDX_0xC14 0 24 #define IDX_0xCA0 1 25 #define KEY 0 26 #define VAL 1 27 28 /* MACRO definition for pRFCalibrateInfo->TxIQC_8723B[1] */ 29 #define PATH_S1 0 /* RF_PATH_A */ 30 #define IDX_0xC9C 0 31 #define IDX_0xC88 1 32 #define IDX_0xC4C 2 33 #define IDX_0xC1C 0 34 #define IDX_0xC78 1 35 36 37 /*---------------------------Define Local Constant---------------------------*/ 38 39 /* In the case that we fail to read TxPowerTrack.txt, we use the table for 40 * 88E as the default table. 41 */ 42 static u8 DeltaSwingTableIdx_2GA_N_8188E[] = { 43 0, 0, 0, 2, 2, 3, 3, 4, 4, 4, 4, 5, 5, 6, 6, 44 7, 7, 7, 7, 8, 8, 9, 9, 10, 10, 10, 11, 11, 11, 11 45 }; 46 static u8 DeltaSwingTableIdx_2GA_P_8188E[] = { 47 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 4, 4, 4, 48 4, 4, 4, 5, 5, 7, 7, 8, 8, 8, 9, 9, 9, 9, 9 49 }; 50 51 /* 3 ============================================================ */ 52 /* 3 Tx Power Tracking */ 53 /* 3 ============================================================ */ 54 55 56 static void setIqkMatrix_8723B( 57 struct dm_odm_t *pDM_Odm, 58 u8 OFDM_index, 59 u8 RFPath, 60 s32 IqkResult_X, 61 s32 IqkResult_Y 62 ) 63 { 64 s32 ele_A = 0, ele_D, ele_C = 0, value32; 65 66 if (OFDM_index >= OFDM_TABLE_SIZE) 67 OFDM_index = OFDM_TABLE_SIZE-1; 68 69 ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22; 70 71 /* new element A = element D x X */ 72 if ((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G)) { 73 if ((IqkResult_X & 0x00000200) != 0) /* consider minus */ 74 IqkResult_X = IqkResult_X | 0xFFFFFC00; 75 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF; 76 77 /* new element C = element D x Y */ 78 if ((IqkResult_Y & 0x00000200) != 0) 79 IqkResult_Y = IqkResult_Y | 0xFFFFFC00; 80 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF; 81 82 /* if (RFPath == ODM_RF_PATH_A) */ 83 switch (RFPath) { 84 case ODM_RF_PATH_A: 85 /* write new elements A, C, D to regC80 and regC94, 86 * element B is always 0 87 */ 88 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; 89 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, value32); 90 91 value32 = (ele_C&0x000003C0)>>6; 92 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, value32); 93 94 value32 = ((IqkResult_X * ele_D)>>7)&0x01; 95 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, value32); 96 break; 97 case ODM_RF_PATH_B: 98 /* write new elements A, C, D to regC88 and regC9C, 99 * element B is always 0 100 */ 101 value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A; 102 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, value32); 103 104 value32 = (ele_C&0x000003C0)>>6; 105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, value32); 106 107 value32 = ((IqkResult_X * ele_D)>>7)&0x01; 108 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, value32); 109 110 break; 111 default: 112 break; 113 } 114 } else { 115 switch (RFPath) { 116 case ODM_RF_PATH_A: 117 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 118 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00); 119 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT24, 0x00); 120 break; 121 122 case ODM_RF_PATH_B: 123 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]); 124 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00); 125 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT28, 0x00); 126 break; 127 128 default: 129 break; 130 } 131 } 132 } 133 134 135 static void setCCKFilterCoefficient(struct dm_odm_t *pDM_Odm, u8 CCKSwingIndex) 136 { 137 if (!pDM_Odm->RFCalibrateInfo.bCCKinCH14) { 138 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][0]); 139 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][1]); 140 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][2]); 141 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][3]); 142 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][4]); 143 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][5]); 144 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][6]); 145 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch1_Ch13_New[CCKSwingIndex][7]); 146 } else { 147 rtw_write8(pDM_Odm->Adapter, 0xa22, CCKSwingTable_Ch14_New[CCKSwingIndex][0]); 148 rtw_write8(pDM_Odm->Adapter, 0xa23, CCKSwingTable_Ch14_New[CCKSwingIndex][1]); 149 rtw_write8(pDM_Odm->Adapter, 0xa24, CCKSwingTable_Ch14_New[CCKSwingIndex][2]); 150 rtw_write8(pDM_Odm->Adapter, 0xa25, CCKSwingTable_Ch14_New[CCKSwingIndex][3]); 151 rtw_write8(pDM_Odm->Adapter, 0xa26, CCKSwingTable_Ch14_New[CCKSwingIndex][4]); 152 rtw_write8(pDM_Odm->Adapter, 0xa27, CCKSwingTable_Ch14_New[CCKSwingIndex][5]); 153 rtw_write8(pDM_Odm->Adapter, 0xa28, CCKSwingTable_Ch14_New[CCKSwingIndex][6]); 154 rtw_write8(pDM_Odm->Adapter, 0xa29, CCKSwingTable_Ch14_New[CCKSwingIndex][7]); 155 } 156 } 157 158 void DoIQK_8723B( 159 struct dm_odm_t *pDM_Odm, 160 u8 DeltaThermalIndex, 161 u8 ThermalValue, 162 u8 Threshold 163 ) 164 { 165 } 166 167 /*----------------------------------------------------------------------------- 168 * Function: odm_TxPwrTrackSetPwr88E() 169 * 170 * Overview: 88E change all channel tx power according to flag. 171 * OFDM & CCK are all different. 172 * 173 * Input: NONE 174 * 175 * Output: NONE 176 * 177 * Return: NONE 178 * 179 * Revised History: 180 *When Who Remark 181 *04/23/2012 MHC Create Version 0. 182 * 183 *---------------------------------------------------------------------------*/ 184 void ODM_TxPwrTrackSetPwr_8723B( 185 struct dm_odm_t *pDM_Odm, 186 enum pwrtrack_method Method, 187 u8 RFPath, 188 u8 ChannelMappedIndex 189 ) 190 { 191 struct adapter *Adapter = pDM_Odm->Adapter; 192 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 193 u8 PwrTrackingLimit_OFDM = 34; /* 0dB */ 194 u8 PwrTrackingLimit_CCK = 28; /* 2dB */ 195 u8 TxRate = 0xFF; 196 u8 Final_OFDM_Swing_Index = 0; 197 u8 Final_CCK_Swing_Index = 0; 198 199 { 200 u16 rate = *(pDM_Odm->pForcedDataRate); 201 202 if (!rate) { /* auto rate */ 203 if (pDM_Odm->TxRate != 0xFF) 204 TxRate = HwRateToMRate(pDM_Odm->TxRate); 205 } else /* force rate */ 206 TxRate = (u8)rate; 207 208 } 209 210 if (TxRate != 0xFF) { 211 /* 2 CCK */ 212 if ((TxRate >= MGN_1M) && (TxRate <= MGN_11M)) 213 PwrTrackingLimit_CCK = 28; /* 2dB */ 214 /* 2 OFDM */ 215 else if ((TxRate >= MGN_6M) && (TxRate <= MGN_48M)) 216 PwrTrackingLimit_OFDM = 36; /* 3dB */ 217 else if (TxRate == MGN_54M) 218 PwrTrackingLimit_OFDM = 34; /* 2dB */ 219 220 /* 2 HT */ 221 else if ((TxRate >= MGN_MCS0) && (TxRate <= MGN_MCS2)) /* QPSK/BPSK */ 222 PwrTrackingLimit_OFDM = 38; /* 4dB */ 223 else if ((TxRate >= MGN_MCS3) && (TxRate <= MGN_MCS4)) /* 16QAM */ 224 PwrTrackingLimit_OFDM = 36; /* 3dB */ 225 else if ((TxRate >= MGN_MCS5) && (TxRate <= MGN_MCS7)) /* 64QAM */ 226 PwrTrackingLimit_OFDM = 34; /* 2dB */ 227 228 else 229 PwrTrackingLimit_OFDM = pDM_Odm->DefaultOfdmIndex; /* Default OFDM index = 30 */ 230 } 231 232 if (Method == TXAGC) { 233 struct adapter *Adapter = pDM_Odm->Adapter; 234 235 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 236 237 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 238 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 239 240 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 241 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 242 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 243 } else if (Method == BBSWING) { 244 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 245 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 246 247 /* Adjust BB swing by OFDM IQ matrix */ 248 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM) 249 Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM; 250 else if (Final_OFDM_Swing_Index <= 0) 251 Final_OFDM_Swing_Index = 0; 252 253 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE) 254 Final_CCK_Swing_Index = CCK_TABLE_SIZE-1; 255 else if (pDM_Odm->BbSwingIdxCck <= 0) 256 Final_CCK_Swing_Index = 0; 257 258 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, 259 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 260 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 261 262 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); 263 264 } else if (Method == MIX_MODE) { 265 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 266 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; 267 268 if (Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM) { /* BBSwing higher then Limit */ 269 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM; 270 271 setIqkMatrix_8723B(pDM_Odm, PwrTrackingLimit_OFDM, RFPath, 272 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 273 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 274 275 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 276 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 277 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 278 } else if (Final_OFDM_Swing_Index <= 0) { 279 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index; 280 281 setIqkMatrix_8723B(pDM_Odm, 0, RFPath, 282 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 283 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 284 285 pDM_Odm->Modify_TxAGC_Flag_PathA = true; 286 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 287 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 288 } else { 289 setIqkMatrix_8723B(pDM_Odm, Final_OFDM_Swing_Index, RFPath, 290 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0], 291 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]); 292 293 if (pDM_Odm->Modify_TxAGC_Flag_PathA) { /* If TxAGC has changed, reset TxAGC again */ 294 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0; 295 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, OFDM); 296 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, HT_MCS0_MCS7); 297 pDM_Odm->Modify_TxAGC_Flag_PathA = false; 298 } 299 } 300 301 if (Final_CCK_Swing_Index > PwrTrackingLimit_CCK) { 302 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK; 303 setCCKFilterCoefficient(pDM_Odm, PwrTrackingLimit_CCK); 304 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 305 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 306 } else if (Final_CCK_Swing_Index <= 0) { /* Lowest CCK Index = 0 */ 307 pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index; 308 setCCKFilterCoefficient(pDM_Odm, 0); 309 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = true; 310 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 311 } else { 312 setCCKFilterCoefficient(pDM_Odm, Final_CCK_Swing_Index); 313 314 if (pDM_Odm->Modify_TxAGC_Flag_PathA_CCK) { /* If TxAGC has changed, reset TxAGC again */ 315 pDM_Odm->Remnant_CCKSwingIdx = 0; 316 PHY_SetTxPowerIndexByRateSection(Adapter, RFPath, pHalData->CurrentChannel, CCK); 317 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = false; 318 } 319 } 320 } else 321 return; /* This method is not supported. */ 322 } 323 324 static void GetDeltaSwingTable_8723B( 325 struct dm_odm_t *pDM_Odm, 326 u8 **TemperatureUP_A, 327 u8 **TemperatureDOWN_A, 328 u8 **TemperatureUP_B, 329 u8 **TemperatureDOWN_B 330 ) 331 { 332 struct adapter *Adapter = pDM_Odm->Adapter; 333 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 334 struct hal_com_data *pHalData = GET_HAL_DATA(Adapter); 335 u16 rate = *(pDM_Odm->pForcedDataRate); 336 u8 channel = pHalData->CurrentChannel; 337 338 if (1 <= channel && channel <= 14) { 339 if (IS_CCK_RATE(rate)) { 340 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_P; 341 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKA_N; 342 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_P; 343 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GCCKB_N; 344 } else { 345 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_P; 346 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_2GA_N; 347 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_P; 348 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_2GB_N; 349 } 350 } /*else if (36 <= channel && channel <= 64) { 351 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[0]; 352 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[0]; 353 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[0]; 354 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[0]; 355 } else if (100 <= channel && channel <= 140) { 356 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[1]; 357 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[1]; 358 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[1]; 359 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[1]; 360 } else if (149 <= channel && channel <= 173) { 361 *TemperatureUP_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_P[2]; 362 *TemperatureDOWN_A = pRFCalibrateInfo->DeltaSwingTableIdx_5GA_N[2]; 363 *TemperatureUP_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_P[2]; 364 *TemperatureDOWN_B = pRFCalibrateInfo->DeltaSwingTableIdx_5GB_N[2]; 365 }*/else { 366 *TemperatureUP_A = (u8 *)DeltaSwingTableIdx_2GA_P_8188E; 367 *TemperatureDOWN_A = (u8 *)DeltaSwingTableIdx_2GA_N_8188E; 368 *TemperatureUP_B = (u8 *)DeltaSwingTableIdx_2GA_P_8188E; 369 *TemperatureDOWN_B = (u8 *)DeltaSwingTableIdx_2GA_N_8188E; 370 } 371 } 372 373 374 void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *pConfig) 375 { 376 pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE; 377 pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE; 378 pConfig->Threshold_IQK = IQK_THRESHOLD; 379 pConfig->AverageThermalNum = AVG_THERMAL_NUM_8723B; 380 pConfig->RfPathCount = MAX_PATH_NUM_8723B; 381 pConfig->ThermalRegAddr = RF_T_METER_8723B; 382 383 pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr_8723B; 384 pConfig->DoIQK = DoIQK_8723B; 385 pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8723B; 386 pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8723B; 387 } 388 389 /* 1 7. IQK */ 390 #define MAX_TOLERANCE 5 391 #define IQK_DELAY_TIME 1 /* ms */ 392 393 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 394 static u8 phy_PathA_IQK_8723B( 395 struct adapter *padapter, bool configPathB, u8 RF_Path 396 ) 397 { 398 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB /*, regEA4*/; 399 u8 result = 0x00; 400 401 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 402 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 403 404 /* Save RF Path */ 405 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 406 407 /* leave IQK mode */ 408 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 409 410 /* enable path A PA in TXIQK mode */ 411 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 412 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 413 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); 414 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); 415 /* disable path B PA in TXIQK mode */ 416 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, bRFRegOffsetMask, 0x00020); */ 417 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x40ec1); */ 418 419 /* 1 Tx IQK */ 420 /* IQK setting */ 421 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 422 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 423 /* path-A IQK setting */ 424 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n")); */ 425 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 426 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 427 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 428 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 429 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x8214010a); */ 430 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); 431 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 432 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 433 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 434 435 /* LO calibration setting */ 436 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 437 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); 438 439 /* enter IQK mode */ 440 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 441 442 /* Ant switch */ 443 if (configPathB || (RF_Path == 0)) 444 /* wifi switch to S1 */ 445 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 446 else 447 /* wifi switch to S0 */ 448 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 449 450 /* GNT_BT = 0 */ 451 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 452 453 /* One shot, path A LOK & IQK */ 454 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 455 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 456 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 457 458 /* delay x ms */ 459 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */ 460 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 461 mdelay(IQK_DELAY_TIME_8723B); 462 463 /* restore Ant Path */ 464 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 465 /* GNT_BT = 1 */ 466 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 467 468 /* leave IQK mode */ 469 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 470 471 472 /* Check failed */ 473 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 474 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 475 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 476 477 478 /* Allen 20131125 */ 479 tmp = (regE9C & 0x03FF0000)>>16; 480 if ((tmp & 0x200) > 0) 481 tmp = 0x400 - tmp; 482 483 if ( 484 !(regEAC & BIT28) && 485 (((regE94 & 0x03FF0000)>>16) != 0x142) && 486 (((regE9C & 0x03FF0000)>>16) != 0x42) && 487 (((regE94 & 0x03FF0000)>>16) < 0x110) && 488 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 489 (tmp < 0xf) 490 ) 491 result |= 0x01; 492 else /* if Tx not OK, ignore Rx */ 493 return result; 494 495 return result; 496 } 497 498 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 499 static u8 phy_PathA_RxIQK8723B( 500 struct adapter *padapter, bool configPathB, u8 RF_Path 501 ) 502 { 503 u32 regEAC, regE94, regE9C, regEA4, u4tmp, tmp, Path_SEL_BB; 504 u8 result = 0x00; 505 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 506 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 507 508 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n")); */ 509 510 /* Save RF Path */ 511 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 512 513 /* leave IQK mode */ 514 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 515 /* 1 Get TXIMR setting */ 516 /* modify RXIQK mode table */ 517 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */ 518 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 519 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 520 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 521 /* LNA2 off, PA on for Dcut */ 522 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 523 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 524 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 525 526 /* IQK setting */ 527 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 528 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 529 530 /* path-A IQK setting */ 531 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 532 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 533 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 534 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 535 536 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ 537 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); 538 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 539 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 540 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 541 542 /* LO calibration setting */ 543 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 544 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); 545 546 /* enter IQK mode */ 547 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 548 549 /* Ant switch */ 550 if (configPathB || (RF_Path == 0)) 551 /* wifi switch to S1 */ 552 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 553 else 554 /* wifi switch to S0 */ 555 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 556 557 /* GNT_BT = 0 */ 558 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 559 560 /* One shot, path A LOK & IQK */ 561 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 562 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 563 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 564 565 /* delay x ms */ 566 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_8723B)); */ 567 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 568 mdelay(IQK_DELAY_TIME_8723B); 569 570 /* restore Ant Path */ 571 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 572 /* GNT_BT = 1 */ 573 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 574 575 /* leave IQK mode */ 576 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 577 578 /* Check failed */ 579 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 580 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 581 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 582 583 /* Allen 20131125 */ 584 tmp = (regE9C & 0x03FF0000)>>16; 585 if ((tmp & 0x200) > 0) 586 tmp = 0x400 - tmp; 587 588 if ( 589 !(regEAC & BIT28) && 590 (((regE94 & 0x03FF0000)>>16) != 0x142) && 591 (((regE9C & 0x03FF0000)>>16) != 0x42) && 592 (((regE94 & 0x03FF0000)>>16) < 0x110) && 593 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 594 (tmp < 0xf) 595 ) 596 result |= 0x01; 597 else /* if Tx not OK, ignore Rx */ 598 return result; 599 600 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); 601 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); 602 603 /* modify RXIQK mode table */ 604 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n")); */ 605 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 606 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 607 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 608 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 609 /* LAN2 on, PA off for Dcut */ 610 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 611 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 612 613 /* PA, PAD setting */ 614 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); 615 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f); 616 617 618 /* IQK setting */ 619 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 620 621 /* path-A IQK setting */ 622 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 623 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 624 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 625 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 626 627 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); 628 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ 629 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); 630 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 631 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 632 633 /* LO calibration setting */ 634 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 635 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); 636 637 /* enter IQK mode */ 638 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 639 640 /* Ant switch */ 641 if (configPathB || (RF_Path == 0)) 642 /* wifi switch to S1 */ 643 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000000); 644 else 645 /* wifi switch to S0 */ 646 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 647 648 /* GNT_BT = 0 */ 649 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 650 651 /* One shot, path A LOK & IQK */ 652 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n")); */ 653 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 654 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 655 656 /* delay x ms */ 657 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 658 /* PlatformStallExecution(IQK_DELAY_TIME_8723B*1000); */ 659 mdelay(IQK_DELAY_TIME_8723B); 660 661 /* restore Ant Path */ 662 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 663 /* GNT_BT = 1 */ 664 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 665 666 /* leave IQK mode */ 667 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 668 669 /* Check failed */ 670 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 671 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord); 672 673 /* PA/PAD controlled by 0x0 */ 674 /* leave IQK mode */ 675 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 676 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x780); 677 678 /* Allen 20131125 */ 679 tmp = (regEAC & 0x03FF0000)>>16; 680 if ((tmp & 0x200) > 0) 681 tmp = 0x400 - tmp; 682 683 if ( 684 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ 685 (((regEA4 & 0x03FF0000)>>16) != 0x132) && 686 (((regEAC & 0x03FF0000)>>16) != 0x36) && 687 (((regEA4 & 0x03FF0000)>>16) < 0x110) && 688 (((regEA4 & 0x03FF0000)>>16) > 0xf0) && 689 (tmp < 0xf) 690 ) 691 result |= 0x02; 692 693 return result; 694 } 695 696 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 697 static u8 phy_PathB_IQK_8723B(struct adapter *padapter) 698 { 699 u32 regEAC, regE94, regE9C, tmp, Path_SEL_BB/*, regEC4, regECC, Path_SEL_BB*/; 700 u8 result = 0x00; 701 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 702 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 703 704 /* Save RF Path */ 705 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 706 707 /* leave IQK mode */ 708 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 709 710 /* in TXIQK mode */ 711 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); */ 712 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x20000); */ 713 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0003f); */ 714 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xc7f87); */ 715 /* enable path B PA in TXIQK mode */ 716 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 717 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1); 718 719 720 721 /* 1 Tx IQK */ 722 /* IQK setting */ 723 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 724 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 725 /* path-A IQK setting */ 726 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-B IQK setting!\n")); */ 727 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 728 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 729 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 730 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 731 732 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82140114); */ 733 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x821303ea); 734 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 735 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 736 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 737 738 /* LO calibration setting */ 739 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 740 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x00462911); 741 742 /* enter IQK mode */ 743 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 744 745 /* switch to path B */ 746 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 747 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 748 749 /* GNT_BT = 0 */ 750 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 751 752 /* One shot, path B LOK & IQK */ 753 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 754 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 755 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 756 757 /* delay x ms */ 758 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 759 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 760 mdelay(IQK_DELAY_TIME_8723B); 761 762 /* restore Ant Path */ 763 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 764 /* GNT_BT = 1 */ 765 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 766 767 /* leave IQK mode */ 768 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 769 770 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0x948 = 0x%x\n", PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord))); */ 771 772 773 /* Check failed */ 774 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 775 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 776 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 777 778 /* Allen 20131125 */ 779 tmp = (regE9C & 0x03FF0000)>>16; 780 if ((tmp & 0x200) > 0) 781 tmp = 0x400 - tmp; 782 783 if ( 784 !(regEAC & BIT28) && 785 (((regE94 & 0x03FF0000)>>16) != 0x142) && 786 (((regE9C & 0x03FF0000)>>16) != 0x42) && 787 (((regE94 & 0x03FF0000)>>16) < 0x110) && 788 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 789 (tmp < 0xf) 790 ) 791 result |= 0x01; 792 793 return result; 794 } 795 796 /* bit0 = 1 => Tx OK, bit1 = 1 => Rx OK */ 797 static u8 phy_PathB_RxIQK8723B(struct adapter *padapter, bool configPathB) 798 { 799 u32 regE94, regE9C, regEA4, regEAC, u4tmp, tmp, Path_SEL_BB; 800 u8 result = 0x00; 801 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 802 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 803 804 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Rx IQK!\n")); */ 805 806 /* Save RF Path */ 807 Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); 808 /* leave IQK mode */ 809 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 810 811 /* switch to path B */ 812 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 813 /* modify RXIQK mode table */ 814 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n")); */ 815 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 816 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 817 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 818 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 819 /* open PA S1 & SMIXER */ 820 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 821 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd); 822 823 824 /* IQK setting */ 825 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00); 826 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 827 828 829 /* path-B IQK setting */ 830 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 831 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 832 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 833 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 834 835 /* PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82160c1f); */ 836 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82130ff0); 837 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x28110000); 838 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 839 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 840 841 /* LO calibration setting */ 842 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 843 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911); 844 845 /* enter IQK mode */ 846 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 847 848 /* switch to path B */ 849 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 850 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 851 852 /* GNT_BT = 0 */ 853 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 854 855 /* One shot, path B TXIQK @ RXIQK */ 856 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 857 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 858 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 859 860 861 /* delay x ms */ 862 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 863 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 864 mdelay(IQK_DELAY_TIME_8723B); 865 866 /* restore Ant Path */ 867 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 868 /* GNT_BT = 1 */ 869 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 870 871 /* leave IQK mode */ 872 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 873 874 /* Check failed */ 875 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 876 regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord); 877 regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord); 878 879 /* Allen 20131125 */ 880 tmp = (regE9C & 0x03FF0000)>>16; 881 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp1 = 0x%x\n", tmp)); */ 882 if ((tmp & 0x200) > 0) 883 tmp = 0x400 - tmp; 884 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("tmp2 = 0x%x\n", tmp)); */ 885 886 if ( 887 !(regEAC & BIT28) && 888 (((regE94 & 0x03FF0000)>>16) != 0x142) && 889 (((regE9C & 0x03FF0000)>>16) != 0x42) && 890 (((regE94 & 0x03FF0000)>>16) < 0x110) && 891 (((regE94 & 0x03FF0000)>>16) > 0xf0) && 892 (tmp < 0xf) 893 ) 894 result |= 0x01; 895 else /* if Tx not OK, ignore Rx */ 896 return result; 897 898 u4tmp = 0x80007C00 | (regE94&0x3FF0000) | ((regE9C&0x3FF0000) >> 16); 899 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, u4tmp); 900 901 /* modify RXIQK mode table */ 902 /* 20121009, Kordan> RF Mode = 3 */ 903 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 904 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 905 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 906 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 907 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7d77); 908 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x0); */ 909 910 /* open PA S1 & close SMIXER */ 911 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 912 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30ebd); 913 914 /* PA, PAD setting */ 915 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80); */ 916 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x56, bRFRegOffsetMask, 0x51000); */ 917 918 /* IQK setting */ 919 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800); 920 921 /* path-B IQK setting */ 922 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x38008c1c); 923 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x18008c1c); 924 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 925 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_B, bMaskDWord, 0x38008c1c); 926 927 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_A, bMaskDWord, 0x82110000); 928 /* PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x281604c2); */ 929 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_A, bMaskDWord, 0x2813001f); 930 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_PI_B, bMaskDWord, 0x82110000); 931 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_PI_B, bMaskDWord, 0x28110000); 932 933 /* LO calibration setting */ 934 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n")); */ 935 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Rsp, bMaskDWord, 0x0046a8d1); 936 937 /* enter IQK mode */ 938 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x808000); 939 940 /* switch to path B */ 941 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, 0x00000280); 942 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, bRFRegOffsetMask, 0xeffe0); */ 943 944 /* GNT_BT = 0 */ 945 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00000800); 946 947 /* One shot, path B LOK & IQK */ 948 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path B LOK & IQK!\n")); */ 949 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000); 950 PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000); 951 952 /* delay x ms */ 953 /* ODM_RT_TRACE(pDM_Odm, ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E)); */ 954 /* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */ 955 mdelay(IQK_DELAY_TIME_8723B); 956 957 /* restore Ant Path */ 958 PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); 959 /* GNT_BT = 1 */ 960 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, 0x00001800); 961 962 /* leave IQK mode */ 963 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 964 965 /* Check failed */ 966 regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord); 967 regEA4 = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord); 968 969 /* PA/PAD controlled by 0x0 */ 970 /* leave IQK mode */ 971 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */ 972 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */ 973 974 975 976 /* Allen 20131125 */ 977 tmp = (regEAC & 0x03FF0000)>>16; 978 if ((tmp & 0x200) > 0) 979 tmp = 0x400 - tmp; 980 981 if ( 982 !(regEAC & BIT27) && /* if Tx is OK, check whether Rx is OK */ 983 (((regEA4 & 0x03FF0000)>>16) != 0x132) && 984 (((regEAC & 0x03FF0000)>>16) != 0x36) && 985 (((regEA4 & 0x03FF0000)>>16) < 0x110) && 986 (((regEA4 & 0x03FF0000)>>16) > 0xf0) && 987 (tmp < 0xf) 988 ) 989 result |= 0x02; 990 991 return result; 992 } 993 994 static void _PHY_PathAFillIQKMatrix8723B( 995 struct adapter *padapter, 996 bool bIQKOK, 997 s32 result[][8], 998 u8 final_candidate, 999 bool bTxOnly 1000 ) 1001 { 1002 u32 Oldval_0, X, TX0_A, reg; 1003 s32 Y, TX0_C; 1004 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1005 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1006 1007 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 1008 1009 if (final_candidate == 0xFF) 1010 return; 1011 1012 else if (bIQKOK) { 1013 Oldval_0 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF; 1014 1015 X = result[final_candidate][0]; 1016 if ((X & 0x00000200) != 0) 1017 X = X | 0xFFFFFC00; 1018 TX0_A = (X * Oldval_0) >> 8; 1019 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); 1020 1021 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(31), ((X*Oldval_0>>7) & 0x1)); 1022 1023 Y = result[final_candidate][1]; 1024 if ((Y & 0x00000200) != 0) 1025 Y = Y | 0xFFFFFC00; 1026 1027 /* 2 Tx IQC */ 1028 TX0_C = (Y * Oldval_0) >> 8; 1029 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6)); 1030 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; 1031 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XCTxAFE, bMaskDWord); 1032 1033 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F)); 1034 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; 1035 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, bMaskDWord); 1036 1037 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(29), ((Y*Oldval_0>>7) & 0x1)); 1038 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; 1039 pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); 1040 1041 if (bTxOnly) { 1042 /* <20130226, Kordan> Saving RxIQC, otherwise not initialized. */ 1043 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1044 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = 0xfffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1045 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1046 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ 1047 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = 0x40000100; 1048 return; 1049 } 1050 1051 reg = result[final_candidate][2]; 1052 1053 /* 2 Rx IQC */ 1054 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0x3FF, reg); 1055 reg = result[final_candidate][3] & 0x3F; 1056 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, 0xFC00, reg); 1057 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1058 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); 1059 1060 reg = (result[final_candidate][3] >> 6) & 0xF; 1061 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg); 1062 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1063 pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1064 1065 } 1066 } 1067 1068 static void _PHY_PathBFillIQKMatrix8723B( 1069 struct adapter *padapter, 1070 bool bIQKOK, 1071 s32 result[][8], 1072 u8 final_candidate, 1073 bool bTxOnly /* do Tx only */ 1074 ) 1075 { 1076 u32 Oldval_1, X, TX1_A, reg; 1077 s32 Y, TX1_C; 1078 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1079 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1080 1081 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 1082 1083 if (final_candidate == 0xFF) 1084 return; 1085 1086 else if (bIQKOK) { 1087 Oldval_1 = (PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF; 1088 1089 X = result[final_candidate][4]; 1090 if ((X & 0x00000200) != 0) 1091 X = X | 0xFFFFFC00; 1092 TX1_A = (X * Oldval_1) >> 8; 1093 1094 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A); 1095 1096 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(27), ((X*Oldval_1>>7) & 0x1)); 1097 1098 Y = result[final_candidate][5]; 1099 if ((Y & 0x00000200) != 0) 1100 Y = Y | 0xFFFFFC00; 1101 1102 TX1_C = (Y * Oldval_1) >> 8; 1103 1104 /* 2 Tx IQC */ 1105 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6)); 1106 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][KEY] = rOFDM0_XDTxAFE; */ 1107 /* pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC9C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); */ 1108 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY] = rOFDM0_XCTxAFE; 1109 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XDTxAFE, bMaskDWord); 1110 1111 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F)); 1112 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY] = rOFDM0_XATxIQImbalance; 1113 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBTxIQImbalance, bMaskDWord); 1114 1115 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, BIT(25), ((Y*Oldval_1>>7) & 0x1)); 1116 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY] = rOFDM0_ECCAThreshold; 1117 pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_ECCAThreshold, bMaskDWord); 1118 1119 if (bTxOnly) { 1120 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1121 /* pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XARxIQImbalance, bMaskDWord); */ 1122 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = 0x40000100; 1123 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1124 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = 0x0fffffff & PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord); 1125 return; 1126 } 1127 1128 /* 2 Rx IQC */ 1129 reg = result[final_candidate][6]; 1130 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg); 1131 reg = result[final_candidate][7] & 0x3F; 1132 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg); 1133 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY] = rOFDM0_XARxIQImbalance; 1134 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] = PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_XBRxIQImbalance, bMaskDWord); 1135 1136 reg = (result[final_candidate][7] >> 6) & 0xF; 1137 /* PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_AGCRSSITable, 0x0000F000, reg); */ 1138 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY] = rOFDM0_RxIQExtAnta; 1139 pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL] = (reg << 28)|(PHY_QueryBBReg(pDM_Odm->Adapter, rOFDM0_RxIQExtAnta, bMaskDWord)&0x0fffffff); 1140 } 1141 } 1142 1143 /* */ 1144 /* 2011/07/26 MH Add an API for testing IQK fail case. */ 1145 /* */ 1146 /* MP Already declare in odm.c */ 1147 1148 void ODM_SetIQCbyRFpath(struct dm_odm_t *pDM_Odm, u32 RFpath) 1149 { 1150 1151 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 1152 1153 if ( 1154 (pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL] != 0x0) && 1155 (pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL] != 0x0) && 1156 (pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL] != 0x0) && 1157 (pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL] != 0x0) 1158 ) { 1159 if (RFpath) { /* S1: RFpath = 0, S0:RFpath = 1 */ 1160 /* S0 TX IQC */ 1161 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC94][VAL]); 1162 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC80][VAL]); 1163 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S0][IDX_0xC4C][VAL]); 1164 /* S0 RX IQC */ 1165 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xC14][VAL]); 1166 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S0][IDX_0xCA0][VAL]); 1167 } else { 1168 /* S1 TX IQC */ 1169 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC94][VAL]); 1170 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC80][VAL]); 1171 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][KEY], bMaskDWord, pRFCalibrateInfo->TxIQC_8723B[PATH_S1][IDX_0xC4C][VAL]); 1172 /* S1 RX IQC */ 1173 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xC14][VAL]); 1174 PHY_SetBBReg(pDM_Odm->Adapter, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][KEY], bMaskDWord, pRFCalibrateInfo->RxIQC_8723B[PATH_S1][IDX_0xCA0][VAL]); 1175 } 1176 } 1177 } 1178 1179 static bool ODM_CheckPowerStatus(struct adapter *Adapter) 1180 { 1181 return true; 1182 } 1183 1184 static void _PHY_SaveADDARegisters8723B( 1185 struct adapter *padapter, 1186 u32 *ADDAReg, 1187 u32 *ADDABackup, 1188 u32 RegisterNum 1189 ) 1190 { 1191 u32 i; 1192 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1193 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1194 1195 if (!ODM_CheckPowerStatus(padapter)) 1196 return; 1197 1198 for (i = 0 ; i < RegisterNum ; i++) { 1199 ADDABackup[i] = PHY_QueryBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord); 1200 } 1201 } 1202 1203 1204 static void _PHY_SaveMACRegisters8723B( 1205 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1206 ) 1207 { 1208 u32 i; 1209 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1210 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1211 1212 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1213 MACBackup[i] = rtw_read8(pDM_Odm->Adapter, MACReg[i]); 1214 } 1215 MACBackup[i] = rtw_read32(pDM_Odm->Adapter, MACReg[i]); 1216 1217 } 1218 1219 1220 static void _PHY_ReloadADDARegisters8723B( 1221 struct adapter *padapter, 1222 u32 *ADDAReg, 1223 u32 *ADDABackup, 1224 u32 RegiesterNum 1225 ) 1226 { 1227 u32 i; 1228 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1229 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1230 1231 for (i = 0 ; i < RegiesterNum; i++) { 1232 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, ADDABackup[i]); 1233 } 1234 } 1235 1236 static void _PHY_ReloadMACRegisters8723B( 1237 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1238 ) 1239 { 1240 u32 i; 1241 1242 for (i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1243 rtw_write8(padapter, MACReg[i], (u8)MACBackup[i]); 1244 } 1245 rtw_write32(padapter, MACReg[i], MACBackup[i]); 1246 } 1247 1248 1249 static void _PHY_PathADDAOn8723B( 1250 struct adapter *padapter, 1251 u32 *ADDAReg, 1252 bool is2T 1253 ) 1254 { 1255 u32 pathOn; 1256 u32 i; 1257 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1258 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1259 1260 pathOn = 0x01c00014; 1261 if (!is2T) { 1262 pathOn = 0x01c00014; 1263 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, 0x01c00014); 1264 } else { 1265 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[0], bMaskDWord, pathOn); 1266 } 1267 1268 for (i = 1 ; i < IQK_ADDA_REG_NUM ; i++) { 1269 PHY_SetBBReg(pDM_Odm->Adapter, ADDAReg[i], bMaskDWord, pathOn); 1270 } 1271 1272 } 1273 1274 static void _PHY_MACSettingCalibration8723B( 1275 struct adapter *padapter, u32 *MACReg, u32 *MACBackup 1276 ) 1277 { 1278 u32 i = 0; 1279 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1280 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1281 1282 rtw_write8(pDM_Odm->Adapter, MACReg[i], 0x3F); 1283 1284 for (i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++) { 1285 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3))); 1286 } 1287 rtw_write8(pDM_Odm->Adapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5))); 1288 1289 } 1290 1291 static bool phy_SimularityCompare_8723B( 1292 struct adapter *padapter, 1293 s32 result[][8], 1294 u8 c1, 1295 u8 c2 1296 ) 1297 { 1298 u32 i, j, diff, SimularityBitMap, bound = 0; 1299 u8 final_candidate[2] = {0xFF, 0xFF}; /* for path A and path B */ 1300 bool bResult = true; 1301 s32 tmp1 = 0, tmp2 = 0; 1302 1303 bound = 8; 1304 SimularityBitMap = 0; 1305 1306 for (i = 0; i < bound; i++) { 1307 1308 if ((i == 1) || (i == 3) || (i == 5) || (i == 7)) { 1309 if ((result[c1][i] & 0x00000200) != 0) 1310 tmp1 = result[c1][i] | 0xFFFFFC00; 1311 else 1312 tmp1 = result[c1][i]; 1313 1314 if ((result[c2][i] & 0x00000200) != 0) 1315 tmp2 = result[c2][i] | 0xFFFFFC00; 1316 else 1317 tmp2 = result[c2][i]; 1318 } else { 1319 tmp1 = result[c1][i]; 1320 tmp2 = result[c2][i]; 1321 } 1322 1323 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); 1324 1325 if (diff > MAX_TOLERANCE) { 1326 if ((i == 2 || i == 6) && !SimularityBitMap) { 1327 if (result[c1][i]+result[c1][i+1] == 0) 1328 final_candidate[(i/4)] = c2; 1329 else if (result[c2][i]+result[c2][i+1] == 0) 1330 final_candidate[(i/4)] = c1; 1331 else 1332 SimularityBitMap = SimularityBitMap|(1<<i); 1333 } else 1334 SimularityBitMap = SimularityBitMap|(1<<i); 1335 } 1336 } 1337 1338 if (SimularityBitMap == 0) { 1339 for (i = 0; i < (bound/4); i++) { 1340 if (final_candidate[i] != 0xFF) { 1341 for (j = i*4; j < (i+1)*4-2; j++) 1342 result[3][j] = result[final_candidate[i]][j]; 1343 bResult = false; 1344 } 1345 } 1346 return bResult; 1347 } else { 1348 1349 if (!(SimularityBitMap & 0x03)) { /* path A TX OK */ 1350 for (i = 0; i < 2; i++) 1351 result[3][i] = result[c1][i]; 1352 } 1353 1354 if (!(SimularityBitMap & 0x0c)) { /* path A RX OK */ 1355 for (i = 2; i < 4; i++) 1356 result[3][i] = result[c1][i]; 1357 } 1358 1359 if (!(SimularityBitMap & 0x30)) { /* path B TX OK */ 1360 for (i = 4; i < 6; i++) 1361 result[3][i] = result[c1][i]; 1362 } 1363 1364 if (!(SimularityBitMap & 0xc0)) { /* path B RX OK */ 1365 for (i = 6; i < 8; i++) 1366 result[3][i] = result[c1][i]; 1367 } 1368 return false; 1369 } 1370 } 1371 1372 1373 1374 static void phy_IQCalibrate_8723B( 1375 struct adapter *padapter, 1376 s32 result[][8], 1377 u8 t, 1378 bool is2T, 1379 u8 RF_Path 1380 ) 1381 { 1382 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1383 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1384 1385 u32 i; 1386 u8 PathAOK, PathBOK; 1387 u8 tmp0xc50 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC50, bMaskByte0); 1388 u8 tmp0xc58 = (u8)PHY_QueryBBReg(pDM_Odm->Adapter, 0xC58, bMaskByte0); 1389 u32 ADDA_REG[IQK_ADDA_REG_NUM] = { 1390 rFPGA0_XCD_SwitchControl, 1391 rBlue_Tooth, 1392 rRx_Wait_CCA, 1393 rTx_CCK_RFON, 1394 rTx_CCK_BBON, 1395 rTx_OFDM_RFON, 1396 rTx_OFDM_BBON, 1397 rTx_To_Rx, 1398 rTx_To_Tx, 1399 rRx_CCK, 1400 rRx_OFDM, 1401 rRx_Wait_RIFS, 1402 rRx_TO_Rx, 1403 rStandby, 1404 rSleep, 1405 rPMPD_ANAEN 1406 }; 1407 u32 IQK_MAC_REG[IQK_MAC_REG_NUM] = { 1408 REG_TXPAUSE, 1409 REG_BCN_CTRL, 1410 REG_BCN_CTRL_1, 1411 REG_GPIO_MUXCFG 1412 }; 1413 1414 /* since 92C & 92D have the different define in IQK_BB_REG */ 1415 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { 1416 rOFDM0_TRxPathEnable, 1417 rOFDM0_TRMuxPar, 1418 rFPGA0_XCD_RFInterfaceSW, 1419 rConfig_AntA, 1420 rConfig_AntB, 1421 rFPGA0_XAB_RFInterfaceSW, 1422 rFPGA0_XA_RFInterfaceOE, 1423 rFPGA0_XB_RFInterfaceOE, 1424 rCCK0_AFESetting 1425 }; 1426 const u32 retryCount = 2; 1427 1428 /* Note: IQ calibration must be performed after loading */ 1429 /* PHY_REG.txt , and radio_a, radio_b.txt */ 1430 1431 /* u32 bbvalue; */ 1432 1433 if (t == 0) { 1434 1435 /* Save ADDA parameters, turn Path A ADDA on */ 1436 _PHY_SaveADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); 1437 _PHY_SaveMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1438 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); 1439 } 1440 1441 _PHY_PathADDAOn8723B(padapter, ADDA_REG, is2T); 1442 1443 /* no serial mode */ 1444 1445 /* save RF path for 8723B */ 1446 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1447 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1448 1449 /* MAC settings */ 1450 _PHY_MACSettingCalibration8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1451 1452 /* BB setting */ 1453 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_RFMOD, BIT24, 0x00); */ 1454 PHY_SetBBReg(pDM_Odm->Adapter, rCCK0_AFESetting, 0x0f000000, 0xf); 1455 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600); 1456 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4); 1457 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000); 1458 1459 1460 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */ 1461 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */ 1462 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */ 1463 /* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */ 1464 1465 1466 /* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */ 1467 1468 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1469 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1470 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000); 1471 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1472 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7fb7); 1473 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 1474 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x60fbd); 1475 1476 /* path A TX IQK */ 1477 for (i = 0 ; i < retryCount ; i++) { 1478 PathAOK = phy_PathA_IQK_8723B(padapter, is2T, RF_Path); 1479 /* if (PathAOK == 0x03) { */ 1480 if (PathAOK == 0x01) { 1481 /* Path A Tx IQK Success */ 1482 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1483 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x8, bRFRegOffsetMask); 1484 1485 result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1486 result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1487 break; 1488 } 1489 } 1490 1491 /* path A RXIQK */ 1492 for (i = 0 ; i < retryCount ; i++) { 1493 PathAOK = phy_PathA_RxIQK8723B(padapter, is2T, RF_Path); 1494 if (PathAOK == 0x03) { 1495 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1496 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1497 result[t][2] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1498 result[t][3] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1499 break; 1500 } 1501 } 1502 1503 if (0x00 == PathAOK) { 1504 } 1505 1506 /* path B IQK */ 1507 if (is2T) { 1508 1509 /* path B TX IQK */ 1510 for (i = 0 ; i < retryCount ; i++) { 1511 PathBOK = phy_PathB_IQK_8723B(padapter); 1512 if (PathBOK == 0x01) { 1513 /* Path B Tx IQK Success */ 1514 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000); 1515 pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B] = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, 0x8, bRFRegOffsetMask); 1516 1517 result[t][4] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1518 result[t][5] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; 1519 break; 1520 } 1521 } 1522 1523 /* path B RX IQK */ 1524 for (i = 0 ; i < retryCount ; i++) { 1525 PathBOK = phy_PathB_RxIQK8723B(padapter, is2T); 1526 if (PathBOK == 0x03) { 1527 /* result[t][0] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1528 /* result[t][1] = (PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16; */ 1529 result[t][6] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1530 result[t][7] = (PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16; 1531 break; 1532 } 1533 } 1534 1535 /* Allen end */ 1536 } 1537 1538 /* Back to BB mode, load original value */ 1539 PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0); 1540 1541 if (t != 0) { 1542 /* Reload ADDA power saving parameters */ 1543 _PHY_ReloadADDARegisters8723B(padapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM); 1544 1545 /* Reload MAC parameters */ 1546 _PHY_ReloadMACRegisters8723B(padapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup); 1547 1548 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM); 1549 1550 /* Reload RF path */ 1551 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 1552 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1553 1554 /* Allen initial gain 0xc50 */ 1555 /* Restore RX initial gain */ 1556 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, 0x50); 1557 PHY_SetBBReg(pDM_Odm->Adapter, 0xc50, bMaskByte0, tmp0xc50); 1558 if (is2T) { 1559 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, 0x50); 1560 PHY_SetBBReg(pDM_Odm->Adapter, 0xc58, bMaskByte0, tmp0xc58); 1561 } 1562 1563 /* load 0xe30 IQC default value */ 1564 PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00); 1565 PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00); 1566 1567 } 1568 1569 } 1570 1571 1572 static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T) 1573 { 1574 u8 tmpReg; 1575 u32 RF_Amode = 0, RF_Bmode = 0, LC_Cal; 1576 struct adapter *padapter = pDM_Odm->Adapter; 1577 1578 /* Check continuous TX and Packet TX */ 1579 tmpReg = rtw_read8(pDM_Odm->Adapter, 0xd03); 1580 1581 if ((tmpReg&0x70) != 0) /* Deal with contisuous TX case */ 1582 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg&0x8F); /* disable all continuous TX */ 1583 else /* Deal with Packet TX case */ 1584 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0xFF); /* block all queues */ 1585 1586 if ((tmpReg&0x70) != 0) { 1587 /* 1. Read original RF mode */ 1588 /* Path-A */ 1589 RF_Amode = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_AC, bMask12Bits); 1590 1591 /* Path-B */ 1592 if (is2T) 1593 RF_Bmode = PHY_QueryRFReg(padapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); 1594 1595 /* 2. Set RF mode = standby mode */ 1596 /* Path-A */ 1597 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000); 1598 1599 /* Path-B */ 1600 if (is2T) 1601 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000); 1602 } 1603 1604 /* 3. Read RF reg18 */ 1605 LC_Cal = PHY_QueryRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits); 1606 1607 /* 4. Set LC calibration begin bit15 */ 1608 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0); /* LDO ON */ 1609 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000); 1610 1611 mdelay(100); 1612 1613 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0); /* LDO OFF */ 1614 1615 /* Channel 10 LC calibration issue for 8723bs with 26M xtal */ 1616 if (pDM_Odm->SupportInterface == ODM_ITRF_SDIO && pDM_Odm->PackageType >= 0x2) { 1617 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal); 1618 } 1619 1620 /* Restore original situation */ 1621 if ((tmpReg&0x70) != 0) { /* Deal with contisuous TX case */ 1622 /* Path-A */ 1623 rtw_write8(pDM_Odm->Adapter, 0xd03, tmpReg); 1624 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode); 1625 1626 /* Path-B */ 1627 if (is2T) 1628 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode); 1629 } else /* Deal with Packet TX case */ 1630 rtw_write8(pDM_Odm->Adapter, REG_TXPAUSE, 0x00); 1631 } 1632 1633 /* Analog Pre-distortion calibration */ 1634 #define APK_BB_REG_NUM 8 1635 #define APK_CURVE_REG_NUM 4 1636 #define PATH_NUM 2 1637 1638 #define DP_BB_REG_NUM 7 1639 #define DP_RF_REG_NUM 1 1640 #define DP_RETRY_LIMIT 10 1641 #define DP_PATH_NUM 2 1642 #define DP_DPK_NUM 3 1643 #define DP_DPK_VALUE_NUM 2 1644 1645 1646 1647 /* IQK version:V2.5 20140123 */ 1648 /* IQK is controlled by Is2ant, RF path */ 1649 void PHY_IQCalibrate_8723B( 1650 struct adapter *padapter, 1651 bool bReCovery, 1652 bool bRestore, 1653 bool Is2ant, /* false:1ant, true:2-ant */ 1654 u8 RF_Path /* 0:S1, 1:S0 */ 1655 ) 1656 { 1657 struct hal_com_data *pHalData = GET_HAL_DATA(padapter); 1658 1659 struct dm_odm_t *pDM_Odm = &pHalData->odmpriv; 1660 1661 s32 result[4][8]; /* last is final result */ 1662 u8 i, final_candidate; 1663 bool bPathAOK, bPathBOK; 1664 s32 RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0; 1665 bool is12simular, is13simular, is23simular; 1666 bool bSingleTone = false, bCarrierSuppression = false; 1667 u32 IQK_BB_REG_92C[IQK_BB_REG_NUM] = { 1668 rOFDM0_XARxIQImbalance, 1669 rOFDM0_XBRxIQImbalance, 1670 rOFDM0_ECCAThreshold, 1671 rOFDM0_AGCRSSITable, 1672 rOFDM0_XATxIQImbalance, 1673 rOFDM0_XBTxIQImbalance, 1674 rOFDM0_XCTxAFE, 1675 rOFDM0_XDTxAFE, 1676 rOFDM0_RxIQExtAnta 1677 }; 1678 /* u32 Path_SEL_BB = 0; */ 1679 u32 GNT_BT_default; 1680 u32 StartTime; 1681 s32 ProgressingTime; 1682 1683 if (!ODM_CheckPowerStatus(padapter)) 1684 return; 1685 1686 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) 1687 return; 1688 1689 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ 1690 if (bSingleTone || bCarrierSuppression) 1691 return; 1692 1693 #if DISABLE_BB_RF 1694 return; 1695 #endif 1696 if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) 1697 return; 1698 1699 1700 pDM_Odm->RFCalibrateInfo.bIQKInProgress = true; 1701 1702 if (bRestore) { 1703 u32 offset, data; 1704 u8 path, bResult = SUCCESS; 1705 struct odm_rf_cal_t *pRFCalibrateInfo = &pDM_Odm->RFCalibrateInfo; 1706 1707 path = (PHY_QueryBBReg(pDM_Odm->Adapter, rS0S1_PathSwitch, bMaskByte0) == 0x00) ? ODM_RF_PATH_A : ODM_RF_PATH_B; 1708 1709 /* Restore TX IQK */ 1710 for (i = 0; i < 3; ++i) { 1711 offset = pRFCalibrateInfo->TxIQC_8723B[path][i][0]; 1712 data = pRFCalibrateInfo->TxIQC_8723B[path][i][1]; 1713 if ((offset == 0) || (data == 0)) { 1714 bResult = FAIL; 1715 break; 1716 } 1717 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); 1718 } 1719 1720 /* Restore RX IQK */ 1721 for (i = 0; i < 2; ++i) { 1722 offset = pRFCalibrateInfo->RxIQC_8723B[path][i][0]; 1723 data = pRFCalibrateInfo->RxIQC_8723B[path][i][1]; 1724 if ((offset == 0) || (data == 0)) { 1725 bResult = FAIL; 1726 break; 1727 } 1728 PHY_SetBBReg(pDM_Odm->Adapter, offset, bMaskDWord, data); 1729 } 1730 1731 if (pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A] == 0) { 1732 bResult = FAIL; 1733 } else { 1734 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_A]); 1735 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_B, RF_TXM_IDAC, bRFRegOffsetMask, pDM_Odm->RFCalibrateInfo.TxLOK[ODM_RF_PATH_B]); 1736 } 1737 1738 if (bResult == SUCCESS) 1739 return; 1740 } 1741 1742 if (bReCovery) { 1743 _PHY_ReloadADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); 1744 return; 1745 } 1746 StartTime = jiffies; 1747 1748 /* save default GNT_BT */ 1749 GNT_BT_default = PHY_QueryBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord); 1750 /* Save RF Path */ 1751 /* Path_SEL_BB = PHY_QueryBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord); */ 1752 /* Path_SEL_RF = PHY_QueryRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff); */ 1753 1754 /* set GNT_BT = 0, pause BT traffic */ 1755 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ 1756 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */ 1757 1758 1759 for (i = 0; i < 8; i++) { 1760 result[0][i] = 0; 1761 result[1][i] = 0; 1762 result[2][i] = 0; 1763 result[3][i] = 0; 1764 } 1765 1766 final_candidate = 0xff; 1767 bPathAOK = false; 1768 bPathBOK = false; 1769 is12simular = false; 1770 is23simular = false; 1771 is13simular = false; 1772 1773 1774 for (i = 0; i < 3; i++) { 1775 phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path); 1776 1777 if (i == 1) { 1778 is12simular = phy_SimularityCompare_8723B(padapter, result, 0, 1); 1779 if (is12simular) { 1780 final_candidate = 0; 1781 break; 1782 } 1783 } 1784 1785 if (i == 2) { 1786 is13simular = phy_SimularityCompare_8723B(padapter, result, 0, 2); 1787 if (is13simular) { 1788 final_candidate = 0; 1789 1790 break; 1791 } 1792 1793 is23simular = phy_SimularityCompare_8723B(padapter, result, 1, 2); 1794 if (is23simular) { 1795 final_candidate = 1; 1796 } else { 1797 for (i = 0; i < 8; i++) 1798 RegTmp += result[3][i]; 1799 1800 if (RegTmp != 0) 1801 final_candidate = 3; 1802 else 1803 final_candidate = 0xFF; 1804 } 1805 } 1806 } 1807 1808 for (i = 0; i < 4; i++) { 1809 RegE94 = result[i][0]; 1810 RegE9C = result[i][1]; 1811 RegEA4 = result[i][2]; 1812 RegEAC = result[i][3]; 1813 RegEB4 = result[i][4]; 1814 RegEBC = result[i][5]; 1815 RegEC4 = result[i][6]; 1816 RegECC = result[i][7]; 1817 } 1818 1819 if (final_candidate != 0xff) { 1820 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0]; 1821 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1]; 1822 RegEA4 = result[final_candidate][2]; 1823 RegEAC = result[final_candidate][3]; 1824 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4]; 1825 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5]; 1826 RegEC4 = result[final_candidate][6]; 1827 RegECC = result[final_candidate][7]; 1828 bPathAOK = bPathBOK = true; 1829 } else { 1830 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100; /* X default value */ 1831 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0; /* Y default value */ 1832 } 1833 1834 { 1835 if (RegE94 != 0) 1836 _PHY_PathAFillIQKMatrix8723B(padapter, bPathAOK, result, final_candidate, (RegEA4 == 0)); 1837 } 1838 { 1839 if (RegEB4 != 0) 1840 _PHY_PathBFillIQKMatrix8723B(padapter, bPathBOK, result, final_candidate, (RegEC4 == 0)); 1841 } 1842 1843 /* To Fix BSOD when final_candidate is 0xff */ 1844 /* by sherry 20120321 */ 1845 if (final_candidate < 4) { 1846 for (i = 0; i < IQK_Matrix_REG_NUM; i++) 1847 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[0].Value[0][i] = result[final_candidate][i]; 1848 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[0].bIQKDone = true; 1849 } 1850 1851 _PHY_SaveADDARegisters8723B(padapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9); 1852 1853 /* restore GNT_BT */ 1854 PHY_SetBBReg(pDM_Odm->Adapter, 0x764, bMaskDWord, GNT_BT_default); 1855 /* Restore RF Path */ 1856 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x948, bMaskDWord, Path_SEL_BB); */ 1857 /* PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xb0, 0xfffff, Path_SEL_RF); */ 1858 1859 /* Resotr RX mode table parameter */ 1860 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_WE_LUT, 0x80000, 0x1); 1861 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x18000); 1862 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0001f); 1863 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xe6177); 1864 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0xed, 0x20, 0x1); 1865 PHY_SetRFReg(pDM_Odm->Adapter, ODM_RF_PATH_A, 0x43, bRFRegOffsetMask, 0x300bd); 1866 1867 /* set GNT_BT = HW control */ 1868 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */ 1869 /* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x0); */ 1870 1871 if (Is2ant) { 1872 if (RF_Path == 0x0) /* S1 */ 1873 ODM_SetIQCbyRFpath(pDM_Odm, 0); 1874 else /* S0 */ 1875 ODM_SetIQCbyRFpath(pDM_Odm, 1); 1876 } 1877 1878 pDM_Odm->RFCalibrateInfo.bIQKInProgress = false; 1879 1880 ProgressingTime = jiffies_to_msecs(jiffies - StartTime); 1881 1882 1883 } 1884 1885 1886 void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm) 1887 { 1888 bool bSingleTone = false, bCarrierSuppression = false; 1889 u32 timeout = 2000, timecount = 0; 1890 u32 StartTime; 1891 s32 ProgressingTime; 1892 1893 #if DISABLE_BB_RF 1894 return; 1895 #endif 1896 1897 if (!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION)) 1898 return; 1899 1900 /* 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu) */ 1901 if (bSingleTone || bCarrierSuppression) 1902 return; 1903 1904 StartTime = jiffies; 1905 while (*(pDM_Odm->pbScanInProcess) && timecount < timeout) { 1906 mdelay(50); 1907 timecount += 50; 1908 } 1909 1910 pDM_Odm->RFCalibrateInfo.bLCKInProgress = true; 1911 1912 1913 phy_LCCalibrate_8723B(pDM_Odm, false); 1914 1915 1916 pDM_Odm->RFCalibrateInfo.bLCKInProgress = false; 1917 1918 ProgressingTime = jiffies_to_msecs(jiffies - StartTime); 1919 } 1920