1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved. 5 * 6 ******************************************************************************/ 7 8 #include "Mp_Precomp.h" 9 10 /* defines */ 11 #define HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(val) \ 12 do { \ 13 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, val); \ 14 pCoexDm->psTdmaDuAdjType = val; \ 15 } while (0) 16 17 /* Global variables, these are static variables */ 18 static struct coex_dm_8723b_2ant GLCoexDm8723b2Ant; 19 static struct coex_dm_8723b_2ant *pCoexDm = &GLCoexDm8723b2Ant; 20 static struct coex_sta_8723b_2ant GLCoexSta8723b2Ant; 21 static struct coex_sta_8723b_2ant *pCoexSta = &GLCoexSta8723b2Ant; 22 23 static const char *const GLBtInfoSrc8723b2Ant[] = { 24 "BT Info[wifi fw]", 25 "BT Info[bt rsp]", 26 "BT Info[bt auto report]", 27 }; 28 29 static u32 GLCoexVerDate8723b2Ant = 20131211; 30 static u32 GLCoexVer8723b2Ant = 0x40; 31 32 /* local function start with halbtc8723b2ant_ */ 33 static u8 halbtc8723b2ant_BtRssiState( 34 u8 levelNum, u8 rssiThresh, u8 rssiThresh1 35 ) 36 { 37 s32 btRssi = 0; 38 u8 btRssiState = pCoexSta->preBtRssiState; 39 40 btRssi = pCoexSta->btRssi; 41 42 if (levelNum == 2) { 43 if ( 44 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || 45 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW) 46 ) { 47 if (btRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 48 btRssiState = BTC_RSSI_STATE_HIGH; 49 } else { 50 btRssiState = BTC_RSSI_STATE_STAY_LOW; 51 } 52 } else { 53 if (btRssi < rssiThresh) { 54 btRssiState = BTC_RSSI_STATE_LOW; 55 } else { 56 btRssiState = BTC_RSSI_STATE_STAY_HIGH; 57 } 58 } 59 } else if (levelNum == 3) { 60 if (rssiThresh > rssiThresh1) { 61 return pCoexSta->preBtRssiState; 62 } 63 64 if ( 65 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_LOW) || 66 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_LOW) 67 ) { 68 if (btRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 69 btRssiState = BTC_RSSI_STATE_MEDIUM; 70 } else { 71 btRssiState = BTC_RSSI_STATE_STAY_LOW; 72 } 73 } else if ( 74 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_MEDIUM) || 75 (pCoexSta->preBtRssiState == BTC_RSSI_STATE_STAY_MEDIUM) 76 ) { 77 if (btRssi >= (rssiThresh1 + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 78 btRssiState = BTC_RSSI_STATE_HIGH; 79 } else if (btRssi < rssiThresh) { 80 btRssiState = BTC_RSSI_STATE_LOW; 81 } else { 82 btRssiState = BTC_RSSI_STATE_STAY_MEDIUM; 83 } 84 } else { 85 if (btRssi < rssiThresh1) { 86 btRssiState = BTC_RSSI_STATE_MEDIUM; 87 } else { 88 btRssiState = BTC_RSSI_STATE_STAY_HIGH; 89 } 90 } 91 } 92 93 pCoexSta->preBtRssiState = btRssiState; 94 95 return btRssiState; 96 } 97 98 static u8 halbtc8723b2ant_WifiRssiState( 99 struct btc_coexist *pBtCoexist, 100 u8 index, 101 u8 levelNum, 102 u8 rssiThresh, 103 u8 rssiThresh1 104 ) 105 { 106 s32 wifiRssi = 0; 107 u8 wifiRssiState = pCoexSta->preWifiRssiState[index]; 108 109 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); 110 111 if (levelNum == 2) { 112 if ( 113 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || 114 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW) 115 ) { 116 if (wifiRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 117 wifiRssiState = BTC_RSSI_STATE_HIGH; 118 } else { 119 wifiRssiState = BTC_RSSI_STATE_STAY_LOW; 120 } 121 } else { 122 if (wifiRssi < rssiThresh) { 123 wifiRssiState = BTC_RSSI_STATE_LOW; 124 } else { 125 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; 126 } 127 } 128 } else if (levelNum == 3) { 129 if (rssiThresh > rssiThresh1) { 130 return pCoexSta->preWifiRssiState[index]; 131 } 132 133 if ( 134 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_LOW) || 135 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_LOW) 136 ) { 137 if (wifiRssi >= (rssiThresh + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 138 wifiRssiState = BTC_RSSI_STATE_MEDIUM; 139 } else { 140 wifiRssiState = BTC_RSSI_STATE_STAY_LOW; 141 } 142 } else if ( 143 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_MEDIUM) || 144 (pCoexSta->preWifiRssiState[index] == BTC_RSSI_STATE_STAY_MEDIUM) 145 ) { 146 if (wifiRssi >= (rssiThresh1 + BTC_RSSI_COEX_THRESH_TOL_8723B_2ANT)) { 147 wifiRssiState = BTC_RSSI_STATE_HIGH; 148 } else if (wifiRssi < rssiThresh) { 149 wifiRssiState = BTC_RSSI_STATE_LOW; 150 } else { 151 wifiRssiState = BTC_RSSI_STATE_STAY_MEDIUM; 152 } 153 } else { 154 if (wifiRssi < rssiThresh1) { 155 wifiRssiState = BTC_RSSI_STATE_MEDIUM; 156 } else { 157 wifiRssiState = BTC_RSSI_STATE_STAY_HIGH; 158 } 159 } 160 } 161 162 pCoexSta->preWifiRssiState[index] = wifiRssiState; 163 164 return wifiRssiState; 165 } 166 167 static void halbtc8723b2ant_LimitedRx( 168 struct btc_coexist *pBtCoexist, 169 bool bForceExec, 170 bool bRejApAggPkt, 171 bool bBtCtrlAggBufSize, 172 u8 aggBufSize 173 ) 174 { 175 bool bRejectRxAgg = bRejApAggPkt; 176 bool bBtCtrlRxAggSize = bBtCtrlAggBufSize; 177 u8 rxAggSize = aggBufSize; 178 179 /* */ 180 /* Rx Aggregation related setting */ 181 /* */ 182 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_TO_REJ_AP_AGG_PKT, &bRejectRxAgg); 183 /* decide BT control aggregation buf size or not */ 184 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_CTRL_AGG_SIZE, &bBtCtrlRxAggSize); 185 /* aggregation buf size, only work when BT control Rx aggregation size. */ 186 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize); 187 /* real update aggregation setting */ 188 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL); 189 } 190 191 static void halbtc8723b2ant_MonitorBtCtr(struct btc_coexist *pBtCoexist) 192 { 193 u32 regHPTxRx, regLPTxRx, u4Tmp; 194 u32 regHPTx = 0, regHPRx = 0, regLPTx = 0, regLPRx = 0; 195 196 regHPTxRx = 0x770; 197 regLPTxRx = 0x774; 198 199 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regHPTxRx); 200 regHPTx = u4Tmp & bMaskLWord; 201 regHPRx = (u4Tmp & bMaskHWord) >> 16; 202 203 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, regLPTxRx); 204 regLPTx = u4Tmp & bMaskLWord; 205 regLPRx = (u4Tmp & bMaskHWord) >> 16; 206 207 pCoexSta->highPriorityTx = regHPTx; 208 pCoexSta->highPriorityRx = regHPRx; 209 pCoexSta->lowPriorityTx = regLPTx; 210 pCoexSta->lowPriorityRx = regLPRx; 211 212 /* reset counter */ 213 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); 214 } 215 216 static void halbtc8723b2ant_QueryBtInfo(struct btc_coexist *pBtCoexist) 217 { 218 u8 H2C_Parameter[1] = {0}; 219 220 pCoexSta->bC2hBtInfoReqSent = true; 221 222 H2C_Parameter[0] |= BIT0; /* trigger */ 223 224 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x61, 1, H2C_Parameter); 225 } 226 227 static bool halbtc8723b2ant_IsWifiStatusChanged(struct btc_coexist *pBtCoexist) 228 { 229 static bool bPreWifiBusy, bPreUnder4way, bPreBtHsOn; 230 bool bWifiBusy = false, bUnder4way = false, bBtHsOn = false; 231 bool bWifiConnected = false; 232 233 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 234 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); 235 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 236 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_4_WAY_PROGRESS, &bUnder4way); 237 238 if (bWifiConnected) { 239 if (bWifiBusy != bPreWifiBusy) { 240 bPreWifiBusy = bWifiBusy; 241 return true; 242 } 243 244 if (bUnder4way != bPreUnder4way) { 245 bPreUnder4way = bUnder4way; 246 return true; 247 } 248 249 if (bBtHsOn != bPreBtHsOn) { 250 bPreBtHsOn = bBtHsOn; 251 return true; 252 } 253 } 254 255 return false; 256 } 257 258 static void halbtc8723b2ant_UpdateBtLinkInfo(struct btc_coexist *pBtCoexist) 259 { 260 struct btc_bt_link_info *pBtLinkInfo = &pBtCoexist->btLinkInfo; 261 bool bBtHsOn = false; 262 263 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 264 265 pBtLinkInfo->bBtLinkExist = pCoexSta->bBtLinkExist; 266 pBtLinkInfo->bScoExist = pCoexSta->bScoExist; 267 pBtLinkInfo->bA2dpExist = pCoexSta->bA2dpExist; 268 pBtLinkInfo->bPanExist = pCoexSta->bPanExist; 269 pBtLinkInfo->bHidExist = pCoexSta->bHidExist; 270 271 /* work around for HS mode. */ 272 if (bBtHsOn) { 273 pBtLinkInfo->bPanExist = true; 274 pBtLinkInfo->bBtLinkExist = true; 275 } 276 277 /* check if Sco only */ 278 if ( 279 pBtLinkInfo->bScoExist && 280 !pBtLinkInfo->bA2dpExist && 281 !pBtLinkInfo->bPanExist && 282 !pBtLinkInfo->bHidExist 283 ) 284 pBtLinkInfo->bScoOnly = true; 285 else 286 pBtLinkInfo->bScoOnly = false; 287 288 /* check if A2dp only */ 289 if ( 290 !pBtLinkInfo->bScoExist && 291 pBtLinkInfo->bA2dpExist && 292 !pBtLinkInfo->bPanExist && 293 !pBtLinkInfo->bHidExist 294 ) 295 pBtLinkInfo->bA2dpOnly = true; 296 else 297 pBtLinkInfo->bA2dpOnly = false; 298 299 /* check if Pan only */ 300 if ( 301 !pBtLinkInfo->bScoExist && 302 !pBtLinkInfo->bA2dpExist && 303 pBtLinkInfo->bPanExist && 304 !pBtLinkInfo->bHidExist 305 ) 306 pBtLinkInfo->bPanOnly = true; 307 else 308 pBtLinkInfo->bPanOnly = false; 309 310 /* check if Hid only */ 311 if ( 312 !pBtLinkInfo->bScoExist && 313 !pBtLinkInfo->bA2dpExist && 314 !pBtLinkInfo->bPanExist && 315 pBtLinkInfo->bHidExist 316 ) 317 pBtLinkInfo->bHidOnly = true; 318 else 319 pBtLinkInfo->bHidOnly = false; 320 } 321 322 static u8 halbtc8723b2ant_ActionAlgorithm(struct btc_coexist *pBtCoexist) 323 { 324 struct btc_bt_link_info *pBtLinkInfo = &pBtCoexist->btLinkInfo; 325 bool bBtHsOn = false; 326 u8 algorithm = BT_8723B_2ANT_COEX_ALGO_UNDEFINED; 327 u8 numOfDiffProfile = 0; 328 329 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 330 331 if (!pBtLinkInfo->bBtLinkExist) { 332 return algorithm; 333 } 334 335 if (pBtLinkInfo->bScoExist) 336 numOfDiffProfile++; 337 338 if (pBtLinkInfo->bHidExist) 339 numOfDiffProfile++; 340 341 if (pBtLinkInfo->bPanExist) 342 numOfDiffProfile++; 343 344 if (pBtLinkInfo->bA2dpExist) 345 numOfDiffProfile++; 346 347 if (numOfDiffProfile == 1) { 348 if (pBtLinkInfo->bScoExist) { 349 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; 350 } else { 351 if (pBtLinkInfo->bHidExist) { 352 algorithm = BT_8723B_2ANT_COEX_ALGO_HID; 353 } else if (pBtLinkInfo->bA2dpExist) { 354 algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP; 355 } else if (pBtLinkInfo->bPanExist) { 356 if (bBtHsOn) { 357 algorithm = BT_8723B_2ANT_COEX_ALGO_PANHS; 358 } else { 359 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR; 360 } 361 } 362 } 363 } else if (numOfDiffProfile == 2) { 364 if (pBtLinkInfo->bScoExist) { 365 if (pBtLinkInfo->bHidExist) { 366 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 367 } else if (pBtLinkInfo->bA2dpExist) { 368 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 369 } else if (pBtLinkInfo->bPanExist) { 370 if (bBtHsOn) { 371 algorithm = BT_8723B_2ANT_COEX_ALGO_SCO; 372 } else { 373 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 374 } 375 } 376 } else { 377 if ( 378 pBtLinkInfo->bHidExist && 379 pBtLinkInfo->bA2dpExist 380 ) { 381 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; 382 } else if ( 383 pBtLinkInfo->bHidExist && 384 pBtLinkInfo->bPanExist 385 ) { 386 if (bBtHsOn) { 387 algorithm = BT_8723B_2ANT_COEX_ALGO_HID; 388 } else { 389 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 390 } 391 } else if ( 392 pBtLinkInfo->bPanExist && 393 pBtLinkInfo->bA2dpExist 394 ) { 395 if (bBtHsOn) { 396 algorithm = BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS; 397 } else { 398 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP; 399 } 400 } 401 } 402 } else if (numOfDiffProfile == 3) { 403 if (pBtLinkInfo->bScoExist) { 404 if ( 405 pBtLinkInfo->bHidExist && 406 pBtLinkInfo->bA2dpExist 407 ) { 408 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 409 } else if ( 410 pBtLinkInfo->bHidExist && 411 pBtLinkInfo->bPanExist 412 ) { 413 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 414 } else if ( 415 pBtLinkInfo->bPanExist && 416 pBtLinkInfo->bA2dpExist 417 ) { 418 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 419 } 420 } else { 421 if ( 422 pBtLinkInfo->bHidExist && 423 pBtLinkInfo->bPanExist && 424 pBtLinkInfo->bA2dpExist 425 ) { 426 if (bBtHsOn) { 427 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP; 428 } else { 429 algorithm = BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR; 430 } 431 } 432 } 433 } else if (numOfDiffProfile >= 3) { 434 if (pBtLinkInfo->bScoExist) { 435 if ( 436 pBtLinkInfo->bHidExist && 437 pBtLinkInfo->bPanExist && 438 pBtLinkInfo->bA2dpExist 439 ) { 440 if (bBtHsOn) { 441 } else { 442 algorithm = BT_8723B_2ANT_COEX_ALGO_PANEDR_HID; 443 } 444 } 445 } 446 } 447 448 return algorithm; 449 } 450 451 static void halbtc8723b2ant_SetFwDacSwingLevel( 452 struct btc_coexist *pBtCoexist, u8 dacSwingLvl 453 ) 454 { 455 u8 H2C_Parameter[1] = {0}; 456 457 /* There are several type of dacswing */ 458 /* 0x18/ 0x10/ 0xc/ 0x8/ 0x4/ 0x6 */ 459 H2C_Parameter[0] = dacSwingLvl; 460 461 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x64, 1, H2C_Parameter); 462 } 463 464 static void halbtc8723b2ant_SetFwDecBtPwr( 465 struct btc_coexist *pBtCoexist, u8 decBtPwrLvl 466 ) 467 { 468 u8 H2C_Parameter[1] = {0}; 469 470 H2C_Parameter[0] = decBtPwrLvl; 471 472 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x62, 1, H2C_Parameter); 473 } 474 475 static void halbtc8723b2ant_DecBtPwr( 476 struct btc_coexist *pBtCoexist, bool bForceExec, u8 decBtPwrLvl 477 ) 478 { 479 pCoexDm->curBtDecPwrLvl = decBtPwrLvl; 480 481 if (!bForceExec) { 482 if (pCoexDm->preBtDecPwrLvl == pCoexDm->curBtDecPwrLvl) 483 return; 484 } 485 halbtc8723b2ant_SetFwDecBtPwr(pBtCoexist, pCoexDm->curBtDecPwrLvl); 486 487 pCoexDm->preBtDecPwrLvl = pCoexDm->curBtDecPwrLvl; 488 } 489 490 static void halbtc8723b2ant_FwDacSwingLvl( 491 struct btc_coexist *pBtCoexist, bool bForceExec, u8 fwDacSwingLvl 492 ) 493 { 494 pCoexDm->curFwDacSwingLvl = fwDacSwingLvl; 495 496 if (!bForceExec) { 497 if (pCoexDm->preFwDacSwingLvl == pCoexDm->curFwDacSwingLvl) 498 return; 499 } 500 501 halbtc8723b2ant_SetFwDacSwingLevel(pBtCoexist, pCoexDm->curFwDacSwingLvl); 502 503 pCoexDm->preFwDacSwingLvl = pCoexDm->curFwDacSwingLvl; 504 } 505 506 static void halbtc8723b2ant_SetSwRfRxLpfCorner( 507 struct btc_coexist *pBtCoexist, 508 bool bRxRfShrinkOn 509 ) 510 { 511 if (bRxRfShrinkOn) { 512 /* Shrink RF Rx LPF corner */ 513 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, 0xffffc); 514 } else { 515 /* Resume RF Rx LPF corner */ 516 /* After initialized, we can use pCoexDm->btRf0x1eBackup */ 517 if (pBtCoexist->bInitilized) { 518 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff, pCoexDm->btRf0x1eBackup); 519 } 520 } 521 } 522 523 static void halbtc8723b2ant_RfShrink( 524 struct btc_coexist *pBtCoexist, bool bForceExec, bool bRxRfShrinkOn 525 ) 526 { 527 pCoexDm->bCurRfRxLpfShrink = bRxRfShrinkOn; 528 529 if (!bForceExec) { 530 if (pCoexDm->bPreRfRxLpfShrink == pCoexDm->bCurRfRxLpfShrink) 531 return; 532 } 533 halbtc8723b2ant_SetSwRfRxLpfCorner(pBtCoexist, pCoexDm->bCurRfRxLpfShrink); 534 535 pCoexDm->bPreRfRxLpfShrink = pCoexDm->bCurRfRxLpfShrink; 536 } 537 538 static void halbtc8723b2ant_SetSwPenaltyTxRateAdaptive( 539 struct btc_coexist *pBtCoexist, bool bLowPenaltyRa 540 ) 541 { 542 u8 H2C_Parameter[6] = {0}; 543 544 H2C_Parameter[0] = 0x6; /* opCode, 0x6 = Retry_Penalty */ 545 546 if (bLowPenaltyRa) { 547 H2C_Parameter[1] |= BIT0; 548 H2C_Parameter[2] = 0x00; /* normal rate except MCS7/6/5, OFDM54/48/36 */ 549 H2C_Parameter[3] = 0xf7; /* MCS7 or OFDM54 */ 550 H2C_Parameter[4] = 0xf8; /* MCS6 or OFDM48 */ 551 H2C_Parameter[5] = 0xf9; /* MCS5 or OFDM36 */ 552 } 553 554 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x69, 6, H2C_Parameter); 555 } 556 557 static void halbtc8723b2ant_LowPenaltyRa( 558 struct btc_coexist *pBtCoexist, bool bForceExec, bool bLowPenaltyRa 559 ) 560 { 561 /* return; */ 562 pCoexDm->bCurLowPenaltyRa = bLowPenaltyRa; 563 564 if (!bForceExec) { 565 if (pCoexDm->bPreLowPenaltyRa == pCoexDm->bCurLowPenaltyRa) 566 return; 567 } 568 halbtc8723b2ant_SetSwPenaltyTxRateAdaptive(pBtCoexist, pCoexDm->bCurLowPenaltyRa); 569 570 pCoexDm->bPreLowPenaltyRa = pCoexDm->bCurLowPenaltyRa; 571 } 572 573 static void halbtc8723b2ant_SetDacSwingReg(struct btc_coexist *pBtCoexist, u32 level) 574 { 575 u8 val = (u8)level; 576 577 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x883, 0x3e, val); 578 } 579 580 static void halbtc8723b2ant_SetSwFullTimeDacSwing( 581 struct btc_coexist *pBtCoexist, bool bSwDacSwingOn, u32 swDacSwingLvl 582 ) 583 { 584 if (bSwDacSwingOn) 585 halbtc8723b2ant_SetDacSwingReg(pBtCoexist, swDacSwingLvl); 586 else 587 halbtc8723b2ant_SetDacSwingReg(pBtCoexist, 0x18); 588 } 589 590 591 static void halbtc8723b2ant_DacSwing( 592 struct btc_coexist *pBtCoexist, 593 bool bForceExec, 594 bool bDacSwingOn, 595 u32 dacSwingLvl 596 ) 597 { 598 pCoexDm->bCurDacSwingOn = bDacSwingOn; 599 pCoexDm->curDacSwingLvl = dacSwingLvl; 600 601 if (!bForceExec) { 602 if ((pCoexDm->bPreDacSwingOn == pCoexDm->bCurDacSwingOn) && 603 (pCoexDm->preDacSwingLvl == pCoexDm->curDacSwingLvl)) 604 return; 605 } 606 mdelay(30); 607 halbtc8723b2ant_SetSwFullTimeDacSwing(pBtCoexist, bDacSwingOn, dacSwingLvl); 608 609 pCoexDm->bPreDacSwingOn = pCoexDm->bCurDacSwingOn; 610 pCoexDm->preDacSwingLvl = pCoexDm->curDacSwingLvl; 611 } 612 613 static void halbtc8723b2ant_SetAgcTable( 614 struct btc_coexist *pBtCoexist, bool bAgcTableEn 615 ) 616 { 617 u8 rssiAdjustVal = 0; 618 619 /* BB AGC Gain Table */ 620 if (bAgcTableEn) { 621 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6e1A0001); 622 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6d1B0001); 623 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6c1C0001); 624 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6b1D0001); 625 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x6a1E0001); 626 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x691F0001); 627 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0x68200001); 628 } else { 629 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xaa1A0001); 630 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa91B0001); 631 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa81C0001); 632 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa71D0001); 633 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa61E0001); 634 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa51F0001); 635 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0xc78, 0xa4200001); 636 } 637 638 639 /* RF Gain */ 640 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x02000); 641 if (bAgcTableEn) { 642 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38fff); 643 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x38ffe); 644 } else { 645 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x380c3); 646 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x3b, 0xfffff, 0x28ce6); 647 } 648 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xef, 0xfffff, 0x0); 649 650 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x1); 651 if (bAgcTableEn) { 652 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38fff); 653 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x38ffe); 654 } else { 655 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x380c3); 656 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x40, 0xfffff, 0x28ce6); 657 } 658 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0xed, 0xfffff, 0x0); 659 660 /* set rssiAdjustVal for wifi module. */ 661 if (bAgcTableEn) 662 rssiAdjustVal = 8; 663 664 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_RSSI_ADJ_VAL_FOR_AGC_TABLE_ON, &rssiAdjustVal); 665 } 666 667 static void halbtc8723b2ant_AgcTable( 668 struct btc_coexist *pBtCoexist, bool bForceExec, bool bAgcTableEn 669 ) 670 { 671 pCoexDm->bCurAgcTableEn = bAgcTableEn; 672 673 if (!bForceExec) { 674 if (pCoexDm->bPreAgcTableEn == pCoexDm->bCurAgcTableEn) 675 return; 676 } 677 halbtc8723b2ant_SetAgcTable(pBtCoexist, bAgcTableEn); 678 679 pCoexDm->bPreAgcTableEn = pCoexDm->bCurAgcTableEn; 680 } 681 682 static void halbtc8723b2ant_SetCoexTable( 683 struct btc_coexist *pBtCoexist, 684 u32 val0x6c0, 685 u32 val0x6c4, 686 u32 val0x6c8, 687 u8 val0x6cc 688 ) 689 { 690 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c0, val0x6c0); 691 692 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c4, val0x6c4); 693 694 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x6c8, val0x6c8); 695 696 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x6cc, val0x6cc); 697 } 698 699 static void halbtc8723b2ant_CoexTable( 700 struct btc_coexist *pBtCoexist, 701 bool bForceExec, 702 u32 val0x6c0, 703 u32 val0x6c4, 704 u32 val0x6c8, 705 u8 val0x6cc 706 ) 707 { 708 pCoexDm->curVal0x6c0 = val0x6c0; 709 pCoexDm->curVal0x6c4 = val0x6c4; 710 pCoexDm->curVal0x6c8 = val0x6c8; 711 pCoexDm->curVal0x6cc = val0x6cc; 712 713 if (!bForceExec) { 714 if ( 715 (pCoexDm->preVal0x6c0 == pCoexDm->curVal0x6c0) && 716 (pCoexDm->preVal0x6c4 == pCoexDm->curVal0x6c4) && 717 (pCoexDm->preVal0x6c8 == pCoexDm->curVal0x6c8) && 718 (pCoexDm->preVal0x6cc == pCoexDm->curVal0x6cc) 719 ) 720 return; 721 } 722 halbtc8723b2ant_SetCoexTable(pBtCoexist, val0x6c0, val0x6c4, val0x6c8, val0x6cc); 723 724 pCoexDm->preVal0x6c0 = pCoexDm->curVal0x6c0; 725 pCoexDm->preVal0x6c4 = pCoexDm->curVal0x6c4; 726 pCoexDm->preVal0x6c8 = pCoexDm->curVal0x6c8; 727 pCoexDm->preVal0x6cc = pCoexDm->curVal0x6cc; 728 } 729 730 static void halbtc8723b2ant_CoexTableWithType( 731 struct btc_coexist *pBtCoexist, bool bForceExec, u8 type 732 ) 733 { 734 switch (type) { 735 case 0: 736 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x55555555, 0xffff, 0x3); 737 break; 738 case 1: 739 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55555555, 0x5afa5afa, 0xffff, 0x3); 740 break; 741 case 2: 742 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5a5a5a5a, 0x5a5a5a5a, 0xffff, 0x3); 743 break; 744 case 3: 745 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xaaaaaaaa, 0xaaaaaaaa, 0xffff, 0x3); 746 break; 747 case 4: 748 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0xffffffff, 0xffffffff, 0xffff, 0x3); 749 break; 750 case 5: 751 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5fff5fff, 0x5fff5fff, 0xffff, 0x3); 752 break; 753 case 6: 754 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5a5a5a, 0xffff, 0x3); 755 break; 756 case 7: 757 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0xfafafafa, 0xffff, 0x3); 758 break; 759 case 8: 760 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x5aea5aea, 0x5aea5aea, 0xffff, 0x3); 761 break; 762 case 9: 763 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5aea5aea, 0xffff, 0x3); 764 break; 765 case 10: 766 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5aff5aff, 0xffff, 0x3); 767 break; 768 case 11: 769 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5a5f5a5f, 0xffff, 0x3); 770 break; 771 case 12: 772 halbtc8723b2ant_CoexTable(pBtCoexist, bForceExec, 0x55ff55ff, 0x5f5f5f5f, 0xffff, 0x3); 773 break; 774 default: 775 break; 776 } 777 } 778 779 static void halbtc8723b2ant_SetFwIgnoreWlanAct( 780 struct btc_coexist *pBtCoexist, bool bEnable 781 ) 782 { 783 u8 H2C_Parameter[1] = {0}; 784 785 if (bEnable) 786 H2C_Parameter[0] |= BIT0; /* function enable */ 787 788 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x63, 1, H2C_Parameter); 789 } 790 791 static void halbtc8723b2ant_IgnoreWlanAct( 792 struct btc_coexist *pBtCoexist, bool bForceExec, bool bEnable 793 ) 794 { 795 pCoexDm->bCurIgnoreWlanAct = bEnable; 796 797 if (!bForceExec) { 798 if (pCoexDm->bPreIgnoreWlanAct == pCoexDm->bCurIgnoreWlanAct) 799 return; 800 } 801 halbtc8723b2ant_SetFwIgnoreWlanAct(pBtCoexist, bEnable); 802 803 pCoexDm->bPreIgnoreWlanAct = pCoexDm->bCurIgnoreWlanAct; 804 } 805 806 static void halbtc8723b2ant_SetFwPstdma( 807 struct btc_coexist *pBtCoexist, 808 u8 byte1, 809 u8 byte2, 810 u8 byte3, 811 u8 byte4, 812 u8 byte5 813 ) 814 { 815 u8 H2C_Parameter[5] = {0}; 816 817 H2C_Parameter[0] = byte1; 818 H2C_Parameter[1] = byte2; 819 H2C_Parameter[2] = byte3; 820 H2C_Parameter[3] = byte4; 821 H2C_Parameter[4] = byte5; 822 823 pCoexDm->psTdmaPara[0] = byte1; 824 pCoexDm->psTdmaPara[1] = byte2; 825 pCoexDm->psTdmaPara[2] = byte3; 826 pCoexDm->psTdmaPara[3] = byte4; 827 pCoexDm->psTdmaPara[4] = byte5; 828 829 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter); 830 } 831 832 static void halbtc8723b2ant_SwMechanism1( 833 struct btc_coexist *pBtCoexist, 834 bool bShrinkRxLPF, 835 bool bLowPenaltyRA, 836 bool bLimitedDIG, 837 bool bBTLNAConstrain 838 ) 839 { 840 halbtc8723b2ant_RfShrink(pBtCoexist, NORMAL_EXEC, bShrinkRxLPF); 841 halbtc8723b2ant_LowPenaltyRa(pBtCoexist, NORMAL_EXEC, bLowPenaltyRA); 842 } 843 844 static void halbtc8723b2ant_SwMechanism2( 845 struct btc_coexist *pBtCoexist, 846 bool bAGCTableShift, 847 bool bADCBackOff, 848 bool bSWDACSwing, 849 u32 dacSwingLvl 850 ) 851 { 852 halbtc8723b2ant_AgcTable(pBtCoexist, NORMAL_EXEC, bAGCTableShift); 853 halbtc8723b2ant_DacSwing(pBtCoexist, NORMAL_EXEC, bSWDACSwing, dacSwingLvl); 854 } 855 856 static void halbtc8723b2ant_SetAntPath( 857 struct btc_coexist *pBtCoexist, u8 antPosType, bool bInitHwCfg, bool bWifiOff 858 ) 859 { 860 struct btc_board_info *pBoardInfo = &pBtCoexist->boardInfo; 861 u32 fwVer = 0, u4Tmp = 0; 862 bool bPgExtSwitch = false; 863 bool bUseExtSwitch = false; 864 u8 H2C_Parameter[2] = {0}; 865 866 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_EXT_SWITCH, &bPgExtSwitch); 867 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); /* [31:16]=fw ver, [15:0]=fw sub ver */ 868 869 if ((fwVer > 0 && fwVer < 0xc0000) || bPgExtSwitch) 870 bUseExtSwitch = true; 871 872 if (bInitHwCfg) { 873 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x39, 0x8, 0x1); 874 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x974, 0xff); 875 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x944, 0x3, 0x3); 876 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x930, 0x77); 877 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); 878 879 if (fwVer >= 0x180000) { 880 /* Use H2C to set GNT_BT to LOW */ 881 H2C_Parameter[0] = 0; 882 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); 883 } else { 884 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x0); 885 } 886 887 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 888 889 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); /* WiFi TRx Mask off */ 890 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); /* BT TRx Mask off */ 891 892 if (pBoardInfo->btdmAntPos == BTC_ANTENNA_AT_MAIN_PORT) { 893 /* tell firmware "no antenna inverse" */ 894 H2C_Parameter[0] = 0; 895 } else { 896 /* tell firmware "antenna inverse" */ 897 H2C_Parameter[0] = 1; 898 } 899 900 if (bUseExtSwitch) { 901 /* ext switch type */ 902 H2C_Parameter[1] = 1; 903 } else { 904 /* int switch type */ 905 H2C_Parameter[1] = 0; 906 } 907 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x65, 2, H2C_Parameter); 908 } 909 910 /* ext switch setting */ 911 if (bUseExtSwitch) { 912 if (bInitHwCfg) { 913 /* 0x4c[23]= 0, 0x4c[24]= 1 Antenna control by WL/BT */ 914 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); 915 u4Tmp &= ~BIT23; 916 u4Tmp |= BIT24; 917 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); 918 } 919 920 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); /* fixed internal switch S1->WiFi, S0->BT */ 921 switch (antPosType) { 922 case BTC_ANT_WIFI_AT_MAIN: 923 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x1); /* ext switch main at wifi */ 924 break; 925 case BTC_ANT_WIFI_AT_AUX: 926 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x92c, 0x3, 0x2); /* ext switch aux at wifi */ 927 break; 928 } 929 } else { /* internal switch */ 930 if (bInitHwCfg) { 931 /* 0x4c[23]= 0, 0x4c[24]= 1 Antenna control by WL/BT */ 932 u4Tmp = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); 933 u4Tmp |= BIT23; 934 u4Tmp &= ~BIT24; 935 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x4c, u4Tmp); 936 } 937 938 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x64, 0x1, 0x0); /* fixed external switch S1->Main, S0->Aux */ 939 switch (antPosType) { 940 case BTC_ANT_WIFI_AT_MAIN: 941 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); /* fixed internal switch S1->WiFi, S0->BT */ 942 break; 943 case BTC_ANT_WIFI_AT_AUX: 944 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); /* fixed internal switch S0->WiFi, S1->BT */ 945 break; 946 } 947 } 948 } 949 950 static void halbtc8723b2ant_PsTdma( 951 struct btc_coexist *pBtCoexist, bool bForceExec, bool bTurnOn, u8 type 952 ) 953 { 954 pCoexDm->bCurPsTdmaOn = bTurnOn; 955 pCoexDm->curPsTdma = type; 956 957 if (!bForceExec) { 958 if ( 959 (pCoexDm->bPrePsTdmaOn == pCoexDm->bCurPsTdmaOn) && 960 (pCoexDm->prePsTdma == pCoexDm->curPsTdma) 961 ) 962 return; 963 } 964 965 if (bTurnOn) { 966 switch (type) { 967 case 1: 968 default: 969 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 970 break; 971 case 2: 972 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); 973 break; 974 case 3: 975 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0xf1, 0x90); 976 break; 977 case 4: 978 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x10, 0x03, 0xf1, 0x90); 979 break; 980 case 5: 981 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); 982 break; 983 case 6: 984 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); 985 break; 986 case 7: 987 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1c, 0x3, 0x70, 0x90); 988 break; 989 case 8: 990 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x10, 0x3, 0x70, 0x90); 991 break; 992 case 9: 993 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 994 break; 995 case 10: 996 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0xe1, 0x90); 997 break; 998 case 11: 999 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0xe1, 0x90); 1000 break; 1001 case 12: 1002 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); 1003 break; 1004 case 13: 1005 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0x60, 0x90); 1006 break; 1007 case 14: 1008 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x12, 0x12, 0x60, 0x90); 1009 break; 1010 case 15: 1011 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0xa, 0xa, 0x60, 0x90); 1012 break; 1013 case 16: 1014 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0x60, 0x90); 1015 break; 1016 case 17: 1017 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xa3, 0x2f, 0x2f, 0x60, 0x90); 1018 break; 1019 case 18: 1020 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x5, 0x5, 0xe1, 0x90); 1021 break; 1022 case 19: 1023 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0xe1, 0x90); 1024 break; 1025 case 20: 1026 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x25, 0x25, 0x60, 0x90); 1027 break; 1028 case 21: 1029 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x15, 0x03, 0x70, 0x90); 1030 break; 1031 case 71: 1032 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0xe3, 0x1a, 0x1a, 0xe1, 0x90); 1033 break; 1034 } 1035 } else { 1036 /* disable PS tdma */ 1037 switch (type) { 1038 case 0: 1039 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); 1040 break; 1041 case 1: 1042 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x48, 0x0); 1043 break; 1044 default: 1045 halbtc8723b2ant_SetFwPstdma(pBtCoexist, 0x0, 0x0, 0x0, 0x40, 0x0); 1046 break; 1047 } 1048 } 1049 1050 /* update pre state */ 1051 pCoexDm->bPrePsTdmaOn = pCoexDm->bCurPsTdmaOn; 1052 pCoexDm->prePsTdma = pCoexDm->curPsTdma; 1053 } 1054 1055 static void halbtc8723b2ant_CoexAllOff(struct btc_coexist *pBtCoexist) 1056 { 1057 /* fw all off */ 1058 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1059 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1060 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1061 1062 /* sw all off */ 1063 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1064 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1065 1066 /* hw all off */ 1067 /* pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); */ 1068 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1069 } 1070 1071 static void halbtc8723b2ant_InitCoexDm(struct btc_coexist *pBtCoexist) 1072 { 1073 /* force to reset coex mechanism */ 1074 1075 halbtc8723b2ant_PsTdma(pBtCoexist, FORCE_EXEC, false, 1); 1076 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); 1077 halbtc8723b2ant_DecBtPwr(pBtCoexist, FORCE_EXEC, 0); 1078 1079 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1080 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1081 } 1082 1083 static void halbtc8723b2ant_ActionBtInquiry(struct btc_coexist *pBtCoexist) 1084 { 1085 bool bWifiConnected = false; 1086 bool bLowPwrDisable = true; 1087 1088 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1089 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 1090 1091 if (bWifiConnected) { 1092 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1093 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 3); 1094 } else { 1095 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1096 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1097 } 1098 1099 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, FORCE_EXEC, 6); 1100 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1101 1102 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1103 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1104 1105 pCoexDm->bNeedRecover0x948 = true; 1106 pCoexDm->backup0x948 = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); 1107 1108 halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_AUX, false, false); 1109 } 1110 1111 static bool halbtc8723b2ant_IsCommonAction(struct btc_coexist *pBtCoexist) 1112 { 1113 u8 btRssiState = BTC_RSSI_STATE_HIGH; 1114 bool bCommon = false, bWifiConnected = false, bWifiBusy = false; 1115 bool bBtHsOn = false, bLowPwrDisable = false; 1116 1117 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 1118 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 1119 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); 1120 1121 if (!bWifiConnected) { 1122 bLowPwrDisable = false; 1123 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1124 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1125 1126 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1127 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1128 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1129 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1130 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1131 1132 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1133 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1134 1135 bCommon = true; 1136 } else { 1137 if (BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) { 1138 bLowPwrDisable = false; 1139 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1140 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1141 1142 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1143 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1144 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1145 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1146 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1147 1148 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1149 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1150 1151 bCommon = true; 1152 } else if (BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) { 1153 bLowPwrDisable = true; 1154 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1155 1156 if (bBtHsOn) 1157 return false; 1158 1159 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1160 1161 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1162 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1163 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1164 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1165 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1166 1167 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1168 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1169 1170 bCommon = true; 1171 } else { 1172 bLowPwrDisable = true; 1173 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_DISABLE_LOW_POWER, &bLowPwrDisable); 1174 1175 if (bWifiBusy) { 1176 bCommon = false; 1177 } else { 1178 if (bBtHsOn) 1179 return false; 1180 1181 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1182 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1183 1184 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1185 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1186 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 21); 1187 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 0xb); 1188 1189 if (BTC_RSSI_HIGH(btRssiState)) 1190 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1191 else 1192 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1193 1194 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1195 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1196 bCommon = true; 1197 } 1198 } 1199 } 1200 1201 return bCommon; 1202 } 1203 1204 static void halbtc8723b2ant_TdmaDurationAdjust( 1205 struct btc_coexist *pBtCoexist, bool bScoHid, bool bTxPause, u8 maxInterval 1206 ) 1207 { 1208 static s32 up, dn, m, n, WaitCount; 1209 s32 result; /* 0: no change, +1: increase WiFi duration, -1: decrease WiFi duration */ 1210 u8 retryCount = 0; 1211 1212 if (!pCoexDm->bAutoTdmaAdjust) { 1213 pCoexDm->bAutoTdmaAdjust = true; 1214 { 1215 if (bScoHid) { 1216 if (bTxPause) { 1217 if (maxInterval == 1) 1218 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1219 else if (maxInterval == 2) 1220 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1221 else 1222 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1223 } else { 1224 if (maxInterval == 1) 1225 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1226 else if (maxInterval == 2) 1227 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1228 else 1229 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1230 } 1231 } else { 1232 if (bTxPause) { 1233 if (maxInterval == 1) 1234 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1235 else if (maxInterval == 2) 1236 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1237 else 1238 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1239 } else { 1240 if (maxInterval == 1) 1241 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1242 else if (maxInterval == 2) 1243 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1244 else 1245 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1246 } 1247 } 1248 } 1249 /* */ 1250 up = 0; 1251 dn = 0; 1252 m = 1; 1253 n = 3; 1254 result = 0; 1255 WaitCount = 0; 1256 } else { 1257 /* acquire the BT TRx retry count from BT_Info byte2 */ 1258 retryCount = pCoexSta->btRetryCnt; 1259 result = 0; 1260 WaitCount++; 1261 1262 if (retryCount == 0) { /* no retry in the last 2-second duration */ 1263 up++; 1264 dn--; 1265 1266 if (dn <= 0) 1267 dn = 0; 1268 1269 if (up >= n) { /* if 連續 n 個2秒 retry count為0, 則調寬WiFi duration */ 1270 WaitCount = 0; 1271 n = 3; 1272 up = 0; 1273 dn = 0; 1274 result = 1; 1275 } 1276 } else if (retryCount <= 3) { /* <=3 retry in the last 2-second duration */ 1277 up--; 1278 dn++; 1279 1280 if (up <= 0) 1281 up = 0; 1282 1283 if (dn == 2) { /* if 連續 2 個2秒 retry count< 3, 則調窄WiFi duration */ 1284 if (WaitCount <= 2) 1285 m++; /* 避免一直在兩個level中來回 */ 1286 else 1287 m = 1; 1288 1289 if (m >= 20) /* m 最大值 = 20 ' 最大120秒 recheck是否調整 WiFi duration. */ 1290 m = 20; 1291 1292 n = 3 * m; 1293 up = 0; 1294 dn = 0; 1295 WaitCount = 0; 1296 result = -1; 1297 } 1298 } else { /* retry count > 3, 只要1次 retry count > 3, 則調窄WiFi duration */ 1299 if (WaitCount == 1) 1300 m++; /* 避免一直在兩個level中來回 */ 1301 else 1302 m = 1; 1303 1304 if (m >= 20) /* m 最大值 = 20 ' 最大120秒 recheck是否調整 WiFi duration. */ 1305 m = 20; 1306 1307 n = 3 * m; 1308 up = 0; 1309 dn = 0; 1310 WaitCount = 0; 1311 result = -1; 1312 } 1313 1314 if (maxInterval == 1) { 1315 if (bTxPause) { 1316 if (pCoexDm->curPsTdma == 71) 1317 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1318 else if (pCoexDm->curPsTdma == 1) 1319 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1320 else if (pCoexDm->curPsTdma == 2) 1321 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1322 else if (pCoexDm->curPsTdma == 3) 1323 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1324 else if (pCoexDm->curPsTdma == 4) 1325 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1326 1327 if (pCoexDm->curPsTdma == 9) 1328 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1329 else if (pCoexDm->curPsTdma == 10) 1330 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1331 else if (pCoexDm->curPsTdma == 11) 1332 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1333 else if (pCoexDm->curPsTdma == 12) 1334 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1335 1336 if (result == -1) { 1337 if (pCoexDm->curPsTdma == 5) 1338 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1339 else if (pCoexDm->curPsTdma == 6) 1340 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1341 else if (pCoexDm->curPsTdma == 7) 1342 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1343 else if (pCoexDm->curPsTdma == 13) 1344 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1345 else if (pCoexDm->curPsTdma == 14) 1346 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1347 else if (pCoexDm->curPsTdma == 15) 1348 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1349 } else if (result == 1) { 1350 if (pCoexDm->curPsTdma == 8) 1351 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1352 else if (pCoexDm->curPsTdma == 7) 1353 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1354 else if (pCoexDm->curPsTdma == 6) 1355 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(5); 1356 else if (pCoexDm->curPsTdma == 16) 1357 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1358 else if (pCoexDm->curPsTdma == 15) 1359 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1360 else if (pCoexDm->curPsTdma == 14) 1361 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(13); 1362 } 1363 } else { 1364 if (pCoexDm->curPsTdma == 5) 1365 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(71); 1366 else if (pCoexDm->curPsTdma == 6) 1367 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1368 else if (pCoexDm->curPsTdma == 7) 1369 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1370 else if (pCoexDm->curPsTdma == 8) 1371 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1372 1373 if (pCoexDm->curPsTdma == 13) 1374 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1375 else if (pCoexDm->curPsTdma == 14) 1376 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1377 else if (pCoexDm->curPsTdma == 15) 1378 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1379 else if (pCoexDm->curPsTdma == 16) 1380 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1381 1382 if (result == -1) { 1383 if (pCoexDm->curPsTdma == 71) 1384 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1385 else if (pCoexDm->curPsTdma == 1) 1386 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1387 else if (pCoexDm->curPsTdma == 2) 1388 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1389 else if (pCoexDm->curPsTdma == 3) 1390 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1391 else if (pCoexDm->curPsTdma == 9) 1392 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1393 else if (pCoexDm->curPsTdma == 10) 1394 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1395 else if (pCoexDm->curPsTdma == 11) 1396 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1397 } else if (result == 1) { 1398 if (pCoexDm->curPsTdma == 4) 1399 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1400 else if (pCoexDm->curPsTdma == 3) 1401 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1402 else if (pCoexDm->curPsTdma == 2) 1403 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(1); 1404 else if (pCoexDm->curPsTdma == 1) 1405 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(71); 1406 else if (pCoexDm->curPsTdma == 12) 1407 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1408 else if (pCoexDm->curPsTdma == 11) 1409 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1410 else if (pCoexDm->curPsTdma == 10) 1411 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(9); 1412 } 1413 } 1414 } else if (maxInterval == 2) { 1415 if (bTxPause) { 1416 if (pCoexDm->curPsTdma == 1) 1417 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1418 else if (pCoexDm->curPsTdma == 2) 1419 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1420 else if (pCoexDm->curPsTdma == 3) 1421 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1422 else if (pCoexDm->curPsTdma == 4) 1423 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1424 1425 if (pCoexDm->curPsTdma == 9) 1426 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1427 else if (pCoexDm->curPsTdma == 10) 1428 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1429 else if (pCoexDm->curPsTdma == 11) 1430 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1431 else if (pCoexDm->curPsTdma == 12) 1432 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1433 1434 if (result == -1) { 1435 if (pCoexDm->curPsTdma == 5) 1436 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1437 else if (pCoexDm->curPsTdma == 6) 1438 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1439 else if (pCoexDm->curPsTdma == 7) 1440 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1441 else if (pCoexDm->curPsTdma == 13) 1442 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1443 else if (pCoexDm->curPsTdma == 14) 1444 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1445 else if (pCoexDm->curPsTdma == 15) 1446 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1447 } else if (result == 1) { 1448 if (pCoexDm->curPsTdma == 8) 1449 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1450 else if (pCoexDm->curPsTdma == 7) 1451 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1452 else if (pCoexDm->curPsTdma == 6) 1453 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(6); 1454 else if (pCoexDm->curPsTdma == 16) 1455 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1456 else if (pCoexDm->curPsTdma == 15) 1457 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1458 else if (pCoexDm->curPsTdma == 14) 1459 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(14); 1460 } 1461 } else { 1462 if (pCoexDm->curPsTdma == 5) 1463 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1464 else if (pCoexDm->curPsTdma == 6) 1465 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1466 else if (pCoexDm->curPsTdma == 7) 1467 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1468 else if (pCoexDm->curPsTdma == 8) 1469 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1470 1471 if (pCoexDm->curPsTdma == 13) 1472 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1473 else if (pCoexDm->curPsTdma == 14) 1474 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1475 else if (pCoexDm->curPsTdma == 15) 1476 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1477 else if (pCoexDm->curPsTdma == 16) 1478 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1479 1480 if (result == -1) { 1481 if (pCoexDm->curPsTdma == 1) 1482 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1483 else if (pCoexDm->curPsTdma == 2) 1484 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1485 else if (pCoexDm->curPsTdma == 3) 1486 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1487 else if (pCoexDm->curPsTdma == 9) 1488 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1489 else if (pCoexDm->curPsTdma == 10) 1490 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1491 else if (pCoexDm->curPsTdma == 11) 1492 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1493 } else if (result == 1) { 1494 if (pCoexDm->curPsTdma == 4) 1495 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1496 else if (pCoexDm->curPsTdma == 3) 1497 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1498 else if (pCoexDm->curPsTdma == 2) 1499 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(2); 1500 else if (pCoexDm->curPsTdma == 12) 1501 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1502 else if (pCoexDm->curPsTdma == 11) 1503 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1504 else if (pCoexDm->curPsTdma == 10) 1505 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(10); 1506 } 1507 } 1508 } else if (maxInterval == 3) { 1509 if (bTxPause) { 1510 if (pCoexDm->curPsTdma == 1) 1511 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1512 else if (pCoexDm->curPsTdma == 2) 1513 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1514 else if (pCoexDm->curPsTdma == 3) 1515 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1516 else if (pCoexDm->curPsTdma == 4) 1517 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1518 1519 if (pCoexDm->curPsTdma == 9) 1520 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1521 else if (pCoexDm->curPsTdma == 10) 1522 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1523 else if (pCoexDm->curPsTdma == 11) 1524 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1525 else if (pCoexDm->curPsTdma == 12) 1526 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1527 1528 if (result == -1) { 1529 if (pCoexDm->curPsTdma == 5) 1530 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1531 else if (pCoexDm->curPsTdma == 6) 1532 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1533 else if (pCoexDm->curPsTdma == 7) 1534 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(8); 1535 else if (pCoexDm->curPsTdma == 13) 1536 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1537 else if (pCoexDm->curPsTdma == 14) 1538 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1539 else if (pCoexDm->curPsTdma == 15) 1540 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(16); 1541 } else if (result == 1) { 1542 if (pCoexDm->curPsTdma == 8) 1543 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1544 else if (pCoexDm->curPsTdma == 7) 1545 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1546 else if (pCoexDm->curPsTdma == 6) 1547 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(7); 1548 else if (pCoexDm->curPsTdma == 16) 1549 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1550 else if (pCoexDm->curPsTdma == 15) 1551 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1552 else if (pCoexDm->curPsTdma == 14) 1553 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(15); 1554 } 1555 } else { 1556 if (pCoexDm->curPsTdma == 5) 1557 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1558 else if (pCoexDm->curPsTdma == 6) 1559 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1560 else if (pCoexDm->curPsTdma == 7) 1561 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1562 else if (pCoexDm->curPsTdma == 8) 1563 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1564 1565 if (pCoexDm->curPsTdma == 13) 1566 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1567 else if (pCoexDm->curPsTdma == 14) 1568 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1569 else if (pCoexDm->curPsTdma == 15) 1570 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1571 else if (pCoexDm->curPsTdma == 16) 1572 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1573 1574 if (result == -1) { 1575 if (pCoexDm->curPsTdma == 1) 1576 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1577 else if (pCoexDm->curPsTdma == 2) 1578 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1579 else if (pCoexDm->curPsTdma == 3) 1580 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(4); 1581 else if (pCoexDm->curPsTdma == 9) 1582 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1583 else if (pCoexDm->curPsTdma == 10) 1584 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1585 else if (pCoexDm->curPsTdma == 11) 1586 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(12); 1587 } else if (result == 1) { 1588 if (pCoexDm->curPsTdma == 4) 1589 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1590 else if (pCoexDm->curPsTdma == 3) 1591 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1592 else if (pCoexDm->curPsTdma == 2) 1593 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(3); 1594 else if (pCoexDm->curPsTdma == 12) 1595 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1596 else if (pCoexDm->curPsTdma == 11) 1597 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1598 else if (pCoexDm->curPsTdma == 10) 1599 HAL_BTC8723B2ANT_DMA_DURATION_ADJUST(11); 1600 } 1601 } 1602 } 1603 } 1604 1605 /* if current PsTdma not match with the recorded one (when scan, dhcp...), */ 1606 /* then we have to adjust it back to the previous record one. */ 1607 if (pCoexDm->curPsTdma != pCoexDm->psTdmaDuAdjType) { 1608 bool bScan = false, bLink = false, bRoam = false; 1609 1610 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); 1611 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); 1612 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); 1613 1614 if (!bScan && !bLink && !bRoam) 1615 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, pCoexDm->psTdmaDuAdjType); 1616 1617 } 1618 } 1619 1620 /* SCO only or SCO+PAN(HS) */ 1621 static void halbtc8723b2ant_ActionSco(struct btc_coexist *pBtCoexist) 1622 { 1623 u8 wifiRssiState, btRssiState; 1624 u32 wifiBw; 1625 1626 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1627 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1628 1629 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1630 1631 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1632 1633 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 4); 1634 1635 if (BTC_RSSI_HIGH(btRssiState)) 1636 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1637 else 1638 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1639 1640 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1641 1642 if (BTC_WIFI_BW_LEGACY == wifiBw) /* for SCO quality at 11b/g mode */ 1643 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 2); 1644 else /* for SCO quality & wifi performance balance at 11n mode */ 1645 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 8); 1646 1647 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 0); /* for voice quality */ 1648 1649 /* sw mechanism */ 1650 if (BTC_WIFI_BW_HT40 == wifiBw) { 1651 if ( 1652 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1653 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1654 ) { 1655 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1656 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x4); 1657 } else { 1658 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1659 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, true, 0x4); 1660 } 1661 } else { 1662 if ( 1663 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1664 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1665 ) { 1666 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1667 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x4); 1668 } else { 1669 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1670 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, true, 0x4); 1671 } 1672 } 1673 } 1674 1675 1676 static void halbtc8723b2ant_ActionHid(struct btc_coexist *pBtCoexist) 1677 { 1678 u8 wifiRssiState, btRssiState; 1679 u32 wifiBw; 1680 1681 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1682 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1683 1684 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1685 1686 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1687 1688 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1689 1690 if (BTC_RSSI_HIGH(btRssiState)) 1691 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1692 else 1693 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1694 1695 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1696 1697 if (BTC_WIFI_BW_LEGACY == wifiBw) /* for HID at 11b/g mode */ 1698 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1699 else /* for HID quality & wifi performance balance at 11n mode */ 1700 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 9); 1701 1702 if ( 1703 (btRssiState == BTC_RSSI_STATE_HIGH) || 1704 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1705 ) 1706 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 9); 1707 else 1708 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 13); 1709 1710 /* sw mechanism */ 1711 if (BTC_WIFI_BW_HT40 == wifiBw) { 1712 if ( 1713 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1714 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1715 ) { 1716 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1717 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1718 } else { 1719 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 1720 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1721 } 1722 } else { 1723 if ( 1724 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1725 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1726 ) { 1727 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1728 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1729 } else { 1730 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 1731 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1732 } 1733 } 1734 } 1735 1736 /* A2DP only / PAN(EDR) only/ A2DP+PAN(HS) */ 1737 static void halbtc8723b2ant_ActionA2dp(struct btc_coexist *pBtCoexist) 1738 { 1739 u8 wifiRssiState, wifiRssiState1, btRssiState; 1740 u32 wifiBw; 1741 u8 apNum = 0; 1742 1743 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1744 wifiRssiState1 = halbtc8723b2ant_WifiRssiState(pBtCoexist, 1, 2, 40, 0); 1745 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1746 1747 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 1748 1749 /* define the office environment */ 1750 if (apNum >= 10 && BTC_RSSI_HIGH(wifiRssiState1)) { 1751 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1752 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1753 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1754 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1755 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 0); 1756 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1757 1758 /* sw mechanism */ 1759 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1760 if (BTC_WIFI_BW_HT40 == wifiBw) { 1761 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1762 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x18); 1763 } else { 1764 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1765 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, true, 0x18); 1766 } 1767 return; 1768 } 1769 1770 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1771 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1772 1773 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1774 1775 if (BTC_RSSI_HIGH(btRssiState)) 1776 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1777 else 1778 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1779 1780 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1781 1782 if ( 1783 (btRssiState == BTC_RSSI_STATE_HIGH) || 1784 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1785 ) 1786 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, false, 1); 1787 else 1788 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 1); 1789 1790 /* sw mechanism */ 1791 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1792 if (BTC_WIFI_BW_HT40 == wifiBw) { 1793 if ( 1794 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1795 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1796 ) { 1797 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1798 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1799 } else { 1800 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1801 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1802 } 1803 } else { 1804 if ( 1805 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1806 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1807 ) { 1808 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1809 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1810 } else { 1811 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1812 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1813 } 1814 } 1815 } 1816 1817 static void halbtc8723b2ant_ActionA2dpPanHs(struct btc_coexist *pBtCoexist) 1818 { 1819 u8 wifiRssiState, btRssiState; 1820 u32 wifiBw; 1821 1822 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1823 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1824 1825 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1826 1827 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1828 1829 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1830 1831 if (BTC_RSSI_HIGH(btRssiState)) 1832 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1833 else 1834 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1835 1836 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1837 1838 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 2); 1839 1840 /* sw mechanism */ 1841 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1842 if (BTC_WIFI_BW_HT40 == wifiBw) { 1843 if ( 1844 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1845 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1846 ) { 1847 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1848 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1849 } else { 1850 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1851 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1852 } 1853 } else { 1854 if ( 1855 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1856 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1857 ) { 1858 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1859 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1860 } else { 1861 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1862 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1863 } 1864 } 1865 } 1866 1867 static void halbtc8723b2ant_ActionPanEdr(struct btc_coexist *pBtCoexist) 1868 { 1869 u8 wifiRssiState, btRssiState; 1870 u32 wifiBw; 1871 1872 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1873 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1874 1875 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1876 1877 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1878 1879 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1880 1881 if (BTC_RSSI_HIGH(btRssiState)) 1882 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1883 else 1884 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1885 1886 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 10); 1887 1888 if ( 1889 (btRssiState == BTC_RSSI_STATE_HIGH) || 1890 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1891 ) 1892 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 1); 1893 else 1894 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, true, 5); 1895 1896 /* sw mechanism */ 1897 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1898 if (BTC_WIFI_BW_HT40 == wifiBw) { 1899 if ( 1900 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1901 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1902 ) { 1903 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1904 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1905 } else { 1906 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1907 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1908 } 1909 } else { 1910 if ( 1911 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1912 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1913 ) { 1914 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1915 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1916 } else { 1917 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1918 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1919 } 1920 } 1921 } 1922 1923 1924 /* PAN(HS) only */ 1925 static void halbtc8723b2ant_ActionPanHs(struct btc_coexist *pBtCoexist) 1926 { 1927 u8 wifiRssiState, btRssiState; 1928 u32 wifiBw; 1929 1930 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1931 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1932 1933 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1934 1935 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1936 1937 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1938 1939 if (BTC_RSSI_HIGH(btRssiState)) 1940 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1941 else 1942 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1943 1944 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 1945 1946 halbtc8723b2ant_PsTdma(pBtCoexist, NORMAL_EXEC, false, 1); 1947 1948 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1949 if (BTC_WIFI_BW_HT40 == wifiBw) { 1950 if ( 1951 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1952 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1953 ) { 1954 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1955 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1956 } else { 1957 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 1958 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1959 } 1960 } else { 1961 if ( 1962 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 1963 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 1964 ) { 1965 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1966 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 1967 } else { 1968 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 1969 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 1970 } 1971 } 1972 } 1973 1974 /* PAN(EDR)+A2DP */ 1975 static void halbtc8723b2ant_ActionPanEdrA2dp(struct btc_coexist *pBtCoexist) 1976 { 1977 u8 wifiRssiState, btRssiState; 1978 u32 wifiBw; 1979 1980 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 1981 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 1982 1983 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 1984 1985 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 1986 1987 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 1988 1989 if (BTC_RSSI_HIGH(btRssiState)) 1990 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 1991 else 1992 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 1993 1994 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 1995 1996 if ( 1997 (btRssiState == BTC_RSSI_STATE_HIGH) || 1998 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 1999 ) { 2000 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 12); 2001 if (BTC_WIFI_BW_HT40 == wifiBw) 2002 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 3); 2003 else 2004 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, false, 3); 2005 } else { 2006 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2007 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, false, true, 3); 2008 } 2009 2010 /* sw mechanism */ 2011 if (BTC_WIFI_BW_HT40 == wifiBw) { 2012 if ( 2013 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2014 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2015 ) { 2016 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 2017 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2018 } else { 2019 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, false, false, false); 2020 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2021 } 2022 } else { 2023 if ( 2024 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2025 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2026 ) { 2027 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 2028 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2029 } else { 2030 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, false, false, false); 2031 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2032 } 2033 } 2034 } 2035 2036 static void halbtc8723b2ant_ActionPanEdrHid(struct btc_coexist *pBtCoexist) 2037 { 2038 u8 wifiRssiState, btRssiState; 2039 u32 wifiBw; 2040 2041 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2042 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 2043 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2044 2045 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 2046 2047 if (BTC_RSSI_HIGH(btRssiState)) 2048 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2049 else 2050 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2051 2052 if ( 2053 (btRssiState == BTC_RSSI_STATE_HIGH) || 2054 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2055 ) { 2056 if (BTC_WIFI_BW_HT40 == wifiBw) { 2057 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 3); 2058 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); 2059 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); 2060 } else { 2061 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2062 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2063 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2064 } 2065 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 2); 2066 } else { 2067 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2068 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 11); 2069 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2070 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2071 } 2072 2073 /* sw mechanism */ 2074 if (BTC_WIFI_BW_HT40 == wifiBw) { 2075 if ( 2076 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2077 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2078 ) { 2079 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2080 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2081 } else { 2082 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2083 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2084 } 2085 } else { 2086 if ( 2087 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2088 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2089 ) { 2090 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2091 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2092 } else { 2093 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2094 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2095 } 2096 } 2097 } 2098 2099 /* HID+A2DP+PAN(EDR) */ 2100 static void halbtc8723b2ant_ActionHidA2dpPanEdr(struct btc_coexist *pBtCoexist) 2101 { 2102 u8 wifiRssiState, btRssiState; 2103 u32 wifiBw; 2104 2105 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2106 btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); 2107 2108 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2109 2110 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, false, 0x8); 2111 2112 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2113 2114 if (BTC_RSSI_HIGH(btRssiState)) 2115 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2116 else 2117 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2118 2119 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2120 2121 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2122 2123 if ( 2124 (btRssiState == BTC_RSSI_STATE_HIGH) || 2125 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2126 ) { 2127 if (BTC_WIFI_BW_HT40 == wifiBw) 2128 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2129 else 2130 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 3); 2131 } else 2132 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 3); 2133 2134 /* sw mechanism */ 2135 if (BTC_WIFI_BW_HT40 == wifiBw) { 2136 if ( 2137 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2138 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2139 ) { 2140 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2141 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2142 } else { 2143 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2144 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2145 } 2146 } else { 2147 if ( 2148 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2149 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2150 ) { 2151 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2152 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2153 } else { 2154 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2155 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2156 } 2157 } 2158 } 2159 2160 static void halbtc8723b2ant_ActionHidA2dp(struct btc_coexist *pBtCoexist) 2161 { 2162 u8 wifiRssiState, btRssiState; 2163 u32 wifiBw; 2164 u8 apNum = 0; 2165 2166 wifiRssiState = halbtc8723b2ant_WifiRssiState(pBtCoexist, 0, 2, 15, 0); 2167 /* btRssiState = halbtc8723b2ant_BtRssiState(2, 29, 0); */ 2168 btRssiState = halbtc8723b2ant_BtRssiState(3, 29, 37); 2169 2170 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x0); 2171 2172 halbtc8723b2ant_LimitedRx(pBtCoexist, NORMAL_EXEC, false, true, 0x5); 2173 2174 halbtc8723b2ant_FwDacSwingLvl(pBtCoexist, NORMAL_EXEC, 6); 2175 2176 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2177 if (BTC_WIFI_BW_LEGACY == wifiBw) { 2178 if (BTC_RSSI_HIGH(btRssiState)) 2179 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2180 else if (BTC_RSSI_MEDIUM(btRssiState)) 2181 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2182 else 2183 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2184 } else { 2185 /* only 802.11N mode we have to dec bt power to 4 degree */ 2186 if (BTC_RSSI_HIGH(btRssiState)) { 2187 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 2188 /* need to check ap Number of Not */ 2189 if (apNum < 10) 2190 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 4); 2191 else 2192 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2193 } else if (BTC_RSSI_MEDIUM(btRssiState)) 2194 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 2); 2195 else 2196 halbtc8723b2ant_DecBtPwr(pBtCoexist, NORMAL_EXEC, 0); 2197 } 2198 2199 halbtc8723b2ant_CoexTableWithType(pBtCoexist, NORMAL_EXEC, 7); 2200 2201 if ( 2202 (btRssiState == BTC_RSSI_STATE_HIGH) || 2203 (btRssiState == BTC_RSSI_STATE_STAY_HIGH) 2204 ) 2205 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, false, 2); 2206 else 2207 halbtc8723b2ant_TdmaDurationAdjust(pBtCoexist, true, true, 2); 2208 2209 /* sw mechanism */ 2210 if (BTC_WIFI_BW_HT40 == wifiBw) { 2211 if ( 2212 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2213 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2214 ) { 2215 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2216 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2217 } else { 2218 halbtc8723b2ant_SwMechanism1(pBtCoexist, true, true, false, false); 2219 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2220 } 2221 } else { 2222 if ( 2223 (wifiRssiState == BTC_RSSI_STATE_HIGH) || 2224 (wifiRssiState == BTC_RSSI_STATE_STAY_HIGH) 2225 ) { 2226 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2227 halbtc8723b2ant_SwMechanism2(pBtCoexist, true, false, false, 0x18); 2228 } else { 2229 halbtc8723b2ant_SwMechanism1(pBtCoexist, false, true, false, false); 2230 halbtc8723b2ant_SwMechanism2(pBtCoexist, false, false, false, 0x18); 2231 } 2232 } 2233 } 2234 2235 static void halbtc8723b2ant_RunCoexistMechanism(struct btc_coexist *pBtCoexist) 2236 { 2237 u8 algorithm = 0; 2238 2239 if (pBtCoexist->bManualControl) { 2240 return; 2241 } 2242 2243 if (pCoexSta->bUnderIps) { 2244 return; 2245 } 2246 2247 algorithm = halbtc8723b2ant_ActionAlgorithm(pBtCoexist); 2248 if (pCoexSta->bC2hBtInquiryPage && (BT_8723B_2ANT_COEX_ALGO_PANHS != algorithm)) { 2249 halbtc8723b2ant_ActionBtInquiry(pBtCoexist); 2250 return; 2251 } else { 2252 if (pCoexDm->bNeedRecover0x948) { 2253 pCoexDm->bNeedRecover0x948 = false; 2254 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, pCoexDm->backup0x948); 2255 } 2256 } 2257 2258 pCoexDm->curAlgorithm = algorithm; 2259 2260 if (halbtc8723b2ant_IsCommonAction(pBtCoexist)) { 2261 pCoexDm->bAutoTdmaAdjust = false; 2262 } else { 2263 if (pCoexDm->curAlgorithm != pCoexDm->preAlgorithm) { 2264 pCoexDm->bAutoTdmaAdjust = false; 2265 } 2266 2267 2268 switch (pCoexDm->curAlgorithm) { 2269 case BT_8723B_2ANT_COEX_ALGO_SCO: 2270 halbtc8723b2ant_ActionSco(pBtCoexist); 2271 break; 2272 case BT_8723B_2ANT_COEX_ALGO_HID: 2273 halbtc8723b2ant_ActionHid(pBtCoexist); 2274 break; 2275 case BT_8723B_2ANT_COEX_ALGO_A2DP: 2276 halbtc8723b2ant_ActionA2dp(pBtCoexist); 2277 break; 2278 case BT_8723B_2ANT_COEX_ALGO_A2DP_PANHS: 2279 halbtc8723b2ant_ActionA2dpPanHs(pBtCoexist); 2280 break; 2281 case BT_8723B_2ANT_COEX_ALGO_PANEDR: 2282 halbtc8723b2ant_ActionPanEdr(pBtCoexist); 2283 break; 2284 case BT_8723B_2ANT_COEX_ALGO_PANHS: 2285 halbtc8723b2ant_ActionPanHs(pBtCoexist); 2286 break; 2287 case BT_8723B_2ANT_COEX_ALGO_PANEDR_A2DP: 2288 halbtc8723b2ant_ActionPanEdrA2dp(pBtCoexist); 2289 break; 2290 case BT_8723B_2ANT_COEX_ALGO_PANEDR_HID: 2291 halbtc8723b2ant_ActionPanEdrHid(pBtCoexist); 2292 break; 2293 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP_PANEDR: 2294 halbtc8723b2ant_ActionHidA2dpPanEdr(pBtCoexist); 2295 break; 2296 case BT_8723B_2ANT_COEX_ALGO_HID_A2DP: 2297 halbtc8723b2ant_ActionHidA2dp(pBtCoexist); 2298 break; 2299 default: 2300 halbtc8723b2ant_CoexAllOff(pBtCoexist); 2301 break; 2302 } 2303 pCoexDm->preAlgorithm = pCoexDm->curAlgorithm; 2304 } 2305 } 2306 2307 static void halbtc8723b2ant_WifiOffHwCfg(struct btc_coexist *pBtCoexist) 2308 { 2309 bool bIsInMpMode = false; 2310 u8 H2C_Parameter[2] = {0}; 2311 u32 fwVer = 0; 2312 2313 /* set wlan_act to low */ 2314 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); 2315 2316 pBtCoexist->fBtcSetRfReg(pBtCoexist, BTC_RF_A, 0x1, 0xfffff, 0x780); /* WiFi goto standby while GNT_BT 0-->1 */ 2317 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); 2318 if (fwVer >= 0x180000) { 2319 /* Use H2C to set GNT_BT to HIGH */ 2320 H2C_Parameter[0] = 1; 2321 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x6E, 1, H2C_Parameter); 2322 } else 2323 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); 2324 2325 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_IS_IN_MP_MODE, &bIsInMpMode); 2326 if (!bIsInMpMode) 2327 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x0); /* BT select s0/s1 is controlled by BT */ 2328 else 2329 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x67, 0x20, 0x1); /* BT select s0/s1 is controlled by WiFi */ 2330 } 2331 2332 static void halbtc8723b2ant_InitHwConfig(struct btc_coexist *pBtCoexist, bool bBackUp) 2333 { 2334 u8 u1Tmp = 0; 2335 2336 /* backup rf 0x1e value */ 2337 pCoexDm->btRf0x1eBackup = 2338 pBtCoexist->fBtcGetRfReg(pBtCoexist, BTC_RF_A, 0x1e, 0xfffff); 2339 2340 /* 0x790[5:0]= 0x5 */ 2341 u1Tmp = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x790); 2342 u1Tmp &= 0xc0; 2343 u1Tmp |= 0x5; 2344 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x790, u1Tmp); 2345 2346 /* Antenna config */ 2347 halbtc8723b2ant_SetAntPath(pBtCoexist, BTC_ANT_WIFI_AT_MAIN, true, false); 2348 2349 /* PTA parameter */ 2350 halbtc8723b2ant_CoexTableWithType(pBtCoexist, FORCE_EXEC, 0); 2351 2352 /* Enable counter statistics */ 2353 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0xc); /* 0x76e[3] = 1, WLAN_Act control by PTA */ 2354 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x778, 0x3); 2355 pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0x40, 0x20, 0x1); 2356 } 2357 2358 /* */ 2359 /* work around function start with wa_halbtc8723b2ant_ */ 2360 /* */ 2361 /* */ 2362 /* extern function start with EXhalbtc8723b2ant_ */ 2363 /* */ 2364 void EXhalbtc8723b2ant_PowerOnSetting(struct btc_coexist *pBtCoexist) 2365 { 2366 struct btc_board_info *pBoardInfo = &pBtCoexist->boardInfo; 2367 u8 u1Tmp = 0x4; /* Set BIT2 by default since it's 2ant case */ 2368 u16 u2Tmp = 0x0; 2369 2370 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x67, 0x20); 2371 2372 /* enable BB, REG_SYS_FUNC_EN such that we can write 0x948 correctly. */ 2373 u2Tmp = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0x2); 2374 pBtCoexist->fBtcWrite2Byte(pBtCoexist, 0x2, u2Tmp | BIT0 | BIT1); 2375 2376 /* set GRAN_BT = 1 */ 2377 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x765, 0x18); 2378 /* set WLAN_ACT = 0 */ 2379 pBtCoexist->fBtcWrite1Byte(pBtCoexist, 0x76e, 0x4); 2380 2381 /* */ 2382 /* S0 or S1 setting and Local register setting(By the setting fw can get ant number, S0/S1, ... info) */ 2383 /* Local setting bit define */ 2384 /* BIT0: "0" for no antenna inverse; "1" for antenna inverse */ 2385 /* BIT1: "0" for internal switch; "1" for external switch */ 2386 /* BIT2: "0" for one antenna; "1" for two antenna */ 2387 /* NOTE: here default all internal switch and 1-antenna ==> BIT1 = 0 and BIT2 = 0 */ 2388 if (pBtCoexist->chipInterface == BTC_INTF_USB) { 2389 /* fixed at S0 for USB interface */ 2390 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 2391 2392 u1Tmp |= 0x1; /* antenna inverse */ 2393 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0xfe08, u1Tmp); 2394 2395 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; 2396 } else { 2397 /* for PCIE and SDIO interface, we check efuse 0xc3[6] */ 2398 if (pBoardInfo->singleAntPath == 0) { 2399 /* set to S1 */ 2400 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x280); 2401 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_MAIN_PORT; 2402 } else if (pBoardInfo->singleAntPath == 1) { 2403 /* set to S0 */ 2404 pBtCoexist->fBtcWrite4Byte(pBtCoexist, 0x948, 0x0); 2405 u1Tmp |= 0x1; /* antenna inverse */ 2406 pBoardInfo->btdmAntPos = BTC_ANTENNA_AT_AUX_PORT; 2407 } 2408 2409 if (pBtCoexist->chipInterface == BTC_INTF_PCI) 2410 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x384, u1Tmp); 2411 else if (pBtCoexist->chipInterface == BTC_INTF_SDIO) 2412 pBtCoexist->fBtcWriteLocalReg1Byte(pBtCoexist, 0x60, u1Tmp); 2413 } 2414 } 2415 2416 void EXhalbtc8723b2ant_InitHwConfig(struct btc_coexist *pBtCoexist, bool bWifiOnly) 2417 { 2418 halbtc8723b2ant_InitHwConfig(pBtCoexist, true); 2419 } 2420 2421 void EXhalbtc8723b2ant_InitCoexDm(struct btc_coexist *pBtCoexist) 2422 { 2423 halbtc8723b2ant_InitCoexDm(pBtCoexist); 2424 } 2425 2426 void EXhalbtc8723b2ant_DisplayCoexInfo(struct btc_coexist *pBtCoexist) 2427 { 2428 struct btc_board_info *pBoardInfo = &pBtCoexist->boardInfo; 2429 struct btc_stack_info *pStackInfo = &pBtCoexist->stackInfo; 2430 struct btc_bt_link_info *pBtLinkInfo = &pBtCoexist->btLinkInfo; 2431 u8 *cliBuf = pBtCoexist->cliBuf; 2432 u8 u1Tmp[4], i, btInfoExt, psTdmaCase = 0; 2433 u32 u4Tmp[4]; 2434 bool bRoam = false, bScan = false, bLink = false; 2435 bool bBtHsOn = false, bWifiBusy = false; 2436 s32 wifiRssi = 0, btHsRssi = 0; 2437 u32 wifiBw, wifiTrafficDir, faOfdm, faCck; 2438 u8 wifiDot11Chnl, wifiHsChnl; 2439 u32 fwVer = 0, btPatchVer = 0; 2440 u8 apNum = 0; 2441 2442 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[BT Coexist info]============"); 2443 CL_PRINTF(cliBuf); 2444 2445 if (pBtCoexist->bManualControl) { 2446 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n ============[Under Manual Control]============"); 2447 CL_PRINTF(cliBuf); 2448 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n =========================================="); 2449 CL_PRINTF(cliBuf); 2450 } 2451 2452 CL_SPRINTF( 2453 cliBuf, 2454 BT_TMP_BUF_SIZE, 2455 "\r\n %-35s = %d/ %d ", "Ant PG number/ Ant mechanism:", \ 2456 pBoardInfo->pgAntNum, 2457 pBoardInfo->btdmAntNum 2458 ); 2459 CL_PRINTF(cliBuf); 2460 2461 CL_SPRINTF( 2462 cliBuf, 2463 BT_TMP_BUF_SIZE, 2464 "\r\n %-35s = %s / %d", "BT stack/ hci ext ver", \ 2465 (pStackInfo->bProfileNotified ? "Yes" : "No"), 2466 pStackInfo->hciVersion 2467 ); 2468 CL_PRINTF(cliBuf); 2469 2470 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); 2471 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); 2472 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s = %d_%x/ 0x%x/ 0x%x(%d)", "CoexVer/ FwVer/ PatchVer", \ 2473 GLCoexVerDate8723b2Ant, GLCoexVer8723b2Ant, fwVer, btPatchVer, btPatchVer); 2474 CL_PRINTF(cliBuf); 2475 2476 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_HS_OPERATION, &bBtHsOn); 2477 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_DOT11_CHNL, &wifiDot11Chnl); 2478 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_HS_CHNL, &wifiHsChnl); 2479 CL_SPRINTF( 2480 cliBuf, 2481 BT_TMP_BUF_SIZE, 2482 "\r\n %-35s = %d / %d(%d)", "Dot11 channel / HsChnl(HsMode)", \ 2483 wifiDot11Chnl, 2484 wifiHsChnl, 2485 bBtHsOn 2486 ); 2487 CL_PRINTF(cliBuf); 2488 2489 CL_SPRINTF( 2490 cliBuf, 2491 BT_TMP_BUF_SIZE, 2492 "\r\n %-35s = %02x %02x %02x ", "H2C Wifi inform bt chnl Info", \ 2493 pCoexDm->wifiChnlInfo[0], 2494 pCoexDm->wifiChnlInfo[1], 2495 pCoexDm->wifiChnlInfo[2] 2496 ); 2497 CL_PRINTF(cliBuf); 2498 2499 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_WIFI_RSSI, &wifiRssi); 2500 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_S4_HS_RSSI, &btHsRssi); 2501 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 2502 CL_SPRINTF( 2503 cliBuf, 2504 BT_TMP_BUF_SIZE, 2505 "\r\n %-35s = %d/ %d/ %d", "Wifi rssi/ HS rssi/ AP#", \ 2506 wifiRssi, 2507 btHsRssi, 2508 apNum 2509 ); 2510 CL_PRINTF(cliBuf); 2511 2512 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_SCAN, &bScan); 2513 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_LINK, &bLink); 2514 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_ROAM, &bRoam); 2515 CL_SPRINTF( 2516 cliBuf, 2517 BT_TMP_BUF_SIZE, 2518 "\r\n %-35s = %d/ %d/ %d ", "Wifi bLink/ bRoam/ bScan", \ 2519 bLink, 2520 bRoam, 2521 bScan 2522 ); 2523 CL_PRINTF(cliBuf); 2524 2525 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2526 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_BUSY, &bWifiBusy); 2527 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_TRAFFIC_DIRECTION, &wifiTrafficDir); 2528 CL_SPRINTF( 2529 cliBuf, 2530 BT_TMP_BUF_SIZE, 2531 "\r\n %-35s = %s / %s/ %s ", "Wifi status", \ 2532 ("2.4G"), 2533 ((BTC_WIFI_BW_LEGACY == wifiBw) ? "Legacy" : (((BTC_WIFI_BW_HT40 == wifiBw) ? "HT40" : "HT20"))), 2534 ((!bWifiBusy) ? "idle" : ((BTC_WIFI_TRAFFIC_TX == wifiTrafficDir) ? "uplink" : "downlink")) 2535 ); 2536 CL_PRINTF(cliBuf); 2537 2538 CL_SPRINTF( 2539 cliBuf, 2540 BT_TMP_BUF_SIZE, 2541 "\r\n %-35s = [%s/ %d/ %d] ", "BT [status/ rssi/ retryCnt]", \ 2542 ((pBtCoexist->btInfo.bBtDisabled) ? ("disabled") : ((pCoexSta->bC2hBtInquiryPage) ? ("inquiry/page scan") : ((BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE == pCoexDm->btStatus) ? "non-connected idle" : 2543 ((BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE == pCoexDm->btStatus) ? "connected-idle" : "busy")))), 2544 pCoexSta->btRssi, 2545 pCoexSta->btRetryCnt 2546 ); 2547 CL_PRINTF(cliBuf); 2548 2549 CL_SPRINTF( 2550 cliBuf, 2551 BT_TMP_BUF_SIZE, 2552 "\r\n %-35s = %d / %d / %d / %d", "SCO/HID/PAN/A2DP", \ 2553 pBtLinkInfo->bScoExist, 2554 pBtLinkInfo->bHidExist, 2555 pBtLinkInfo->bPanExist, 2556 pBtLinkInfo->bA2dpExist 2557 ); 2558 CL_PRINTF(cliBuf); 2559 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_BT_LINK_INFO); 2560 2561 btInfoExt = pCoexSta->btInfoExt; 2562 CL_SPRINTF( 2563 cliBuf, 2564 BT_TMP_BUF_SIZE, 2565 "\r\n %-35s = %s", "BT Info A2DP rate", \ 2566 (btInfoExt & BIT0) ? "Basic rate" : "EDR rate" 2567 ); 2568 CL_PRINTF(cliBuf); 2569 2570 for (i = 0; i < BT_INFO_SRC_8723B_2ANT_MAX; i++) { 2571 if (pCoexSta->btInfoC2hCnt[i]) { 2572 CL_SPRINTF( 2573 cliBuf, 2574 BT_TMP_BUF_SIZE, 2575 "\r\n %-35s = %02x %02x %02x %02x %02x %02x %02x(%d)", GLBtInfoSrc8723b2Ant[i], \ 2576 pCoexSta->btInfoC2h[i][0], 2577 pCoexSta->btInfoC2h[i][1], 2578 pCoexSta->btInfoC2h[i][2], 2579 pCoexSta->btInfoC2h[i][3], 2580 pCoexSta->btInfoC2h[i][4], 2581 pCoexSta->btInfoC2h[i][5], 2582 pCoexSta->btInfoC2h[i][6], 2583 pCoexSta->btInfoC2hCnt[i] 2584 ); 2585 CL_PRINTF(cliBuf); 2586 } 2587 } 2588 2589 CL_SPRINTF( 2590 cliBuf, 2591 BT_TMP_BUF_SIZE, 2592 "\r\n %-35s = %s/%s", "PS state, IPS/LPS", \ 2593 ((pCoexSta->bUnderIps ? "IPS ON" : "IPS OFF")), 2594 ((pCoexSta->bUnderLps ? "LPS ON" : "LPS OFF")) 2595 ); 2596 CL_PRINTF(cliBuf); 2597 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_FW_PWR_MODE_CMD); 2598 2599 /* Sw mechanism */ 2600 CL_SPRINTF( 2601 cliBuf, 2602 BT_TMP_BUF_SIZE, 2603 "\r\n %-35s", "============[Sw mechanism]============" 2604 ); 2605 CL_PRINTF(cliBuf); 2606 CL_SPRINTF( 2607 cliBuf, 2608 BT_TMP_BUF_SIZE, 2609 "\r\n %-35s = %d/ %d/ %d ", "SM1[ShRf/ LpRA/ LimDig]", \ 2610 pCoexDm->bCurRfRxLpfShrink, 2611 pCoexDm->bCurLowPenaltyRa, 2612 pCoexDm->bLimitedDig 2613 ); 2614 CL_PRINTF(cliBuf); 2615 CL_SPRINTF( 2616 cliBuf, 2617 BT_TMP_BUF_SIZE, 2618 "\r\n %-35s = %d/ %d/ %d(0x%x) ", 2619 "SM2[AgcT/ AdcB/ SwDacSwing(lvl)]", \ 2620 pCoexDm->bCurAgcTableEn, 2621 pCoexDm->bCurAdcBackOff, 2622 pCoexDm->bCurDacSwingOn, 2623 pCoexDm->curDacSwingLvl 2624 ); 2625 CL_PRINTF(cliBuf); 2626 2627 /* Fw mechanism */ 2628 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Fw mechanism]============"); 2629 CL_PRINTF(cliBuf); 2630 2631 psTdmaCase = pCoexDm->curPsTdma; 2632 CL_SPRINTF( 2633 cliBuf, 2634 BT_TMP_BUF_SIZE, 2635 "\r\n %-35s = %02x %02x %02x %02x %02x case-%d (auto:%d)", "PS TDMA", \ 2636 pCoexDm->psTdmaPara[0], 2637 pCoexDm->psTdmaPara[1], 2638 pCoexDm->psTdmaPara[2], 2639 pCoexDm->psTdmaPara[3], 2640 pCoexDm->psTdmaPara[4], 2641 psTdmaCase, pCoexDm->bAutoTdmaAdjust 2642 ); 2643 CL_PRINTF(cliBuf); 2644 2645 CL_SPRINTF( 2646 cliBuf, 2647 BT_TMP_BUF_SIZE, 2648 "\r\n %-35s = %d/ %d ", "DecBtPwr/ IgnWlanAct", \ 2649 pCoexDm->curBtDecPwrLvl, 2650 pCoexDm->bCurIgnoreWlanAct 2651 ); 2652 CL_PRINTF(cliBuf); 2653 2654 /* Hw setting */ 2655 CL_SPRINTF(cliBuf, BT_TMP_BUF_SIZE, "\r\n %-35s", "============[Hw setting]============"); 2656 CL_PRINTF(cliBuf); 2657 2658 CL_SPRINTF( 2659 cliBuf, 2660 BT_TMP_BUF_SIZE, 2661 "\r\n %-35s = 0x%x", "RF-A, 0x1e initVal", \ 2662 pCoexDm->btRf0x1eBackup 2663 ); 2664 CL_PRINTF(cliBuf); 2665 2666 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x778); 2667 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x880); 2668 CL_SPRINTF( 2669 cliBuf, 2670 BT_TMP_BUF_SIZE, 2671 "\r\n %-35s = 0x%x/ 0x%x", "0x778/0x880[29:25]", \ 2672 u1Tmp[0], 2673 (u4Tmp[0] & 0x3e000000) >> 25 2674 ); 2675 CL_PRINTF(cliBuf); 2676 2677 2678 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x948); 2679 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x67); 2680 u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x765); 2681 CL_SPRINTF( 2682 cliBuf, 2683 BT_TMP_BUF_SIZE, 2684 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x948/ 0x67[5] / 0x765", \ 2685 u4Tmp[0], 2686 ((u1Tmp[0] & 0x20) >> 5), 2687 u1Tmp[1] 2688 ); 2689 CL_PRINTF(cliBuf); 2690 2691 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x92c); 2692 u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x930); 2693 u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x944); 2694 CL_SPRINTF( 2695 cliBuf, 2696 BT_TMP_BUF_SIZE, 2697 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "0x92c[1:0]/ 0x930[7:0]/0x944[1:0]", \ 2698 u4Tmp[0] & 0x3, 2699 u4Tmp[1] & 0xff, 2700 u4Tmp[2] & 0x3 2701 ); 2702 CL_PRINTF(cliBuf); 2703 2704 2705 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x39); 2706 u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x40); 2707 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x4c); 2708 u1Tmp[2] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x64); 2709 CL_SPRINTF( 2710 cliBuf, 2711 BT_TMP_BUF_SIZE, 2712 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x38[11]/0x40/0x4c[24:23]/0x64[0]", \ 2713 ((u1Tmp[0] & 0x8) >> 3), 2714 u1Tmp[1], 2715 ((u4Tmp[0] & 0x01800000) >> 23), 2716 u1Tmp[2] & 0x1 2717 ); 2718 CL_PRINTF(cliBuf); 2719 2720 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x550); 2721 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x522); 2722 CL_SPRINTF( 2723 cliBuf, 2724 BT_TMP_BUF_SIZE, 2725 "\r\n %-35s = 0x%x/ 0x%x", "0x550(bcn ctrl)/0x522", \ 2726 u4Tmp[0], 2727 u1Tmp[0] 2728 ); 2729 CL_PRINTF(cliBuf); 2730 2731 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xc50); 2732 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x49c); 2733 CL_SPRINTF( 2734 cliBuf, 2735 BT_TMP_BUF_SIZE, 2736 "\r\n %-35s = 0x%x/ 0x%x", "0xc50(dig)/0x49c(null-drop)", \ 2737 u4Tmp[0] & 0xff, 2738 u1Tmp[0] 2739 ); 2740 CL_PRINTF(cliBuf); 2741 2742 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda0); 2743 u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda4); 2744 u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xda8); 2745 u4Tmp[3] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0xcf0); 2746 2747 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5b); 2748 u1Tmp[1] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0xa5c); 2749 2750 faOfdm = 2751 ((u4Tmp[0] & 0xffff0000) >> 16) + 2752 ((u4Tmp[1] & 0xffff0000) >> 16) + 2753 (u4Tmp[1] & 0xffff) + (u4Tmp[2] & 0xffff) + \ 2754 ((u4Tmp[3] & 0xffff0000) >> 16) + 2755 (u4Tmp[3] & 0xffff); 2756 2757 faCck = (u1Tmp[0] << 8) + u1Tmp[1]; 2758 2759 CL_SPRINTF( 2760 cliBuf, 2761 BT_TMP_BUF_SIZE, 2762 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x", "OFDM-CCA/OFDM-FA/CCK-FA", \ 2763 u4Tmp[0] & 0xffff, 2764 faOfdm, 2765 faCck 2766 ); 2767 CL_PRINTF(cliBuf); 2768 2769 u4Tmp[0] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c0); 2770 u4Tmp[1] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c4); 2771 u4Tmp[2] = pBtCoexist->fBtcRead4Byte(pBtCoexist, 0x6c8); 2772 u1Tmp[0] = pBtCoexist->fBtcRead1Byte(pBtCoexist, 0x6cc); 2773 CL_SPRINTF( 2774 cliBuf, 2775 BT_TMP_BUF_SIZE, 2776 "\r\n %-35s = 0x%x/ 0x%x/ 0x%x/ 0x%x", "0x6c0/0x6c4/0x6c8/0x6cc(coexTable)", \ 2777 u4Tmp[0], 2778 u4Tmp[1], 2779 u4Tmp[2], 2780 u1Tmp[0] 2781 ); 2782 CL_PRINTF(cliBuf); 2783 2784 CL_SPRINTF( 2785 cliBuf, 2786 BT_TMP_BUF_SIZE, 2787 "\r\n %-35s = %d/ %d", "0x770(high-pri rx/tx)", \ 2788 pCoexSta->highPriorityRx, 2789 pCoexSta->highPriorityTx 2790 ); 2791 CL_PRINTF(cliBuf); 2792 CL_SPRINTF( 2793 cliBuf, 2794 BT_TMP_BUF_SIZE, 2795 "\r\n %-35s = %d/ %d", "0x774(low-pri rx/tx)", \ 2796 pCoexSta->lowPriorityRx, 2797 pCoexSta->lowPriorityTx 2798 ); 2799 CL_PRINTF(cliBuf); 2800 2801 halbtc8723b2ant_MonitorBtCtr(pBtCoexist); 2802 pBtCoexist->fBtcDispDbgMsg(pBtCoexist, BTC_DBG_DISP_COEX_STATISTICS); 2803 } 2804 2805 2806 void EXhalbtc8723b2ant_IpsNotify(struct btc_coexist *pBtCoexist, u8 type) 2807 { 2808 if (BTC_IPS_ENTER == type) { 2809 pCoexSta->bUnderIps = true; 2810 halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); 2811 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true); 2812 halbtc8723b2ant_CoexAllOff(pBtCoexist); 2813 } else if (BTC_IPS_LEAVE == type) { 2814 pCoexSta->bUnderIps = false; 2815 halbtc8723b2ant_InitHwConfig(pBtCoexist, false); 2816 halbtc8723b2ant_InitCoexDm(pBtCoexist); 2817 halbtc8723b2ant_QueryBtInfo(pBtCoexist); 2818 } 2819 } 2820 2821 void EXhalbtc8723b2ant_LpsNotify(struct btc_coexist *pBtCoexist, u8 type) 2822 { 2823 if (BTC_LPS_ENABLE == type) { 2824 pCoexSta->bUnderLps = true; 2825 } else if (BTC_LPS_DISABLE == type) { 2826 pCoexSta->bUnderLps = false; 2827 } 2828 } 2829 2830 void EXhalbtc8723b2ant_ScanNotify(struct btc_coexist *pBtCoexist, u8 type) 2831 { 2832 if (BTC_SCAN_START == type) { 2833 } else if (BTC_SCAN_FINISH == type) { 2834 } 2835 } 2836 2837 void EXhalbtc8723b2ant_ConnectNotify(struct btc_coexist *pBtCoexist, u8 type) 2838 { 2839 if (BTC_ASSOCIATE_START == type) { 2840 } else if (BTC_ASSOCIATE_FINISH == type) { 2841 } 2842 } 2843 2844 void EXhalbtc8723b2ant_MediaStatusNotify(struct btc_coexist *pBtCoexist, u8 type) 2845 { 2846 u8 H2C_Parameter[3] = {0}; 2847 u32 wifiBw; 2848 u8 wifiCentralChnl; 2849 u8 apNum = 0; 2850 2851 /* only 2.4G we need to inform bt the chnl mask */ 2852 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_WIFI_CENTRAL_CHNL, &wifiCentralChnl); 2853 if ((BTC_MEDIA_CONNECT == type) && (wifiCentralChnl <= 14)) { 2854 H2C_Parameter[0] = 0x1; 2855 H2C_Parameter[1] = wifiCentralChnl; 2856 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_BW, &wifiBw); 2857 if (BTC_WIFI_BW_HT40 == wifiBw) 2858 H2C_Parameter[2] = 0x30; 2859 else { 2860 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U1_AP_NUM, &apNum); 2861 if (apNum < 10) 2862 H2C_Parameter[2] = 0x30; 2863 else 2864 H2C_Parameter[2] = 0x20; 2865 } 2866 } 2867 2868 pCoexDm->wifiChnlInfo[0] = H2C_Parameter[0]; 2869 pCoexDm->wifiChnlInfo[1] = H2C_Parameter[1]; 2870 pCoexDm->wifiChnlInfo[2] = H2C_Parameter[2]; 2871 2872 pBtCoexist->fBtcFillH2c(pBtCoexist, 0x66, 3, H2C_Parameter); 2873 } 2874 2875 void EXhalbtc8723b2ant_SpecialPacketNotify(struct btc_coexist *pBtCoexist, u8 type) 2876 { 2877 } 2878 2879 void EXhalbtc8723b2ant_BtInfoNotify( 2880 struct btc_coexist *pBtCoexist, u8 *tmpBuf, u8 length 2881 ) 2882 { 2883 u8 btInfo = 0; 2884 u8 i, rspSource = 0; 2885 bool bBtBusy = false, bLimitedDig = false; 2886 bool bWifiConnected = false; 2887 2888 pCoexSta->bC2hBtInfoReqSent = false; 2889 2890 rspSource = tmpBuf[0] & 0xf; 2891 if (rspSource >= BT_INFO_SRC_8723B_2ANT_MAX) 2892 rspSource = BT_INFO_SRC_8723B_2ANT_WIFI_FW; 2893 2894 pCoexSta->btInfoC2hCnt[rspSource]++; 2895 2896 for (i = 0; i < length; i++) { 2897 pCoexSta->btInfoC2h[rspSource][i] = tmpBuf[i]; 2898 if (i == 1) 2899 btInfo = tmpBuf[i]; 2900 2901 } 2902 2903 if (pBtCoexist->bManualControl) { 2904 return; 2905 } 2906 2907 if (BT_INFO_SRC_8723B_2ANT_WIFI_FW != rspSource) { 2908 pCoexSta->btRetryCnt = pCoexSta->btInfoC2h[rspSource][2] & 0xf; /* [3:0] */ 2909 2910 pCoexSta->btRssi = pCoexSta->btInfoC2h[rspSource][3] * 2 + 10; 2911 2912 pCoexSta->btInfoExt = pCoexSta->btInfoC2h[rspSource][4]; 2913 2914 pCoexSta->bBtTxRxMask = (pCoexSta->btInfoC2h[rspSource][2] & 0x40); 2915 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TX_RX_MASK, &pCoexSta->bBtTxRxMask); 2916 if (pCoexSta->bBtTxRxMask) { 2917 /* BT into is responded by BT FW and BT RF REG 0x3C != 0x01 => Need to switch BT TRx Mask */ 2918 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x01); 2919 } 2920 2921 /* Here we need to resend some wifi info to BT */ 2922 /* because bt is reset and loss of the info. */ 2923 if ((pCoexSta->btInfoExt & BIT1)) { 2924 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_BL_WIFI_CONNECTED, &bWifiConnected); 2925 2926 if (bWifiConnected) 2927 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_CONNECT); 2928 else 2929 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); 2930 } 2931 2932 if ((pCoexSta->btInfoExt & BIT3)) { 2933 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, false); 2934 } else { 2935 /* BT already NOT ignore Wlan active, do nothing here. */ 2936 } 2937 } 2938 2939 /* check BIT2 first ==> check if bt is under inquiry or page scan */ 2940 if (btInfo & BT_INFO_8723B_2ANT_B_INQ_PAGE) 2941 pCoexSta->bC2hBtInquiryPage = true; 2942 else 2943 pCoexSta->bC2hBtInquiryPage = false; 2944 2945 /* set link exist status */ 2946 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) { 2947 pCoexSta->bBtLinkExist = false; 2948 pCoexSta->bPanExist = false; 2949 pCoexSta->bA2dpExist = false; 2950 pCoexSta->bHidExist = false; 2951 pCoexSta->bScoExist = false; 2952 } else { /* connection exists */ 2953 pCoexSta->bBtLinkExist = true; 2954 if (btInfo & BT_INFO_8723B_2ANT_B_FTP) 2955 pCoexSta->bPanExist = true; 2956 else 2957 pCoexSta->bPanExist = false; 2958 if (btInfo & BT_INFO_8723B_2ANT_B_A2DP) 2959 pCoexSta->bA2dpExist = true; 2960 else 2961 pCoexSta->bA2dpExist = false; 2962 if (btInfo & BT_INFO_8723B_2ANT_B_HID) 2963 pCoexSta->bHidExist = true; 2964 else 2965 pCoexSta->bHidExist = false; 2966 if (btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) 2967 pCoexSta->bScoExist = true; 2968 else 2969 pCoexSta->bScoExist = false; 2970 } 2971 2972 halbtc8723b2ant_UpdateBtLinkInfo(pBtCoexist); 2973 2974 if (!(btInfo & BT_INFO_8723B_2ANT_B_CONNECTION)) { 2975 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_NON_CONNECTED_IDLE; 2976 } else if (btInfo == BT_INFO_8723B_2ANT_B_CONNECTION) { /* connection exists but no busy */ 2977 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_CONNECTED_IDLE; 2978 } else if ( 2979 (btInfo & BT_INFO_8723B_2ANT_B_SCO_ESCO) || 2980 (btInfo & BT_INFO_8723B_2ANT_B_SCO_BUSY) 2981 ) { 2982 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_SCO_BUSY; 2983 } else if (btInfo & BT_INFO_8723B_2ANT_B_ACL_BUSY) { 2984 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_ACL_BUSY; 2985 } else { 2986 pCoexDm->btStatus = BT_8723B_2ANT_BT_STATUS_MAX; 2987 } 2988 2989 if ( 2990 (BT_8723B_2ANT_BT_STATUS_ACL_BUSY == pCoexDm->btStatus) || 2991 (BT_8723B_2ANT_BT_STATUS_SCO_BUSY == pCoexDm->btStatus) || 2992 (BT_8723B_2ANT_BT_STATUS_ACL_SCO_BUSY == pCoexDm->btStatus) 2993 ) { 2994 bBtBusy = true; 2995 bLimitedDig = true; 2996 } else { 2997 bBtBusy = false; 2998 bLimitedDig = false; 2999 } 3000 3001 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_TRAFFIC_BUSY, &bBtBusy); 3002 3003 pCoexDm->bLimitedDig = bLimitedDig; 3004 pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_BL_BT_LIMITED_DIG, &bLimitedDig); 3005 3006 halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); 3007 } 3008 3009 void EXhalbtc8723b2ant_HaltNotify(struct btc_coexist *pBtCoexist) 3010 { 3011 halbtc8723b2ant_WifiOffHwCfg(pBtCoexist); 3012 pBtCoexist->fBtcSetBtReg(pBtCoexist, BTC_BT_REG_RF, 0x3c, 0x15); /* BT goto standby while GNT_BT 1-->0 */ 3013 halbtc8723b2ant_IgnoreWlanAct(pBtCoexist, FORCE_EXEC, true); 3014 3015 EXhalbtc8723b2ant_MediaStatusNotify(pBtCoexist, BTC_MEDIA_DISCONNECT); 3016 } 3017 3018 void EXhalbtc8723b2ant_PnpNotify(struct btc_coexist *pBtCoexist, u8 pnpState) 3019 { 3020 if (BTC_WIFI_PNP_SLEEP == pnpState) { 3021 } else if (BTC_WIFI_PNP_WAKE_UP == pnpState) { 3022 halbtc8723b2ant_InitHwConfig(pBtCoexist, false); 3023 halbtc8723b2ant_InitCoexDm(pBtCoexist); 3024 halbtc8723b2ant_QueryBtInfo(pBtCoexist); 3025 } 3026 } 3027 3028 void EXhalbtc8723b2ant_Periodical(struct btc_coexist *pBtCoexist) 3029 { 3030 static u8 disVerInfoCnt; 3031 u32 fwVer = 0, btPatchVer = 0; 3032 3033 if (disVerInfoCnt <= 5) { 3034 disVerInfoCnt += 1; 3035 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_BT_PATCH_VER, &btPatchVer); 3036 pBtCoexist->fBtcGet(pBtCoexist, BTC_GET_U4_WIFI_FW_VER, &fwVer); 3037 } 3038 3039 if ( 3040 halbtc8723b2ant_IsWifiStatusChanged(pBtCoexist) || 3041 pCoexDm->bAutoTdmaAdjust 3042 ) 3043 halbtc8723b2ant_RunCoexistMechanism(pBtCoexist); 3044 } 3045