1 // SPDX-License-Identifier: GPL-2.0 2 #include "r8192U.h" 3 #include "r8192U_hw.h" 4 #include "r819xU_phy.h" 5 #include "r819xU_phyreg.h" 6 #include "r8190_rtl8256.h" 7 #include "r8192U_dm.h" 8 #include "r819xU_firmware_img.h" 9 10 #include "dot11d.h" 11 #include <linux/bitops.h> 12 13 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 14 0, 15 0x085c, /* 2412 1 */ 16 0x08dc, /* 2417 2 */ 17 0x095c, /* 2422 3 */ 18 0x09dc, /* 2427 4 */ 19 0x0a5c, /* 2432 5 */ 20 0x0adc, /* 2437 6 */ 21 0x0b5c, /* 2442 7 */ 22 0x0bdc, /* 2447 8 */ 23 0x0c5c, /* 2452 9 */ 24 0x0cdc, /* 2457 10 */ 25 0x0d5c, /* 2462 11 */ 26 0x0ddc, /* 2467 12 */ 27 0x0e5c, /* 2472 13 */ 28 0x0f72, /* 2484 */ 29 }; 30 31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array 32 33 /****************************************************************************** 34 * function: This function checks different RF type to execute legal judgement. 35 * If RF Path is illegal, we will return false. 36 * input: net_device *dev 37 * u32 e_rfpath 38 * output: none 39 * return: 0(illegal, false), 1(legal, true) 40 *****************************************************************************/ 41 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath) 42 { 43 u8 ret = 1; 44 struct r8192_priv *priv = ieee80211_priv(dev); 45 46 if (priv->rf_type == RF_2T4R) { 47 ret = 0; 48 } else if (priv->rf_type == RF_1T2R) { 49 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B) 50 ret = 1; 51 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D) 52 ret = 0; 53 } 54 return ret; 55 } 56 57 /****************************************************************************** 58 * function: This function sets specific bits to BB register 59 * input: net_device *dev 60 * u32 reg_addr //target addr to be modified 61 * u32 bitmask //taget bit pos to be modified 62 * u32 data //value to be write 63 * output: none 64 * return: none 65 * notice: 66 ******************************************************************************/ 67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, 68 u32 data) 69 { 70 71 u32 reg, bitshift; 72 73 if (bitmask != bMaskDWord) { 74 read_nic_dword(dev, reg_addr, ®); 75 bitshift = ffs(bitmask) - 1; 76 reg &= ~bitmask; 77 reg |= data << bitshift; 78 write_nic_dword(dev, reg_addr, reg); 79 } else { 80 write_nic_dword(dev, reg_addr, data); 81 } 82 } 83 84 /****************************************************************************** 85 * function: This function reads specific bits from BB register 86 * input: net_device *dev 87 * u32 reg_addr //target addr to be readback 88 * u32 bitmask //taget bit pos to be readback 89 * output: none 90 * return: u32 data //the readback register value 91 * notice: 92 ******************************************************************************/ 93 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask) 94 { 95 u32 reg, bitshift; 96 97 read_nic_dword(dev, reg_addr, ®); 98 bitshift = ffs(bitmask) - 1; 99 100 return (reg & bitmask) >> bitshift; 101 } 102 103 static u32 phy_FwRFSerialRead(struct net_device *dev, 104 enum rf90_radio_path_e e_rfpath, 105 u32 offset); 106 107 static void phy_FwRFSerialWrite(struct net_device *dev, 108 enum rf90_radio_path_e e_rfpath, 109 u32 offset, 110 u32 data); 111 112 /****************************************************************************** 113 * function: This function reads register from RF chip 114 * input: net_device *dev 115 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 116 * u32 offset //target address to be read 117 * output: none 118 * return: u32 readback value 119 * notice: There are three types of serial operations: 120 * (1) Software serial write. 121 * (2)Hardware LSSI-Low Speed Serial Interface. 122 * (3)Hardware HSSI-High speed serial write. 123 * Driver here need to implement (1) and (2) 124 * ---need more spec for this information. 125 ******************************************************************************/ 126 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, 127 enum rf90_radio_path_e e_rfpath, u32 offset) 128 { 129 struct r8192_priv *priv = ieee80211_priv(dev); 130 u32 ret = 0; 131 u32 new_offset = 0; 132 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; 133 134 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); 135 /* Make sure RF register offset is correct */ 136 offset &= 0x3f; 137 138 /* Switch page for 8256 RF IC */ 139 if (priv->rf_chip == RF_8256) { 140 if (offset >= 31) { 141 priv->RfReg0Value[e_rfpath] |= 0x140; 142 /* Switch to Reg_Mode2 for Reg 31-45 */ 143 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 144 bMaskDWord, 145 priv->RfReg0Value[e_rfpath]<<16); 146 /* Modify offset */ 147 new_offset = offset - 30; 148 } else if (offset >= 16) { 149 priv->RfReg0Value[e_rfpath] |= 0x100; 150 priv->RfReg0Value[e_rfpath] &= (~0x40); 151 /* Switch to Reg_Mode1 for Reg16-30 */ 152 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 153 bMaskDWord, 154 priv->RfReg0Value[e_rfpath]<<16); 155 156 new_offset = offset - 15; 157 } else { 158 new_offset = offset; 159 } 160 } else { 161 RT_TRACE((COMP_PHY|COMP_ERR), 162 "check RF type here, need to be 8256\n"); 163 new_offset = offset; 164 } 165 /* Put desired read addr to LSSI control Register */ 166 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 167 new_offset); 168 /* Issue a posedge trigger */ 169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 170 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 171 172 173 /* TODO: we should not delay such a long time. Ask for help from SD3 */ 174 usleep_range(1000, 1000); 175 176 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, 177 bLSSIReadBackData); 178 179 180 /* Switch back to Reg_Mode0 */ 181 if (priv->rf_chip == RF_8256) { 182 priv->RfReg0Value[e_rfpath] &= 0xebf; 183 184 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 185 priv->RfReg0Value[e_rfpath] << 16); 186 } 187 188 return ret; 189 } 190 191 /****************************************************************************** 192 * function: This function writes data to RF register 193 * input: net_device *dev 194 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 195 * u32 offset //target address to be written 196 * u32 data //the new register data to be written 197 * output: none 198 * return: none 199 * notice: For RF8256 only. 200 * =========================================================================== 201 * Reg Mode RegCTL[1] RegCTL[0] Note 202 * (Reg00[12]) (Reg00[10]) 203 * =========================================================================== 204 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf) 205 * --------------------------------------------------------------------------- 206 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf) 207 * --------------------------------------------------------------------------- 208 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 209 * --------------------------------------------------------------------------- 210 *****************************************************************************/ 211 static void rtl8192_phy_RFSerialWrite(struct net_device *dev, 212 enum rf90_radio_path_e e_rfpath, 213 u32 offset, 214 u32 data) 215 { 216 struct r8192_priv *priv = ieee80211_priv(dev); 217 u32 DataAndAddr = 0, new_offset = 0; 218 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; 219 220 offset &= 0x3f; 221 if (priv->rf_chip == RF_8256) { 222 223 if (offset >= 31) { 224 priv->RfReg0Value[e_rfpath] |= 0x140; 225 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 226 bMaskDWord, 227 priv->RfReg0Value[e_rfpath] << 16); 228 new_offset = offset - 30; 229 } else if (offset >= 16) { 230 priv->RfReg0Value[e_rfpath] |= 0x100; 231 priv->RfReg0Value[e_rfpath] &= (~0x40); 232 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 233 bMaskDWord, 234 priv->RfReg0Value[e_rfpath]<<16); 235 new_offset = offset - 15; 236 } else { 237 new_offset = offset; 238 } 239 } else { 240 RT_TRACE((COMP_PHY|COMP_ERR), 241 "check RF type here, need to be 8256\n"); 242 new_offset = offset; 243 } 244 245 /* Put write addr in [5:0] and write data in [31:16] */ 246 DataAndAddr = (data<<16) | (new_offset&0x3f); 247 248 /* Write operation */ 249 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 250 251 252 if (offset == 0x0) 253 priv->RfReg0Value[e_rfpath] = data; 254 255 /* Switch back to Reg_Mode0 */ 256 if (priv->rf_chip == RF_8256) { 257 if (offset != 0) { 258 priv->RfReg0Value[e_rfpath] &= 0xebf; 259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 260 bMaskDWord, 261 priv->RfReg0Value[e_rfpath] << 16); 262 } 263 } 264 } 265 266 /****************************************************************************** 267 * function: This function set specific bits to RF register 268 * input: net_device dev 269 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 270 * u32 reg_addr //target addr to be modified 271 * u32 bitmask //taget bit pos to be modified 272 * u32 data //value to be written 273 * output: none 274 * return: none 275 * notice: 276 *****************************************************************************/ 277 void rtl8192_phy_SetRFReg(struct net_device *dev, 278 enum rf90_radio_path_e e_rfpath, 279 u32 reg_addr, u32 bitmask, u32 data) 280 { 281 struct r8192_priv *priv = ieee80211_priv(dev); 282 u32 reg, bitshift; 283 284 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath)) 285 return; 286 287 if (priv->Rf_Mode == RF_OP_By_FW) { 288 if (bitmask != bMask12Bits) { 289 /* RF data is 12 bits only */ 290 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); 291 bitshift = ffs(bitmask) - 1; 292 reg &= ~bitmask; 293 reg |= data << bitshift; 294 295 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg); 296 } else { 297 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data); 298 } 299 300 udelay(200); 301 302 } else { 303 if (bitmask != bMask12Bits) { 304 /* RF data is 12 bits only */ 305 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); 306 bitshift = ffs(bitmask) - 1; 307 reg &= ~bitmask; 308 reg |= data << bitshift; 309 310 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg); 311 } else { 312 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data); 313 } 314 } 315 } 316 317 /****************************************************************************** 318 * function: This function reads specific bits from RF register 319 * input: net_device *dev 320 * u32 reg_addr //target addr to be readback 321 * u32 bitmask //taget bit pos to be readback 322 * output: none 323 * return: u32 data //the readback register value 324 * notice: 325 *****************************************************************************/ 326 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, 327 enum rf90_radio_path_e e_rfpath, 328 u32 reg_addr, u32 bitmask) 329 { 330 u32 reg, bitshift; 331 struct r8192_priv *priv = ieee80211_priv(dev); 332 333 334 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath)) 335 return 0; 336 if (priv->Rf_Mode == RF_OP_By_FW) { 337 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); 338 udelay(200); 339 } else { 340 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); 341 } 342 bitshift = ffs(bitmask) - 1; 343 reg = (reg & bitmask) >> bitshift; 344 return reg; 345 346 } 347 348 /****************************************************************************** 349 * function: We support firmware to execute RF-R/W. 350 * input: net_device *dev 351 * rf90_radio_path_e e_rfpath 352 * u32 offset 353 * output: none 354 * return: u32 355 * notice: 356 ****************************************************************************/ 357 static u32 phy_FwRFSerialRead(struct net_device *dev, 358 enum rf90_radio_path_e e_rfpath, 359 u32 offset) 360 { 361 u32 reg = 0; 362 u32 data = 0; 363 u8 time = 0; 364 u32 tmp; 365 366 /* Firmware RF Write control. 367 * We can not execute the scheme in the initial step. 368 * Otherwise, RF-R/W will waste much time. 369 * This is only for site survey. 370 */ 371 /* 1. Read operation need not insert data. bit 0-11 */ 372 /* 2. Write RF register address. bit 12-19 */ 373 data |= ((offset&0xFF)<<12); 374 /* 3. Write RF path. bit 20-21 */ 375 data |= ((e_rfpath&0x3)<<20); 376 /* 4. Set RF read indicator. bit 22=0 */ 377 /* 5. Trigger Fw to operate the command. bit 31 */ 378 data |= 0x80000000; 379 /* 6. We can not execute read operation if bit 31 is 1. */ 380 read_nic_dword(dev, QPNR, &tmp); 381 while (tmp & 0x80000000) { 382 /* If FW can not finish RF-R/W for more than ?? times. 383 * We must reset FW. 384 */ 385 if (time++ < 100) { 386 udelay(10); 387 read_nic_dword(dev, QPNR, &tmp); 388 } else { 389 break; 390 } 391 } 392 /* 7. Execute read operation. */ 393 write_nic_dword(dev, QPNR, data); 394 /* 8. Check if firmware send back RF content. */ 395 read_nic_dword(dev, QPNR, &tmp); 396 while (tmp & 0x80000000) { 397 /* If FW can not finish RF-R/W for more than ?? times. 398 * We must reset FW. 399 */ 400 if (time++ < 100) { 401 udelay(10); 402 read_nic_dword(dev, QPNR, &tmp); 403 } else { 404 return 0; 405 } 406 } 407 read_nic_dword(dev, RF_DATA, ®); 408 409 return reg; 410 } 411 412 /****************************************************************************** 413 * function: We support firmware to execute RF-R/W. 414 * input: net_device *dev 415 * rf90_radio_path_e e_rfpath 416 * u32 offset 417 * u32 data 418 * output: none 419 * return: none 420 * notice: 421 ****************************************************************************/ 422 static void phy_FwRFSerialWrite(struct net_device *dev, 423 enum rf90_radio_path_e e_rfpath, 424 u32 offset, u32 data) 425 { 426 u8 time = 0; 427 u32 tmp; 428 429 /* Firmware RF Write control. 430 * We can not execute the scheme in the initial step. 431 * Otherwise, RF-R/W will waste much time. 432 * This is only for site survey. 433 */ 434 435 /* 1. Set driver write bit and 12 bit data. bit 0-11 */ 436 /* 2. Write RF register address. bit 12-19 */ 437 data |= ((offset&0xFF)<<12); 438 /* 3. Write RF path. bit 20-21 */ 439 data |= ((e_rfpath&0x3)<<20); 440 /* 4. Set RF write indicator. bit 22=1 */ 441 data |= 0x400000; 442 /* 5. Trigger Fw to operate the command. bit 31=1 */ 443 data |= 0x80000000; 444 445 /* 6. Write operation. We can not write if bit 31 is 1. */ 446 read_nic_dword(dev, QPNR, &tmp); 447 while (tmp & 0x80000000) { 448 /* If FW can not finish RF-R/W for more than ?? times. 449 * We must reset FW. 450 */ 451 if (time++ < 100) { 452 udelay(10); 453 read_nic_dword(dev, QPNR, &tmp); 454 } else { 455 break; 456 } 457 } 458 /* 7. No matter check bit. We always force the write. 459 * Because FW will not accept the command. 460 */ 461 write_nic_dword(dev, QPNR, data); 462 /* According to test, we must delay 20us to wait firmware 463 * to finish RF write operation. 464 */ 465 /* We support delay in firmware side now. */ 466 } 467 468 /****************************************************************************** 469 * function: This function reads BB parameters from header file we generate, 470 * and do register read/write 471 * input: net_device *dev 472 * output: none 473 * return: none 474 * notice: BB parameters may change all the time, so please make 475 * sure it has been synced with the newest. 476 *****************************************************************************/ 477 void rtl8192_phy_configmac(struct net_device *dev) 478 { 479 u32 dwArrayLen = 0, i; 480 u32 *pdwArray = NULL; 481 struct r8192_priv *priv = ieee80211_priv(dev); 482 483 if (priv->btxpowerdata_readfromEEPORM) { 484 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); 485 dwArrayLen = MACPHY_Array_PGLength; 486 pdwArray = Rtl8192UsbMACPHY_Array_PG; 487 488 } else { 489 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); 490 dwArrayLen = MACPHY_ArrayLength; 491 pdwArray = rtl819XMACPHY_Array; 492 } 493 for (i = 0; i < dwArrayLen; i = i+3) { 494 if (pdwArray[i] == 0x318) 495 pdwArray[i+2] = 0x00000800; 496 497 RT_TRACE(COMP_DBG, 498 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n", 499 pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 500 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], 501 pdwArray[i+2]); 502 } 503 } 504 505 /****************************************************************************** 506 * function: This function does dirty work 507 * input: net_device *dev 508 * u8 ConfigType 509 * output: none 510 * return: none 511 * notice: BB parameters may change all the time, so please make 512 * sure it has been synced with the newest. 513 *****************************************************************************/ 514 static void rtl8192_phyConfigBB(struct net_device *dev, 515 enum baseband_config_type ConfigType) 516 { 517 u32 i; 518 519 if (ConfigType == BASEBAND_CONFIG_PHY_REG) { 520 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { 521 rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i], 522 bMaskDWord, 523 Rtl8192UsbPHY_REG_1T2RArray[i+1]); 524 RT_TRACE(COMP_DBG, 525 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n", 526 i, Rtl8192UsbPHY_REG_1T2RArray[i], 527 Rtl8192UsbPHY_REG_1T2RArray[i+1]); 528 } 529 } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) { 530 for (i = 0; i < AGCTAB_ArrayLength; i += 2) { 531 rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i], 532 bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]); 533 RT_TRACE(COMP_DBG, 534 "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n", 535 i, Rtl8192UsbAGCTAB_Array[i], 536 Rtl8192UsbAGCTAB_Array[i+1]); 537 } 538 } 539 } 540 541 /****************************************************************************** 542 * function: This function initializes Register definition offset for 543 * Radio Path A/B/C/D 544 * input: net_device *dev 545 * output: none 546 * return: none 547 * notice: Initialization value here is constant and it should never 548 * be changed 549 *****************************************************************************/ 550 static void rtl8192_InitBBRFRegDef(struct net_device *dev) 551 { 552 struct r8192_priv *priv = ieee80211_priv(dev); 553 554 /* RF Interface Software Control */ 555 /* 16 LSBs if read 32-bit from 0x870 */ 556 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 557 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 558 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 559 /* 16 LSBs if read 32-bit from 0x874 */ 560 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 561 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 562 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 563 564 /* RF Interface Readback Value */ 565 /* 16 LSBs if read 32-bit from 0x8E0 */ 566 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 567 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 568 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 569 /* 16 LSBs if read 32-bit from 0x8E4 */ 570 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 571 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 572 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 573 574 /* RF Interface Output (and Enable) */ 575 /* 16 LSBs if read 32-bit from 0x860 */ 576 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 577 /* 16 LSBs if read 32-bit from 0x864 */ 578 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 579 /* 16 LSBs if read 32-bit from 0x868 */ 580 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 581 /* 16 LSBs if read 32-bit from 0x86C */ 582 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 583 584 /* RF Interface (Output and) Enable */ 585 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 586 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 587 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 588 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 589 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */ 590 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 591 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */ 592 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 593 594 /* Addr of LSSI. Write RF register by driver */ 595 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 596 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 597 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 598 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 599 600 /* RF parameter */ 601 /* BB Band Select */ 602 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 603 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 604 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 605 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 606 607 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 608 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 609 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 610 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 611 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 612 613 /* Tranceiver A~D HSSI Parameter-1 */ 614 /* wire control parameter1 */ 615 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 616 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 617 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 618 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 619 620 /* Tranceiver A~D HSSI Parameter-2 */ 621 /* wire control parameter2 */ 622 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 623 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 624 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 625 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 626 627 /* RF Switch Control */ 628 /* TR/Ant switch control */ 629 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 630 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 631 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 632 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 633 634 /* AGC control 1 */ 635 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 636 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 637 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 638 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 639 640 /* AGC control 2 */ 641 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 642 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 643 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 644 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 645 646 /* RX AFE control 1 */ 647 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 648 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 649 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 650 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 651 652 /* RX AFE control 1 */ 653 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 654 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 655 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 656 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 657 658 /* Tx AFE control 1 */ 659 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 660 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 661 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 662 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 663 664 /* Tx AFE control 2 */ 665 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 666 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 667 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 668 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 669 670 /* Tranceiver LSSI Readback */ 671 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 672 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 673 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 674 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 675 } 676 677 /****************************************************************************** 678 * function: This function is to write register and then readback to make 679 * sure whether BB and RF is OK 680 * input: net_device *dev 681 * hw90_block_e CheckBlock 682 * rf90_radio_path_e e_rfpath //only used when checkblock is 683 * //HW90_BLOCK_RF 684 * output: none 685 * return: return whether BB and RF is ok (0:OK, 1:Fail) 686 * notice: This function may be removed in the ASIC 687 ******************************************************************************/ 688 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock, 689 enum rf90_radio_path_e e_rfpath) 690 { 691 u8 ret = 0; 692 u32 i, CheckTimes = 4, reg = 0; 693 u32 WriteAddr[4]; 694 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 695 696 /* Initialize register address offset to be checked */ 697 WriteAddr[HW90_BLOCK_MAC] = 0x100; 698 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 699 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 700 WriteAddr[HW90_BLOCK_RF] = 0x3; 701 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); 702 for (i = 0; i < CheckTimes; i++) { 703 704 /* Write data to register and readback */ 705 switch (CheckBlock) { 706 case HW90_BLOCK_MAC: 707 RT_TRACE(COMP_ERR, 708 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); 709 break; 710 711 case HW90_BLOCK_PHY0: 712 case HW90_BLOCK_PHY1: 713 write_nic_dword(dev, WriteAddr[CheckBlock], 714 WriteData[i]); 715 read_nic_dword(dev, WriteAddr[CheckBlock], ®); 716 break; 717 718 case HW90_BLOCK_RF: 719 WriteData[i] &= 0xfff; 720 rtl8192_phy_SetRFReg(dev, e_rfpath, 721 WriteAddr[HW90_BLOCK_RF], 722 bMask12Bits, WriteData[i]); 723 /* TODO: we should not delay for such a long time. 724 * Ask SD3 725 */ 726 usleep_range(1000, 1000); 727 reg = rtl8192_phy_QueryRFReg(dev, e_rfpath, 728 WriteAddr[HW90_BLOCK_RF], 729 bMask12Bits); 730 usleep_range(1000, 1000); 731 break; 732 733 default: 734 ret = 1; 735 break; 736 } 737 738 739 /* Check whether readback data is correct */ 740 if (reg != WriteData[i]) { 741 RT_TRACE((COMP_PHY|COMP_ERR), 742 "error reg: %x, WriteData: %x\n", 743 reg, WriteData[i]); 744 ret = 1; 745 break; 746 } 747 } 748 749 return ret; 750 } 751 752 /****************************************************************************** 753 * function: This function initializes BB&RF 754 * input: net_device *dev 755 * output: none 756 * return: none 757 * notice: Initialization value may change all the time, so please make 758 * sure it has been synced with the newest. 759 ******************************************************************************/ 760 static void rtl8192_BB_Config_ParaFile(struct net_device *dev) 761 { 762 struct r8192_priv *priv = ieee80211_priv(dev); 763 u8 reg_u8 = 0, eCheckItem = 0, status = 0; 764 u32 reg_u32 = 0; 765 766 /************************************** 767 * <1> Initialize BaseBand 768 *************************************/ 769 770 /* --set BB Global Reset-- */ 771 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8); 772 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT)); 773 mdelay(50); 774 /* ---set BB reset Active--- */ 775 read_nic_dword(dev, CPU_GEN, ®_u32); 776 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST))); 777 778 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */ 779 /* TODO: this function should be removed on ASIC */ 780 for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0; 781 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 782 /* don't care RF path */ 783 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem, 784 (enum rf90_radio_path_e)0); 785 if (status != 0) { 786 RT_TRACE((COMP_ERR | COMP_PHY), 787 "phy_rf8256_config(): Check PHY%d Fail!!\n", 788 eCheckItem-1); 789 return; 790 } 791 } 792 /* ---- Set CCK and OFDM Block "OFF"---- */ 793 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 794 /* ----BB Register Initilazation---- */ 795 /* ==m==>Set PHY REG From Header<==m== */ 796 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG); 797 798 /* ----Set BB reset de-Active---- */ 799 read_nic_dword(dev, CPU_GEN, ®_u32); 800 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST)); 801 802 /* ----BB AGC table Initialization---- */ 803 /* ==m==>Set PHY REG From Header<==m== */ 804 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB); 805 806 /* ----Enable XSTAL ---- */ 807 write_nic_byte_E(dev, 0x5e, 0x00); 808 if (priv->card_8192_version == VERSION_819XU_A) { 809 /* Antenna gain offset from B/C/D to A */ 810 reg_u32 = priv->AntennaTxPwDiff[1]<<4 | 811 priv->AntennaTxPwDiff[0]; 812 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), 813 reg_u32); 814 815 /* XSTALLCap */ 816 reg_u32 = priv->CrystalCap & 0xf; 817 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, 818 reg_u32); 819 } 820 821 /* Check if the CCK HighPower is turned ON. 822 * This is used to calculate PWDB. 823 */ 824 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev, 825 rFPGA0_XA_HSSIParameter2, 826 0x200); 827 } 828 829 /****************************************************************************** 830 * function: This function initializes BB&RF 831 * input: net_device *dev 832 * output: none 833 * return: none 834 * notice: Initialization value may change all the time, so please make 835 * sure it has been synced with the newest. 836 *****************************************************************************/ 837 void rtl8192_BBConfig(struct net_device *dev) 838 { 839 rtl8192_InitBBRFRegDef(dev); 840 /* config BB&RF. As hardCode based initialization has not been well 841 * implemented, so use file first. 842 * FIXME: should implement it for hardcode? 843 */ 844 rtl8192_BB_Config_ParaFile(dev); 845 } 846 847 848 /****************************************************************************** 849 * function: This function obtains the initialization value of Tx power Level 850 * offset 851 * input: net_device *dev 852 * output: none 853 * return: none 854 *****************************************************************************/ 855 void rtl8192_phy_getTxPower(struct net_device *dev) 856 { 857 struct r8192_priv *priv = ieee80211_priv(dev); 858 u8 tmp; 859 860 read_nic_dword(dev, rTxAGC_Rate18_06, 861 &priv->MCSTxPowerLevelOriginalOffset[0]); 862 read_nic_dword(dev, rTxAGC_Rate54_24, 863 &priv->MCSTxPowerLevelOriginalOffset[1]); 864 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, 865 &priv->MCSTxPowerLevelOriginalOffset[2]); 866 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, 867 &priv->MCSTxPowerLevelOriginalOffset[3]); 868 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, 869 &priv->MCSTxPowerLevelOriginalOffset[4]); 870 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, 871 &priv->MCSTxPowerLevelOriginalOffset[5]); 872 873 /* Read rx initial gain */ 874 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); 875 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); 876 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); 877 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); 878 RT_TRACE(COMP_INIT, 879 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 880 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 881 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 882 883 /* Read framesync */ 884 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); 885 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); 886 priv->framesyncC34 = tmp; 887 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", 888 rOFDM0_RxDetector3, priv->framesync); 889 890 /* Read SIFS (save the value read fome MACPHY_REG.txt) */ 891 read_nic_word(dev, SIFS, &priv->SifsTime); 892 } 893 894 /****************************************************************************** 895 * function: This function sets the initialization value of Tx power Level 896 * offset 897 * input: net_device *dev 898 * u8 channel 899 * output: none 900 * return: none 901 ******************************************************************************/ 902 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) 903 { 904 struct r8192_priv *priv = ieee80211_priv(dev); 905 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 906 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 907 908 switch (priv->rf_chip) { 909 case RF_8256: 910 /* need further implement */ 911 phy_set_rf8256_cck_tx_power(dev, powerlevel); 912 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G); 913 break; 914 default: 915 RT_TRACE((COMP_PHY|COMP_ERR), 916 "error RF chipID(8225 or 8258) in function %s()\n", 917 __func__); 918 break; 919 } 920 } 921 922 /****************************************************************************** 923 * function: This function checks Rf chip to do RF config 924 * input: net_device *dev 925 * output: none 926 * return: only 8256 is supported 927 ******************************************************************************/ 928 void rtl8192_phy_RFConfig(struct net_device *dev) 929 { 930 struct r8192_priv *priv = ieee80211_priv(dev); 931 932 switch (priv->rf_chip) { 933 case RF_8256: 934 phy_rf8256_config(dev); 935 break; 936 default: 937 RT_TRACE(COMP_ERR, "error chip id\n"); 938 break; 939 } 940 } 941 942 /****************************************************************************** 943 * function: This function updates Initial gain 944 * input: net_device *dev 945 * output: none 946 * return: As Windows has not implemented this, wait for complement 947 ******************************************************************************/ 948 void rtl8192_phy_updateInitGain(struct net_device *dev) 949 { 950 } 951 952 /****************************************************************************** 953 * function: This function read RF parameters from general head file, 954 * and do RF 3-wire 955 * input: net_device *dev 956 * rf90_radio_path_e e_rfpath 957 * output: none 958 * return: return code show if RF configuration is successful(0:pass, 1:fail) 959 * notice: Delay may be required for RF configuration 960 *****************************************************************************/ 961 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, 962 enum rf90_radio_path_e e_rfpath) 963 { 964 965 int i; 966 967 switch (e_rfpath) { 968 case RF90_PATH_A: 969 for (i = 0; i < RadioA_ArrayLength; i = i+2) { 970 971 if (Rtl8192UsbRadioA_Array[i] == 0xfe) { 972 mdelay(100); 973 continue; 974 } 975 rtl8192_phy_SetRFReg(dev, e_rfpath, 976 Rtl8192UsbRadioA_Array[i], 977 bMask12Bits, 978 Rtl8192UsbRadioA_Array[i+1]); 979 mdelay(1); 980 981 } 982 break; 983 case RF90_PATH_B: 984 for (i = 0; i < RadioB_ArrayLength; i = i+2) { 985 986 if (Rtl8192UsbRadioB_Array[i] == 0xfe) { 987 mdelay(100); 988 continue; 989 } 990 rtl8192_phy_SetRFReg(dev, e_rfpath, 991 Rtl8192UsbRadioB_Array[i], 992 bMask12Bits, 993 Rtl8192UsbRadioB_Array[i+1]); 994 mdelay(1); 995 996 } 997 break; 998 case RF90_PATH_C: 999 for (i = 0; i < RadioC_ArrayLength; i = i+2) { 1000 1001 if (Rtl8192UsbRadioC_Array[i] == 0xfe) { 1002 mdelay(100); 1003 continue; 1004 } 1005 rtl8192_phy_SetRFReg(dev, e_rfpath, 1006 Rtl8192UsbRadioC_Array[i], 1007 bMask12Bits, 1008 Rtl8192UsbRadioC_Array[i+1]); 1009 mdelay(1); 1010 1011 } 1012 break; 1013 case RF90_PATH_D: 1014 for (i = 0; i < RadioD_ArrayLength; i = i+2) { 1015 1016 if (Rtl8192UsbRadioD_Array[i] == 0xfe) { 1017 mdelay(100); 1018 continue; 1019 } 1020 rtl8192_phy_SetRFReg(dev, e_rfpath, 1021 Rtl8192UsbRadioD_Array[i], 1022 bMask12Bits, 1023 Rtl8192UsbRadioD_Array[i+1]); 1024 mdelay(1); 1025 1026 } 1027 break; 1028 default: 1029 break; 1030 } 1031 1032 return 0; 1033 1034 } 1035 1036 /****************************************************************************** 1037 * function: This function sets Tx Power of the channel 1038 * input: net_device *dev 1039 * u8 channel 1040 * output: none 1041 * return: none 1042 * notice: 1043 ******************************************************************************/ 1044 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) 1045 { 1046 struct r8192_priv *priv = ieee80211_priv(dev); 1047 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 1048 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 1049 1050 switch (priv->rf_chip) { 1051 case RF_8225: 1052 break; 1053 1054 case RF_8256: 1055 phy_set_rf8256_cck_tx_power(dev, powerlevel); 1056 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G); 1057 break; 1058 1059 case RF_8258: 1060 break; 1061 default: 1062 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__); 1063 break; 1064 } 1065 } 1066 1067 /****************************************************************************** 1068 * function: This function sets RF state on or off 1069 * input: net_device *dev 1070 * RT_RF_POWER_STATE eRFPowerState //Power State to set 1071 * output: none 1072 * return: none 1073 * notice: 1074 *****************************************************************************/ 1075 bool rtl8192_SetRFPowerState(struct net_device *dev, 1076 RT_RF_POWER_STATE eRFPowerState) 1077 { 1078 bool bResult = true; 1079 struct r8192_priv *priv = ieee80211_priv(dev); 1080 1081 if (eRFPowerState == priv->ieee80211->eRFPowerState) 1082 return false; 1083 1084 if (priv->SetRFPowerStateInProgress) 1085 return false; 1086 1087 priv->SetRFPowerStateInProgress = true; 1088 1089 switch (priv->rf_chip) { 1090 case RF_8256: 1091 switch (eRFPowerState) { 1092 case eRfOn: 1093 /* RF-A, RF-B */ 1094 /* enable RF-Chip A/B - 0x860[4] */ 1095 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1096 0x1); 1097 /* analog to digital on - 0x88c[9:8] */ 1098 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 1099 0x3); 1100 /* digital to analog on - 0x880[4:3] */ 1101 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1102 0x3); 1103 /* rx antenna on - 0xc04[1:0] */ 1104 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); 1105 /* rx antenna on - 0xd04[1:0] */ 1106 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); 1107 /* analog to digital part2 on - 0x880[6:5] */ 1108 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1109 0x3); 1110 1111 break; 1112 1113 case eRfSleep: 1114 1115 break; 1116 1117 case eRfOff: 1118 /* RF-A, RF-B */ 1119 /* disable RF-Chip A/B - 0x860[4] */ 1120 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1121 0x0); 1122 /* analog to digital off, for power save */ 1123 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 1124 0x0); /* 0x88c[11:8] */ 1125 /* digital to analog off, for power save - 0x880[4:3] */ 1126 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1127 0x0); 1128 /* rx antenna off - 0xc04[3:0] */ 1129 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1130 /* rx antenna off - 0xd04[3:0] */ 1131 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1132 /* analog to digital part2 off, for power save */ 1133 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1134 0x0); /* 0x880[6:5] */ 1135 1136 break; 1137 1138 default: 1139 bResult = false; 1140 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n", 1141 __func__, eRFPowerState); 1142 break; 1143 } 1144 break; 1145 default: 1146 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); 1147 break; 1148 } 1149 priv->SetRFPowerStateInProgress = false; 1150 1151 return bResult; 1152 } 1153 1154 /****************************************************************************** 1155 * function: This function sets command table variable (struct sw_chnl_cmd). 1156 * input: sw_chnl_cmd *CmdTable //table to be set 1157 * u32 CmdTableIdx //variable index in table to be set 1158 * u32 CmdTableSz //table size 1159 * switch_chan_cmd_id CmdID //command ID to set 1160 * u32 Para1 1161 * u32 Para2 1162 * u32 msDelay 1163 * output: 1164 * return: true if finished, false otherwise 1165 * notice: 1166 ******************************************************************************/ 1167 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx, 1168 u32 CmdTableSz, enum switch_chan_cmd_id CmdID, 1169 u32 Para1, u32 Para2, u32 msDelay) 1170 { 1171 struct sw_chnl_cmd *pCmd; 1172 1173 if (CmdTable == NULL) { 1174 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__); 1175 return false; 1176 } 1177 if (CmdTableIdx >= CmdTableSz) { 1178 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", 1179 __func__, CmdTableIdx, CmdTableSz); 1180 return false; 1181 } 1182 1183 pCmd = CmdTable + CmdTableIdx; 1184 pCmd->cmd_id = CmdID; 1185 pCmd->para_1 = Para1; 1186 pCmd->para_2 = Para2; 1187 pCmd->ms_delay = msDelay; 1188 1189 return true; 1190 } 1191 1192 /****************************************************************************** 1193 * function: This function sets channel step by step 1194 * input: net_device *dev 1195 * u8 channel 1196 * u8 *stage //3 stages 1197 * u8 *step 1198 * u32 *delay //whether need to delay 1199 * output: store new stage, step and delay for next step 1200 * (combine with function above) 1201 * return: true if finished, false otherwise 1202 * notice: Wait for simpler function to replace it 1203 *****************************************************************************/ 1204 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, 1205 u8 *stage, u8 *step, u32 *delay) 1206 { 1207 struct r8192_priv *priv = ieee80211_priv(dev); 1208 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; 1209 u32 PreCommonCmdCnt; 1210 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT]; 1211 u32 PostCommonCmdCnt; 1212 struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; 1213 u32 RfDependCmdCnt; 1214 struct sw_chnl_cmd *CurrentCmd = NULL; 1215 u8 e_rfpath; 1216 1217 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n", 1218 __func__, *stage, *step, channel); 1219 if (!is_legal_channel(priv->ieee80211, channel)) { 1220 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel); 1221 /* return true to tell upper caller function this channel 1222 * setting is finished! Or it will in while loop. 1223 */ 1224 return true; 1225 } 1226 /* FIXME: need to check whether channel is legal or not here */ 1227 1228 1229 /* <1> Fill up pre common command. */ 1230 PreCommonCmdCnt = 0; 1231 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1232 MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL, 1233 0, 0, 0); 1234 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1235 MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0); 1236 1237 /* <2> Fill up post common command. */ 1238 PostCommonCmdCnt = 0; 1239 1240 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, 1241 MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0); 1242 1243 /* <3> Fill up RF dependent command. */ 1244 RfDependCmdCnt = 0; 1245 switch (priv->rf_chip) { 1246 case RF_8225: 1247 if (!(channel >= 1 && channel <= 14)) { 1248 RT_TRACE(COMP_ERR, 1249 "illegal channel for Zebra 8225: %d\n", 1250 channel); 1251 return true; 1252 } 1253 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1254 MAX_RFDEPENDCMD_CNT, 1255 CMD_ID_RF_WRITE_REG, 1256 rZebra1_Channel, 1257 RF_CHANNEL_TABLE_ZEBRA[channel], 1258 10); 1259 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1260 MAX_RFDEPENDCMD_CNT, 1261 CMD_ID_END, 0, 0, 0); 1262 break; 1263 1264 case RF_8256: 1265 /* TEST!! This is not the table for 8256!! */ 1266 if (!(channel >= 1 && channel <= 14)) { 1267 RT_TRACE(COMP_ERR, 1268 "illegal channel for Zebra 8256: %d\n", 1269 channel); 1270 return true; 1271 } 1272 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1273 MAX_RFDEPENDCMD_CNT, 1274 CMD_ID_RF_WRITE_REG, 1275 rZebra1_Channel, channel, 10); 1276 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1277 MAX_RFDEPENDCMD_CNT, 1278 CMD_ID_END, 0, 0, 0); 1279 break; 1280 1281 case RF_8258: 1282 break; 1283 1284 default: 1285 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1286 return true; 1287 } 1288 1289 1290 do { 1291 switch (*stage) { 1292 case 0: 1293 CurrentCmd = &PreCommonCmd[*step]; 1294 break; 1295 case 1: 1296 CurrentCmd = &RfDependCmd[*step]; 1297 break; 1298 case 2: 1299 CurrentCmd = &PostCommonCmd[*step]; 1300 break; 1301 } 1302 1303 if (CurrentCmd->cmd_id == CMD_ID_END) { 1304 if ((*stage) == 2) { 1305 (*delay) = CurrentCmd->ms_delay; 1306 return true; 1307 } 1308 (*stage)++; 1309 (*step) = 0; 1310 continue; 1311 } 1312 1313 switch (CurrentCmd->cmd_id) { 1314 case CMD_ID_SET_TX_PWR_LEVEL: 1315 if (priv->card_8192_version == VERSION_819XU_A) 1316 /* consider it later! */ 1317 rtl8192_SetTxPowerLevel(dev, channel); 1318 break; 1319 case CMD_ID_WRITE_PORT_ULONG: 1320 write_nic_dword(dev, CurrentCmd->para_1, 1321 CurrentCmd->para_2); 1322 break; 1323 case CMD_ID_WRITE_PORT_USHORT: 1324 write_nic_word(dev, CurrentCmd->para_1, 1325 (u16)CurrentCmd->para_2); 1326 break; 1327 case CMD_ID_WRITE_PORT_UCHAR: 1328 write_nic_byte(dev, CurrentCmd->para_1, 1329 (u8)CurrentCmd->para_2); 1330 break; 1331 case CMD_ID_RF_WRITE_REG: 1332 for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) { 1333 rtl8192_phy_SetRFReg(dev, 1334 (enum rf90_radio_path_e)e_rfpath, 1335 CurrentCmd->para_1, 1336 bZebra1_ChannelNum, 1337 CurrentCmd->para_2); 1338 } 1339 break; 1340 default: 1341 break; 1342 } 1343 1344 break; 1345 } while (true); 1346 1347 (*delay) = CurrentCmd->ms_delay; 1348 (*step)++; 1349 return false; 1350 } 1351 1352 /****************************************************************************** 1353 * function: This function does actually set channel work 1354 * input: net_device *dev 1355 * u8 channel 1356 * output: none 1357 * return: none 1358 * notice: We should not call this function directly 1359 *****************************************************************************/ 1360 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) 1361 { 1362 struct r8192_priv *priv = ieee80211_priv(dev); 1363 u32 delay = 0; 1364 1365 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, 1366 &priv->SwChnlStep, &delay)) { 1367 if (!priv->up) 1368 break; 1369 } 1370 } 1371 1372 /****************************************************************************** 1373 * function: Callback routine of the work item for switch channel. 1374 * input: net_device *dev 1375 * 1376 * output: none 1377 * return: none 1378 *****************************************************************************/ 1379 void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1380 { 1381 1382 struct r8192_priv *priv = ieee80211_priv(dev); 1383 1384 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", 1385 priv->chan); 1386 1387 1388 rtl8192_phy_FinishSwChnlNow(dev, priv->chan); 1389 1390 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); 1391 } 1392 1393 /****************************************************************************** 1394 * function: This function scheduled actual work item to set channel 1395 * input: net_device *dev 1396 * u8 channel //channel to set 1397 * output: none 1398 * return: return code show if workitem is scheduled (1:pass, 0:fail) 1399 * notice: Delay may be required for RF configuration 1400 ******************************************************************************/ 1401 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) 1402 { 1403 struct r8192_priv *priv = ieee80211_priv(dev); 1404 1405 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__, 1406 priv->SwChnlInProgress); 1407 if (!priv->up) 1408 return false; 1409 if (priv->SwChnlInProgress) 1410 return false; 1411 1412 /* -------------------------------------------- */ 1413 switch (priv->ieee80211->mode) { 1414 case WIRELESS_MODE_A: 1415 case WIRELESS_MODE_N_5G: 1416 if (channel <= 14) { 1417 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); 1418 return false; 1419 } 1420 break; 1421 case WIRELESS_MODE_B: 1422 if (channel > 14) { 1423 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); 1424 return false; 1425 } 1426 break; 1427 case WIRELESS_MODE_G: 1428 case WIRELESS_MODE_N_24G: 1429 if (channel > 14) { 1430 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); 1431 return false; 1432 } 1433 break; 1434 } 1435 /* -------------------------------------------- */ 1436 1437 priv->SwChnlInProgress = true; 1438 if (channel == 0) 1439 channel = 1; 1440 1441 priv->chan = channel; 1442 1443 priv->SwChnlStage = 0; 1444 priv->SwChnlStep = 0; 1445 if (priv->up) 1446 rtl8192_SwChnl_WorkItem(dev); 1447 1448 priv->SwChnlInProgress = false; 1449 return true; 1450 } 1451 1452 /****************************************************************************** 1453 * function: Callback routine of the work item for set bandwidth mode. 1454 * input: net_device *dev 1455 * output: none 1456 * return: none 1457 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1458 * test whether current work in the queue or not.//do I? 1459 *****************************************************************************/ 1460 void rtl8192_SetBWModeWorkItem(struct net_device *dev) 1461 { 1462 1463 struct r8192_priv *priv = ieee80211_priv(dev); 1464 u8 regBwOpMode; 1465 1466 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, 1467 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); 1468 1469 1470 if (priv->rf_chip == RF_PSEUDO_11N) { 1471 priv->SetBWModeInProgress = false; 1472 return; 1473 } 1474 1475 /* <1> Set MAC register */ 1476 read_nic_byte(dev, BW_OPMODE, ®BwOpMode); 1477 1478 switch (priv->CurrentChannelBW) { 1479 case HT_CHANNEL_WIDTH_20: 1480 regBwOpMode |= BW_OPMODE_20MHZ; 1481 /* We have not verify whether this register works */ 1482 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1483 break; 1484 1485 case HT_CHANNEL_WIDTH_20_40: 1486 regBwOpMode &= ~BW_OPMODE_20MHZ; 1487 /* We have not verify whether this register works */ 1488 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1489 break; 1490 1491 default: 1492 RT_TRACE(COMP_ERR, 1493 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1494 priv->CurrentChannelBW); 1495 break; 1496 } 1497 1498 /* <2> Set PHY related register */ 1499 switch (priv->CurrentChannelBW) { 1500 case HT_CHANNEL_WIDTH_20: 1501 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1502 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1503 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 1504 0x00100000, 1); 1505 1506 /* Correct the tx power for CCK rate in 20M. */ 1507 priv->cck_present_attenuation = 1508 priv->cck_present_attenuation_20Mdefault + 1509 priv->cck_present_attenuation_difference; 1510 1511 if (priv->cck_present_attenuation > 22) 1512 priv->cck_present_attenuation = 22; 1513 if (priv->cck_present_attenuation < 0) 1514 priv->cck_present_attenuation = 0; 1515 RT_TRACE(COMP_INIT, 1516 "20M, pHalData->CCKPresentAttentuation = %d\n", 1517 priv->cck_present_attenuation); 1518 1519 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1520 priv->bcck_in_ch14 = true; 1521 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1522 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1523 priv->bcck_in_ch14 = false; 1524 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1525 } else { 1526 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1527 } 1528 1529 break; 1530 case HT_CHANNEL_WIDTH_20_40: 1531 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1532 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1533 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, 1534 priv->nCur40MhzPrimeSC>>1); 1535 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1536 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, 1537 priv->nCur40MhzPrimeSC); 1538 priv->cck_present_attenuation = 1539 priv->cck_present_attenuation_40Mdefault + 1540 priv->cck_present_attenuation_difference; 1541 1542 if (priv->cck_present_attenuation > 22) 1543 priv->cck_present_attenuation = 22; 1544 if (priv->cck_present_attenuation < 0) 1545 priv->cck_present_attenuation = 0; 1546 1547 RT_TRACE(COMP_INIT, 1548 "40M, pHalData->CCKPresentAttentuation = %d\n", 1549 priv->cck_present_attenuation); 1550 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1551 priv->bcck_in_ch14 = true; 1552 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1553 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1554 priv->bcck_in_ch14 = false; 1555 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1556 } else { 1557 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1558 } 1559 1560 break; 1561 default: 1562 RT_TRACE(COMP_ERR, 1563 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1564 priv->CurrentChannelBW); 1565 break; 1566 1567 } 1568 /* Skip over setting of J-mode in BB register here. 1569 * Default value is "None J mode". 1570 */ 1571 1572 /* <3> Set RF related register */ 1573 switch (priv->rf_chip) { 1574 case RF_8225: 1575 break; 1576 1577 case RF_8256: 1578 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW); 1579 break; 1580 1581 case RF_8258: 1582 break; 1583 1584 case RF_PSEUDO_11N: 1585 break; 1586 1587 default: 1588 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1589 break; 1590 } 1591 priv->SetBWModeInProgress = false; 1592 1593 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n", 1594 atomic_read(&priv->ieee80211->atm_swbw)); 1595 } 1596 1597 /****************************************************************************** 1598 * function: This function schedules bandwidth switch work. 1599 * input: struct net_deviceq *dev 1600 * HT_CHANNEL_WIDTH bandwidth //20M or 40M 1601 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care 1602 * output: none 1603 * return: none 1604 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1605 * test whether current work in the queue or not.//do I? 1606 *****************************************************************************/ 1607 void rtl8192_SetBWMode(struct net_device *dev, 1608 enum ht_channel_width bandwidth, 1609 enum ht_extension_chan_offset offset) 1610 { 1611 struct r8192_priv *priv = ieee80211_priv(dev); 1612 1613 if (priv->SetBWModeInProgress) 1614 return; 1615 priv->SetBWModeInProgress = true; 1616 1617 priv->CurrentChannelBW = bandwidth; 1618 1619 if (offset == HT_EXTCHNL_OFFSET_LOWER) 1620 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1621 else if (offset == HT_EXTCHNL_OFFSET_UPPER) 1622 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1623 else 1624 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1625 1626 rtl8192_SetBWModeWorkItem(dev); 1627 1628 } 1629 1630 void InitialGain819xUsb(struct net_device *dev, u8 Operation) 1631 { 1632 struct r8192_priv *priv = ieee80211_priv(dev); 1633 1634 priv->InitialGainOperateType = Operation; 1635 1636 if (priv->up) 1637 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0); 1638 } 1639 1640 void InitialGainOperateWorkItemCallBack(struct work_struct *work) 1641 { 1642 struct delayed_work *dwork = to_delayed_work(work); 1643 struct r8192_priv *priv = container_of(dwork, struct r8192_priv, 1644 initialgain_operate_wq); 1645 struct net_device *dev = priv->ieee80211->dev; 1646 #define SCAN_RX_INITIAL_GAIN 0x17 1647 #define POWER_DETECTION_TH 0x08 1648 u32 bitmask; 1649 u8 initial_gain; 1650 u8 Operation; 1651 1652 Operation = priv->InitialGainOperateType; 1653 1654 switch (Operation) { 1655 case IG_Backup: 1656 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); 1657 initial_gain = SCAN_RX_INITIAL_GAIN; 1658 bitmask = bMaskByte0; 1659 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1660 /* FW DIG OFF */ 1661 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1662 priv->initgain_backup.xaagccore1 = 1663 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask); 1664 priv->initgain_backup.xbagccore1 = 1665 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask); 1666 priv->initgain_backup.xcagccore1 = 1667 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask); 1668 priv->initgain_backup.xdagccore1 = 1669 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask); 1670 bitmask = bMaskByte2; 1671 priv->initgain_backup.cca = 1672 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask); 1673 1674 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", 1675 priv->initgain_backup.xaagccore1); 1676 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", 1677 priv->initgain_backup.xbagccore1); 1678 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", 1679 priv->initgain_backup.xcagccore1); 1680 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", 1681 priv->initgain_backup.xdagccore1); 1682 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", 1683 priv->initgain_backup.cca); 1684 1685 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", 1686 initial_gain); 1687 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1688 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 1689 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 1690 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 1691 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", 1692 POWER_DETECTION_TH); 1693 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); 1694 break; 1695 case IG_Restore: 1696 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 1697 bitmask = 0x7f; /* Bit0 ~ Bit6 */ 1698 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1699 /* FW DIG OFF */ 1700 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1701 1702 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, 1703 (u32)priv->initgain_backup.xaagccore1); 1704 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, 1705 (u32)priv->initgain_backup.xbagccore1); 1706 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, 1707 (u32)priv->initgain_backup.xcagccore1); 1708 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, 1709 (u32)priv->initgain_backup.xdagccore1); 1710 bitmask = bMaskByte2; 1711 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, 1712 (u32)priv->initgain_backup.cca); 1713 1714 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", 1715 priv->initgain_backup.xaagccore1); 1716 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", 1717 priv->initgain_backup.xbagccore1); 1718 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", 1719 priv->initgain_backup.xcagccore1); 1720 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", 1721 priv->initgain_backup.xdagccore1); 1722 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", 1723 priv->initgain_backup.cca); 1724 1725 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); 1726 1727 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1728 /* FW DIG ON */ 1729 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); 1730 break; 1731 default: 1732 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); 1733 break; 1734 } 1735 } 1736