1 #include "r8192U.h" 2 #include "r8192U_hw.h" 3 #include "r819xU_phy.h" 4 #include "r819xU_phyreg.h" 5 #include "r8190_rtl8256.h" 6 #include "r8192U_dm.h" 7 #include "r819xU_firmware_img.h" 8 9 #include "dot11d.h" 10 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 11 0, 12 0x085c, //2412 1 13 0x08dc, //2417 2 14 0x095c, //2422 3 15 0x09dc, //2427 4 16 0x0a5c, //2432 5 17 0x0adc, //2437 6 18 0x0b5c, //2442 7 19 0x0bdc, //2447 8 20 0x0c5c, //2452 9 21 0x0cdc, //2457 10 22 0x0d5c, //2462 11 23 0x0ddc, //2467 12 24 0x0e5c, //2472 13 25 0x0f72, //2484 26 }; 27 28 29 #define rtl819XPHY_REG_1T2RArray Rtl8192UsbPHY_REG_1T2RArray 30 #define rtl819XMACPHY_Array_PG Rtl8192UsbMACPHY_Array_PG 31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array 32 #define rtl819XRadioA_Array Rtl8192UsbRadioA_Array 33 #define rtl819XRadioB_Array Rtl8192UsbRadioB_Array 34 #define rtl819XRadioC_Array Rtl8192UsbRadioC_Array 35 #define rtl819XRadioD_Array Rtl8192UsbRadioD_Array 36 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array 37 38 /****************************************************************************** 39 *function: This function read BB parameters from Header file we gen, 40 * and do register read/write 41 * input: u32 dwBitMask //taget bit pos in the addr to be modified 42 * output: none 43 * return: u32 return the shift bit position of the mask 44 * ****************************************************************************/ 45 u32 rtl8192_CalculateBitShift(u32 dwBitMask) 46 { 47 u32 i; 48 for (i=0; i<=31; i++) 49 { 50 if (((dwBitMask>>i)&0x1) == 1) 51 break; 52 } 53 return i; 54 } 55 /****************************************************************************** 56 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false. 57 * input: none 58 * output: none 59 * return: 0(illegal, false), 1(legal,true) 60 * ***************************************************************************/ 61 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) 62 { 63 u8 ret = 1; 64 struct r8192_priv *priv = ieee80211_priv(dev); 65 if (priv->rf_type == RF_2T4R) 66 ret = 0; 67 else if (priv->rf_type == RF_1T2R) 68 { 69 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) 70 ret = 1; 71 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) 72 ret = 0; 73 } 74 return ret; 75 } 76 /****************************************************************************** 77 *function: This function set specific bits to BB register 78 * input: net_device dev 79 * u32 dwRegAddr //target addr to be modified 80 * u32 dwBitMask //taget bit pos in the addr to be modified 81 * u32 dwData //value to be write 82 * output: none 83 * return: none 84 * notice: 85 * ****************************************************************************/ 86 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData) 87 { 88 89 u32 OriginalValue, BitShift, NewValue; 90 91 if(dwBitMask!= bMaskDWord) 92 {//if not "double word" write 93 OriginalValue = read_nic_dword(dev, dwRegAddr); 94 BitShift = rtl8192_CalculateBitShift(dwBitMask); 95 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); 96 write_nic_dword(dev, dwRegAddr, NewValue); 97 }else 98 write_nic_dword(dev, dwRegAddr, dwData); 99 return; 100 } 101 /****************************************************************************** 102 *function: This function reads specific bits from BB register 103 * input: net_device dev 104 * u32 dwRegAddr //target addr to be readback 105 * u32 dwBitMask //taget bit pos in the addr to be readback 106 * output: none 107 * return: u32 Data //the readback register value 108 * notice: 109 * ****************************************************************************/ 110 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) 111 { 112 u32 Ret = 0, OriginalValue, BitShift; 113 114 OriginalValue = read_nic_dword(dev, dwRegAddr); 115 BitShift = rtl8192_CalculateBitShift(dwBitMask); 116 Ret =(OriginalValue & dwBitMask) >> BitShift; 117 118 return (Ret); 119 } 120 static u32 phy_FwRFSerialRead( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset ); 121 122 static void phy_FwRFSerialWrite( struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data); 123 124 /****************************************************************************** 125 *function: This function read register from RF chip 126 * input: net_device dev 127 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 128 * u32 Offset //target address to be read 129 * output: none 130 * return: u32 readback value 131 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information. 132 * ****************************************************************************/ 133 u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset) 134 { 135 struct r8192_priv *priv = ieee80211_priv(dev); 136 u32 ret = 0; 137 u32 NewOffset = 0; 138 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath]; 139 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); 140 //make sure RF register offset is correct 141 Offset &= 0x3f; 142 143 //switch page for 8256 RF IC 144 if (priv->rf_chip == RF_8256) 145 { 146 if (Offset >= 31) 147 { 148 priv->RfReg0Value[eRFPath] |= 0x140; 149 //Switch to Reg_Mode2 for Reg 31-45 150 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); 151 //modify offset 152 NewOffset = Offset -30; 153 } 154 else if (Offset >= 16) 155 { 156 priv->RfReg0Value[eRFPath] |= 0x100; 157 priv->RfReg0Value[eRFPath] &= (~0x40); 158 //Switch to Reg_Mode 1 for Reg16-30 159 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); 160 161 NewOffset = Offset - 15; 162 } 163 else 164 NewOffset = Offset; 165 } 166 else 167 { 168 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); 169 NewOffset = Offset; 170 } 171 //put desired read addr to LSSI control Register 172 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); 173 //Issue a posedge trigger 174 // 175 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 176 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 177 178 179 // TODO: we should not delay such a long time. Ask for help from SD3 180 msleep(1); 181 182 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData); 183 184 185 // Switch back to Reg_Mode0; 186 if(priv->rf_chip == RF_8256) 187 { 188 priv->RfReg0Value[eRFPath] &= 0xebf; 189 190 rtl8192_setBBreg( 191 dev, 192 pPhyReg->rf3wireOffset, 193 bMaskDWord, 194 (priv->RfReg0Value[eRFPath] << 16)); 195 } 196 197 return ret; 198 199 } 200 201 /****************************************************************************** 202 *function: This function write data to RF register 203 * input: net_device dev 204 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 205 * u32 Offset //target address to be written 206 * u32 Data //The new register data to be written 207 * output: none 208 * return: none 209 * notice: For RF8256 only. 210 =========================================================== 211 *Reg Mode RegCTL[1] RegCTL[0] Note 212 * (Reg00[12]) (Reg00[10]) 213 *=========================================================== 214 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf) 215 *------------------------------------------------------------------ 216 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf) 217 *------------------------------------------------------------------ 218 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 219 *------------------------------------------------------------------ 220 * ****************************************************************************/ 221 void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data) 222 { 223 struct r8192_priv *priv = ieee80211_priv(dev); 224 u32 DataAndAddr = 0, NewOffset = 0; 225 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 226 227 Offset &= 0x3f; 228 //spin_lock_irqsave(&priv->rf_lock, flags); 229 // down(&priv->rf_sem); 230 if (priv->rf_chip == RF_8256) 231 { 232 233 if (Offset >= 31) 234 { 235 priv->RfReg0Value[eRFPath] |= 0x140; 236 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); 237 NewOffset = Offset - 30; 238 } 239 else if (Offset >= 16) 240 { 241 priv->RfReg0Value[eRFPath] |= 0x100; 242 priv->RfReg0Value[eRFPath] &= (~0x40); 243 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); 244 NewOffset = Offset - 15; 245 } 246 else 247 NewOffset = Offset; 248 } 249 else 250 { 251 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n"); 252 NewOffset = Offset; 253 } 254 255 // Put write addr in [5:0] and write data in [31:16] 256 DataAndAddr = (Data<<16) | (NewOffset&0x3f); 257 258 // Write Operation 259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 260 261 262 if(Offset==0x0) 263 priv->RfReg0Value[eRFPath] = Data; 264 265 // Switch back to Reg_Mode0; 266 if(priv->rf_chip == RF_8256) 267 { 268 if(Offset != 0) 269 { 270 priv->RfReg0Value[eRFPath] &= 0xebf; 271 rtl8192_setBBreg( 272 dev, 273 pPhyReg->rf3wireOffset, 274 bMaskDWord, 275 (priv->RfReg0Value[eRFPath] << 16)); 276 } 277 } 278 //spin_unlock_irqrestore(&priv->rf_lock, flags); 279 // up(&priv->rf_sem); 280 return; 281 } 282 283 /****************************************************************************** 284 *function: This function set specific bits to RF register 285 * input: net_device dev 286 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D 287 * u32 RegAddr //target addr to be modified 288 * u32 BitMask //taget bit pos in the addr to be modified 289 * u32 Data //value to be write 290 * output: none 291 * return: none 292 * notice: 293 * ****************************************************************************/ 294 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data) 295 { 296 struct r8192_priv *priv = ieee80211_priv(dev); 297 u32 Original_Value, BitShift, New_Value; 298 // u8 time = 0; 299 300 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 301 return; 302 303 if (priv->Rf_Mode == RF_OP_By_FW) 304 { 305 if (BitMask != bMask12Bits) // RF data is 12 bits only 306 { 307 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); 308 BitShift = rtl8192_CalculateBitShift(BitMask); 309 New_Value = ((Original_Value) & (~BitMask)) | (Data<< BitShift); 310 311 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); 312 }else 313 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); 314 315 udelay(200); 316 317 } 318 else 319 { 320 if (BitMask != bMask12Bits) // RF data is 12 bits only 321 { 322 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); 323 BitShift = rtl8192_CalculateBitShift(BitMask); 324 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); 325 326 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); 327 }else 328 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); 329 } 330 return; 331 } 332 333 /****************************************************************************** 334 *function: This function reads specific bits from RF register 335 * input: net_device dev 336 * u32 RegAddr //target addr to be readback 337 * u32 BitMask //taget bit pos in the addr to be readback 338 * output: none 339 * return: u32 Data //the readback register value 340 * notice: 341 * ****************************************************************************/ 342 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask) 343 { 344 u32 Original_Value, Readback_Value, BitShift; 345 struct r8192_priv *priv = ieee80211_priv(dev); 346 347 348 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 349 return 0; 350 if (priv->Rf_Mode == RF_OP_By_FW) 351 { 352 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); 353 BitShift = rtl8192_CalculateBitShift(BitMask); 354 Readback_Value = (Original_Value & BitMask) >> BitShift; 355 udelay(200); 356 return (Readback_Value); 357 } 358 else 359 { 360 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr); 361 BitShift = rtl8192_CalculateBitShift(BitMask); 362 Readback_Value = (Original_Value & BitMask) >> BitShift; 363 return (Readback_Value); 364 } 365 } 366 /****************************************************************************** 367 *function: We support firmware to execute RF-R/W. 368 * input: dev 369 * output: none 370 * return: none 371 * notice: 372 * ***************************************************************************/ 373 static u32 374 phy_FwRFSerialRead( 375 struct net_device* dev, 376 RF90_RADIO_PATH_E eRFPath, 377 u32 Offset ) 378 { 379 u32 retValue = 0; 380 u32 Data = 0; 381 u8 time = 0; 382 //DbgPrint("FW RF CTRL\n\r"); 383 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can 384 not execute the scheme in the initial step. Otherwise, RF-R/W will waste 385 much time. This is only for site survey. */ 386 // 1. Read operation need not insert data. bit 0-11 387 //Data &= bMask12Bits; 388 // 2. Write RF register address. Bit 12-19 389 Data |= ((Offset&0xFF)<<12); 390 // 3. Write RF path. bit 20-21 391 Data |= ((eRFPath&0x3)<<20); 392 // 4. Set RF read indicator. bit 22=0 393 //Data |= 0x00000; 394 // 5. Trigger Fw to operate the command. bit 31 395 Data |= 0x80000000; 396 // 6. We can not execute read operation if bit 31 is 1. 397 while (read_nic_dword(dev, QPNR)&0x80000000) 398 { 399 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 400 if (time++ < 100) 401 { 402 //DbgPrint("FW not finish RF-R Time=%d\n\r", time); 403 udelay(10); 404 } 405 else 406 break; 407 } 408 // 7. Execute read operation. 409 write_nic_dword(dev, QPNR, Data); 410 // 8. Check if firmawre send back RF content. 411 while (read_nic_dword(dev, QPNR)&0x80000000) 412 { 413 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 414 if (time++ < 100) 415 { 416 //DbgPrint("FW not finish RF-W Time=%d\n\r", time); 417 udelay(10); 418 } 419 else 420 return (0); 421 } 422 retValue = read_nic_dword(dev, RF_DATA); 423 424 return (retValue); 425 426 } /* phy_FwRFSerialRead */ 427 428 /****************************************************************************** 429 *function: We support firmware to execute RF-R/W. 430 * input: dev 431 * output: none 432 * return: none 433 * notice: 434 * ***************************************************************************/ 435 static void 436 phy_FwRFSerialWrite( 437 struct net_device* dev, 438 RF90_RADIO_PATH_E eRFPath, 439 u32 Offset, 440 u32 Data ) 441 { 442 u8 time = 0; 443 444 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data); 445 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can 446 not execute the scheme in the initial step. Otherwise, RF-R/W will waste 447 much time. This is only for site survey. */ 448 449 // 1. Set driver write bit and 12 bit data. bit 0-11 450 //Data &= bMask12Bits; // Done by uper layer. 451 // 2. Write RF register address. bit 12-19 452 Data |= ((Offset&0xFF)<<12); 453 // 3. Write RF path. bit 20-21 454 Data |= ((eRFPath&0x3)<<20); 455 // 4. Set RF write indicator. bit 22=1 456 Data |= 0x400000; 457 // 5. Trigger Fw to operate the command. bit 31=1 458 Data |= 0x80000000; 459 460 // 6. Write operation. We can not write if bit 31 is 1. 461 while (read_nic_dword(dev, QPNR)&0x80000000) 462 { 463 // If FW can not finish RF-R/W for more than ?? times. We must reset FW. 464 if (time++ < 100) 465 { 466 //DbgPrint("FW not finish RF-W Time=%d\n\r", time); 467 udelay(10); 468 } 469 else 470 break; 471 } 472 // 7. No matter check bit. We always force the write. Because FW will 473 // not accept the command. 474 write_nic_dword(dev, QPNR, Data); 475 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware 476 to finish RF write operation. */ 477 /* 2008/01/17 MH We support delay in firmware side now. */ 478 //delay_us(20); 479 480 } /* phy_FwRFSerialWrite */ 481 482 483 /****************************************************************************** 484 *function: This function read BB parameters from Header file we gen, 485 * and do register read/write 486 * input: dev 487 * output: none 488 * return: none 489 * notice: BB parameters may change all the time, so please make 490 * sure it has been synced with the newest. 491 * ***************************************************************************/ 492 void rtl8192_phy_configmac(struct net_device* dev) 493 { 494 u32 dwArrayLen = 0, i; 495 u32* pdwArray = NULL; 496 struct r8192_priv *priv = ieee80211_priv(dev); 497 498 if(priv->btxpowerdata_readfromEEPORM) 499 { 500 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); 501 dwArrayLen = MACPHY_Array_PGLength; 502 pdwArray = rtl819XMACPHY_Array_PG; 503 504 } 505 else 506 { 507 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); 508 dwArrayLen = MACPHY_ArrayLength; 509 pdwArray = rtl819XMACPHY_Array; 510 } 511 for(i = 0; i<dwArrayLen; i=i+3){ 512 if(pdwArray[i] == 0x318) 513 { 514 pdwArray[i+2] = 0x00000800; 515 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n", 516 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]); 517 } 518 519 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", 520 pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 521 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 522 } 523 return; 524 525 } 526 527 /****************************************************************************** 528 *function: This function does dirty work 529 * input: dev 530 * output: none 531 * return: none 532 * notice: BB parameters may change all the time, so please make 533 * sure it has been synced with the newest. 534 * ***************************************************************************/ 535 536 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) 537 { 538 u32 i; 539 540 #ifdef TO_DO_LIST 541 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; 542 if(Adapter->bInHctTest) 543 { 544 PHY_REGArrayLen = PHY_REGArrayLengthDTM; 545 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; 546 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; 547 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; 548 } 549 #endif 550 if (ConfigType == BaseBand_Config_PHY_REG) 551 { 552 for (i=0; i<PHY_REG_1T2RArrayLength; i+=2) 553 { 554 rtl8192_setBBreg(dev, rtl819XPHY_REG_1T2RArray[i], bMaskDWord, rtl819XPHY_REG_1T2RArray[i+1]); 555 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, rtl819XPHY_REG_1T2RArray[i], rtl819XPHY_REG_1T2RArray[i+1]); 556 } 557 } 558 else if (ConfigType == BaseBand_Config_AGC_TAB) 559 { 560 for (i=0; i<AGCTAB_ArrayLength; i+=2) 561 { 562 rtl8192_setBBreg(dev, rtl819XAGCTAB_Array[i], bMaskDWord, rtl819XAGCTAB_Array[i+1]); 563 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, rtl819XAGCTAB_Array[i], rtl819XAGCTAB_Array[i+1]); 564 } 565 } 566 return; 567 568 569 } 570 /****************************************************************************** 571 *function: This function initialize Register definition offset for Radio Path 572 * A/B/C/D 573 * input: net_device dev 574 * output: none 575 * return: none 576 * notice: Initialization value here is constant and it should never be changed 577 * ***************************************************************************/ 578 void rtl8192_InitBBRFRegDef(struct net_device* dev) 579 { 580 struct r8192_priv *priv = ieee80211_priv(dev); 581 // RF Interface Software Control 582 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870 583 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) 584 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874 585 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) 586 587 // RF Interface Readback Value 588 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0 589 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) 590 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4 591 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) 592 593 // RF Interface Output (and Enable) 594 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860 595 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864 596 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868 597 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C 598 599 // RF Interface (Output and) Enable 600 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) 601 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) 602 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) 603 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) 604 605 //Addr of LSSI. Write RF register by driver 606 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter 607 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 608 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 609 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 610 611 // RF parameter 612 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select 613 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 614 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 615 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 616 617 // Tx AGC Gain Stage (same for all path. Should we remove this?) 618 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 619 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 620 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 621 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage 622 623 // Tranceiver A~D HSSI Parameter-1 624 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1 625 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1 626 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1 627 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1 628 629 // Tranceiver A~D HSSI Parameter-2 630 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2 631 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2 632 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2 633 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1 634 635 // RF switch Control 636 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control 637 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 638 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 639 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 640 641 // AGC control 1 642 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 643 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 644 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 645 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 646 647 // AGC control 2 648 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 649 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 650 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 651 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 652 653 // RX AFE control 1 654 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 655 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 656 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 657 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 658 659 // RX AFE control 1 660 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 661 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 662 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 663 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 664 665 // Tx AFE control 1 666 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 667 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 668 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 669 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 670 671 // Tx AFE control 2 672 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 673 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 674 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 675 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 676 677 // Tranceiver LSSI Readback 678 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 679 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 680 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 681 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 682 683 } 684 /****************************************************************************** 685 *function: This function is to write register and then readback to make sure whether BB and RF is OK 686 * input: net_device dev 687 * HW90_BLOCK_E CheckBlock 688 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF 689 * output: none 690 * return: return whether BB and RF is ok(0:OK; 1:Fail) 691 * notice: This function may be removed in the ASIC 692 * ***************************************************************************/ 693 u8 rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath) 694 { 695 // struct r8192_priv *priv = ieee80211_priv(dev); 696 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath]; 697 u8 ret = 0; 698 u32 i, CheckTimes = 4, dwRegRead = 0; 699 u32 WriteAddr[4]; 700 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 701 // Initialize register address offset to be checked 702 WriteAddr[HW90_BLOCK_MAC] = 0x100; 703 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 704 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 705 WriteAddr[HW90_BLOCK_RF] = 0x3; 706 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock); 707 for(i=0 ; i < CheckTimes ; i++) 708 { 709 710 // 711 // Write Data to register and readback 712 // 713 switch(CheckBlock) 714 { 715 case HW90_BLOCK_MAC: 716 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); 717 break; 718 719 case HW90_BLOCK_PHY0: 720 case HW90_BLOCK_PHY1: 721 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); 722 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); 723 break; 724 725 case HW90_BLOCK_RF: 726 WriteData[i] &= 0xfff; 727 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); 728 // TODO: we should not delay for such a long time. Ask SD3 729 msleep(1); 730 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits); 731 msleep(1); 732 break; 733 734 default: 735 ret = 1; 736 break; 737 } 738 739 740 // 741 // Check whether readback data is correct 742 // 743 if(dwRegRead != WriteData[i]) 744 { 745 RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); 746 ret = 1; 747 break; 748 } 749 } 750 751 return ret; 752 } 753 754 755 /****************************************************************************** 756 *function: This function initialize BB&RF 757 * input: net_device dev 758 * output: none 759 * return: none 760 * notice: Initialization value may change all the time, so please make 761 * sure it has been synced with the newest. 762 * ***************************************************************************/ 763 void rtl8192_BB_Config_ParaFile(struct net_device* dev) 764 { 765 struct r8192_priv *priv = ieee80211_priv(dev); 766 u8 bRegValue = 0, eCheckItem = 0, rtStatus = 0; 767 u32 dwRegValue = 0; 768 /************************************** 769 //<1>Initialize BaseBand 770 **************************************/ 771 772 /*--set BB Global Reset--*/ 773 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); 774 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); 775 mdelay(50); 776 /*---set BB reset Active---*/ 777 dwRegValue = read_nic_dword(dev, CPU_GEN); 778 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); 779 780 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/ 781 // TODO: this function should be removed on ASIC , Emily 2007.2.2 782 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) 783 { 784 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path 785 if(rtStatus != 0) 786 { 787 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); 788 return ; 789 } 790 } 791 /*---- Set CCK and OFDM Block "OFF"----*/ 792 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 793 /*----BB Register Initilazation----*/ 794 //==m==>Set PHY REG From Header<==m== 795 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG); 796 797 /*----Set BB reset de-Active----*/ 798 dwRegValue = read_nic_dword(dev, CPU_GEN); 799 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST)); 800 801 /*----BB AGC table Initialization----*/ 802 //==m==>Set PHY REG From Header<==m== 803 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); 804 805 /*----Enable XSTAL ----*/ 806 write_nic_byte_E(dev, 0x5e, 0x00); 807 if (priv->card_8192_version == (u8)VERSION_819xU_A) 808 { 809 //Antenna gain offset from B/C/D to A 810 dwRegValue = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]); 811 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), dwRegValue); 812 813 //XSTALLCap 814 dwRegValue = priv->CrystalCap & 0xf; 815 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, dwRegValue); 816 } 817 818 // Check if the CCK HighPower is turned ON. 819 // This is used to calculate PWDB. 820 priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200)); 821 return; 822 } 823 /****************************************************************************** 824 *function: This function initialize BB&RF 825 * input: net_device dev 826 * output: none 827 * return: none 828 * notice: Initialization value may change all the time, so please make 829 * sure it has been synced with the newest. 830 * ***************************************************************************/ 831 void rtl8192_BBConfig(struct net_device* dev) 832 { 833 rtl8192_InitBBRFRegDef(dev); 834 //config BB&RF. As hardCode based initialization has not been well 835 //implemented, so use file first.FIXME:should implement it for hardcode? 836 rtl8192_BB_Config_ParaFile(dev); 837 return; 838 } 839 840 /****************************************************************************** 841 *function: This function obtains the initialization value of Tx power Level offset 842 * input: net_device dev 843 * output: none 844 * return: none 845 * ***************************************************************************/ 846 void rtl8192_phy_getTxPower(struct net_device* dev) 847 { 848 struct r8192_priv *priv = ieee80211_priv(dev); 849 priv->MCSTxPowerLevelOriginalOffset[0] = 850 read_nic_dword(dev, rTxAGC_Rate18_06); 851 priv->MCSTxPowerLevelOriginalOffset[1] = 852 read_nic_dword(dev, rTxAGC_Rate54_24); 853 priv->MCSTxPowerLevelOriginalOffset[2] = 854 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00); 855 priv->MCSTxPowerLevelOriginalOffset[3] = 856 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04); 857 priv->MCSTxPowerLevelOriginalOffset[4] = 858 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08); 859 priv->MCSTxPowerLevelOriginalOffset[5] = 860 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12); 861 862 // read rx initial gain 863 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1); 864 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); 865 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); 866 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); 867 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", 868 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 869 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 870 871 // read framesync 872 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); 873 priv->framesyncC34 = read_nic_byte(dev, rOFDM0_RxDetector2); 874 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", 875 rOFDM0_RxDetector3, priv->framesync); 876 877 // read SIFS (save the value read fome MACPHY_REG.txt) 878 priv->SifsTime = read_nic_word(dev, SIFS); 879 880 return; 881 } 882 883 /****************************************************************************** 884 *function: This function obtains the initialization value of Tx power Level offset 885 * input: net_device dev 886 * output: none 887 * return: none 888 * ***************************************************************************/ 889 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) 890 { 891 struct r8192_priv *priv = ieee80211_priv(dev); 892 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 893 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 894 895 switch(priv->rf_chip) 896 { 897 case RF_8256: 898 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement 899 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 900 break; 901 default: 902 // case RF_8225: 903 // case RF_8258: 904 RT_TRACE((COMP_PHY|COMP_ERR), "error RF chipID(8225 or 8258) in function %s()\n", __FUNCTION__); 905 break; 906 } 907 return; 908 } 909 910 /****************************************************************************** 911 *function: This function check Rf chip to do RF config 912 * input: net_device dev 913 * output: none 914 * return: only 8256 is supported 915 * ***************************************************************************/ 916 void rtl8192_phy_RFConfig(struct net_device* dev) 917 { 918 struct r8192_priv *priv = ieee80211_priv(dev); 919 920 switch(priv->rf_chip) 921 { 922 case RF_8256: 923 PHY_RF8256_Config(dev); 924 break; 925 // case RF_8225: 926 // case RF_8258: 927 default: 928 RT_TRACE(COMP_ERR, "error chip id\n"); 929 break; 930 } 931 return; 932 } 933 934 /****************************************************************************** 935 *function: This function update Initial gain 936 * input: net_device dev 937 * output: none 938 * return: As Windows has not implemented this, wait for complement 939 * ***************************************************************************/ 940 void rtl8192_phy_updateInitGain(struct net_device* dev) 941 { 942 return; 943 } 944 945 /****************************************************************************** 946 *function: This function read RF parameters from general head file, and do RF 3-wire 947 * input: net_device dev 948 * output: none 949 * return: return code show if RF configuration is successful(0:pass, 1:fail) 950 * Note: Delay may be required for RF configuration 951 * ***************************************************************************/ 952 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath) 953 { 954 955 int i; 956 //u32* pRFArray; 957 u8 ret = 0; 958 959 switch(eRFPath){ 960 case RF90_PATH_A: 961 for(i = 0;i<RadioA_ArrayLength; i=i+2){ 962 963 if(rtl819XRadioA_Array[i] == 0xfe){ 964 mdelay(100); 965 continue; 966 } 967 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioA_Array[i], bMask12Bits, rtl819XRadioA_Array[i+1]); 968 mdelay(1); 969 970 } 971 break; 972 case RF90_PATH_B: 973 for(i = 0;i<RadioB_ArrayLength; i=i+2){ 974 975 if(rtl819XRadioB_Array[i] == 0xfe){ 976 mdelay(100); 977 continue; 978 } 979 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioB_Array[i], bMask12Bits, rtl819XRadioB_Array[i+1]); 980 mdelay(1); 981 982 } 983 break; 984 case RF90_PATH_C: 985 for(i = 0;i<RadioC_ArrayLength; i=i+2){ 986 987 if(rtl819XRadioC_Array[i] == 0xfe){ 988 mdelay(100); 989 continue; 990 } 991 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioC_Array[i], bMask12Bits, rtl819XRadioC_Array[i+1]); 992 mdelay(1); 993 994 } 995 break; 996 case RF90_PATH_D: 997 for(i = 0;i<RadioD_ArrayLength; i=i+2){ 998 999 if(rtl819XRadioD_Array[i] == 0xfe){ 1000 mdelay(100); 1001 continue; 1002 } 1003 rtl8192_phy_SetRFReg(dev, eRFPath, rtl819XRadioD_Array[i], bMask12Bits, rtl819XRadioD_Array[i+1]); 1004 mdelay(1); 1005 1006 } 1007 break; 1008 default: 1009 break; 1010 } 1011 1012 return ret; 1013 1014 } 1015 /****************************************************************************** 1016 *function: This function set Tx Power of the channel 1017 * input: struct net_device *dev 1018 * u8 channel 1019 * output: none 1020 * return: none 1021 * Note: 1022 * ***************************************************************************/ 1023 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) 1024 { 1025 struct r8192_priv *priv = ieee80211_priv(dev); 1026 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 1027 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 1028 1029 switch(priv->rf_chip) 1030 { 1031 case RF_8225: 1032 #ifdef TO_DO_LIST 1033 PHY_SetRF8225CckTxPower(Adapter, powerlevel); 1034 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); 1035 #endif 1036 break; 1037 1038 case RF_8256: 1039 PHY_SetRF8256CCKTxPower(dev, powerlevel); 1040 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G); 1041 break; 1042 1043 case RF_8258: 1044 break; 1045 default: 1046 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); 1047 break; 1048 } 1049 return; 1050 } 1051 1052 /****************************************************************************** 1053 *function: This function set RF state on or off 1054 * input: struct net_device *dev 1055 * RT_RF_POWER_STATE eRFPowerState //Power State to set 1056 * output: none 1057 * return: none 1058 * Note: 1059 * ***************************************************************************/ 1060 bool rtl8192_SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState) 1061 { 1062 bool bResult = true; 1063 // u8 eRFPath; 1064 struct r8192_priv *priv = ieee80211_priv(dev); 1065 1066 if(eRFPowerState == priv->ieee80211->eRFPowerState) 1067 return false; 1068 1069 if(priv->SetRFPowerStateInProgress == true) 1070 return false; 1071 1072 priv->SetRFPowerStateInProgress = true; 1073 1074 switch(priv->rf_chip) 1075 { 1076 case RF_8256: 1077 switch( eRFPowerState ) 1078 { 1079 case eRfOn: 1080 //RF-A, RF-B 1081 //enable RF-Chip A/B 1082 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); // 0x860[4] 1083 //analog to digital on 1084 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8] 1085 //digital to analog on 1086 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3] 1087 //rx antenna on 1088 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0] 1089 //rx antenna on 1090 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0] 1091 //analog to digital part2 on 1092 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5] 1093 1094 break; 1095 1096 case eRfSleep: 1097 1098 break; 1099 1100 case eRfOff: 1101 //RF-A, RF-B 1102 //disable RF-Chip A/B 1103 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); // 0x860[4] 1104 //analog to digital off, for power save 1105 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8] 1106 //digital to analog off, for power save 1107 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3] 1108 //rx antenna off 1109 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0] 1110 //rx antenna off 1111 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0] 1112 //analog to digital part2 off, for power save 1113 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5] 1114 1115 break; 1116 1117 default: 1118 bResult = false; 1119 RT_TRACE(COMP_ERR, "SetRFPowerState819xUsb(): unknow state to set: 0x%X!!!\n", eRFPowerState); 1120 break; 1121 } 1122 break; 1123 default: 1124 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); 1125 break; 1126 } 1127 #ifdef TO_DO_LIST 1128 if(bResult) 1129 { 1130 // Update current RF state variable. 1131 pHalData->eRFPowerState = eRFPowerState; 1132 switch(pHalData->RFChipID ) 1133 { 1134 case RF_8256: 1135 switch(pHalData->eRFPowerState) 1136 { 1137 case eRfOff: 1138 // 1139 //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015 1140 // 1141 if(pMgntInfo->RfOffReason==RF_CHANGE_BY_IPS ) 1142 { 1143 Adapter->HalFunc.LedControlHandler(Adapter,LED_CTL_NO_LINK); 1144 } 1145 else 1146 { 1147 // Turn off LED if RF is not ON. 1148 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); 1149 } 1150 break; 1151 1152 case eRfOn: 1153 // Turn on RF we are still linked, which might happen when 1154 // we quickly turn off and on HW RF. 2006.05.12, by rcnjko. 1155 if( pMgntInfo->bMediaConnect == TRUE ) 1156 { 1157 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); 1158 } 1159 else 1160 { 1161 // Turn off LED if RF is not ON. 1162 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); 1163 } 1164 break; 1165 1166 default: 1167 // do nothing. 1168 break; 1169 }// Switch RF state 1170 break; 1171 1172 default: 1173 RT_TRACE(COMP_RF, DBG_LOUD, ("SetRFPowerState8190(): Unknown RF type\n")); 1174 break; 1175 } 1176 1177 } 1178 #endif 1179 priv->SetRFPowerStateInProgress = false; 1180 1181 return bResult; 1182 } 1183 1184 /**************************************************************************************** 1185 *function: This function set command table variable(struct SwChnlCmd). 1186 * input: SwChnlCmd* CmdTable //table to be set. 1187 * u32 CmdTableIdx //variable index in table to be set 1188 * u32 CmdTableSz //table size. 1189 * SwChnlCmdID CmdID //command ID to set. 1190 * u32 Para1 1191 * u32 Para2 1192 * u32 msDelay 1193 * output: 1194 * return: true if finished, false otherwise 1195 * Note: 1196 * ************************************************************************************/ 1197 u8 rtl8192_phy_SetSwChnlCmdArray( 1198 SwChnlCmd* CmdTable, 1199 u32 CmdTableIdx, 1200 u32 CmdTableSz, 1201 SwChnlCmdID CmdID, 1202 u32 Para1, 1203 u32 Para2, 1204 u32 msDelay 1205 ) 1206 { 1207 SwChnlCmd* pCmd; 1208 1209 if(CmdTable == NULL) 1210 { 1211 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); 1212 return false; 1213 } 1214 if(CmdTableIdx >= CmdTableSz) 1215 { 1216 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", 1217 CmdTableIdx, CmdTableSz); 1218 return false; 1219 } 1220 1221 pCmd = CmdTable + CmdTableIdx; 1222 pCmd->CmdID = CmdID; 1223 pCmd->Para1 = Para1; 1224 pCmd->Para2 = Para2; 1225 pCmd->msDelay = msDelay; 1226 1227 return true; 1228 } 1229 /****************************************************************************** 1230 *function: This function set channel step by step 1231 * input: struct net_device *dev 1232 * u8 channel 1233 * u8* stage //3 stages 1234 * u8* step // 1235 * u32* delay //whether need to delay 1236 * output: store new stage, step and delay for next step(combine with function above) 1237 * return: true if finished, false otherwise 1238 * Note: Wait for simpler function to replace it //wb 1239 * ***************************************************************************/ 1240 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay) 1241 { 1242 struct r8192_priv *priv = ieee80211_priv(dev); 1243 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting; 1244 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT]; 1245 u32 PreCommonCmdCnt; 1246 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT]; 1247 u32 PostCommonCmdCnt; 1248 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; 1249 u32 RfDependCmdCnt; 1250 SwChnlCmd *CurrentCmd = NULL; 1251 //RF90_RADIO_PATH_E eRFPath; 1252 u8 eRFPath; 1253 // u32 RfRetVal; 1254 // u8 RetryCnt; 1255 1256 RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel); 1257 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel)); 1258 if (!IsLegalChannel(priv->ieee80211, channel)) 1259 { 1260 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); 1261 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop. 1262 } 1263 //FIXME:need to check whether channel is legal or not here.WB 1264 1265 1266 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++) 1267 // for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++) 1268 // { 1269 // if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath)) 1270 // continue; 1271 // <1> Fill up pre common command. 1272 PreCommonCmdCnt = 0; 1273 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, 1274 CmdID_SetTxPowerLevel, 0, 0, 0); 1275 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, 1276 CmdID_End, 0, 0, 0); 1277 1278 // <2> Fill up post common command. 1279 PostCommonCmdCnt = 0; 1280 1281 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, 1282 CmdID_End, 0, 0, 0); 1283 1284 // <3> Fill up RF dependent command. 1285 RfDependCmdCnt = 0; 1286 switch( priv->rf_chip ) 1287 { 1288 case RF_8225: 1289 if (!(channel >= 1 && channel <= 14)) 1290 { 1291 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); 1292 return true; 1293 } 1294 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, 1295 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); 1296 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, 1297 CmdID_End, 0, 0, 0); 1298 break; 1299 1300 case RF_8256: 1301 // TEST!! This is not the table for 8256!! 1302 if (!(channel >= 1 && channel <= 14)) 1303 { 1304 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); 1305 return true; 1306 } 1307 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, 1308 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); 1309 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, 1310 CmdID_End, 0, 0, 0); 1311 break; 1312 1313 case RF_8258: 1314 break; 1315 1316 default: 1317 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1318 return true; 1319 break; 1320 } 1321 1322 1323 do{ 1324 switch(*stage) 1325 { 1326 case 0: 1327 CurrentCmd=&PreCommonCmd[*step]; 1328 break; 1329 case 1: 1330 CurrentCmd=&RfDependCmd[*step]; 1331 break; 1332 case 2: 1333 CurrentCmd=&PostCommonCmd[*step]; 1334 break; 1335 } 1336 1337 if(CurrentCmd->CmdID==CmdID_End) 1338 { 1339 if((*stage)==2) 1340 { 1341 (*delay)=CurrentCmd->msDelay; 1342 return true; 1343 } 1344 else 1345 { 1346 (*stage)++; 1347 (*step)=0; 1348 continue; 1349 } 1350 } 1351 1352 switch(CurrentCmd->CmdID) 1353 { 1354 case CmdID_SetTxPowerLevel: 1355 if(priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later! 1356 rtl8192_SetTxPowerLevel(dev,channel); 1357 break; 1358 case CmdID_WritePortUlong: 1359 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); 1360 break; 1361 case CmdID_WritePortUshort: 1362 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); 1363 break; 1364 case CmdID_WritePortUchar: 1365 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); 1366 break; 1367 case CmdID_RF_WriteReg: 1368 for(eRFPath = 0; eRFPath < RF90_PATH_MAX; eRFPath++) 1369 { 1370 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bZebra1_ChannelNum, CurrentCmd->Para2); 1371 } 1372 break; 1373 default: 1374 break; 1375 } 1376 1377 break; 1378 }while(true); 1379 // }/*for(Number of RF paths)*/ 1380 1381 (*delay)=CurrentCmd->msDelay; 1382 (*step)++; 1383 return false; 1384 } 1385 1386 /****************************************************************************** 1387 *function: This function does actually set channel work 1388 * input: struct net_device *dev 1389 * u8 channel 1390 * output: none 1391 * return: noin 1392 * Note: We should not call this function directly 1393 * ***************************************************************************/ 1394 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) 1395 { 1396 struct r8192_priv *priv = ieee80211_priv(dev); 1397 u32 delay = 0; 1398 1399 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) 1400 { 1401 // if(delay>0) 1402 // msleep(delay);//or mdelay? need further consideration 1403 if(!priv->up) 1404 break; 1405 } 1406 } 1407 /****************************************************************************** 1408 *function: Callback routine of the work item for switch channel. 1409 * input: 1410 * 1411 * output: none 1412 * return: noin 1413 * ***************************************************************************/ 1414 void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1415 { 1416 1417 struct r8192_priv *priv = ieee80211_priv(dev); 1418 1419 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", priv->chan); 1420 1421 1422 rtl8192_phy_FinishSwChnlNow(dev , priv->chan); 1423 1424 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); 1425 } 1426 1427 /****************************************************************************** 1428 *function: This function scheduled actual work item to set channel 1429 * input: net_device dev 1430 * u8 channel //channel to set 1431 * output: none 1432 * return: return code show if workitem is scheduled(1:pass, 0:fail) 1433 * Note: Delay may be required for RF configuration 1434 * ***************************************************************************/ 1435 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) 1436 { 1437 struct r8192_priv *priv = ieee80211_priv(dev); 1438 RT_TRACE(COMP_CH, "=====>%s(), SwChnlInProgress:%d\n", __FUNCTION__, priv->SwChnlInProgress); 1439 if(!priv->up) 1440 return false; 1441 if(priv->SwChnlInProgress) 1442 return false; 1443 1444 // if(pHalData->SetBWModeInProgress) 1445 // return; 1446 if (0) //to test current channel from RF reg 0x7. 1447 { 1448 u8 eRFPath; 1449 for(eRFPath = 0; eRFPath < 2; eRFPath++){ 1450 printk("====>set channel:%x\n",rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x7, bZebra1_ChannelNum)); 1451 udelay(10); 1452 } 1453 } 1454 //-------------------------------------------- 1455 switch(priv->ieee80211->mode) 1456 { 1457 case WIRELESS_MODE_A: 1458 case WIRELESS_MODE_N_5G: 1459 if (channel<=14){ 1460 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); 1461 return false; 1462 } 1463 break; 1464 case WIRELESS_MODE_B: 1465 if (channel>14){ 1466 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); 1467 return false; 1468 } 1469 break; 1470 case WIRELESS_MODE_G: 1471 case WIRELESS_MODE_N_24G: 1472 if (channel>14){ 1473 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); 1474 return false; 1475 } 1476 break; 1477 } 1478 //-------------------------------------------- 1479 1480 priv->SwChnlInProgress = true; 1481 if(channel == 0) 1482 channel = 1; 1483 1484 priv->chan=channel; 1485 1486 priv->SwChnlStage=0; 1487 priv->SwChnlStep=0; 1488 // schedule_work(&(priv->SwChnlWorkItem)); 1489 // rtl8192_SwChnl_WorkItem(dev); 1490 if(priv->up) { 1491 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem)); 1492 rtl8192_SwChnl_WorkItem(dev); 1493 } 1494 1495 priv->SwChnlInProgress = false; 1496 return true; 1497 } 1498 1499 1500 // 1501 /****************************************************************************** 1502 *function: Callback routine of the work item for set bandwidth mode. 1503 * input: struct net_device *dev 1504 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M 1505 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care 1506 * output: none 1507 * return: none 1508 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can 1509 * test whether current work in the queue or not.//do I? 1510 * ***************************************************************************/ 1511 void rtl8192_SetBWModeWorkItem(struct net_device *dev) 1512 { 1513 1514 struct r8192_priv *priv = ieee80211_priv(dev); 1515 u8 regBwOpMode; 1516 1517 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ 1518 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") 1519 1520 1521 if(priv->rf_chip == RF_PSEUDO_11N) 1522 { 1523 priv->SetBWModeInProgress= false; 1524 return; 1525 } 1526 1527 //<1>Set MAC register 1528 regBwOpMode = read_nic_byte(dev, BW_OPMODE); 1529 1530 switch(priv->CurrentChannelBW) 1531 { 1532 case HT_CHANNEL_WIDTH_20: 1533 regBwOpMode |= BW_OPMODE_20MHZ; 1534 // 2007/02/07 Mark by Emily because we have not verify whether this register works 1535 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1536 break; 1537 1538 case HT_CHANNEL_WIDTH_20_40: 1539 regBwOpMode &= ~BW_OPMODE_20MHZ; 1540 // 2007/02/07 Mark by Emily because we have not verify whether this register works 1541 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1542 break; 1543 1544 default: 1545 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); 1546 break; 1547 } 1548 1549 //<2>Set PHY related register 1550 switch(priv->CurrentChannelBW) 1551 { 1552 case HT_CHANNEL_WIDTH_20: 1553 // Add by Vivi 20071119 1554 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1555 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1556 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1); 1557 1558 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207 1559 priv->cck_present_attentuation = 1560 priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference; 1561 1562 if(priv->cck_present_attentuation > 22) 1563 priv->cck_present_attentuation= 22; 1564 if(priv->cck_present_attentuation< 0) 1565 priv->cck_present_attentuation = 0; 1566 RT_TRACE(COMP_INIT, "20M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); 1567 1568 if(priv->chan == 14 && !priv->bcck_in_ch14) 1569 { 1570 priv->bcck_in_ch14 = TRUE; 1571 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1572 } 1573 else if(priv->chan != 14 && priv->bcck_in_ch14) 1574 { 1575 priv->bcck_in_ch14 = FALSE; 1576 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1577 } 1578 else 1579 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1580 1581 break; 1582 case HT_CHANNEL_WIDTH_20_40: 1583 // Add by Vivi 20071119 1584 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1585 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1586 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); 1587 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1588 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); 1589 priv->cck_present_attentuation = 1590 priv->cck_present_attentuation_40Mdefault + priv->cck_present_attentuation_difference; 1591 1592 if(priv->cck_present_attentuation > 22) 1593 priv->cck_present_attentuation = 22; 1594 if(priv->cck_present_attentuation < 0) 1595 priv->cck_present_attentuation = 0; 1596 1597 RT_TRACE(COMP_INIT, "40M, pHalData->CCKPresentAttentuation = %d\n", priv->cck_present_attentuation); 1598 if(priv->chan == 14 && !priv->bcck_in_ch14) 1599 { 1600 priv->bcck_in_ch14 = true; 1601 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1602 } 1603 else if(priv->chan!= 14 && priv->bcck_in_ch14) 1604 { 1605 priv->bcck_in_ch14 = false; 1606 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1607 } 1608 else 1609 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); 1610 1611 break; 1612 default: 1613 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); 1614 break; 1615 1616 } 1617 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315 1618 1619 //<3>Set RF related register 1620 switch( priv->rf_chip ) 1621 { 1622 case RF_8225: 1623 #ifdef TO_DO_LIST 1624 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); 1625 #endif 1626 break; 1627 1628 case RF_8256: 1629 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); 1630 break; 1631 1632 case RF_8258: 1633 // PHY_SetRF8258Bandwidth(); 1634 break; 1635 1636 case RF_PSEUDO_11N: 1637 // Do Nothing 1638 break; 1639 1640 default: 1641 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1642 break; 1643 } 1644 priv->SetBWModeInProgress= false; 1645 1646 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d", atomic_read(&(priv->ieee80211->atm_swbw)) ); 1647 } 1648 1649 /****************************************************************************** 1650 *function: This function schedules bandwidth switch work. 1651 * input: struct net_device *dev 1652 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M 1653 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care 1654 * output: none 1655 * return: none 1656 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can 1657 * test whether current work in the queue or not.//do I? 1658 * ***************************************************************************/ 1659 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset) 1660 { 1661 struct r8192_priv *priv = ieee80211_priv(dev); 1662 1663 if(priv->SetBWModeInProgress) 1664 return; 1665 priv->SetBWModeInProgress= true; 1666 1667 priv->CurrentChannelBW = Bandwidth; 1668 1669 if(Offset==HT_EXTCHNL_OFFSET_LOWER) 1670 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1671 else if(Offset==HT_EXTCHNL_OFFSET_UPPER) 1672 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1673 else 1674 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1675 1676 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem)); 1677 // schedule_work(&(priv->SetBWModeWorkItem)); 1678 rtl8192_SetBWModeWorkItem(dev); 1679 1680 } 1681 1682 void InitialGain819xUsb(struct net_device *dev, u8 Operation) 1683 { 1684 struct r8192_priv *priv = ieee80211_priv(dev); 1685 1686 priv->InitialGainOperateType = Operation; 1687 1688 if(priv->up) 1689 { 1690 queue_delayed_work(priv->priv_wq,&priv->initialgain_operate_wq,0); 1691 } 1692 } 1693 1694 extern void InitialGainOperateWorkItemCallBack(struct work_struct *work) 1695 { 1696 struct delayed_work *dwork = container_of(work,struct delayed_work,work); 1697 struct r8192_priv *priv = container_of(dwork,struct r8192_priv,initialgain_operate_wq); 1698 struct net_device *dev = priv->ieee80211->dev; 1699 #define SCAN_RX_INITIAL_GAIN 0x17 1700 #define POWER_DETECTION_TH 0x08 1701 u32 BitMask; 1702 u8 initial_gain; 1703 u8 Operation; 1704 1705 Operation = priv->InitialGainOperateType; 1706 1707 switch(Operation) 1708 { 1709 case IG_Backup: 1710 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); 1711 initial_gain = SCAN_RX_INITIAL_GAIN;//priv->DefaultInitialGain[0];// 1712 BitMask = bMaskByte0; 1713 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1714 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF 1715 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); 1716 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); 1717 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); 1718 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); 1719 BitMask = bMaskByte2; 1720 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); 1721 1722 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); 1723 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); 1724 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); 1725 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); 1726 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); 1727 1728 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); 1729 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1730 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 1731 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 1732 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 1733 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); 1734 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); 1735 break; 1736 case IG_Restore: 1737 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 1738 BitMask = 0x7f; //Bit0~ Bit6 1739 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1740 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF 1741 1742 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1); 1743 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); 1744 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); 1745 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); 1746 BitMask = bMaskByte2; 1747 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); 1748 1749 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); 1750 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); 1751 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); 1752 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); 1753 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); 1754 1755 #ifdef RTL8190P 1756 SetTxPowerLevel8190(Adapter,priv->CurrentChannel); 1757 #endif 1758 #ifdef RTL8192E 1759 SetTxPowerLevel8190(Adapter,priv->CurrentChannel); 1760 #endif 1761 //#ifdef RTL8192U 1762 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel); 1763 //#endif 1764 1765 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1766 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON 1767 break; 1768 default: 1769 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); 1770 break; 1771 } 1772 } 1773 1774