1 // SPDX-License-Identifier: GPL-2.0 2 #include "r8192U.h" 3 #include "r8192U_hw.h" 4 #include "r819xU_phy.h" 5 #include "r819xU_phyreg.h" 6 #include "r8190_rtl8256.h" 7 #include "r8192U_dm.h" 8 #include "r819xU_firmware_img.h" 9 10 #include "dot11d.h" 11 #include <linux/bitops.h> 12 13 static u32 RF_CHANNEL_TABLE_ZEBRA[] = { 14 0, 15 0x085c, /* 2412 1 */ 16 0x08dc, /* 2417 2 */ 17 0x095c, /* 2422 3 */ 18 0x09dc, /* 2427 4 */ 19 0x0a5c, /* 2432 5 */ 20 0x0adc, /* 2437 6 */ 21 0x0b5c, /* 2442 7 */ 22 0x0bdc, /* 2447 8 */ 23 0x0c5c, /* 2452 9 */ 24 0x0cdc, /* 2457 10 */ 25 0x0d5c, /* 2462 11 */ 26 0x0ddc, /* 2467 12 */ 27 0x0e5c, /* 2472 13 */ 28 0x0f72, /* 2484 */ 29 }; 30 31 #define rtl819XMACPHY_Array Rtl8192UsbMACPHY_Array 32 33 /****************************************************************************** 34 * function: This function checks different RF type to execute legal judgement. 35 * If RF Path is illegal, we will return false. 36 * input: net_device *dev 37 * u32 e_rfpath 38 * output: none 39 * return: 0(illegal, false), 1(legal, true) 40 *****************************************************************************/ 41 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 e_rfpath) 42 { 43 u8 ret = 1; 44 struct r8192_priv *priv = ieee80211_priv(dev); 45 46 if (priv->rf_type == RF_2T4R) { 47 ret = 0; 48 } else if (priv->rf_type == RF_1T2R) { 49 if (e_rfpath == RF90_PATH_A || e_rfpath == RF90_PATH_B) 50 ret = 1; 51 else if (e_rfpath == RF90_PATH_C || e_rfpath == RF90_PATH_D) 52 ret = 0; 53 } 54 return ret; 55 } 56 57 /****************************************************************************** 58 * function: This function sets specific bits to BB register 59 * input: net_device *dev 60 * u32 reg_addr //target addr to be modified 61 * u32 bitmask //taget bit pos to be modified 62 * u32 data //value to be write 63 * output: none 64 * return: none 65 * notice: 66 ******************************************************************************/ 67 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask, 68 u32 data) 69 { 70 71 u32 reg, bitshift; 72 73 if (bitmask != bMaskDWord) { 74 read_nic_dword(dev, reg_addr, ®); 75 bitshift = ffs(bitmask) - 1; 76 reg &= ~bitmask; 77 reg |= data << bitshift; 78 write_nic_dword(dev, reg_addr, reg); 79 } else { 80 write_nic_dword(dev, reg_addr, data); 81 } 82 } 83 84 /****************************************************************************** 85 * function: This function reads specific bits from BB register 86 * input: net_device *dev 87 * u32 reg_addr //target addr to be readback 88 * u32 bitmask //taget bit pos to be readback 89 * output: none 90 * return: u32 data //the readback register value 91 * notice: 92 ******************************************************************************/ 93 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask) 94 { 95 u32 reg, bitshift; 96 97 read_nic_dword(dev, reg_addr, ®); 98 bitshift = ffs(bitmask) - 1; 99 100 return (reg & bitmask) >> bitshift; 101 } 102 103 static u32 phy_FwRFSerialRead(struct net_device *dev, 104 enum rf90_radio_path_e e_rfpath, 105 u32 offset); 106 107 static void phy_FwRFSerialWrite(struct net_device *dev, 108 enum rf90_radio_path_e e_rfpath, 109 u32 offset, 110 u32 data); 111 112 /****************************************************************************** 113 * function: This function reads register from RF chip 114 * input: net_device *dev 115 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 116 * u32 offset //target address to be read 117 * output: none 118 * return: u32 readback value 119 * notice: There are three types of serial operations: 120 * (1) Software serial write. 121 * (2)Hardware LSSI-Low Speed Serial Interface. 122 * (3)Hardware HSSI-High speed serial write. 123 * Driver here need to implement (1) and (2) 124 * ---need more spec for this information. 125 ******************************************************************************/ 126 static u32 rtl8192_phy_RFSerialRead(struct net_device *dev, 127 enum rf90_radio_path_e e_rfpath, u32 offset) 128 { 129 struct r8192_priv *priv = ieee80211_priv(dev); 130 u32 ret = 0; 131 u32 new_offset = 0; 132 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; 133 134 rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0); 135 /* Make sure RF register offset is correct */ 136 offset &= 0x3f; 137 138 /* Switch page for 8256 RF IC */ 139 if (priv->rf_chip == RF_8256) { 140 if (offset >= 31) { 141 priv->RfReg0Value[e_rfpath] |= 0x140; 142 /* Switch to Reg_Mode2 for Reg 31-45 */ 143 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 144 bMaskDWord, 145 priv->RfReg0Value[e_rfpath]<<16); 146 /* Modify offset */ 147 new_offset = offset - 30; 148 } else if (offset >= 16) { 149 priv->RfReg0Value[e_rfpath] |= 0x100; 150 priv->RfReg0Value[e_rfpath] &= (~0x40); 151 /* Switch to Reg_Mode1 for Reg16-30 */ 152 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 153 bMaskDWord, 154 priv->RfReg0Value[e_rfpath]<<16); 155 156 new_offset = offset - 15; 157 } else { 158 new_offset = offset; 159 } 160 } else { 161 RT_TRACE((COMP_PHY|COMP_ERR), 162 "check RF type here, need to be 8256\n"); 163 new_offset = offset; 164 } 165 /* Put desired read addr to LSSI control Register */ 166 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, 167 new_offset); 168 /* Issue a posedge trigger */ 169 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); 170 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); 171 172 173 /* TODO: we should not delay such a long time. Ask for help from SD3 */ 174 usleep_range(1000, 1000); 175 176 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, 177 bLSSIReadBackData); 178 179 180 /* Switch back to Reg_Mode0 */ 181 if (priv->rf_chip == RF_8256) { 182 priv->RfReg0Value[e_rfpath] &= 0xebf; 183 184 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, 185 priv->RfReg0Value[e_rfpath] << 16); 186 } 187 188 return ret; 189 } 190 191 /****************************************************************************** 192 * function: This function writes data to RF register 193 * input: net_device *dev 194 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 195 * u32 offset //target address to be written 196 * u32 data //the new register data to be written 197 * output: none 198 * return: none 199 * notice: For RF8256 only. 200 * =========================================================================== 201 * Reg Mode RegCTL[1] RegCTL[0] Note 202 * (Reg00[12]) (Reg00[10]) 203 * =========================================================================== 204 * Reg_Mode0 0 x Reg 0 ~ 15(0x0 ~ 0xf) 205 * --------------------------------------------------------------------------- 206 * Reg_Mode1 1 0 Reg 16 ~ 30(0x1 ~ 0xf) 207 * --------------------------------------------------------------------------- 208 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf) 209 * --------------------------------------------------------------------------- 210 *****************************************************************************/ 211 static void rtl8192_phy_RFSerialWrite(struct net_device *dev, 212 enum rf90_radio_path_e e_rfpath, 213 u32 offset, 214 u32 data) 215 { 216 struct r8192_priv *priv = ieee80211_priv(dev); 217 u32 DataAndAddr = 0, new_offset = 0; 218 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[e_rfpath]; 219 220 offset &= 0x3f; 221 if (priv->rf_chip == RF_8256) { 222 223 if (offset >= 31) { 224 priv->RfReg0Value[e_rfpath] |= 0x140; 225 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 226 bMaskDWord, 227 priv->RfReg0Value[e_rfpath] << 16); 228 new_offset = offset - 30; 229 } else if (offset >= 16) { 230 priv->RfReg0Value[e_rfpath] |= 0x100; 231 priv->RfReg0Value[e_rfpath] &= (~0x40); 232 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 233 bMaskDWord, 234 priv->RfReg0Value[e_rfpath]<<16); 235 new_offset = offset - 15; 236 } else { 237 new_offset = offset; 238 } 239 } else { 240 RT_TRACE((COMP_PHY|COMP_ERR), 241 "check RF type here, need to be 8256\n"); 242 new_offset = offset; 243 } 244 245 /* Put write addr in [5:0] and write data in [31:16] */ 246 DataAndAddr = (data<<16) | (new_offset&0x3f); 247 248 /* Write operation */ 249 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); 250 251 252 if (offset == 0x0) 253 priv->RfReg0Value[e_rfpath] = data; 254 255 /* Switch back to Reg_Mode0 */ 256 if (priv->rf_chip == RF_8256) { 257 if (offset != 0) { 258 priv->RfReg0Value[e_rfpath] &= 0xebf; 259 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, 260 bMaskDWord, 261 priv->RfReg0Value[e_rfpath] << 16); 262 } 263 } 264 } 265 266 /****************************************************************************** 267 * function: This function set specific bits to RF register 268 * input: net_device dev 269 * rf90_radio_path_e e_rfpath //radio path of A/B/C/D 270 * u32 reg_addr //target addr to be modified 271 * u32 bitmask //taget bit pos to be modified 272 * u32 data //value to be written 273 * output: none 274 * return: none 275 * notice: 276 *****************************************************************************/ 277 void rtl8192_phy_SetRFReg(struct net_device *dev, 278 enum rf90_radio_path_e e_rfpath, 279 u32 reg_addr, u32 bitmask, u32 data) 280 { 281 struct r8192_priv *priv = ieee80211_priv(dev); 282 u32 reg, bitshift; 283 284 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath)) 285 return; 286 287 if (priv->Rf_Mode == RF_OP_By_FW) { 288 if (bitmask != bMask12Bits) { 289 /* RF data is 12 bits only */ 290 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); 291 bitshift = ffs(bitmask) - 1; 292 reg &= ~bitmask; 293 reg |= data << bitshift; 294 295 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, reg); 296 } else { 297 phy_FwRFSerialWrite(dev, e_rfpath, reg_addr, data); 298 } 299 300 udelay(200); 301 302 } else { 303 if (bitmask != bMask12Bits) { 304 /* RF data is 12 bits only */ 305 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); 306 bitshift = ffs(bitmask) - 1; 307 reg &= ~bitmask; 308 reg |= data << bitshift; 309 310 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, reg); 311 } else { 312 rtl8192_phy_RFSerialWrite(dev, e_rfpath, reg_addr, data); 313 } 314 } 315 } 316 317 /****************************************************************************** 318 * function: This function reads specific bits from RF register 319 * input: net_device *dev 320 * u32 reg_addr //target addr to be readback 321 * u32 bitmask //taget bit pos to be readback 322 * output: none 323 * return: u32 data //the readback register value 324 * notice: 325 *****************************************************************************/ 326 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, 327 enum rf90_radio_path_e e_rfpath, 328 u32 reg_addr, u32 bitmask) 329 { 330 u32 reg, bitshift; 331 struct r8192_priv *priv = ieee80211_priv(dev); 332 333 334 if (!rtl8192_phy_CheckIsLegalRFPath(dev, e_rfpath)) 335 return 0; 336 if (priv->Rf_Mode == RF_OP_By_FW) { 337 reg = phy_FwRFSerialRead(dev, e_rfpath, reg_addr); 338 udelay(200); 339 } else { 340 reg = rtl8192_phy_RFSerialRead(dev, e_rfpath, reg_addr); 341 } 342 bitshift = ffs(bitmask) - 1; 343 reg = (reg & bitmask) >> bitshift; 344 return reg; 345 346 } 347 348 /****************************************************************************** 349 * function: We support firmware to execute RF-R/W. 350 * input: net_device *dev 351 * rf90_radio_path_e e_rfpath 352 * u32 offset 353 * output: none 354 * return: u32 355 * notice: 356 ****************************************************************************/ 357 static u32 phy_FwRFSerialRead(struct net_device *dev, 358 enum rf90_radio_path_e e_rfpath, 359 u32 offset) 360 { 361 u32 reg = 0; 362 u32 data = 0; 363 u8 time = 0; 364 u32 tmp; 365 366 /* Firmware RF Write control. 367 * We can not execute the scheme in the initial step. 368 * Otherwise, RF-R/W will waste much time. 369 * This is only for site survey. 370 */ 371 /* 1. Read operation need not insert data. bit 0-11 */ 372 /* 2. Write RF register address. bit 12-19 */ 373 data |= ((offset&0xFF)<<12); 374 /* 3. Write RF path. bit 20-21 */ 375 data |= ((e_rfpath&0x3)<<20); 376 /* 4. Set RF read indicator. bit 22=0 */ 377 /* 5. Trigger Fw to operate the command. bit 31 */ 378 data |= 0x80000000; 379 /* 6. We can not execute read operation if bit 31 is 1. */ 380 read_nic_dword(dev, QPNR, &tmp); 381 while (tmp & 0x80000000) { 382 /* If FW can not finish RF-R/W for more than ?? times. 383 * We must reset FW. 384 */ 385 if (time++ < 100) { 386 udelay(10); 387 read_nic_dword(dev, QPNR, &tmp); 388 } else { 389 break; 390 } 391 } 392 /* 7. Execute read operation. */ 393 write_nic_dword(dev, QPNR, data); 394 /* 8. Check if firmware send back RF content. */ 395 read_nic_dword(dev, QPNR, &tmp); 396 while (tmp & 0x80000000) { 397 /* If FW can not finish RF-R/W for more than ?? times. 398 * We must reset FW. 399 */ 400 if (time++ < 100) { 401 udelay(10); 402 read_nic_dword(dev, QPNR, &tmp); 403 } else { 404 return 0; 405 } 406 } 407 read_nic_dword(dev, RF_DATA, ®); 408 409 return reg; 410 } 411 412 /****************************************************************************** 413 * function: We support firmware to execute RF-R/W. 414 * input: net_device *dev 415 * rf90_radio_path_e e_rfpath 416 * u32 offset 417 * u32 data 418 * output: none 419 * return: none 420 * notice: 421 ****************************************************************************/ 422 static void phy_FwRFSerialWrite(struct net_device *dev, 423 enum rf90_radio_path_e e_rfpath, 424 u32 offset, u32 data) 425 { 426 u8 time = 0; 427 u32 tmp; 428 429 /* Firmware RF Write control. 430 * We can not execute the scheme in the initial step. 431 * Otherwise, RF-R/W will waste much time. 432 * This is only for site survey. 433 */ 434 435 /* 1. Set driver write bit and 12 bit data. bit 0-11 */ 436 /* 2. Write RF register address. bit 12-19 */ 437 data |= ((offset&0xFF)<<12); 438 /* 3. Write RF path. bit 20-21 */ 439 data |= ((e_rfpath&0x3)<<20); 440 /* 4. Set RF write indicator. bit 22=1 */ 441 data |= 0x400000; 442 /* 5. Trigger Fw to operate the command. bit 31=1 */ 443 data |= 0x80000000; 444 445 /* 6. Write operation. We can not write if bit 31 is 1. */ 446 read_nic_dword(dev, QPNR, &tmp); 447 while (tmp & 0x80000000) { 448 /* If FW can not finish RF-R/W for more than ?? times. 449 * We must reset FW. 450 */ 451 if (time++ < 100) { 452 udelay(10); 453 read_nic_dword(dev, QPNR, &tmp); 454 } else { 455 break; 456 } 457 } 458 /* 7. No matter check bit. We always force the write. 459 * Because FW will not accept the command. 460 */ 461 write_nic_dword(dev, QPNR, data); 462 /* According to test, we must delay 20us to wait firmware 463 * to finish RF write operation. 464 */ 465 /* We support delay in firmware side now. */ 466 } 467 468 /****************************************************************************** 469 * function: This function reads BB parameters from header file we generate, 470 * and do register read/write 471 * input: net_device *dev 472 * output: none 473 * return: none 474 * notice: BB parameters may change all the time, so please make 475 * sure it has been synced with the newest. 476 *****************************************************************************/ 477 void rtl8192_phy_configmac(struct net_device *dev) 478 { 479 u32 dwArrayLen = 0, i; 480 u32 *pdwArray = NULL; 481 struct r8192_priv *priv = ieee80211_priv(dev); 482 483 if (priv->btxpowerdata_readfromEEPORM) { 484 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); 485 dwArrayLen = MACPHY_Array_PGLength; 486 pdwArray = Rtl8192UsbMACPHY_Array_PG; 487 488 } else { 489 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array\n"); 490 dwArrayLen = MACPHY_ArrayLength; 491 pdwArray = rtl819XMACPHY_Array; 492 } 493 for (i = 0; i < dwArrayLen; i = i+3) { 494 if (pdwArray[i] == 0x318) 495 pdwArray[i+2] = 0x00000800; 496 497 RT_TRACE(COMP_DBG, 498 "Rtl8190MACPHY_Array[0]=%x Rtl8190MACPHY_Array[1]=%x Rtl8190MACPHY_Array[2]=%x\n", 499 pdwArray[i], pdwArray[i+1], pdwArray[i+2]); 500 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], 501 pdwArray[i+2]); 502 } 503 } 504 505 /****************************************************************************** 506 * function: This function does dirty work 507 * input: net_device *dev 508 * u8 ConfigType 509 * output: none 510 * return: none 511 * notice: BB parameters may change all the time, so please make 512 * sure it has been synced with the newest. 513 *****************************************************************************/ 514 static void rtl8192_phyConfigBB(struct net_device *dev, 515 enum baseband_config_type ConfigType) 516 { 517 u32 i; 518 519 #ifdef TO_DO_LIST 520 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL; 521 522 if (Adapter->bInHctTest) { 523 PHY_REGArrayLen = PHY_REGArrayLengthDTM; 524 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM; 525 Rtl8190PHY_REGArray_Table = Rtl819XPHY_REGArrayDTM; 526 Rtl8190AGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM; 527 } 528 #endif 529 if (ConfigType == BASEBAND_CONFIG_PHY_REG) { 530 for (i = 0; i < PHY_REG_1T2RArrayLength; i += 2) { 531 rtl8192_setBBreg(dev, Rtl8192UsbPHY_REG_1T2RArray[i], 532 bMaskDWord, 533 Rtl8192UsbPHY_REG_1T2RArray[i+1]); 534 RT_TRACE(COMP_DBG, 535 "i: %x, Rtl819xUsbPHY_REGArray[0]=%x Rtl819xUsbPHY_REGArray[1]=%x\n", 536 i, Rtl8192UsbPHY_REG_1T2RArray[i], 537 Rtl8192UsbPHY_REG_1T2RArray[i+1]); 538 } 539 } else if (ConfigType == BASEBAND_CONFIG_AGC_TAB) { 540 for (i = 0; i < AGCTAB_ArrayLength; i += 2) { 541 rtl8192_setBBreg(dev, Rtl8192UsbAGCTAB_Array[i], 542 bMaskDWord, Rtl8192UsbAGCTAB_Array[i+1]); 543 RT_TRACE(COMP_DBG, 544 "i: %x, Rtl8192UsbAGCTAB_Array[0]=%x Rtl8192UsbAGCTAB_Array[1]=%x\n", 545 i, Rtl8192UsbAGCTAB_Array[i], 546 Rtl8192UsbAGCTAB_Array[i+1]); 547 } 548 } 549 } 550 551 /****************************************************************************** 552 * function: This function initializes Register definition offset for 553 * Radio Path A/B/C/D 554 * input: net_device *dev 555 * output: none 556 * return: none 557 * notice: Initialization value here is constant and it should never 558 * be changed 559 *****************************************************************************/ 560 static void rtl8192_InitBBRFRegDef(struct net_device *dev) 561 { 562 struct r8192_priv *priv = ieee80211_priv(dev); 563 564 /* RF Interface Software Control */ 565 /* 16 LSBs if read 32-bit from 0x870 */ 566 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; 567 /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */ 568 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; 569 /* 16 LSBs if read 32-bit from 0x874 */ 570 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; 571 /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */ 572 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW; 573 574 /* RF Interface Readback Value */ 575 /* 16 LSBs if read 32-bit from 0x8E0 */ 576 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; 577 /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */ 578 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB; 579 /* 16 LSBs if read 32-bit from 0x8E4 */ 580 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB; 581 /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */ 582 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB; 583 584 /* RF Interface Output (and Enable) */ 585 /* 16 LSBs if read 32-bit from 0x860 */ 586 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; 587 /* 16 LSBs if read 32-bit from 0x864 */ 588 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; 589 /* 16 LSBs if read 32-bit from 0x868 */ 590 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE; 591 /* 16 LSBs if read 32-bit from 0x86C */ 592 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE; 593 594 /* RF Interface (Output and) Enable */ 595 /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */ 596 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; 597 /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */ 598 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; 599 /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */ 600 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE; 601 /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */ 602 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE; 603 604 /* Addr of LSSI. Write RF register by driver */ 605 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; 606 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter; 607 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter; 608 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter; 609 610 /* RF parameter */ 611 /* BB Band Select */ 612 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; 613 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter; 614 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter; 615 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter; 616 617 /* Tx AGC Gain Stage (same for all path. Should we remove this?) */ 618 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; 619 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; 620 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; 621 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; 622 623 /* Tranceiver A~D HSSI Parameter-1 */ 624 /* wire control parameter1 */ 625 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; 626 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; 627 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; 628 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; 629 630 /* Tranceiver A~D HSSI Parameter-2 */ 631 /* wire control parameter2 */ 632 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; 633 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; 634 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; 635 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; 636 637 /* RF Switch Control */ 638 /* TR/Ant switch control */ 639 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; 640 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl; 641 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl; 642 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl; 643 644 /* AGC control 1 */ 645 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1; 646 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1; 647 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1; 648 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1; 649 650 /* AGC control 2 */ 651 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2; 652 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2; 653 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2; 654 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2; 655 656 /* RX AFE control 1 */ 657 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance; 658 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance; 659 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance; 660 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance; 661 662 /* RX AFE control 1 */ 663 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE; 664 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE; 665 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE; 666 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE; 667 668 /* Tx AFE control 1 */ 669 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance; 670 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance; 671 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance; 672 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance; 673 674 /* Tx AFE control 2 */ 675 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE; 676 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE; 677 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE; 678 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE; 679 680 /* Tranceiver LSSI Readback */ 681 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack; 682 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack; 683 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack; 684 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; 685 } 686 687 /****************************************************************************** 688 * function: This function is to write register and then readback to make 689 * sure whether BB and RF is OK 690 * input: net_device *dev 691 * hw90_block_e CheckBlock 692 * rf90_radio_path_e e_rfpath //only used when checkblock is 693 * //HW90_BLOCK_RF 694 * output: none 695 * return: return whether BB and RF is ok (0:OK, 1:Fail) 696 * notice: This function may be removed in the ASIC 697 ******************************************************************************/ 698 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, enum hw90_block_e CheckBlock, 699 enum rf90_radio_path_e e_rfpath) 700 { 701 u8 ret = 0; 702 u32 i, CheckTimes = 4, reg = 0; 703 u32 WriteAddr[4]; 704 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; 705 706 /* Initialize register address offset to be checked */ 707 WriteAddr[HW90_BLOCK_MAC] = 0x100; 708 WriteAddr[HW90_BLOCK_PHY0] = 0x900; 709 WriteAddr[HW90_BLOCK_PHY1] = 0x800; 710 WriteAddr[HW90_BLOCK_RF] = 0x3; 711 RT_TRACE(COMP_PHY, "%s(), CheckBlock: %d\n", __func__, CheckBlock); 712 for (i = 0; i < CheckTimes; i++) { 713 714 /* Write data to register and readback */ 715 switch (CheckBlock) { 716 case HW90_BLOCK_MAC: 717 RT_TRACE(COMP_ERR, 718 "PHY_CheckBBRFOK(): Never Write 0x100 here!\n"); 719 break; 720 721 case HW90_BLOCK_PHY0: 722 case HW90_BLOCK_PHY1: 723 write_nic_dword(dev, WriteAddr[CheckBlock], 724 WriteData[i]); 725 read_nic_dword(dev, WriteAddr[CheckBlock], ®); 726 break; 727 728 case HW90_BLOCK_RF: 729 WriteData[i] &= 0xfff; 730 rtl8192_phy_SetRFReg(dev, e_rfpath, 731 WriteAddr[HW90_BLOCK_RF], 732 bMask12Bits, WriteData[i]); 733 /* TODO: we should not delay for such a long time. 734 * Ask SD3 735 */ 736 usleep_range(1000, 1000); 737 reg = rtl8192_phy_QueryRFReg(dev, e_rfpath, 738 WriteAddr[HW90_BLOCK_RF], 739 bMask12Bits); 740 usleep_range(1000, 1000); 741 break; 742 743 default: 744 ret = 1; 745 break; 746 } 747 748 749 /* Check whether readback data is correct */ 750 if (reg != WriteData[i]) { 751 RT_TRACE((COMP_PHY|COMP_ERR), 752 "error reg: %x, WriteData: %x\n", 753 reg, WriteData[i]); 754 ret = 1; 755 break; 756 } 757 } 758 759 return ret; 760 } 761 762 /****************************************************************************** 763 * function: This function initializes BB&RF 764 * input: net_device *dev 765 * output: none 766 * return: none 767 * notice: Initialization value may change all the time, so please make 768 * sure it has been synced with the newest. 769 ******************************************************************************/ 770 static void rtl8192_BB_Config_ParaFile(struct net_device *dev) 771 { 772 struct r8192_priv *priv = ieee80211_priv(dev); 773 u8 reg_u8 = 0, eCheckItem = 0, status = 0; 774 u32 reg_u32 = 0; 775 776 /************************************** 777 * <1> Initialize BaseBand 778 *************************************/ 779 780 /* --set BB Global Reset-- */ 781 read_nic_byte(dev, BB_GLOBAL_RESET, ®_u8); 782 write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT)); 783 mdelay(50); 784 /* ---set BB reset Active--- */ 785 read_nic_dword(dev, CPU_GEN, ®_u32); 786 write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST))); 787 788 /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */ 789 /* TODO: this function should be removed on ASIC */ 790 for (eCheckItem = (enum hw90_block_e)HW90_BLOCK_PHY0; 791 eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) { 792 /* don't care RF path */ 793 status = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block_e)eCheckItem, 794 (enum rf90_radio_path_e)0); 795 if (status != 0) { 796 RT_TRACE((COMP_ERR | COMP_PHY), 797 "phy_rf8256_config(): Check PHY%d Fail!!\n", 798 eCheckItem-1); 799 return; 800 } 801 } 802 /* ---- Set CCK and OFDM Block "OFF"---- */ 803 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); 804 /* ----BB Register Initilazation---- */ 805 /* ==m==>Set PHY REG From Header<==m== */ 806 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_PHY_REG); 807 808 /* ----Set BB reset de-Active---- */ 809 read_nic_dword(dev, CPU_GEN, ®_u32); 810 write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST)); 811 812 /* ----BB AGC table Initialization---- */ 813 /* ==m==>Set PHY REG From Header<==m== */ 814 rtl8192_phyConfigBB(dev, BASEBAND_CONFIG_AGC_TAB); 815 816 /* ----Enable XSTAL ---- */ 817 write_nic_byte_E(dev, 0x5e, 0x00); 818 if (priv->card_8192_version == VERSION_819XU_A) { 819 /* Antenna gain offset from B/C/D to A */ 820 reg_u32 = priv->AntennaTxPwDiff[1]<<4 | 821 priv->AntennaTxPwDiff[0]; 822 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), 823 reg_u32); 824 825 /* XSTALLCap */ 826 reg_u32 = priv->CrystalCap & 0xf; 827 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, 828 reg_u32); 829 } 830 831 /* Check if the CCK HighPower is turned ON. 832 * This is used to calculate PWDB. 833 */ 834 priv->bCckHighPower = (u8)rtl8192_QueryBBReg(dev, 835 rFPGA0_XA_HSSIParameter2, 836 0x200); 837 } 838 839 /****************************************************************************** 840 * function: This function initializes BB&RF 841 * input: net_device *dev 842 * output: none 843 * return: none 844 * notice: Initialization value may change all the time, so please make 845 * sure it has been synced with the newest. 846 *****************************************************************************/ 847 void rtl8192_BBConfig(struct net_device *dev) 848 { 849 rtl8192_InitBBRFRegDef(dev); 850 /* config BB&RF. As hardCode based initialization has not been well 851 * implemented, so use file first. 852 * FIXME: should implement it for hardcode? 853 */ 854 rtl8192_BB_Config_ParaFile(dev); 855 } 856 857 858 /****************************************************************************** 859 * function: This function obtains the initialization value of Tx power Level 860 * offset 861 * input: net_device *dev 862 * output: none 863 * return: none 864 *****************************************************************************/ 865 void rtl8192_phy_getTxPower(struct net_device *dev) 866 { 867 struct r8192_priv *priv = ieee80211_priv(dev); 868 u8 tmp; 869 870 read_nic_dword(dev, rTxAGC_Rate18_06, 871 &priv->MCSTxPowerLevelOriginalOffset[0]); 872 read_nic_dword(dev, rTxAGC_Rate54_24, 873 &priv->MCSTxPowerLevelOriginalOffset[1]); 874 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00, 875 &priv->MCSTxPowerLevelOriginalOffset[2]); 876 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04, 877 &priv->MCSTxPowerLevelOriginalOffset[3]); 878 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, 879 &priv->MCSTxPowerLevelOriginalOffset[4]); 880 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, 881 &priv->MCSTxPowerLevelOriginalOffset[5]); 882 883 /* Read rx initial gain */ 884 read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]); 885 read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]); 886 read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]); 887 read_nic_byte(dev, rOFDM0_XDAGCCore1, &priv->DefaultInitialGain[3]); 888 RT_TRACE(COMP_INIT, 889 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x)\n", 890 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], 891 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); 892 893 /* Read framesync */ 894 read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync); 895 read_nic_byte(dev, rOFDM0_RxDetector2, &tmp); 896 priv->framesyncC34 = tmp; 897 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n", 898 rOFDM0_RxDetector3, priv->framesync); 899 900 /* Read SIFS (save the value read fome MACPHY_REG.txt) */ 901 read_nic_word(dev, SIFS, &priv->SifsTime); 902 } 903 904 /****************************************************************************** 905 * function: This function sets the initialization value of Tx power Level 906 * offset 907 * input: net_device *dev 908 * u8 channel 909 * output: none 910 * return: none 911 ******************************************************************************/ 912 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel) 913 { 914 struct r8192_priv *priv = ieee80211_priv(dev); 915 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 916 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 917 918 switch (priv->rf_chip) { 919 case RF_8256: 920 /* need further implement */ 921 phy_set_rf8256_cck_tx_power(dev, powerlevel); 922 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G); 923 break; 924 default: 925 RT_TRACE((COMP_PHY|COMP_ERR), 926 "error RF chipID(8225 or 8258) in function %s()\n", 927 __func__); 928 break; 929 } 930 } 931 932 /****************************************************************************** 933 * function: This function checks Rf chip to do RF config 934 * input: net_device *dev 935 * output: none 936 * return: only 8256 is supported 937 ******************************************************************************/ 938 void rtl8192_phy_RFConfig(struct net_device *dev) 939 { 940 struct r8192_priv *priv = ieee80211_priv(dev); 941 942 switch (priv->rf_chip) { 943 case RF_8256: 944 phy_rf8256_config(dev); 945 break; 946 default: 947 RT_TRACE(COMP_ERR, "error chip id\n"); 948 break; 949 } 950 } 951 952 /****************************************************************************** 953 * function: This function updates Initial gain 954 * input: net_device *dev 955 * output: none 956 * return: As Windows has not implemented this, wait for complement 957 ******************************************************************************/ 958 void rtl8192_phy_updateInitGain(struct net_device *dev) 959 { 960 } 961 962 /****************************************************************************** 963 * function: This function read RF parameters from general head file, 964 * and do RF 3-wire 965 * input: net_device *dev 966 * rf90_radio_path_e e_rfpath 967 * output: none 968 * return: return code show if RF configuration is successful(0:pass, 1:fail) 969 * notice: Delay may be required for RF configuration 970 *****************************************************************************/ 971 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev, 972 enum rf90_radio_path_e e_rfpath) 973 { 974 975 int i; 976 977 switch (e_rfpath) { 978 case RF90_PATH_A: 979 for (i = 0; i < RadioA_ArrayLength; i = i+2) { 980 981 if (Rtl8192UsbRadioA_Array[i] == 0xfe) { 982 mdelay(100); 983 continue; 984 } 985 rtl8192_phy_SetRFReg(dev, e_rfpath, 986 Rtl8192UsbRadioA_Array[i], 987 bMask12Bits, 988 Rtl8192UsbRadioA_Array[i+1]); 989 mdelay(1); 990 991 } 992 break; 993 case RF90_PATH_B: 994 for (i = 0; i < RadioB_ArrayLength; i = i+2) { 995 996 if (Rtl8192UsbRadioB_Array[i] == 0xfe) { 997 mdelay(100); 998 continue; 999 } 1000 rtl8192_phy_SetRFReg(dev, e_rfpath, 1001 Rtl8192UsbRadioB_Array[i], 1002 bMask12Bits, 1003 Rtl8192UsbRadioB_Array[i+1]); 1004 mdelay(1); 1005 1006 } 1007 break; 1008 case RF90_PATH_C: 1009 for (i = 0; i < RadioC_ArrayLength; i = i+2) { 1010 1011 if (Rtl8192UsbRadioC_Array[i] == 0xfe) { 1012 mdelay(100); 1013 continue; 1014 } 1015 rtl8192_phy_SetRFReg(dev, e_rfpath, 1016 Rtl8192UsbRadioC_Array[i], 1017 bMask12Bits, 1018 Rtl8192UsbRadioC_Array[i+1]); 1019 mdelay(1); 1020 1021 } 1022 break; 1023 case RF90_PATH_D: 1024 for (i = 0; i < RadioD_ArrayLength; i = i+2) { 1025 1026 if (Rtl8192UsbRadioD_Array[i] == 0xfe) { 1027 mdelay(100); 1028 continue; 1029 } 1030 rtl8192_phy_SetRFReg(dev, e_rfpath, 1031 Rtl8192UsbRadioD_Array[i], 1032 bMask12Bits, 1033 Rtl8192UsbRadioD_Array[i+1]); 1034 mdelay(1); 1035 1036 } 1037 break; 1038 default: 1039 break; 1040 } 1041 1042 return 0; 1043 1044 } 1045 1046 /****************************************************************************** 1047 * function: This function sets Tx Power of the channel 1048 * input: net_device *dev 1049 * u8 channel 1050 * output: none 1051 * return: none 1052 * notice: 1053 ******************************************************************************/ 1054 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) 1055 { 1056 struct r8192_priv *priv = ieee80211_priv(dev); 1057 u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; 1058 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; 1059 1060 switch (priv->rf_chip) { 1061 case RF_8225: 1062 #ifdef TO_DO_LIST 1063 PHY_SetRF8225CckTxPower(Adapter, powerlevel); 1064 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G); 1065 #endif 1066 break; 1067 1068 case RF_8256: 1069 phy_set_rf8256_cck_tx_power(dev, powerlevel); 1070 phy_set_rf8256_ofdm_tx_power(dev, powerlevelOFDM24G); 1071 break; 1072 1073 case RF_8258: 1074 break; 1075 default: 1076 RT_TRACE(COMP_ERR, "unknown rf chip ID in %s()\n", __func__); 1077 break; 1078 } 1079 } 1080 1081 /****************************************************************************** 1082 * function: This function sets RF state on or off 1083 * input: net_device *dev 1084 * RT_RF_POWER_STATE eRFPowerState //Power State to set 1085 * output: none 1086 * return: none 1087 * notice: 1088 *****************************************************************************/ 1089 bool rtl8192_SetRFPowerState(struct net_device *dev, 1090 RT_RF_POWER_STATE eRFPowerState) 1091 { 1092 bool bResult = true; 1093 struct r8192_priv *priv = ieee80211_priv(dev); 1094 1095 if (eRFPowerState == priv->ieee80211->eRFPowerState) 1096 return false; 1097 1098 if (priv->SetRFPowerStateInProgress) 1099 return false; 1100 1101 priv->SetRFPowerStateInProgress = true; 1102 1103 switch (priv->rf_chip) { 1104 case RF_8256: 1105 switch (eRFPowerState) { 1106 case eRfOn: 1107 /* RF-A, RF-B */ 1108 /* enable RF-Chip A/B - 0x860[4] */ 1109 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1110 0x1); 1111 /* analog to digital on - 0x88c[9:8] */ 1112 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 1113 0x3); 1114 /* digital to analog on - 0x880[4:3] */ 1115 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1116 0x3); 1117 /* rx antenna on - 0xc04[1:0] */ 1118 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); 1119 /* rx antenna on - 0xd04[1:0] */ 1120 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); 1121 /* analog to digital part2 on - 0x880[6:5] */ 1122 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1123 0x3); 1124 1125 break; 1126 1127 case eRfSleep: 1128 1129 break; 1130 1131 case eRfOff: 1132 /* RF-A, RF-B */ 1133 /* disable RF-Chip A/B - 0x860[4] */ 1134 rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT(4), 1135 0x0); 1136 /* analog to digital off, for power save */ 1137 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 1138 0x0); /* 0x88c[11:8] */ 1139 /* digital to analog off, for power save - 0x880[4:3] */ 1140 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 1141 0x0); 1142 /* rx antenna off - 0xc04[3:0] */ 1143 rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); 1144 /* rx antenna off - 0xd04[3:0] */ 1145 rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); 1146 /* analog to digital part2 off, for power save */ 1147 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 1148 0x0); /* 0x880[6:5] */ 1149 1150 break; 1151 1152 default: 1153 bResult = false; 1154 RT_TRACE(COMP_ERR, "%s(): unknown state to set: 0x%X\n", 1155 __func__, eRFPowerState); 1156 break; 1157 } 1158 break; 1159 default: 1160 RT_TRACE(COMP_ERR, "Not support rf_chip(%x)\n", priv->rf_chip); 1161 break; 1162 } 1163 #ifdef TO_DO_LIST 1164 if (bResult) { 1165 /* Update current RF state variable. */ 1166 pHalData->eRFPowerState = eRFPowerState; 1167 switch (pHalData->RFChipID) { 1168 case RF_8256: 1169 switch (pHalData->eRFPowerState) { 1170 case eRfOff: 1171 /* If Rf off reason is from IPS, 1172 * LED should blink with no link 1173 */ 1174 if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS) 1175 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); 1176 else 1177 /* Turn off LED if RF is not ON. */ 1178 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF); 1179 break; 1180 1181 case eRfOn: 1182 /* Turn on RF we are still linked, which might 1183 * happen when we quickly turn off and on HW RF. 1184 */ 1185 if (pMgntInfo->bMediaConnect) 1186 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK); 1187 else 1188 /* Turn off LED if RF is not ON. */ 1189 Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK); 1190 break; 1191 1192 default: 1193 break; 1194 } 1195 break; 1196 1197 default: 1198 RT_TRACE(COMP_RF, DBG_LOUD, "%s(): Unknown RF type\n", 1199 __func__); 1200 break; 1201 } 1202 1203 } 1204 #endif 1205 priv->SetRFPowerStateInProgress = false; 1206 1207 return bResult; 1208 } 1209 1210 /****************************************************************************** 1211 * function: This function sets command table variable (struct sw_chnl_cmd). 1212 * input: sw_chnl_cmd *CmdTable //table to be set 1213 * u32 CmdTableIdx //variable index in table to be set 1214 * u32 CmdTableSz //table size 1215 * switch_chan_cmd_id CmdID //command ID to set 1216 * u32 Para1 1217 * u32 Para2 1218 * u32 msDelay 1219 * output: 1220 * return: true if finished, false otherwise 1221 * notice: 1222 ******************************************************************************/ 1223 static u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx, 1224 u32 CmdTableSz, enum switch_chan_cmd_id CmdID, 1225 u32 Para1, u32 Para2, u32 msDelay) 1226 { 1227 struct sw_chnl_cmd *pCmd; 1228 1229 if (CmdTable == NULL) { 1230 RT_TRACE(COMP_ERR, "%s(): CmdTable cannot be NULL\n", __func__); 1231 return false; 1232 } 1233 if (CmdTableIdx >= CmdTableSz) { 1234 RT_TRACE(COMP_ERR, "%s(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", 1235 __func__, CmdTableIdx, CmdTableSz); 1236 return false; 1237 } 1238 1239 pCmd = CmdTable + CmdTableIdx; 1240 pCmd->cmd_id = CmdID; 1241 pCmd->para_1 = Para1; 1242 pCmd->para_2 = Para2; 1243 pCmd->ms_delay = msDelay; 1244 1245 return true; 1246 } 1247 1248 /****************************************************************************** 1249 * function: This function sets channel step by step 1250 * input: net_device *dev 1251 * u8 channel 1252 * u8 *stage //3 stages 1253 * u8 *step 1254 * u32 *delay //whether need to delay 1255 * output: store new stage, step and delay for next step 1256 * (combine with function above) 1257 * return: true if finished, false otherwise 1258 * notice: Wait for simpler function to replace it 1259 *****************************************************************************/ 1260 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, 1261 u8 *stage, u8 *step, u32 *delay) 1262 { 1263 struct r8192_priv *priv = ieee80211_priv(dev); 1264 struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; 1265 u32 PreCommonCmdCnt; 1266 struct sw_chnl_cmd PostCommonCmd[MAX_POSTCMD_CNT]; 1267 u32 PostCommonCmdCnt; 1268 struct sw_chnl_cmd RfDependCmd[MAX_RFDEPENDCMD_CNT]; 1269 u32 RfDependCmdCnt; 1270 struct sw_chnl_cmd *CurrentCmd = NULL; 1271 u8 e_rfpath; 1272 1273 RT_TRACE(COMP_CH, "%s() stage: %d, step: %d, channel: %d\n", 1274 __func__, *stage, *step, channel); 1275 if (!is_legal_channel(priv->ieee80211, channel)) { 1276 RT_TRACE(COMP_ERR, "set to illegal channel: %d\n", channel); 1277 /* return true to tell upper caller function this channel 1278 * setting is finished! Or it will in while loop. 1279 */ 1280 return true; 1281 } 1282 /* FIXME: need to check whether channel is legal or not here */ 1283 1284 1285 /* <1> Fill up pre common command. */ 1286 PreCommonCmdCnt = 0; 1287 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1288 MAX_PRECMD_CNT, CMD_ID_SET_TX_PWR_LEVEL, 1289 0, 0, 0); 1290 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, 1291 MAX_PRECMD_CNT, CMD_ID_END, 0, 0, 0); 1292 1293 /* <2> Fill up post common command. */ 1294 PostCommonCmdCnt = 0; 1295 1296 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, 1297 MAX_POSTCMD_CNT, CMD_ID_END, 0, 0, 0); 1298 1299 /* <3> Fill up RF dependent command. */ 1300 RfDependCmdCnt = 0; 1301 switch (priv->rf_chip) { 1302 case RF_8225: 1303 if (!(channel >= 1 && channel <= 14)) { 1304 RT_TRACE(COMP_ERR, 1305 "illegal channel for Zebra 8225: %d\n", 1306 channel); 1307 return true; 1308 } 1309 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1310 MAX_RFDEPENDCMD_CNT, 1311 CMD_ID_RF_WRITE_REG, 1312 rZebra1_Channel, 1313 RF_CHANNEL_TABLE_ZEBRA[channel], 1314 10); 1315 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1316 MAX_RFDEPENDCMD_CNT, 1317 CMD_ID_END, 0, 0, 0); 1318 break; 1319 1320 case RF_8256: 1321 /* TEST!! This is not the table for 8256!! */ 1322 if (!(channel >= 1 && channel <= 14)) { 1323 RT_TRACE(COMP_ERR, 1324 "illegal channel for Zebra 8256: %d\n", 1325 channel); 1326 return true; 1327 } 1328 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1329 MAX_RFDEPENDCMD_CNT, 1330 CMD_ID_RF_WRITE_REG, 1331 rZebra1_Channel, channel, 10); 1332 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, 1333 MAX_RFDEPENDCMD_CNT, 1334 CMD_ID_END, 0, 0, 0); 1335 break; 1336 1337 case RF_8258: 1338 break; 1339 1340 default: 1341 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1342 return true; 1343 } 1344 1345 1346 do { 1347 switch (*stage) { 1348 case 0: 1349 CurrentCmd = &PreCommonCmd[*step]; 1350 break; 1351 case 1: 1352 CurrentCmd = &RfDependCmd[*step]; 1353 break; 1354 case 2: 1355 CurrentCmd = &PostCommonCmd[*step]; 1356 break; 1357 } 1358 1359 if (CurrentCmd->cmd_id == CMD_ID_END) { 1360 if ((*stage) == 2) { 1361 (*delay) = CurrentCmd->ms_delay; 1362 return true; 1363 } 1364 (*stage)++; 1365 (*step) = 0; 1366 continue; 1367 } 1368 1369 switch (CurrentCmd->cmd_id) { 1370 case CMD_ID_SET_TX_PWR_LEVEL: 1371 if (priv->card_8192_version == VERSION_819XU_A) 1372 /* consider it later! */ 1373 rtl8192_SetTxPowerLevel(dev, channel); 1374 break; 1375 case CMD_ID_WRITE_PORT_ULONG: 1376 write_nic_dword(dev, CurrentCmd->para_1, 1377 CurrentCmd->para_2); 1378 break; 1379 case CMD_ID_WRITE_PORT_USHORT: 1380 write_nic_word(dev, CurrentCmd->para_1, 1381 (u16)CurrentCmd->para_2); 1382 break; 1383 case CMD_ID_WRITE_PORT_UCHAR: 1384 write_nic_byte(dev, CurrentCmd->para_1, 1385 (u8)CurrentCmd->para_2); 1386 break; 1387 case CMD_ID_RF_WRITE_REG: 1388 for (e_rfpath = 0; e_rfpath < RF90_PATH_MAX; e_rfpath++) { 1389 rtl8192_phy_SetRFReg(dev, 1390 (enum rf90_radio_path_e)e_rfpath, 1391 CurrentCmd->para_1, 1392 bZebra1_ChannelNum, 1393 CurrentCmd->para_2); 1394 } 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 break; 1401 } while (true); 1402 1403 (*delay) = CurrentCmd->ms_delay; 1404 (*step)++; 1405 return false; 1406 } 1407 1408 /****************************************************************************** 1409 * function: This function does actually set channel work 1410 * input: net_device *dev 1411 * u8 channel 1412 * output: none 1413 * return: none 1414 * notice: We should not call this function directly 1415 *****************************************************************************/ 1416 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) 1417 { 1418 struct r8192_priv *priv = ieee80211_priv(dev); 1419 u32 delay = 0; 1420 1421 while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage, 1422 &priv->SwChnlStep, &delay)) { 1423 if (!priv->up) 1424 break; 1425 } 1426 } 1427 1428 /****************************************************************************** 1429 * function: Callback routine of the work item for switch channel. 1430 * input: net_device *dev 1431 * 1432 * output: none 1433 * return: none 1434 *****************************************************************************/ 1435 void rtl8192_SwChnl_WorkItem(struct net_device *dev) 1436 { 1437 1438 struct r8192_priv *priv = ieee80211_priv(dev); 1439 1440 RT_TRACE(COMP_CH, "==> SwChnlCallback819xUsbWorkItem(), chan:%d\n", 1441 priv->chan); 1442 1443 1444 rtl8192_phy_FinishSwChnlNow(dev, priv->chan); 1445 1446 RT_TRACE(COMP_CH, "<== SwChnlCallback819xUsbWorkItem()\n"); 1447 } 1448 1449 /****************************************************************************** 1450 * function: This function scheduled actual work item to set channel 1451 * input: net_device *dev 1452 * u8 channel //channel to set 1453 * output: none 1454 * return: return code show if workitem is scheduled (1:pass, 0:fail) 1455 * notice: Delay may be required for RF configuration 1456 ******************************************************************************/ 1457 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel) 1458 { 1459 struct r8192_priv *priv = ieee80211_priv(dev); 1460 1461 RT_TRACE(COMP_CH, "%s(), SwChnlInProgress: %d\n", __func__, 1462 priv->SwChnlInProgress); 1463 if (!priv->up) 1464 return false; 1465 if (priv->SwChnlInProgress) 1466 return false; 1467 1468 /* -------------------------------------------- */ 1469 switch (priv->ieee80211->mode) { 1470 case WIRELESS_MODE_A: 1471 case WIRELESS_MODE_N_5G: 1472 if (channel <= 14) { 1473 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14\n"); 1474 return false; 1475 } 1476 break; 1477 case WIRELESS_MODE_B: 1478 if (channel > 14) { 1479 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14\n"); 1480 return false; 1481 } 1482 break; 1483 case WIRELESS_MODE_G: 1484 case WIRELESS_MODE_N_24G: 1485 if (channel > 14) { 1486 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14\n"); 1487 return false; 1488 } 1489 break; 1490 } 1491 /* -------------------------------------------- */ 1492 1493 priv->SwChnlInProgress = true; 1494 if (channel == 0) 1495 channel = 1; 1496 1497 priv->chan = channel; 1498 1499 priv->SwChnlStage = 0; 1500 priv->SwChnlStep = 0; 1501 if (priv->up) 1502 rtl8192_SwChnl_WorkItem(dev); 1503 1504 priv->SwChnlInProgress = false; 1505 return true; 1506 } 1507 1508 /****************************************************************************** 1509 * function: Callback routine of the work item for set bandwidth mode. 1510 * input: net_device *dev 1511 * output: none 1512 * return: none 1513 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1514 * test whether current work in the queue or not.//do I? 1515 *****************************************************************************/ 1516 void rtl8192_SetBWModeWorkItem(struct net_device *dev) 1517 { 1518 1519 struct r8192_priv *priv = ieee80211_priv(dev); 1520 u8 regBwOpMode; 1521 1522 RT_TRACE(COMP_SWBW, "%s() Switch to %s bandwidth\n", __func__, 1523 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"); 1524 1525 1526 if (priv->rf_chip == RF_PSEUDO_11N) { 1527 priv->SetBWModeInProgress = false; 1528 return; 1529 } 1530 1531 /* <1> Set MAC register */ 1532 read_nic_byte(dev, BW_OPMODE, ®BwOpMode); 1533 1534 switch (priv->CurrentChannelBW) { 1535 case HT_CHANNEL_WIDTH_20: 1536 regBwOpMode |= BW_OPMODE_20MHZ; 1537 /* We have not verify whether this register works */ 1538 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1539 break; 1540 1541 case HT_CHANNEL_WIDTH_20_40: 1542 regBwOpMode &= ~BW_OPMODE_20MHZ; 1543 /* We have not verify whether this register works */ 1544 write_nic_byte(dev, BW_OPMODE, regBwOpMode); 1545 break; 1546 1547 default: 1548 RT_TRACE(COMP_ERR, 1549 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1550 priv->CurrentChannelBW); 1551 break; 1552 } 1553 1554 /* <2> Set PHY related register */ 1555 switch (priv->CurrentChannelBW) { 1556 case HT_CHANNEL_WIDTH_20: 1557 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); 1558 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0); 1559 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 1560 0x00100000, 1); 1561 1562 /* Correct the tx power for CCK rate in 20M. */ 1563 priv->cck_present_attenuation = 1564 priv->cck_present_attenuation_20Mdefault + 1565 priv->cck_present_attenuation_difference; 1566 1567 if (priv->cck_present_attenuation > 22) 1568 priv->cck_present_attenuation = 22; 1569 if (priv->cck_present_attenuation < 0) 1570 priv->cck_present_attenuation = 0; 1571 RT_TRACE(COMP_INIT, 1572 "20M, pHalData->CCKPresentAttentuation = %d\n", 1573 priv->cck_present_attenuation); 1574 1575 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1576 priv->bcck_in_ch14 = true; 1577 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1578 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1579 priv->bcck_in_ch14 = false; 1580 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1581 } else { 1582 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1583 } 1584 1585 break; 1586 case HT_CHANNEL_WIDTH_20_40: 1587 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); 1588 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1); 1589 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, 1590 priv->nCur40MhzPrimeSC>>1); 1591 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); 1592 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, 1593 priv->nCur40MhzPrimeSC); 1594 priv->cck_present_attenuation = 1595 priv->cck_present_attenuation_40Mdefault + 1596 priv->cck_present_attenuation_difference; 1597 1598 if (priv->cck_present_attenuation > 22) 1599 priv->cck_present_attenuation = 22; 1600 if (priv->cck_present_attenuation < 0) 1601 priv->cck_present_attenuation = 0; 1602 1603 RT_TRACE(COMP_INIT, 1604 "40M, pHalData->CCKPresentAttentuation = %d\n", 1605 priv->cck_present_attenuation); 1606 if (priv->chan == 14 && !priv->bcck_in_ch14) { 1607 priv->bcck_in_ch14 = true; 1608 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1609 } else if (priv->chan != 14 && priv->bcck_in_ch14) { 1610 priv->bcck_in_ch14 = false; 1611 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1612 } else { 1613 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); 1614 } 1615 1616 break; 1617 default: 1618 RT_TRACE(COMP_ERR, 1619 "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n", 1620 priv->CurrentChannelBW); 1621 break; 1622 1623 } 1624 /* Skip over setting of J-mode in BB register here. 1625 * Default value is "None J mode". 1626 */ 1627 1628 /* <3> Set RF related register */ 1629 switch (priv->rf_chip) { 1630 case RF_8225: 1631 #ifdef TO_DO_LIST 1632 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW); 1633 #endif 1634 break; 1635 1636 case RF_8256: 1637 phy_set_rf8256_bandwidth(dev, priv->CurrentChannelBW); 1638 break; 1639 1640 case RF_8258: 1641 break; 1642 1643 case RF_PSEUDO_11N: 1644 break; 1645 1646 default: 1647 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); 1648 break; 1649 } 1650 priv->SetBWModeInProgress = false; 1651 1652 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb(), %d\n", 1653 atomic_read(&priv->ieee80211->atm_swbw)); 1654 } 1655 1656 /****************************************************************************** 1657 * function: This function schedules bandwidth switch work. 1658 * input: struct net_deviceq *dev 1659 * HT_CHANNEL_WIDTH bandwidth //20M or 40M 1660 * HT_EXTCHNL_OFFSET offset //Upper, Lower, or Don't care 1661 * output: none 1662 * return: none 1663 * notice: I doubt whether SetBWModeInProgress flag is necessary as we can 1664 * test whether current work in the queue or not.//do I? 1665 *****************************************************************************/ 1666 void rtl8192_SetBWMode(struct net_device *dev, 1667 enum ht_channel_width bandwidth, 1668 enum ht_extension_chan_offset offset) 1669 { 1670 struct r8192_priv *priv = ieee80211_priv(dev); 1671 1672 if (priv->SetBWModeInProgress) 1673 return; 1674 priv->SetBWModeInProgress = true; 1675 1676 priv->CurrentChannelBW = bandwidth; 1677 1678 if (offset == HT_EXTCHNL_OFFSET_LOWER) 1679 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; 1680 else if (offset == HT_EXTCHNL_OFFSET_UPPER) 1681 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; 1682 else 1683 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; 1684 1685 rtl8192_SetBWModeWorkItem(dev); 1686 1687 } 1688 1689 void InitialGain819xUsb(struct net_device *dev, u8 Operation) 1690 { 1691 struct r8192_priv *priv = ieee80211_priv(dev); 1692 1693 priv->InitialGainOperateType = Operation; 1694 1695 if (priv->up) 1696 queue_delayed_work(priv->priv_wq, &priv->initialgain_operate_wq, 0); 1697 } 1698 1699 void InitialGainOperateWorkItemCallBack(struct work_struct *work) 1700 { 1701 struct delayed_work *dwork = to_delayed_work(work); 1702 struct r8192_priv *priv = container_of(dwork, struct r8192_priv, 1703 initialgain_operate_wq); 1704 struct net_device *dev = priv->ieee80211->dev; 1705 #define SCAN_RX_INITIAL_GAIN 0x17 1706 #define POWER_DETECTION_TH 0x08 1707 u32 bitmask; 1708 u8 initial_gain; 1709 u8 Operation; 1710 1711 Operation = priv->InitialGainOperateType; 1712 1713 switch (Operation) { 1714 case IG_Backup: 1715 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); 1716 initial_gain = SCAN_RX_INITIAL_GAIN; 1717 bitmask = bMaskByte0; 1718 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1719 /* FW DIG OFF */ 1720 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1721 priv->initgain_backup.xaagccore1 = 1722 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask); 1723 priv->initgain_backup.xbagccore1 = 1724 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask); 1725 priv->initgain_backup.xcagccore1 = 1726 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask); 1727 priv->initgain_backup.xdagccore1 = 1728 (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, bitmask); 1729 bitmask = bMaskByte2; 1730 priv->initgain_backup.cca = 1731 (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, bitmask); 1732 1733 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n", 1734 priv->initgain_backup.xaagccore1); 1735 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n", 1736 priv->initgain_backup.xbagccore1); 1737 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n", 1738 priv->initgain_backup.xcagccore1); 1739 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n", 1740 priv->initgain_backup.xdagccore1); 1741 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n", 1742 priv->initgain_backup.cca); 1743 1744 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n", 1745 initial_gain); 1746 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); 1747 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); 1748 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain); 1749 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); 1750 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n", 1751 POWER_DETECTION_TH); 1752 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); 1753 break; 1754 case IG_Restore: 1755 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); 1756 bitmask = 0x7f; /* Bit0 ~ Bit6 */ 1757 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1758 /* FW DIG OFF */ 1759 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); 1760 1761 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, 1762 (u32)priv->initgain_backup.xaagccore1); 1763 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, 1764 (u32)priv->initgain_backup.xbagccore1); 1765 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, bitmask, 1766 (u32)priv->initgain_backup.xcagccore1); 1767 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, bitmask, 1768 (u32)priv->initgain_backup.xdagccore1); 1769 bitmask = bMaskByte2; 1770 rtl8192_setBBreg(dev, rCCK0_CCA, bitmask, 1771 (u32)priv->initgain_backup.cca); 1772 1773 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n", 1774 priv->initgain_backup.xaagccore1); 1775 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n", 1776 priv->initgain_backup.xbagccore1); 1777 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n", 1778 priv->initgain_backup.xcagccore1); 1779 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n", 1780 priv->initgain_backup.xdagccore1); 1781 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n", 1782 priv->initgain_backup.cca); 1783 1784 rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel); 1785 1786 if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) 1787 /* FW DIG ON */ 1788 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); 1789 break; 1790 default: 1791 RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n"); 1792 break; 1793 } 1794 } 1795